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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id d5sm3906205lji.85.2019.05.20.08.27.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 20 May 2019 08:27:52 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com, Jici.Gao@arm.com, rebecca@bluestop.org, kettenis@jive.eu Subject: [edk2-devel] [edk2-platforms: PATCH v2 03/14] Marvell/Library: ArmadaBoardDescLib: Add PCIE information Date: Mon, 20 May 2019 17:27:16 +0200 Message-Id: <1558366047-15994-4-git-send-email-mw@semihalf.com> In-Reply-To: <1558366047-15994-1-git-send-email-mw@semihalf.com> References: <1558366047-15994-1-git-send-email-mw@semihalf.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1558366075; bh=uuM+S3tzSaFNAgnW8dy5mCrkjvKrSFn+Jbjfqy+mw0w=; h=Cc:Date:From:Reply-To:Subject:To; b=X4ExgNZ+JTDpmT1Ga0zq4KkF1ynUKdJ9LT/xBVfuOzVO3TNefZpuT/JfWg1aIPYl2Ao WUzj5ovJaUJZukPX/17bmGrLIyXTQWbVp3KsT0OC7GRkO5Mzut4keiWhO5XDNwOJjw+bP 7m4cRiY6FA3xVuo1/SQQ1IDwpVamZDxGtN4= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Introduce new callback that can provide information about PCIE controller per-board description. A new structure is defined containing base addresses, windows/bus configuration and reset GPIO usage indication. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h | 46 ++++++++++++++++= ++++ 1 file changed, 46 insertions(+) diff --git a/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h b/Silicon= /Marvell/Include/Library/ArmadaBoardDescLib.h index a6d39c4..2ad19aa 100644 --- a/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h +++ b/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h @@ -9,6 +9,7 @@ #define __ARMADA_BOARD_DESC_LIB_H__ =20 #include +#include =20 // // COMPHY controllers per-board description @@ -105,6 +106,51 @@ typedef struct { } MV_BOARD_XHCI_DESC; =20 // +// PCIE controllers description +// +typedef struct { + EFI_PHYSICAL_ADDRESS PcieDbiAddress; + EFI_PHYSICAL_ADDRESS ConfigSpaceAddress; + BOOLEAN HaveResetGpio; + MV_GPIO_PIN PcieResetGpio; + UINT64 PcieBusMin; + UINT64 PcieBusMax; + UINT64 PcieIoTranslation; + UINT64 PcieIoWinBase; + UINT64 PcieIoWinSize; + UINT64 PcieMmio32Translation; + UINT64 PcieMmio32WinBase; + UINT64 PcieMmio32WinSize; + UINT64 PcieMmio64Translation; + UINT64 PcieMmio64WinBase; + UINT64 PcieMmio64WinSize; +} MV_PCIE_CONTROLLER; + +typedef struct { + MV_PCIE_CONTROLLER CONST *PcieControllers; + UINTN PcieControllerCount; +} MV_BOARD_PCIE_DESCRIPTION; + +/** + Return the number and description of PCIE controllers used on the platfo= rm. + + @param[in out] **PcieControllers Array containing PCIE controllers' + description. + @param[in out] *PcieControllerCount Amount of used PCIE controllers. + + @retval EFI_SUCCESS The data were obtained successfull= y. + @retval EFI_NOT_FOUND None of the controllers is used. + @retval other Return error status. + +**/ +EFI_STATUS +EFIAPI +ArmadaBoardPcieControllerGet ( + IN OUT MV_PCIE_CONTROLLER CONST **PcieControllers, + IN OUT UINTN *PcieControllerCount + ); + +// // PP2 NIC devices per-board description // typedef struct { --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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