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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id l25sm276668lfk.57.2019.05.09.02.54.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 09 May 2019 02:54:01 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com, Jici.Gao@arm.com, rebecca@bluestop.org, kettenis@jive.eu Subject: [edk2-devel] [edk2-platforms: PATCH 05/14] Marvell/Armada7k8k: MvBoardDesc: Extend protocol with PCIE support Date: Thu, 9 May 2019 11:53:33 +0200 Message-Id: <1557395622-32425-6-git-send-email-mw@semihalf.com> In-Reply-To: <1557395622-32425-1-git-send-email-mw@semihalf.com> References: <1557395622-32425-1-git-send-email-mw@semihalf.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1557395644; bh=SEexb7+DmIxoYj2tDGCEQf9l/vOauZlAo4xD5Ivg1/k=; h=Cc:Date:From:Reply-To:Subject:To; b=Pvv8tHBfOexr2KxZTkQj+n+kEKYsONbiUs5MpBaj7jc5fVRzVXQaI3zURy7IM7yfJBk ciTYUe9OpI4+NJueAz2DeYIPnxhs78w3Ne2hQif0UefKQEJb5rQIQjtXa+mn7y+C8ruqQ fHgf8PL7mcIphK4vYlp/c42HfvbcpfVoVoQ= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Introduce new callback that can provide information about PCIE controllers, which are used on the platform. According ArmadaSoCDescLib ArmadaBoardDescLib routines are used for obtaining required data. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Include/Protocol/BoardDesc.h | 22 +++++ Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c | 86 ++++++++++++++++++= ++ 2 files changed, 108 insertions(+) diff --git a/Silicon/Marvell/Include/Protocol/BoardDesc.h b/Silicon/Marvell= /Include/Protocol/BoardDesc.h index 02905ea..c38ad86 100644 --- a/Silicon/Marvell/Include/Protocol/BoardDesc.h +++ b/Silicon/Marvell/Include/Protocol/BoardDesc.h @@ -90,6 +90,27 @@ EFI_STATUS IN OUT MV_BOARD_XHCI_DESC **XhciDesc ); =20 +/** + Return the description of PCIE controllers used on the platform. + + @param[in out] *This Pointer to board description proto= col. + @param[in out] **PcieDescription Array containing PCIE controllers' + description. + + @retval EFI_SUCCESS The data were obtained successfull= y. + @retval EFI_NOT_FOUND None of the controllers is used. + @retval EFI_INVALID_PARAMETER Description wrongly defined. + @retval EFI_OUT_OF_RESOURCES Lack of resources. + @retval Other Return error status. + +**/ +typedef +EFI_STATUS +(EFIAPI *MV_BOARD_PCIE_DESCRIPTION_GET) ( + IN MARVELL_BOARD_DESC_PROTOCOL *This, + IN OUT MV_BOARD_PCIE_DESCRIPTION **PcieDescription + ); + typedef EFI_STATUS (EFIAPI *MV_BOARD_DESC_PP2_GET) ( @@ -121,6 +142,7 @@ struct _MARVELL_BOARD_DESC_PROTOCOL { MV_BOARD_DESC_XHCI_GET BoardDescXhciGet; MV_BOARD_DESC_FREE BoardDescFree; MV_BOARD_GPIO_DESCRIPTION_GET GpioDescriptionGet; + MV_BOARD_PCIE_DESCRIPTION_GET PcieDescriptionGet; }; =20 #endif // __MARVELL_BOARD_DESC_PROTOCOL_H__ diff --git a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c b/Silicon/M= arvell/Drivers/BoardDesc/MvBoardDescDxe.c index 973c362..9cd95bd 100644 --- a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c +++ b/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c @@ -36,6 +36,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. MV_BOARD_DESC *mBoardDescInstance; =20 STATIC MV_BOARD_GPIO_DESCRIPTION *mGpioDescription; +STATIC MV_BOARD_PCIE_DESCRIPTION *mPcieDescription; =20 STATIC EFI_STATUS @@ -444,6 +445,90 @@ MvBoardDescXhciGet ( return EFI_SUCCESS; } =20 +/** + Return the description of PCIE controllers used on the platform. + + @param[in out] *This Pointer to board description proto= col. + @param[in out] **PcieDescription Array containing PCIE controllers' + description. + + @retval EFI_SUCCESS The data were obtained successfull= y. + @retval EFI_NOT_FOUND None of the controllers is used. + @retval EFI_INVALID_PARAMETER Description wrongly defined. + @retval EFI_OUT_OF_RESOURCES Lack of resources. + @retval Other Return error status. + +**/ +STATIC +EFI_STATUS +MvBoardPcieDescriptionGet ( + IN MARVELL_BOARD_DESC_PROTOCOL *This, + IN OUT MV_BOARD_PCIE_DESCRIPTION **PcieDescription + ) +{ + UINTN SoCPcieControllerCount, BoardPcieControllerCount, SoCIndex, BoardI= ndex; + EFI_PHYSICAL_ADDRESS *PcieBaseAddresses; + MV_PCIE_CONTROLLER *PcieControllers; + EFI_STATUS Status; + + /* Use existing structure if already created. */ + if (mPcieDescription !=3D NULL) { + *PcieDescription =3D mPcieDescription; + return EFI_SUCCESS; + } + + /* Get SoC data about all available PCIE controllers. */ + Status =3D ArmadaSoCPcieGet (&PcieBaseAddresses, &SoCPcieControllerCount= ); + if (EFI_ERROR (Status)) { + return Status; + } + + /* Get per-board information about all used PCIE controllers. */ + Status =3D ArmadaBoardPcieControllerGet (&PcieControllers, + &BoardPcieControllerCount); + if (EFI_ERROR (Status)) { + return Status; + } + + /* Sanity check of the board description. */ + if (BoardPcieControllerCount > SoCPcieControllerCount) { + DEBUG ((DEBUG_ERROR, "%a: Too many controllers described\n", __FUNCTIO= N__)); + return EFI_INVALID_PARAMETER; + } + + for (BoardIndex =3D 0; BoardIndex < BoardPcieControllerCount; BoardIndex= ++) { + for (SoCIndex =3D 0; SoCIndex < SoCPcieControllerCount; SoCIndex++) { + if (PcieControllers[BoardIndex].PcieBaseAddress =3D=3D + PcieBaseAddresses[SoCIndex]) { + /* Match found */ + break; + } + } + if (SoCIndex =3D=3D SoCPcieControllerCount) { + DEBUG ((DEBUG_ERROR, + "%a: Controller #%d base address invalid: 0x%x\n", + __FUNCTION__, + BoardIndex, + PcieControllers[BoardIndex].PcieBaseAddress)); + return EFI_INVALID_PARAMETER; + } + } + + /* Allocate and fill board description. */ + mPcieDescription =3D AllocateZeroPool (sizeof (MV_BOARD_PCIE_DESCRIPTION= )); + if (mPcieDescription =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + mPcieDescription->PcieControllers =3D PcieControllers; + mPcieDescription->PcieControllerCount =3D BoardPcieControllerCount; + + *PcieDescription =3D mPcieDescription; + + return EFI_SUCCESS; +} + STATIC EFI_STATUS MvBoardDescPp2Get ( @@ -621,6 +706,7 @@ MvBoardDescInitProtocol ( BoardDescProtocol->BoardDescXhciGet =3D MvBoardDescXhciGet; BoardDescProtocol->BoardDescFree =3D MvBoardDescFree; BoardDescProtocol->GpioDescriptionGet =3D MvBoardGpioDescriptionGet; + BoardDescProtocol->PcieDescriptionGet =3D MvBoardPcieDescriptionGet; =20 return EFI_SUCCESS; } --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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