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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id l25sm276668lfk.57.2019.05.09.02.53.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 09 May 2019 02:53:59 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com, Jici.Gao@arm.com, rebecca@bluestop.org, kettenis@jive.eu Subject: [edk2-devel] [edk2-platforms: PATCH 04/14] Marvell/Armada7k8k: Extend board description libraries with PCIE Date: Thu, 9 May 2019 11:53:32 +0200 Message-Id: <1557395622-32425-5-git-send-email-mw@semihalf.com> In-Reply-To: <1557395622-32425-1-git-send-email-mw@semihalf.com> References: <1557395622-32425-1-git-send-email-mw@semihalf.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1557395643; bh=S3fHsm5V6pdlk8PkkOElMhsclHqwsOmZG/abXM3FMoc=; h=Cc:Date:From:Reply-To:Subject:To; b=hZns7tZ4rxDUZsQ76Bpwb6UVUvxiojDu+g2C170GBViTw5hK72fTbPUp4GeRW1yHg5b jLdNxSnLKGlKFCZ1ZHeGAMNT6L33+JM37AfdZnFs4YdR7LC7qb/SsSQkhyr2oTtmXGEyt q2RNQWipjI0yRQkz9aVx3otW0rz/+IZtd1U= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch extends ArmadaBoardDescLib libraries for all existing Armada7k8k-based platforms with PCIE. It introduces ArmadaBoardPcieControllerGet routine with per-board PCIE controllers description. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Platform/Marvell/Armada70x0Db/Armada70x0DbBoardDescLib/Armada70x0DbBoardDe= scLib.c | 48 ++++++++++++++++++++ Platform/Marvell/Armada80x0Db/Armada80x0DbBoardDescLib/Armada80x0DbBoardDe= scLib.c | 48 ++++++++++++++++++++ Platform/SolidRun/Armada80x0McBin/Armada80x0McBinBoardDescLib/Armada80x0Mc= BinBoardDescLib.c | 48 ++++++++++++++++++++ 3 files changed, 144 insertions(+) diff --git a/Platform/Marvell/Armada70x0Db/Armada70x0DbBoardDescLib/Armada7= 0x0DbBoardDescLib.c b/Platform/Marvell/Armada70x0Db/Armada70x0DbBoardDescLi= b/Armada70x0DbBoardDescLib.c index f0133ec..cbd23cc 100644 --- a/Platform/Marvell/Armada70x0Db/Armada70x0DbBoardDescLib/Armada70x0DbBo= ardDescLib.c +++ b/Platform/Marvell/Armada70x0Db/Armada70x0DbBoardDescLib/Armada70x0DbBo= ardDescLib.c @@ -46,6 +46,54 @@ ArmadaBoardGpioExpanderGet ( } =20 // +// PCIE +// +STATIC +MV_PCIE_CONTROLLER mPcieController[] =3D { + { /* PCIE2 @0xF2640000 */ + .PcieBaseAddress =3D 0xF2640000, + .ConfigSpaceAddress =3D 0xE0000000, + .HaveResetGpio =3D FALSE, + .PcieResetGpio =3D { 0 }, + .PcieBusMin =3D 0, + .PcieBusMax =3D 0xFE, + .PcieIoTranslation =3D 0xEFF00000, + .PcieIoWinBase =3D 0x0, + .PcieIoWinSize =3D 0x10000, + .PcieMmio32Translation =3D 0, + .PcieMmio32WinBase =3D 0xC0000000, + .PcieMmio32WinSize =3D 0x20000000, + .PcieMmio64Translation =3D 0, + .PcieMmio64WinBase =3D 0x800000000, + .PcieMmio64WinSize =3D 0x100000000, + } +}; + +/** + Return the number and description of PCIE controllers used on the platfo= rm. + + @param[in out] **PcieControllers Array containing PCIE controllers' + description. + @param[in out] *PcieControllerCount Amount of used PCIE controllers. + + @retval EFI_SUCCESS The data were obtained successfull= y. + @retval other Return error status. + +**/ +EFI_STATUS +EFIAPI +ArmadaBoardPcieControllerGet ( + IN OUT MV_PCIE_CONTROLLER **PcieControllers, + IN OUT UINTN *PcieControllerCount + ) +{ + *PcieControllers =3D mPcieController; + *PcieControllerCount =3D ARRAY_SIZE (mPcieController); + + return EFI_SUCCESS; +} + +// // Order of devices in SdMmcDescTemplate has to be in par with ArmadaSoCDe= scLib // STATIC diff --git a/Platform/Marvell/Armada80x0Db/Armada80x0DbBoardDescLib/Armada8= 0x0DbBoardDescLib.c b/Platform/Marvell/Armada80x0Db/Armada80x0DbBoardDescLi= b/Armada80x0DbBoardDescLib.c index 61b6202..5781756 100644 --- a/Platform/Marvell/Armada80x0Db/Armada80x0DbBoardDescLib/Armada80x0DbBo= ardDescLib.c +++ b/Platform/Marvell/Armada80x0Db/Armada80x0DbBoardDescLib/Armada80x0DbBo= ardDescLib.c @@ -52,6 +52,54 @@ ArmadaBoardGpioExpanderGet ( } =20 // +// PCIE +// +STATIC +MV_PCIE_CONTROLLER mPcieController[] =3D { + { /* PCIE0 @0xF2600000 */ + .PcieBaseAddress =3D 0xF2600000, + .ConfigSpaceAddress =3D 0xE0000000, + .HaveResetGpio =3D FALSE, + .PcieResetGpio =3D { 0 }, + .PcieBusMin =3D 0, + .PcieBusMax =3D 0xFE, + .PcieIoTranslation =3D 0xEFF00000, + .PcieIoWinBase =3D 0x0, + .PcieIoWinSize =3D 0x10000, + .PcieMmio32Translation =3D 0, + .PcieMmio32WinBase =3D 0xC0000000, + .PcieMmio32WinSize =3D 0x20000000, + .PcieMmio64Translation =3D 0, + .PcieMmio64WinBase =3D 0x800000000, + .PcieMmio64WinSize =3D 0x100000000, + } +}; + +/** + Return the number and description of PCIE controllers used on the platfo= rm. + + @param[in out] **PcieControllers Array containing PCIE controllers' + description. + @param[in out] *PcieControllerCount Amount of used PCIE controllers. + + @retval EFI_SUCCESS The data were obtained successfull= y. + @retval other Return error status. + +**/ +EFI_STATUS +EFIAPI +ArmadaBoardPcieControllerGet ( + IN OUT MV_PCIE_CONTROLLER **PcieControllers, + IN OUT UINTN *PcieControllerCount + ) +{ + *PcieControllers =3D mPcieController; + *PcieControllerCount =3D ARRAY_SIZE (mPcieController); + + return EFI_SUCCESS; +} + +// // Order of devices in SdMmcDescTemplate has to be in par with ArmadaSoCDe= scLib // STATIC diff --git a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBinBoardDescLib/= Armada80x0McBinBoardDescLib.c b/Platform/SolidRun/Armada80x0McBin/Armada80x= 0McBinBoardDescLib/Armada80x0McBinBoardDescLib.c index 32596ad..11a889b 100644 --- a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBinBoardDescLib/Armada8= 0x0McBinBoardDescLib.c +++ b/Platform/SolidRun/Armada80x0McBin/Armada80x0McBinBoardDescLib/Armada8= 0x0McBinBoardDescLib.c @@ -39,6 +39,54 @@ ArmadaBoardGpioExpanderGet ( } =20 // +// PCIE +// +STATIC +MV_PCIE_CONTROLLER mPcieController[] =3D { + { /* PCIE0 @0xF2600000 */ + .PcieBaseAddress =3D 0xF2600000, + .ConfigSpaceAddress =3D 0xE0000000, + .HaveResetGpio =3D FALSE, + .PcieResetGpio =3D { 0 }, + .PcieBusMin =3D 0, + .PcieBusMax =3D 0xFE, + .PcieIoTranslation =3D 0xEFF00000, + .PcieIoWinBase =3D 0x0, + .PcieIoWinSize =3D 0x10000, + .PcieMmio32Translation =3D 0, + .PcieMmio32WinBase =3D 0xC0000000, + .PcieMmio32WinSize =3D 0x20000000, + .PcieMmio64Translation =3D 0, + .PcieMmio64WinBase =3D 0x800000000, + .PcieMmio64WinSize =3D 0x100000000, + } +}; + +/** + Return the number and description of PCIE controllers used on the platfo= rm. + + @param[in out] **PcieControllers Array containing PCIE controllers' + description. + @param[in out] *PcieControllerCount Amount of used PCIE controllers. + + @retval EFI_SUCCESS The data were obtained successfull= y. + @retval other Return error status. + +**/ +EFI_STATUS +EFIAPI +ArmadaBoardPcieControllerGet ( + IN OUT MV_PCIE_CONTROLLER **PcieControllers, + IN OUT UINTN *PcieControllerCount + ) +{ + *PcieControllers =3D mPcieController; + *PcieControllerCount =3D ARRAY_SIZE (mPcieController); + + return EFI_SUCCESS; +} + +// // Order of devices in SdMmcDescTemplate has to be in par with ArmadaSoCDe= scLib // STATIC --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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