From nobody Mon Feb 9 16:19:25 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+40315+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+40315+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1557395640; cv=none; d=zoho.com; s=zohoarc; b=YcihZf4xIpAivZOyjVDFYZ7VDXu930tp9/JApxKh6fe1h3F/bjV5slgMtwaMk0moemkinFmYobSB98zGIzHCveEQbivIicJeWyBTWEK4Reeb6kK2hpKrgs3BnAstvQ0N9uxWcGh7n1IcatYZT89/LPdaT8q0lYvsfswSg7+UEMM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557395640; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=eWC8Qtf/yqZ3E6iJsmGyveDRnLFw8m8mvFz7gcnHfWI=; b=QpIbt2Pja7Sat59RggaBxlsXP627wr5L4gNSgwydhVKAGLYfVvU/hXO2+yPXYANkwWjRTbEMBmn072OvufFVlK4ufGgwRAbHKWhhGjQv2VobXMR0QyPdRpwln0ZFdxCQaG5c+H9hdL+o/zABM0BXYghZHNVPDNq9ylSis44SRO4= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+40315+1787277+3901457@groups.io Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1557395640172886.8191481758384; Thu, 9 May 2019 02:54:00 -0700 (PDT) Return-Path: X-Received: from mail-lf1-f68.google.com (mail-lf1-f68.google.com [209.85.167.68]) by groups.io with SMTP; Thu, 09 May 2019 02:53:59 -0700 X-Received: by mail-lf1-f68.google.com with SMTP id n22so1070625lfe.12 for ; Thu, 09 May 2019 02:53:58 -0700 (PDT) X-Gm-Message-State: APjAAAXs1z6uX0H3rmiJl/E+blGR/Ag3XARsY8orFkngxfxvcfFFNYOB KFlsMkhdQLSv5nWz90fHgRJ1ZmjHo30= X-Google-Smtp-Source: APXvYqwyEot2ioJLiYZBYd4tgH4XrbgCnQwWGEkxr1UeJ54kr9QV89gSiNsh0XbkmTnE6WVzw0Husg== X-Received: by 2002:ac2:538a:: with SMTP id g10mr1982349lfh.141.1557395636874; Thu, 09 May 2019 02:53:56 -0700 (PDT) X-Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id l25sm276668lfk.57.2019.05.09.02.53.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 09 May 2019 02:53:56 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com, Jici.Gao@arm.com, rebecca@bluestop.org, kettenis@jive.eu Subject: [edk2-devel] [edk2-platforms: PATCH 01/14] Marvell/Library: MvGpioLib: Extend GPIO pin description Date: Thu, 9 May 2019 11:53:29 +0200 Message-Id: <1557395622-32425-2-git-send-email-mw@semihalf.com> In-Reply-To: <1557395622-32425-1-git-send-email-mw@semihalf.com> References: <1557395622-32425-1-git-send-email-mw@semihalf.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1557395639; bh=ZsTfE00EHLDDnxmeNSx5wmIUC1w9ECJkjyQl3YmmJ1s=; h=Cc:Date:From:Reply-To:Subject:To; b=ew6ONSowAEhQsNj7Mc1kw8cQTbolHexdIDj+7KHa6DvPYq/PaKy4Hisq+HjAaPvUyFg 4uxr+gQMfrgpCdFqFp20Md6MOgm0FjqZSF8fzltGf5zV8FUNOQ1DqRNRvK+HTj6ejN28K eRJDuQWQPs1M0lEJX31BYSWCeCy2pq448v4= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" In order to avoid hardcoding the controller type when using MV_GPIO_PIN, extend this structure with new according field. This patch is required to properly handle PCIE slot reset with the GPIO pin. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Include/Library/MvGpioLib.h = | 1 + Platform/Marvell/Armada70x0Db/NonDiscoverableInitLib/NonDiscoverableInitLi= b.c | 4 ++++ Platform/Marvell/Armada80x0Db/NonDiscoverableInitLib/NonDiscoverableInitLi= b.c | 6 ++++++ Platform/SolidRun/Armada80x0McBin/NonDiscoverableInitLib/NonDiscoverableIn= itLib.c | 1 + 4 files changed, 12 insertions(+) diff --git a/Silicon/Marvell/Include/Library/MvGpioLib.h b/Silicon/Marvell/= Include/Library/MvGpioLib.h index a14acdf..2d5fa94 100644 --- a/Silicon/Marvell/Include/Library/MvGpioLib.h +++ b/Silicon/Marvell/Include/Library/MvGpioLib.h @@ -53,6 +53,7 @@ typedef struct { } MV_GPIO_DEVICE_PATH; =20 typedef struct { + MV_GPIO_DRIVER_TYPE ControllerType; UINTN ControllerId; UINTN PinNumber; BOOLEAN ActiveHigh; diff --git a/Platform/Marvell/Armada70x0Db/NonDiscoverableInitLib/NonDiscov= erableInitLib.c b/Platform/Marvell/Armada70x0Db/NonDiscoverableInitLib/NonD= iscoverableInitLib.c index d8dba6e..62a57f7 100644 --- a/Platform/Marvell/Armada70x0Db/NonDiscoverableInitLib/NonDiscoverableI= nitLib.c +++ b/Platform/Marvell/Armada70x0Db/NonDiscoverableInitLib/NonDiscoverableI= nitLib.c @@ -29,21 +29,25 @@ =20 STATIC CONST MV_GPIO_PIN mXhciVbusPins[] =3D { { + MV_GPIO_DRIVER_TYPE_PCA95XX, ARMADA_70x0_DB_IO_EXPANDER0, ARMADA_70x0_DB_VBUS0_PIN, TRUE, }, { + MV_GPIO_DRIVER_TYPE_PCA95XX, ARMADA_70x0_DB_IO_EXPANDER0, ARMADA_70x0_DB_VBUS0_LIMIT_PIN, TRUE, }, { + MV_GPIO_DRIVER_TYPE_PCA95XX, ARMADA_70x0_DB_IO_EXPANDER0, ARMADA_70x0_DB_VBUS1_PIN, TRUE, }, { + MV_GPIO_DRIVER_TYPE_PCA95XX, ARMADA_70x0_DB_IO_EXPANDER0, ARMADA_70x0_DB_VBUS1_LIMIT_PIN, TRUE, diff --git a/Platform/Marvell/Armada80x0Db/NonDiscoverableInitLib/NonDiscov= erableInitLib.c b/Platform/Marvell/Armada80x0Db/NonDiscoverableInitLib/NonD= iscoverableInitLib.c index e7a1d1e..1220163 100644 --- a/Platform/Marvell/Armada80x0Db/NonDiscoverableInitLib/NonDiscoverableI= nitLib.c +++ b/Platform/Marvell/Armada80x0Db/NonDiscoverableInitLib/NonDiscoverableI= nitLib.c @@ -29,31 +29,37 @@ =20 STATIC CONST MV_GPIO_PIN mXhciVbusPins[] =3D { { + MV_GPIO_DRIVER_TYPE_PCA95XX, ARMADA_80x0_DB_IO_EXPANDER0, ARMADA_80x0_DB_VBUS0_PIN, TRUE, }, { + MV_GPIO_DRIVER_TYPE_PCA95XX, ARMADA_80x0_DB_IO_EXPANDER0, ARMADA_80x0_DB_VBUS0_LIMIT_PIN, TRUE, }, { + MV_GPIO_DRIVER_TYPE_PCA95XX, ARMADA_80x0_DB_IO_EXPANDER0, ARMADA_80x0_DB_VBUS1_PIN, TRUE, }, { + MV_GPIO_DRIVER_TYPE_PCA95XX, ARMADA_80x0_DB_IO_EXPANDER0, ARMADA_80x0_DB_VBUS1_LIMIT_PIN, TRUE, }, { + MV_GPIO_DRIVER_TYPE_PCA95XX, ARMADA_80x0_DB_IO_EXPANDER1, ARMADA_80x0_DB_VBUS2_PIN, TRUE, }, { + MV_GPIO_DRIVER_TYPE_PCA95XX, ARMADA_80x0_DB_IO_EXPANDER1, ARMADA_80x0_DB_VBUS2_LIMIT_PIN, TRUE, diff --git a/Platform/SolidRun/Armada80x0McBin/NonDiscoverableInitLib/NonDi= scoverableInitLib.c b/Platform/SolidRun/Armada80x0McBin/NonDiscoverableInit= Lib/NonDiscoverableInitLib.c index d1055cb..08c383f 100644 --- a/Platform/SolidRun/Armada80x0McBin/NonDiscoverableInitLib/NonDiscovera= bleInitLib.c +++ b/Platform/SolidRun/Armada80x0McBin/NonDiscoverableInitLib/NonDiscovera= bleInitLib.c @@ -28,6 +28,7 @@ #include "NonDiscoverableInitLib.h" =20 STATIC CONST MV_GPIO_PIN mXhciVbusPin =3D { + MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER, MV_GPIO_CP0_CONTROLLER1, ARMADA_80x0_MCBIN_VBUS0_PIN, TRUE, --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#40315): https://edk2.groups.io/g/devel/message/40315 Mute This Topic: https://groups.io/mt/31553474/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-