From nobody Sat May 4 20:05:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+40315+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+40315+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1557395640; cv=none; d=zoho.com; s=zohoarc; b=YcihZf4xIpAivZOyjVDFYZ7VDXu930tp9/JApxKh6fe1h3F/bjV5slgMtwaMk0moemkinFmYobSB98zGIzHCveEQbivIicJeWyBTWEK4Reeb6kK2hpKrgs3BnAstvQ0N9uxWcGh7n1IcatYZT89/LPdaT8q0lYvsfswSg7+UEMM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557395640; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=eWC8Qtf/yqZ3E6iJsmGyveDRnLFw8m8mvFz7gcnHfWI=; b=QpIbt2Pja7Sat59RggaBxlsXP627wr5L4gNSgwydhVKAGLYfVvU/hXO2+yPXYANkwWjRTbEMBmn072OvufFVlK4ufGgwRAbHKWhhGjQv2VobXMR0QyPdRpwln0ZFdxCQaG5c+H9hdL+o/zABM0BXYghZHNVPDNq9ylSis44SRO4= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+40315+1787277+3901457@groups.io Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1557395640172886.8191481758384; Thu, 9 May 2019 02:54:00 -0700 (PDT) Return-Path: X-Received: from mail-lf1-f68.google.com (mail-lf1-f68.google.com [209.85.167.68]) by groups.io with SMTP; Thu, 09 May 2019 02:53:59 -0700 X-Received: by mail-lf1-f68.google.com with SMTP id n22so1070625lfe.12 for ; Thu, 09 May 2019 02:53:58 -0700 (PDT) X-Gm-Message-State: APjAAAXs1z6uX0H3rmiJl/E+blGR/Ag3XARsY8orFkngxfxvcfFFNYOB KFlsMkhdQLSv5nWz90fHgRJ1ZmjHo30= X-Google-Smtp-Source: APXvYqwyEot2ioJLiYZBYd4tgH4XrbgCnQwWGEkxr1UeJ54kr9QV89gSiNsh0XbkmTnE6WVzw0Husg== X-Received: by 2002:ac2:538a:: with SMTP id g10mr1982349lfh.141.1557395636874; Thu, 09 May 2019 02:53:56 -0700 (PDT) X-Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id l25sm276668lfk.57.2019.05.09.02.53.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 09 May 2019 02:53:56 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com, Jici.Gao@arm.com, rebecca@bluestop.org, kettenis@jive.eu Subject: [edk2-devel] [edk2-platforms: PATCH 01/14] Marvell/Library: MvGpioLib: Extend GPIO pin description Date: Thu, 9 May 2019 11:53:29 +0200 Message-Id: <1557395622-32425-2-git-send-email-mw@semihalf.com> In-Reply-To: <1557395622-32425-1-git-send-email-mw@semihalf.com> References: <1557395622-32425-1-git-send-email-mw@semihalf.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1557395639; bh=ZsTfE00EHLDDnxmeNSx5wmIUC1w9ECJkjyQl3YmmJ1s=; h=Cc:Date:From:Reply-To:Subject:To; b=ew6ONSowAEhQsNj7Mc1kw8cQTbolHexdIDj+7KHa6DvPYq/PaKy4Hisq+HjAaPvUyFg 4uxr+gQMfrgpCdFqFp20Md6MOgm0FjqZSF8fzltGf5zV8FUNOQ1DqRNRvK+HTj6ejN28K eRJDuQWQPs1M0lEJX31BYSWCeCy2pq448v4= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" In order to avoid hardcoding the controller type when using MV_GPIO_PIN, extend this structure with new according field. This patch is required to properly handle PCIE slot reset with the GPIO pin. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Include/Library/MvGpioLib.h = | 1 + Platform/Marvell/Armada70x0Db/NonDiscoverableInitLib/NonDiscoverableInitLi= b.c | 4 ++++ Platform/Marvell/Armada80x0Db/NonDiscoverableInitLib/NonDiscoverableInitLi= b.c | 6 ++++++ Platform/SolidRun/Armada80x0McBin/NonDiscoverableInitLib/NonDiscoverableIn= itLib.c | 1 + 4 files changed, 12 insertions(+) diff --git a/Silicon/Marvell/Include/Library/MvGpioLib.h b/Silicon/Marvell/= Include/Library/MvGpioLib.h index a14acdf..2d5fa94 100644 --- a/Silicon/Marvell/Include/Library/MvGpioLib.h +++ b/Silicon/Marvell/Include/Library/MvGpioLib.h @@ -53,6 +53,7 @@ typedef struct { } MV_GPIO_DEVICE_PATH; =20 typedef struct { + MV_GPIO_DRIVER_TYPE ControllerType; UINTN ControllerId; UINTN PinNumber; BOOLEAN ActiveHigh; diff --git a/Platform/Marvell/Armada70x0Db/NonDiscoverableInitLib/NonDiscov= erableInitLib.c b/Platform/Marvell/Armada70x0Db/NonDiscoverableInitLib/NonD= iscoverableInitLib.c index d8dba6e..62a57f7 100644 --- a/Platform/Marvell/Armada70x0Db/NonDiscoverableInitLib/NonDiscoverableI= nitLib.c +++ b/Platform/Marvell/Armada70x0Db/NonDiscoverableInitLib/NonDiscoverableI= nitLib.c @@ -29,21 +29,25 @@ =20 STATIC CONST MV_GPIO_PIN mXhciVbusPins[] =3D { { + MV_GPIO_DRIVER_TYPE_PCA95XX, ARMADA_70x0_DB_IO_EXPANDER0, ARMADA_70x0_DB_VBUS0_PIN, TRUE, }, { + MV_GPIO_DRIVER_TYPE_PCA95XX, ARMADA_70x0_DB_IO_EXPANDER0, ARMADA_70x0_DB_VBUS0_LIMIT_PIN, TRUE, }, { + MV_GPIO_DRIVER_TYPE_PCA95XX, ARMADA_70x0_DB_IO_EXPANDER0, ARMADA_70x0_DB_VBUS1_PIN, TRUE, }, { + MV_GPIO_DRIVER_TYPE_PCA95XX, ARMADA_70x0_DB_IO_EXPANDER0, ARMADA_70x0_DB_VBUS1_LIMIT_PIN, TRUE, diff --git a/Platform/Marvell/Armada80x0Db/NonDiscoverableInitLib/NonDiscov= erableInitLib.c b/Platform/Marvell/Armada80x0Db/NonDiscoverableInitLib/NonD= iscoverableInitLib.c index e7a1d1e..1220163 100644 --- a/Platform/Marvell/Armada80x0Db/NonDiscoverableInitLib/NonDiscoverableI= nitLib.c +++ b/Platform/Marvell/Armada80x0Db/NonDiscoverableInitLib/NonDiscoverableI= nitLib.c @@ -29,31 +29,37 @@ =20 STATIC CONST MV_GPIO_PIN mXhciVbusPins[] =3D { { + MV_GPIO_DRIVER_TYPE_PCA95XX, ARMADA_80x0_DB_IO_EXPANDER0, ARMADA_80x0_DB_VBUS0_PIN, TRUE, }, { + MV_GPIO_DRIVER_TYPE_PCA95XX, ARMADA_80x0_DB_IO_EXPANDER0, ARMADA_80x0_DB_VBUS0_LIMIT_PIN, TRUE, }, { + MV_GPIO_DRIVER_TYPE_PCA95XX, ARMADA_80x0_DB_IO_EXPANDER0, ARMADA_80x0_DB_VBUS1_PIN, TRUE, }, { + MV_GPIO_DRIVER_TYPE_PCA95XX, ARMADA_80x0_DB_IO_EXPANDER0, ARMADA_80x0_DB_VBUS1_LIMIT_PIN, TRUE, }, { + MV_GPIO_DRIVER_TYPE_PCA95XX, ARMADA_80x0_DB_IO_EXPANDER1, ARMADA_80x0_DB_VBUS2_PIN, TRUE, }, { + MV_GPIO_DRIVER_TYPE_PCA95XX, ARMADA_80x0_DB_IO_EXPANDER1, ARMADA_80x0_DB_VBUS2_LIMIT_PIN, TRUE, diff --git a/Platform/SolidRun/Armada80x0McBin/NonDiscoverableInitLib/NonDi= scoverableInitLib.c b/Platform/SolidRun/Armada80x0McBin/NonDiscoverableInit= Lib/NonDiscoverableInitLib.c index d1055cb..08c383f 100644 --- a/Platform/SolidRun/Armada80x0McBin/NonDiscoverableInitLib/NonDiscovera= bleInitLib.c +++ b/Platform/SolidRun/Armada80x0McBin/NonDiscoverableInitLib/NonDiscovera= bleInitLib.c @@ -28,6 +28,7 @@ #include "NonDiscoverableInitLib.h" =20 STATIC CONST MV_GPIO_PIN mXhciVbusPin =3D { + MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER, MV_GPIO_CP0_CONTROLLER1, ARMADA_80x0_MCBIN_VBUS0_PIN, TRUE, --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id l25sm276668lfk.57.2019.05.09.02.53.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 09 May 2019 02:53:57 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com, Jici.Gao@arm.com, rebecca@bluestop.org, kettenis@jive.eu Subject: [edk2-devel] [edk2-platforms: PATCH 02/14] Marvell/Library: ArmadaSoCDescLib: Add PCIE information Date: Thu, 9 May 2019 11:53:30 +0200 Message-Id: <1557395622-32425-3-git-send-email-mw@semihalf.com> In-Reply-To: <1557395622-32425-1-git-send-email-mw@semihalf.com> References: <1557395622-32425-1-git-send-email-mw@semihalf.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1557395641; bh=oMV9kcTIOXIVqSvjtc2e3TetRHiZIRdTekBDqbk6WDA=; h=Cc:Date:From:Reply-To:Subject:To; b=QqkJgh1RFL+QrGt+yx+bttEM5ksxSdcdQOs5xz3t4ROmlPVNAJG1QacQ7z8x2Rt9xgD gzLqw9mo43EqSWxa5UaamrzUA4wYCtYEX1TcTPS5JZeKghoCXw+QjLTY8n0YP6cjvgCi3 HJFuF1sGtd/kWruhq8Gc+JnA/vPXLLhlmis= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch introduces new library callback (ArmadaSoCPcieGet ()), which dynamically allocates and fills array with all available PCIE controllers' base addresses. It is needed for the configuration of PCIE, whose support will be added in the upcoming patches. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescL= ib.h | 6 +++ Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h = | 20 +++++++++ Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescL= ib.c | 44 ++++++++++++++++++++ 3 files changed, 70 insertions(+) diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada= 7k8kSoCDescLib.h b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/= Armada7k8kSoCDescLib.h index 8bbc5b0..e904222 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.h +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.h @@ -82,6 +82,12 @@ #define MV_SOC_MDIO_ID(Cp) (Cp) =20 // +// Platform description of PCIE +// +#define MV_SOC_PCIE_PER_CP_COUNT 3 +#define MV_SOC_PCIE_BASE(Index) (0x600000 + ((Index) * 0x20000)) + +// // Platform description of PP2 NIC // #define MV_SOC_PP2_BASE(Cp) MV_SOC_CP_BASE (Cp) diff --git a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h b/Silicon/M= arvell/Include/Library/ArmadaSoCDescLib.h index fc17c3a..ff617e6 100644 --- a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h +++ b/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h @@ -191,6 +191,26 @@ ArmadaSoCDescXhciGet ( IN OUT UINTN *DescCount ); =20 +/** + This function returns the total number of PCIE controllers and an array + with their base addresses. + + @param[in out] **PcieBaseAddresses Array containing PCIE controllers' b= ase + adresses. + @param[in out] *Count Total amount of available PCIE contro= llers. + + @retval EFI_SUCCESS The data were obtained successfully. + @retval EFI_OUT_OF_RESOURCES The request could not be completed du= e to a + lack of resources. + +**/ +EFI_STATUS +EFIAPI +ArmadaSoCPcieGet ( + IN OUT EFI_PHYSICAL_ADDRESS **PcieBaseAddresses, + IN OUT UINTN *Count + ); + // // PP2 NIC devices SoC description // diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada= 7k8kSoCDescLib.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/= Armada7k8kSoCDescLib.c index 355be64..4f8a59a 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.c +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.c @@ -278,6 +278,50 @@ ArmadaSoCDescAhciGet ( return EFI_SUCCESS; } =20 +/** + This function returns the total number of PCIE controllers and an array + with their base addresses. + + @param[in out] **PcieBaseAddresses Array containing PCIE controllers' ba= se + adresses. + @param[in out] *Count Total amount of available PCIE contro= llers. + + @retval EFI_SUCCESS The data were obtained successfully. + @retval EFI_OUT_OF_RESOURCES The request could not be completed du= e to a + lack of resources. + +**/ +EFI_STATUS +EFIAPI +ArmadaSoCPcieGet ( + IN OUT EFI_PHYSICAL_ADDRESS **PcieBaseAddresses, + IN OUT UINTN *Count + ) +{ + UINTN CpCount, CpIndex, Index; + EFI_PHYSICAL_ADDRESS *BaseAddress; + + CpCount =3D FixedPcdGet8 (PcdMaxCpCount); + + *Count =3D CpCount * MV_SOC_PCIE_PER_CP_COUNT; + BaseAddress =3D AllocateZeroPool (*Count * sizeof (EFI_PHYSICAL_ADDRESS)= ); + if (BaseAddress =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + *PcieBaseAddresses =3D BaseAddress; + + for (CpIndex =3D 0; CpIndex < CpCount; CpIndex++) { + for (Index =3D 0; Index < MV_SOC_PCIE_PER_CP_COUNT; Index++) { + *BaseAddress =3D MV_SOC_CP_BASE (CpIndex) + MV_SOC_PCIE_BASE (Index); + BaseAddress++; + } + } + + return EFI_SUCCESS; +} + EFI_STATUS EFIAPI ArmadaSoCDescPp2Get ( --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id l25sm276668lfk.57.2019.05.09.02.53.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 09 May 2019 02:53:58 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com, Jici.Gao@arm.com, rebecca@bluestop.org, kettenis@jive.eu Subject: [edk2-devel] [edk2-platforms: PATCH 03/14] Marvell/Library: ArmadaBoardDescLib: Add PCIE information Date: Thu, 9 May 2019 11:53:31 +0200 Message-Id: <1557395622-32425-4-git-send-email-mw@semihalf.com> In-Reply-To: <1557395622-32425-1-git-send-email-mw@semihalf.com> References: <1557395622-32425-1-git-send-email-mw@semihalf.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1557395642; bh=bGh1fkhOxU6KzWsPiXQpDmz4A9u+3ScgAFjJoBVXoGs=; h=Cc:Date:From:Reply-To:Subject:To; b=xALEDPZ85JnldwZfAMCmrrgBjlzZ04rNBslQFX7gecsYutP2rqpi+CctN6nxhfgj3q9 w9e5yClm6P3Q7SNZCO/s5Wmjiy+walJ+P9/b5gIxh8UQWGE+3av9XA4Rj8v5auEx93WUK DYYsHsy7MCWkS9erbuWJKqHkml7nzgqYZgM= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Introduce new callback that can provide information about PCIE controller per-board description. A new structure is defined containing base addresses, windows/bus configuration and reset GPIO usage indication. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h | 46 ++++++++++++++++= ++++ 1 file changed, 46 insertions(+) diff --git a/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h b/Silicon= /Marvell/Include/Library/ArmadaBoardDescLib.h index 6ec5ace..530a2ba 100644 --- a/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h +++ b/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h @@ -15,6 +15,7 @@ #define __ARMADA_BOARD_DESC_LIB_H__ =20 #include +#include =20 // // COMPHY controllers per-board description @@ -111,6 +112,51 @@ typedef struct { } MV_BOARD_XHCI_DESC; =20 // +// PCIE controllers description +// +typedef struct { + EFI_PHYSICAL_ADDRESS PcieBaseAddress; + EFI_PHYSICAL_ADDRESS ConfigSpaceAddress; + BOOLEAN HaveResetGpio; + MV_GPIO_PIN PcieResetGpio; + UINT64 PcieBusMin; + UINT64 PcieBusMax; + UINT64 PcieIoTranslation; + UINT64 PcieIoWinBase; + UINT64 PcieIoWinSize; + UINT64 PcieMmio32Translation; + UINT64 PcieMmio32WinBase; + UINT64 PcieMmio32WinSize; + UINT64 PcieMmio64Translation; + UINT64 PcieMmio64WinBase; + UINT64 PcieMmio64WinSize; +} MV_PCIE_CONTROLLER; + +typedef struct { + MV_PCIE_CONTROLLER *PcieControllers; + UINTN PcieControllerCount; +} MV_BOARD_PCIE_DESCRIPTION; + +/** + Return the number and description of PCIE controllers used on the platfo= rm. + + @param[in out] **PcieControllers Array containing PCIE controllers' + description. + @param[in out] *PcieControllerCount Amount of used PCIE controllers. + + @retval EFI_SUCCESS The data were obtained successfull= y. + @retval EFI_NOT_FOUND None of the controllers is used. + @retval other Return error status. + +**/ +EFI_STATUS +EFIAPI +ArmadaBoardPcieControllerGet ( + IN OUT MV_PCIE_CONTROLLER **PcieControllers, + IN OUT UINTN *PcieControllerCount + ); + +// // PP2 NIC devices per-board description // typedef struct { --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id l25sm276668lfk.57.2019.05.09.02.53.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 09 May 2019 02:53:59 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com, Jici.Gao@arm.com, rebecca@bluestop.org, kettenis@jive.eu Subject: [edk2-devel] [edk2-platforms: PATCH 04/14] Marvell/Armada7k8k: Extend board description libraries with PCIE Date: Thu, 9 May 2019 11:53:32 +0200 Message-Id: <1557395622-32425-5-git-send-email-mw@semihalf.com> In-Reply-To: <1557395622-32425-1-git-send-email-mw@semihalf.com> References: <1557395622-32425-1-git-send-email-mw@semihalf.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1557395643; bh=S3fHsm5V6pdlk8PkkOElMhsclHqwsOmZG/abXM3FMoc=; h=Cc:Date:From:Reply-To:Subject:To; b=hZns7tZ4rxDUZsQ76Bpwb6UVUvxiojDu+g2C170GBViTw5hK72fTbPUp4GeRW1yHg5b jLdNxSnLKGlKFCZ1ZHeGAMNT6L33+JM37AfdZnFs4YdR7LC7qb/SsSQkhyr2oTtmXGEyt q2RNQWipjI0yRQkz9aVx3otW0rz/+IZtd1U= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch extends ArmadaBoardDescLib libraries for all existing Armada7k8k-based platforms with PCIE. It introduces ArmadaBoardPcieControllerGet routine with per-board PCIE controllers description. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Platform/Marvell/Armada70x0Db/Armada70x0DbBoardDescLib/Armada70x0DbBoardDe= scLib.c | 48 ++++++++++++++++++++ Platform/Marvell/Armada80x0Db/Armada80x0DbBoardDescLib/Armada80x0DbBoardDe= scLib.c | 48 ++++++++++++++++++++ Platform/SolidRun/Armada80x0McBin/Armada80x0McBinBoardDescLib/Armada80x0Mc= BinBoardDescLib.c | 48 ++++++++++++++++++++ 3 files changed, 144 insertions(+) diff --git a/Platform/Marvell/Armada70x0Db/Armada70x0DbBoardDescLib/Armada7= 0x0DbBoardDescLib.c b/Platform/Marvell/Armada70x0Db/Armada70x0DbBoardDescLi= b/Armada70x0DbBoardDescLib.c index f0133ec..cbd23cc 100644 --- a/Platform/Marvell/Armada70x0Db/Armada70x0DbBoardDescLib/Armada70x0DbBo= ardDescLib.c +++ b/Platform/Marvell/Armada70x0Db/Armada70x0DbBoardDescLib/Armada70x0DbBo= ardDescLib.c @@ -46,6 +46,54 @@ ArmadaBoardGpioExpanderGet ( } =20 // +// PCIE +// +STATIC +MV_PCIE_CONTROLLER mPcieController[] =3D { + { /* PCIE2 @0xF2640000 */ + .PcieBaseAddress =3D 0xF2640000, + .ConfigSpaceAddress =3D 0xE0000000, + .HaveResetGpio =3D FALSE, + .PcieResetGpio =3D { 0 }, + .PcieBusMin =3D 0, + .PcieBusMax =3D 0xFE, + .PcieIoTranslation =3D 0xEFF00000, + .PcieIoWinBase =3D 0x0, + .PcieIoWinSize =3D 0x10000, + .PcieMmio32Translation =3D 0, + .PcieMmio32WinBase =3D 0xC0000000, + .PcieMmio32WinSize =3D 0x20000000, + .PcieMmio64Translation =3D 0, + .PcieMmio64WinBase =3D 0x800000000, + .PcieMmio64WinSize =3D 0x100000000, + } +}; + +/** + Return the number and description of PCIE controllers used on the platfo= rm. + + @param[in out] **PcieControllers Array containing PCIE controllers' + description. + @param[in out] *PcieControllerCount Amount of used PCIE controllers. + + @retval EFI_SUCCESS The data were obtained successfull= y. + @retval other Return error status. + +**/ +EFI_STATUS +EFIAPI +ArmadaBoardPcieControllerGet ( + IN OUT MV_PCIE_CONTROLLER **PcieControllers, + IN OUT UINTN *PcieControllerCount + ) +{ + *PcieControllers =3D mPcieController; + *PcieControllerCount =3D ARRAY_SIZE (mPcieController); + + return EFI_SUCCESS; +} + +// // Order of devices in SdMmcDescTemplate has to be in par with ArmadaSoCDe= scLib // STATIC diff --git a/Platform/Marvell/Armada80x0Db/Armada80x0DbBoardDescLib/Armada8= 0x0DbBoardDescLib.c b/Platform/Marvell/Armada80x0Db/Armada80x0DbBoardDescLi= b/Armada80x0DbBoardDescLib.c index 61b6202..5781756 100644 --- a/Platform/Marvell/Armada80x0Db/Armada80x0DbBoardDescLib/Armada80x0DbBo= ardDescLib.c +++ b/Platform/Marvell/Armada80x0Db/Armada80x0DbBoardDescLib/Armada80x0DbBo= ardDescLib.c @@ -52,6 +52,54 @@ ArmadaBoardGpioExpanderGet ( } =20 // +// PCIE +// +STATIC +MV_PCIE_CONTROLLER mPcieController[] =3D { + { /* PCIE0 @0xF2600000 */ + .PcieBaseAddress =3D 0xF2600000, + .ConfigSpaceAddress =3D 0xE0000000, + .HaveResetGpio =3D FALSE, + .PcieResetGpio =3D { 0 }, + .PcieBusMin =3D 0, + .PcieBusMax =3D 0xFE, + .PcieIoTranslation =3D 0xEFF00000, + .PcieIoWinBase =3D 0x0, + .PcieIoWinSize =3D 0x10000, + .PcieMmio32Translation =3D 0, + .PcieMmio32WinBase =3D 0xC0000000, + .PcieMmio32WinSize =3D 0x20000000, + .PcieMmio64Translation =3D 0, + .PcieMmio64WinBase =3D 0x800000000, + .PcieMmio64WinSize =3D 0x100000000, + } +}; + +/** + Return the number and description of PCIE controllers used on the platfo= rm. + + @param[in out] **PcieControllers Array containing PCIE controllers' + description. + @param[in out] *PcieControllerCount Amount of used PCIE controllers. + + @retval EFI_SUCCESS The data were obtained successfull= y. + @retval other Return error status. + +**/ +EFI_STATUS +EFIAPI +ArmadaBoardPcieControllerGet ( + IN OUT MV_PCIE_CONTROLLER **PcieControllers, + IN OUT UINTN *PcieControllerCount + ) +{ + *PcieControllers =3D mPcieController; + *PcieControllerCount =3D ARRAY_SIZE (mPcieController); + + return EFI_SUCCESS; +} + +// // Order of devices in SdMmcDescTemplate has to be in par with ArmadaSoCDe= scLib // STATIC diff --git a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBinBoardDescLib/= Armada80x0McBinBoardDescLib.c b/Platform/SolidRun/Armada80x0McBin/Armada80x= 0McBinBoardDescLib/Armada80x0McBinBoardDescLib.c index 32596ad..11a889b 100644 --- a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBinBoardDescLib/Armada8= 0x0McBinBoardDescLib.c +++ b/Platform/SolidRun/Armada80x0McBin/Armada80x0McBinBoardDescLib/Armada8= 0x0McBinBoardDescLib.c @@ -39,6 +39,54 @@ ArmadaBoardGpioExpanderGet ( } =20 // +// PCIE +// +STATIC +MV_PCIE_CONTROLLER mPcieController[] =3D { + { /* PCIE0 @0xF2600000 */ + .PcieBaseAddress =3D 0xF2600000, + .ConfigSpaceAddress =3D 0xE0000000, + .HaveResetGpio =3D FALSE, + .PcieResetGpio =3D { 0 }, + .PcieBusMin =3D 0, + .PcieBusMax =3D 0xFE, + .PcieIoTranslation =3D 0xEFF00000, + .PcieIoWinBase =3D 0x0, + .PcieIoWinSize =3D 0x10000, + .PcieMmio32Translation =3D 0, + .PcieMmio32WinBase =3D 0xC0000000, + .PcieMmio32WinSize =3D 0x20000000, + .PcieMmio64Translation =3D 0, + .PcieMmio64WinBase =3D 0x800000000, + .PcieMmio64WinSize =3D 0x100000000, + } +}; + +/** + Return the number and description of PCIE controllers used on the platfo= rm. + + @param[in out] **PcieControllers Array containing PCIE controllers' + description. + @param[in out] *PcieControllerCount Amount of used PCIE controllers. + + @retval EFI_SUCCESS The data were obtained successfull= y. + @retval other Return error status. + +**/ +EFI_STATUS +EFIAPI +ArmadaBoardPcieControllerGet ( + IN OUT MV_PCIE_CONTROLLER **PcieControllers, + IN OUT UINTN *PcieControllerCount + ) +{ + *PcieControllers =3D mPcieController; + *PcieControllerCount =3D ARRAY_SIZE (mPcieController); + + return EFI_SUCCESS; +} + +// // Order of devices in SdMmcDescTemplate has to be in par with ArmadaSoCDe= scLib // STATIC --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#40318): https://edk2.groups.io/g/devel/message/40318 Mute This Topic: https://groups.io/mt/31553477/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat May 4 20:05:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+40319+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+40319+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1557395645; cv=none; d=zoho.com; s=zohoarc; b=HqO2D5rX9S14QoWLHcCCWBQ+GQ1y25rvow88e/6KymYHjnaRQ982DNXg+lLQnVIATUOQv7bIQS3/d8XKv580j5YKq6vymzK3y4c80E9z8H+9R67z4/AFq3PbTNkrhXyOS0zewfR5fxLB20ZotiiySx6u7EO4jbKL5GMC8j4m7W0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557395645; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=8l8hgD8ix9/xb+444iDjWujkF2z5w0+3N7OsEx6quns=; b=C9hkFMM2k5exh1+TSCTzoXFkLH3CbBMDClAEYDdj9ue0SX2eQjfYY3CFkzGQpImYjujtzNSBzhs5pT+EkPKCZiob0EXSBqkj6H1fIyR09yb+F8jh4+ETTHLkIiz16BUMVf+QphK8aalFtwR9dwffJDeM8+xXQhekuBZLQ08n924= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+40319+1787277+3901457@groups.io Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1557395645544298.1832767761407; Thu, 9 May 2019 02:54:05 -0700 (PDT) Return-Path: X-Received: from mail-lj1-f193.google.com (mail-lj1-f193.google.com [209.85.208.193]) by groups.io with SMTP; Thu, 09 May 2019 02:54:04 -0700 X-Received: by mail-lj1-f193.google.com with SMTP id d15so1460158ljc.7 for ; Thu, 09 May 2019 02:54:03 -0700 (PDT) X-Gm-Message-State: APjAAAUf4uqmit1qPorRRJcxo3uZtFrGexyqtXw0yGXP95uZSHkFxx31 M/Q344Ew8E8RFnJB4yf+6cTRXtjzuTw= X-Google-Smtp-Source: APXvYqwDiWP/0rh50el7FWm4aNuuUz6pay90oOzQlJv1TNKmUTXCAleHz7+d5wMTA7MzlsmmcCdbow== X-Received: by 2002:a2e:9e9a:: with SMTP id f26mr1887145ljk.170.1557395641851; Thu, 09 May 2019 02:54:01 -0700 (PDT) X-Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id l25sm276668lfk.57.2019.05.09.02.54.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 09 May 2019 02:54:01 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com, Jici.Gao@arm.com, rebecca@bluestop.org, kettenis@jive.eu Subject: [edk2-devel] [edk2-platforms: PATCH 05/14] Marvell/Armada7k8k: MvBoardDesc: Extend protocol with PCIE support Date: Thu, 9 May 2019 11:53:33 +0200 Message-Id: <1557395622-32425-6-git-send-email-mw@semihalf.com> In-Reply-To: <1557395622-32425-1-git-send-email-mw@semihalf.com> References: <1557395622-32425-1-git-send-email-mw@semihalf.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1557395644; bh=SEexb7+DmIxoYj2tDGCEQf9l/vOauZlAo4xD5Ivg1/k=; h=Cc:Date:From:Reply-To:Subject:To; b=Pvv8tHBfOexr2KxZTkQj+n+kEKYsONbiUs5MpBaj7jc5fVRzVXQaI3zURy7IM7yfJBk ciTYUe9OpI4+NJueAz2DeYIPnxhs78w3Ne2hQif0UefKQEJb5rQIQjtXa+mn7y+C8ruqQ fHgf8PL7mcIphK4vYlp/c42HfvbcpfVoVoQ= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Introduce new callback that can provide information about PCIE controllers, which are used on the platform. According ArmadaSoCDescLib ArmadaBoardDescLib routines are used for obtaining required data. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Include/Protocol/BoardDesc.h | 22 +++++ Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c | 86 ++++++++++++++++++= ++ 2 files changed, 108 insertions(+) diff --git a/Silicon/Marvell/Include/Protocol/BoardDesc.h b/Silicon/Marvell= /Include/Protocol/BoardDesc.h index 02905ea..c38ad86 100644 --- a/Silicon/Marvell/Include/Protocol/BoardDesc.h +++ b/Silicon/Marvell/Include/Protocol/BoardDesc.h @@ -90,6 +90,27 @@ EFI_STATUS IN OUT MV_BOARD_XHCI_DESC **XhciDesc ); =20 +/** + Return the description of PCIE controllers used on the platform. + + @param[in out] *This Pointer to board description proto= col. + @param[in out] **PcieDescription Array containing PCIE controllers' + description. + + @retval EFI_SUCCESS The data were obtained successfull= y. + @retval EFI_NOT_FOUND None of the controllers is used. + @retval EFI_INVALID_PARAMETER Description wrongly defined. + @retval EFI_OUT_OF_RESOURCES Lack of resources. + @retval Other Return error status. + +**/ +typedef +EFI_STATUS +(EFIAPI *MV_BOARD_PCIE_DESCRIPTION_GET) ( + IN MARVELL_BOARD_DESC_PROTOCOL *This, + IN OUT MV_BOARD_PCIE_DESCRIPTION **PcieDescription + ); + typedef EFI_STATUS (EFIAPI *MV_BOARD_DESC_PP2_GET) ( @@ -121,6 +142,7 @@ struct _MARVELL_BOARD_DESC_PROTOCOL { MV_BOARD_DESC_XHCI_GET BoardDescXhciGet; MV_BOARD_DESC_FREE BoardDescFree; MV_BOARD_GPIO_DESCRIPTION_GET GpioDescriptionGet; + MV_BOARD_PCIE_DESCRIPTION_GET PcieDescriptionGet; }; =20 #endif // __MARVELL_BOARD_DESC_PROTOCOL_H__ diff --git a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c b/Silicon/M= arvell/Drivers/BoardDesc/MvBoardDescDxe.c index 973c362..9cd95bd 100644 --- a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c +++ b/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c @@ -36,6 +36,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. MV_BOARD_DESC *mBoardDescInstance; =20 STATIC MV_BOARD_GPIO_DESCRIPTION *mGpioDescription; +STATIC MV_BOARD_PCIE_DESCRIPTION *mPcieDescription; =20 STATIC EFI_STATUS @@ -444,6 +445,90 @@ MvBoardDescXhciGet ( return EFI_SUCCESS; } =20 +/** + Return the description of PCIE controllers used on the platform. + + @param[in out] *This Pointer to board description proto= col. + @param[in out] **PcieDescription Array containing PCIE controllers' + description. + + @retval EFI_SUCCESS The data were obtained successfull= y. + @retval EFI_NOT_FOUND None of the controllers is used. + @retval EFI_INVALID_PARAMETER Description wrongly defined. + @retval EFI_OUT_OF_RESOURCES Lack of resources. + @retval Other Return error status. + +**/ +STATIC +EFI_STATUS +MvBoardPcieDescriptionGet ( + IN MARVELL_BOARD_DESC_PROTOCOL *This, + IN OUT MV_BOARD_PCIE_DESCRIPTION **PcieDescription + ) +{ + UINTN SoCPcieControllerCount, BoardPcieControllerCount, SoCIndex, BoardI= ndex; + EFI_PHYSICAL_ADDRESS *PcieBaseAddresses; + MV_PCIE_CONTROLLER *PcieControllers; + EFI_STATUS Status; + + /* Use existing structure if already created. */ + if (mPcieDescription !=3D NULL) { + *PcieDescription =3D mPcieDescription; + return EFI_SUCCESS; + } + + /* Get SoC data about all available PCIE controllers. */ + Status =3D ArmadaSoCPcieGet (&PcieBaseAddresses, &SoCPcieControllerCount= ); + if (EFI_ERROR (Status)) { + return Status; + } + + /* Get per-board information about all used PCIE controllers. */ + Status =3D ArmadaBoardPcieControllerGet (&PcieControllers, + &BoardPcieControllerCount); + if (EFI_ERROR (Status)) { + return Status; + } + + /* Sanity check of the board description. */ + if (BoardPcieControllerCount > SoCPcieControllerCount) { + DEBUG ((DEBUG_ERROR, "%a: Too many controllers described\n", __FUNCTIO= N__)); + return EFI_INVALID_PARAMETER; + } + + for (BoardIndex =3D 0; BoardIndex < BoardPcieControllerCount; BoardIndex= ++) { + for (SoCIndex =3D 0; SoCIndex < SoCPcieControllerCount; SoCIndex++) { + if (PcieControllers[BoardIndex].PcieBaseAddress =3D=3D + PcieBaseAddresses[SoCIndex]) { + /* Match found */ + break; + } + } + if (SoCIndex =3D=3D SoCPcieControllerCount) { + DEBUG ((DEBUG_ERROR, + "%a: Controller #%d base address invalid: 0x%x\n", + __FUNCTION__, + BoardIndex, + PcieControllers[BoardIndex].PcieBaseAddress)); + return EFI_INVALID_PARAMETER; + } + } + + /* Allocate and fill board description. */ + mPcieDescription =3D AllocateZeroPool (sizeof (MV_BOARD_PCIE_DESCRIPTION= )); + if (mPcieDescription =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + mPcieDescription->PcieControllers =3D PcieControllers; + mPcieDescription->PcieControllerCount =3D BoardPcieControllerCount; + + *PcieDescription =3D mPcieDescription; + + return EFI_SUCCESS; +} + STATIC EFI_STATUS MvBoardDescPp2Get ( @@ -621,6 +706,7 @@ MvBoardDescInitProtocol ( BoardDescProtocol->BoardDescXhciGet =3D MvBoardDescXhciGet; BoardDescProtocol->BoardDescFree =3D MvBoardDescFree; BoardDescProtocol->GpioDescriptionGet =3D MvBoardGpioDescriptionGet; + BoardDescProtocol->PcieDescriptionGet =3D MvBoardPcieDescriptionGet; =20 return EFI_SUCCESS; } --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#40319): https://edk2.groups.io/g/devel/message/40319 Mute This Topic: https://groups.io/mt/31553478/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat May 4 20:05:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+40320+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+40320+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1557395648; cv=none; d=zoho.com; s=zohoarc; b=bzsjoBHcRnrsTqqLA+4b72EDm2rorFyBnxQvjJ6nnR017Z0sIhDRpUTh4A+aeig4tZHQvpLST+41U230ysV8M6hW0P5CK9d14ZvENXT3uihGHutOUitbtz6vZ1Cv+nPOG2X7kixUF0WTOlhSg+iwjH3A6vk1Uz/4NtsyV6qMfWs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557395648; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=dxLFXGyXS4bAN0YnVXSgbiQDnQnMJ5Nyik+YPLoXjdE=; b=oVl42YGKKJXSdROBk9wE4gD/3hYVu9qDSjTtXFBdb5i/FlLnK+YKvsuilrodIPDbDvkdsPFSC4LkOzg53lHBv0ExAGjhIZoypsNq8DjjKKK6GtZEqnb+RZkjX8WICKUf4j0Vy4cNp+LBvRu1w0n+mKkqJaz8gpljtAx7XO4UFBo= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+40320+1787277+3901457@groups.io Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1557395648616935.0355870162653; Thu, 9 May 2019 02:54:08 -0700 (PDT) Return-Path: X-Received: from mail-lf1-f68.google.com (mail-lf1-f68.google.com [209.85.167.68]) by groups.io with SMTP; Thu, 09 May 2019 02:54:06 -0700 X-Received: by mail-lf1-f68.google.com with SMTP id n22so1070876lfe.12 for ; Thu, 09 May 2019 02:54:05 -0700 (PDT) X-Gm-Message-State: APjAAAUqUq1M9hWtGU8RpM86oYnSweqd1mh3J5sx5xsMHKmAPQrN0qf5 rFZsx1s2Oxa8Cb+1hzt8jvWaUsbxCzg= X-Google-Smtp-Source: APXvYqwMcQhZHzbRqcQwuwffUXd1HPX6q0Cg4wkv7FKOE96O1f63maDJubkCch62uUFsuXlllYRr9g== X-Received: by 2002:ac2:518b:: with SMTP id u11mr1887317lfi.30.1557395643247; Thu, 09 May 2019 02:54:03 -0700 (PDT) X-Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id l25sm276668lfk.57.2019.05.09.02.54.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 09 May 2019 02:54:02 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com, Jici.Gao@arm.com, rebecca@bluestop.org, kettenis@jive.eu Subject: [edk2-devel] [edk2-platforms: PATCH 06/14] Marvell/Armada7k8k: Add PciExpressLib implementation Date: Thu, 9 May 2019 11:53:34 +0200 Message-Id: <1557395622-32425-7-git-send-email-mw@semihalf.com> In-Reply-To: <1557395622-32425-1-git-send-email-mw@semihalf.com> References: <1557395622-32425-1-git-send-email-mw@semihalf.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1557395647; bh=nbfW/3hk1iBcs5XvsfKNclekJ1em/rBlMyzPpzBFTug=; h=Cc:Date:From:Reply-To:Subject:To; b=fdLROQetIy/LuUe/yxKWpCQ+feVQ4OxsR2n0TW7aSzNiwcpgNpFeuaPtU/rYghor9uV siJdoAajEHcFgcOeaZKUqwiiOXcJWHeDXv6XypnaTJ5ncl24Gqo4ZZdEskfmnHEgWMWsY Q3JdaMr/e3t/O7dfPI1Ca/23h2gwBlNQy6k= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Ard Biesheuvel Implement a special version of PciExpressLib that takes the quirky nature of the Synopsys Designware PCIe IP into account. In particular, we need to ignores config space accesses to all devices on the first bus except device 0, because the broadcast nature of type 0 configuration cycles will result in whatever device is in the slot to appear at each of the 32 device positions. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciExpressLib/PciExpressLib.i= nf | 42 + Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciExpressLib/PciExpressLib.c= | 1529 ++++++++++++++++++++ 2 files changed, 1571 insertions(+) create mode 100644 Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciExpress= Lib/PciExpressLib.inf create mode 100644 Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciExpress= Lib/PciExpressLib.c diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciExpressLib/Pci= ExpressLib.inf b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciExpressLib= /PciExpressLib.inf new file mode 100644 index 0000000..8f09820 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciExpressLib/PciExpress= Lib.inf @@ -0,0 +1,42 @@ +## @file +# +# Copyright (c) 2017, Linaro, Ltd. All rights reserved.
+# Copyright (c) 2019 Marvell International Ltd. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may b= e found at +# http://opensource.org/licenses/bsd-license.php. +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +# +## + +[Defines] + INF_VERSION =3D 0x0001001B + BASE_NAME =3D Armada7k8kPciExpressLib + FILE_GUID =3D f0926204-3061-40ed-8261-2aeccc7914c9 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D PciExpressLib + +[Sources] + PciExpressLib.c + +[Packages] + ArmPkg/ArmPkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses] + BaseLib + DebugLib + IoLib + PcdLib + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES + +[FixedPcd] + gArmTokenSpaceGuid.PcdPciBusMin + gArmTokenSpaceGuid.PcdPciBusMax diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciExpressLib/Pci= ExpressLib.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciExpressLib/P= ciExpressLib.c new file mode 100644 index 0000000..8fa2eb6 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciExpressLib/PciExpress= Lib.c @@ -0,0 +1,1529 @@ +/** @file + + Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.
+ Copyright (c) 2019 Marvell International Ltd. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + + +#include + +#include +#include +#include +#include +#include + +/** + Assert the validity of a PCI address. A valid PCI address should contain= 1's + only in the low 28 bits. + + @param A The address to validate. + +**/ +#define ASSERT_INVALID_PCI_ADDRESS(A) \ + ASSERT (((A) & ~0xfffffff) =3D=3D 0) + +/** + Registers a PCI device so PCI configuration registers may be accessed af= ter + SetVirtualAddressMap(). + + Registers the PCI device specified by Address so all the PCI configurati= on + registers associated with that PCI device may be accessed after SetVirtu= alAddressMap() + is called. + + If Address > 0x0FFFFFFF, then ASSERT(). + + @param Address The address that encodes the PCI Bus, Device, Function a= nd + Register. + + @retval RETURN_SUCCESS The PCI device was registered for runti= me access. + @retval RETURN_UNSUPPORTED An attempt was made to call this functi= on + after ExitBootServices(). + @retval RETURN_UNSUPPORTED The resources required to access the PC= I device + at runtime could not be mapped. + @retval RETURN_OUT_OF_RESOURCES There are not enough resources availabl= e to + complete the registration. + +**/ +RETURN_STATUS +EFIAPI +PciExpressRegisterForRuntimeAccess ( + IN UINTN Address + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + return RETURN_UNSUPPORTED; +} + +#define ECAM_BUS_SIZE SIZE_1MB +#define ECAM_DEV_SIZE SIZE_32KB + +STATIC +BOOLEAN +IgnoreBusDeviceFunction ( + IN UINTN Address + ) +{ + ASSERT (Address >=3D FixedPcdGet32 (PcdPciBusMin) * ECAM_BUS_SIZE); + ASSERT (Address < (FixedPcdGet32 (PcdPciBusMax) + 1) * ECAM_BUS_SIZE); + + // + // Type 0 configuration cycles don't contain a b/d/f specifier, and so it + // is up to the bus that delivers them to ensure they only end up at the + // correct device/function. Sadly, the Synopsys IP does not implement th= is, + // and so we have to ignore config space accesses for all devices on the + // first bus except device 0. + // + return (Address >=3D (FixedPcdGet32 (PcdPciBusMin) * ECAM_BUS_SIZE + + ECAM_DEV_SIZE) && + Address < (FixedPcdGet32 (PcdPciBusMin) + 1) * ECAM_BUS_SIZE); +} + +/** + Gets the base address of PCI Express. + + This internal functions retrieves PCI Express Base Address via a PCD ent= ry + PcdPciExpressBaseAddress. + + @return The base address of PCI Express. + +**/ +VOID* +GetPciExpressBaseAddress ( + VOID + ) +{ + return (VOID*)(UINTN) PcdGet64 (PcdPciExpressBaseAddress); +} + +/** + Reads an 8-bit PCI configuration register. + + Reads and returns the 8-bit PCI configuration register specified by Addr= ess. + This function must guarantee that all PCI read and write operations are + serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + + @param Address The address that encodes the PCI Bus, Device, Function a= nd + Register. + + @return The read value from the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciExpressRead8 ( + IN UINTN Address + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + if (IgnoreBusDeviceFunction (Address)) { + return 0xff; + } + return MmioRead8 ((UINTN) GetPciExpressBaseAddress () + Address); +} + +/** + Writes an 8-bit PCI configuration register. + + Writes the 8-bit PCI configuration register specified by Address with the + value specified by Value. Value is returned. This function must guarantee + that all PCI read and write operations are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + + @param Address The address that encodes the PCI Bus, Device, Function a= nd + Register. + @param Value The value to write. + + @return The value written to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciExpressWrite8 ( + IN UINTN Address, + IN UINT8 Value + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + if (IgnoreBusDeviceFunction (Address)) { + return 0xff; + } + return MmioWrite8 ((UINTN) GetPciExpressBaseAddress () + Address, Value); +} + +/** + Performs a bitwise OR of an 8-bit PCI configuration register with + an 8-bit value. + + Reads the 8-bit PCI configuration register specified by Address, perform= s a + bitwise OR between the read result and the value specified by + OrData, and writes the result to the 8-bit PCI configuration register + specified by Address. The value written to the PCI configuration registe= r is + returned. This function must guarantee that all PCI read and write opera= tions + are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + + @param Address The address that encodes the PCI Bus, Device, Function a= nd + Register. + @param OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciExpressOr8 ( + IN UINTN Address, + IN UINT8 OrData + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + if (IgnoreBusDeviceFunction (Address)) { + return 0xff; + } + return MmioOr8 ((UINTN) GetPciExpressBaseAddress () + Address, OrData); +} + +/** + Performs a bitwise AND of an 8-bit PCI configuration register with an 8-= bit + value. + + Reads the 8-bit PCI configuration register specified by Address, perform= s a + bitwise AND between the read result and the value specified by AndData, = and + writes the result to the 8-bit PCI configuration register specified by + Address. The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are + serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + + @param Address The address that encodes the PCI Bus, Device, Function a= nd + Register. + @param AndData The value to AND with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciExpressAnd8 ( + IN UINTN Address, + IN UINT8 AndData + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + if (IgnoreBusDeviceFunction (Address)) { + return 0xff; + } + return MmioAnd8 ((UINTN) GetPciExpressBaseAddress () + Address, AndData); +} + +/** + Performs a bitwise AND of an 8-bit PCI configuration register with an 8-= bit + value, followed a bitwise OR with another 8-bit value. + + Reads the 8-bit PCI configuration register specified by Address, perform= s a + bitwise AND between the read result and the value specified by AndData, + performs a bitwise OR between the result of the AND operation and + the value specified by OrData, and writes the result to the 8-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that al= l PCI + read and write operations are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + + @param Address The address that encodes the PCI Bus, Device, Function a= nd + Register. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciExpressAndThenOr8 ( + IN UINTN Address, + IN UINT8 AndData, + IN UINT8 OrData + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + if (IgnoreBusDeviceFunction (Address)) { + return 0xff; + } + return MmioAndThenOr8 ( + (UINTN) GetPciExpressBaseAddress () + Address, + AndData, + OrData + ); +} + +/** + Reads a bit field of a PCI configuration register. + + Reads the bit field in an 8-bit PCI configuration register. The bit fiel= d is + specified by the StartBit and the EndBit. The value of the bit field is + returned. + + If Address > 0x0FFFFFFF, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param Address The PCI configuration register to read. + @param StartBit The ordinal of the least significant bit in the bit fi= eld. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit fie= ld. + Range 0..7. + + @return The value of the bit field read from the PCI configuration regis= ter. + +**/ +UINT8 +EFIAPI +PciExpressBitFieldRead8 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + if (IgnoreBusDeviceFunction (Address)) { + return 0xff; + } + return MmioBitFieldRead8 ( + (UINTN) GetPciExpressBaseAddress () + Address, + StartBit, + EndBit + ); +} + +/** + Writes a bit field to a PCI configuration register. + + Writes Value to the bit field of the PCI configuration register. The bit + field is specified by the StartBit and the EndBit. All other bits in the + destination PCI configuration register are preserved. The new value of t= he + 8-bit register is returned. + + If Address > 0x0FFFFFFF, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If Value is larger than the bitmask value range specified by StartBit an= d EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit fi= eld. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit fie= ld. + Range 0..7. + @param Value The new value of the bit field. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciExpressBitFieldWrite8 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 Value + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + if (IgnoreBusDeviceFunction (Address)) { + return 0xff; + } + return MmioBitFieldWrite8 ( + (UINTN) GetPciExpressBaseAddress () + Address, + StartBit, + EndBit, + Value + ); +} + +/** + Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, = and + writes the result back to the bit field in the 8-bit port. + + Reads the 8-bit PCI configuration register specified by Address, perform= s a + bitwise OR between the read result and the value specified by + OrData, and writes the result to the 8-bit PCI configuration register + specified by Address. The value written to the PCI configuration registe= r is + returned. This function must guarantee that all PCI read and write opera= tions + are serialized. Extra left bits in OrData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit a= nd EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit fi= eld. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit fie= ld. + Range 0..7. + @param OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciExpressBitFieldOr8 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 OrData + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + if (IgnoreBusDeviceFunction (Address)) { + return 0xff; + } + return MmioBitFieldOr8 ( + (UINTN) GetPciExpressBaseAddress () + Address, + StartBit, + EndBit, + OrData + ); +} + +/** + Reads a bit field in an 8-bit PCI configuration register, performs a bit= wise + AND, and writes the result back to the bit field in the 8-bit register. + + Reads the 8-bit PCI configuration register specified by Address, perform= s a + bitwise AND between the read result and the value specified by AndData, = and + writes the result to the 8-bit PCI configuration register specified by + Address. The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are + serialized. Extra left bits in AndData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit = and EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit fi= eld. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit fie= ld. + Range 0..7. + @param AndData The value to AND with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciExpressBitFieldAnd8 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 AndData + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + if (IgnoreBusDeviceFunction (Address)) { + return 0xff; + } + return MmioBitFieldAnd8 ( + (UINTN) GetPciExpressBaseAddress () + Address, + StartBit, + EndBit, + AndData + ); +} + +/** + Reads a bit field in an 8-bit port, performs a bitwise AND followed by a + bitwise OR, and writes the result back to the bit field in the + 8-bit port. + + Reads the 8-bit PCI configuration register specified by Address, perform= s a + bitwise AND followed by a bitwise OR between the read result and + the value specified by AndData, and writes the result to the 8-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that al= l PCI + read and write operations are serialized. Extra left bits in both AndDat= a and + OrData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit = and EndBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit a= nd EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit fi= eld. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit fie= ld. + Range 0..7. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciExpressBitFieldAndThenOr8 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 AndData, + IN UINT8 OrData + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + if (IgnoreBusDeviceFunction (Address)) { + return 0xff; + } + return MmioBitFieldAndThenOr8 ( + (UINTN) GetPciExpressBaseAddress () + Address, + StartBit, + EndBit, + AndData, + OrData + ); +} + +/** + Reads a 16-bit PCI configuration register. + + Reads and returns the 16-bit PCI configuration register specified by Add= ress. + This function must guarantee that all PCI read and write operations are + serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Bus, Device, Function a= nd + Register. + + @return The read value from the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciExpressRead16 ( + IN UINTN Address + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + if (IgnoreBusDeviceFunction (Address)) { + return 0xffff; + } + return MmioRead16 ((UINTN) GetPciExpressBaseAddress () + Address); +} + +/** + Writes a 16-bit PCI configuration register. + + Writes the 16-bit PCI configuration register specified by Address with t= he + value specified by Value. Value is returned. This function must guarantee + that all PCI read and write operations are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Bus, Device, Function a= nd + Register. + @param Value The value to write. + + @return The value written to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciExpressWrite16 ( + IN UINTN Address, + IN UINT16 Value + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + if (IgnoreBusDeviceFunction (Address)) { + return 0xffff; + } + return MmioWrite16 ((UINTN) GetPciExpressBaseAddress () + Address, Value= ); +} + +/** + Performs a bitwise OR of a 16-bit PCI configuration register with + a 16-bit value. + + Reads the 16-bit PCI configuration register specified by Address, perfor= ms a + bitwise OR between the read result and the value specified by + OrData, and writes the result to the 16-bit PCI configuration register + specified by Address. The value written to the PCI configuration registe= r is + returned. This function must guarantee that all PCI read and write opera= tions + are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Bus, Device, Function a= nd + Register. + @param OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciExpressOr16 ( + IN UINTN Address, + IN UINT16 OrData + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + if (IgnoreBusDeviceFunction (Address)) { + return 0xffff; + } + return MmioOr16 ((UINTN) GetPciExpressBaseAddress () + Address, OrData); +} + +/** + Performs a bitwise AND of a 16-bit PCI configuration register with a 16-= bit + value. + + Reads the 16-bit PCI configuration register specified by Address, perfor= ms a + bitwise AND between the read result and the value specified by AndData, = and + writes the result to the 16-bit PCI configuration register specified by + Address. The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are + serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Bus, Device, Function a= nd + Register. + @param AndData The value to AND with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciExpressAnd16 ( + IN UINTN Address, + IN UINT16 AndData + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + if (IgnoreBusDeviceFunction (Address)) { + return 0xffff; + } + return MmioAnd16 ((UINTN) GetPciExpressBaseAddress () + Address, AndData= ); +} + +/** + Performs a bitwise AND of a 16-bit PCI configuration register with a 16-= bit + value, followed a bitwise OR with another 16-bit value. + + Reads the 16-bit PCI configuration register specified by Address, perfor= ms a + bitwise AND between the read result and the value specified by AndData, + performs a bitwise OR between the result of the AND operation and + the value specified by OrData, and writes the result to the 16-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that al= l PCI + read and write operations are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Bus, Device, Function a= nd + Register. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciExpressAndThenOr16 ( + IN UINTN Address, + IN UINT16 AndData, + IN UINT16 OrData + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + if (IgnoreBusDeviceFunction (Address)) { + return 0xffff; + } + return MmioAndThenOr16 ( + (UINTN) GetPciExpressBaseAddress () + Address, + AndData, + OrData + ); +} + +/** + Reads a bit field of a PCI configuration register. + + Reads the bit field in a 16-bit PCI configuration register. The bit fiel= d is + specified by the StartBit and the EndBit. The value of the bit field is + returned. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param Address The PCI configuration register to read. + @param StartBit The ordinal of the least significant bit in the bit fi= eld. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit fie= ld. + Range 0..15. + + @return The value of the bit field read from the PCI configuration regis= ter. + +**/ +UINT16 +EFIAPI +PciExpressBitFieldRead16 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + if (IgnoreBusDeviceFunction (Address)) { + return 0xffff; + } + return MmioBitFieldRead16 ( + (UINTN) GetPciExpressBaseAddress () + Address, + StartBit, + EndBit + ); +} + +/** + Writes a bit field to a PCI configuration register. + + Writes Value to the bit field of the PCI configuration register. The bit + field is specified by the StartBit and the EndBit. All other bits in the + destination PCI configuration register are preserved. The new value of t= he + 16-bit register is returned. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If Value is larger than the bitmask value range specified by StartBit an= d EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit fi= eld. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit fie= ld. + Range 0..15. + @param Value The new value of the bit field. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciExpressBitFieldWrite16 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 Value + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + if (IgnoreBusDeviceFunction (Address)) { + return 0xffff; + } + return MmioBitFieldWrite16 ( + (UINTN) GetPciExpressBaseAddress () + Address, + StartBit, + EndBit, + Value + ); +} + +/** + Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, = and + writes the result back to the bit field in the 16-bit port. + + Reads the 16-bit PCI configuration register specified by Address, perfor= ms a + bitwise OR between the read result and the value specified by + OrData, and writes the result to the 16-bit PCI configuration register + specified by Address. The value written to the PCI configuration registe= r is + returned. This function must guarantee that all PCI read and write opera= tions + are serialized. Extra left bits in OrData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit a= nd EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit fi= eld. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit fie= ld. + Range 0..15. + @param OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciExpressBitFieldOr16 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 OrData + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + if (IgnoreBusDeviceFunction (Address)) { + return 0xffff; + } + return MmioBitFieldOr16 ( + (UINTN) GetPciExpressBaseAddress () + Address, + StartBit, + EndBit, + OrData + ); +} + +/** + Reads a bit field in a 16-bit PCI configuration register, performs a bit= wise + AND, and writes the result back to the bit field in the 16-bit register. + + Reads the 16-bit PCI configuration register specified by Address, perfor= ms a + bitwise AND between the read result and the value specified by AndData, = and + writes the result to the 16-bit PCI configuration register specified by + Address. The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are + serialized. Extra left bits in AndData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit = and EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit fi= eld. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit fie= ld. + Range 0..15. + @param AndData The value to AND with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciExpressBitFieldAnd16 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 AndData + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + if (IgnoreBusDeviceFunction (Address)) { + return 0xffff; + } + return MmioBitFieldAnd16 ( + (UINTN) GetPciExpressBaseAddress () + Address, + StartBit, + EndBit, + AndData + ); +} + +/** + Reads a bit field in a 16-bit port, performs a bitwise AND followed by a + bitwise OR, and writes the result back to the bit field in the + 16-bit port. + + Reads the 16-bit PCI configuration register specified by Address, perfor= ms a + bitwise AND followed by a bitwise OR between the read result and + the value specified by AndData, and writes the result to the 16-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that al= l PCI + read and write operations are serialized. Extra left bits in both AndDat= a and + OrData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit = and EndBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit a= nd EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit fi= eld. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit fie= ld. + Range 0..15. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciExpressBitFieldAndThenOr16 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 AndData, + IN UINT16 OrData + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + if (IgnoreBusDeviceFunction (Address)) { + return 0xffff; + } + return MmioBitFieldAndThenOr16 ( + (UINTN) GetPciExpressBaseAddress () + Address, + StartBit, + EndBit, + AndData, + OrData + ); +} + +/** + Reads a 32-bit PCI configuration register. + + Reads and returns the 32-bit PCI configuration register specified by Add= ress. + This function must guarantee that all PCI read and write operations are + serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Bus, Device, Function a= nd + Register. + + @return The read value from the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciExpressRead32 ( + IN UINTN Address + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + if (IgnoreBusDeviceFunction (Address)) { + return 0xffffffff; + } + return MmioRead32 ((UINTN) GetPciExpressBaseAddress () + Address); +} + +/** + Writes a 32-bit PCI configuration register. + + Writes the 32-bit PCI configuration register specified by Address with t= he + value specified by Value. Value is returned. This function must guarantee + that all PCI read and write operations are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Bus, Device, Function a= nd + Register. + @param Value The value to write. + + @return The value written to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciExpressWrite32 ( + IN UINTN Address, + IN UINT32 Value + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + if (IgnoreBusDeviceFunction (Address)) { + return 0xffffffff; + } + return MmioWrite32 ((UINTN) GetPciExpressBaseAddress () + Address, Value= ); +} + +/** + Performs a bitwise OR of a 32-bit PCI configuration register with + a 32-bit value. + + Reads the 32-bit PCI configuration register specified by Address, perfor= ms a + bitwise OR between the read result and the value specified by + OrData, and writes the result to the 32-bit PCI configuration register + specified by Address. The value written to the PCI configuration registe= r is + returned. This function must guarantee that all PCI read and write opera= tions + are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Bus, Device, Function a= nd + Register. + @param OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciExpressOr32 ( + IN UINTN Address, + IN UINT32 OrData + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + if (IgnoreBusDeviceFunction (Address)) { + return 0xffffffff; + } + return MmioOr32 ((UINTN) GetPciExpressBaseAddress () + Address, OrData); +} + +/** + Performs a bitwise AND of a 32-bit PCI configuration register with a 32-= bit + value. + + Reads the 32-bit PCI configuration register specified by Address, perfor= ms a + bitwise AND between the read result and the value specified by AndData, = and + writes the result to the 32-bit PCI configuration register specified by + Address. The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are + serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Bus, Device, Function a= nd + Register. + @param AndData The value to AND with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciExpressAnd32 ( + IN UINTN Address, + IN UINT32 AndData + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + if (IgnoreBusDeviceFunction (Address)) { + return 0xffffffff; + } +return MmioAnd32 ((UINTN) GetPciExpressBaseAddress () + Address, AndData); +} + +/** + Performs a bitwise AND of a 32-bit PCI configuration register with a 32-= bit + value, followed a bitwise OR with another 32-bit value. + + Reads the 32-bit PCI configuration register specified by Address, perfor= ms a + bitwise AND between the read result and the value specified by AndData, + performs a bitwise OR between the result of the AND operation and + the value specified by OrData, and writes the result to the 32-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that al= l PCI + read and write operations are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Bus, Device, Function a= nd + Register. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciExpressAndThenOr32 ( + IN UINTN Address, + IN UINT32 AndData, + IN UINT32 OrData + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + if (IgnoreBusDeviceFunction (Address)) { + return 0xffffffff; + } + return MmioAndThenOr32 ( + (UINTN) GetPciExpressBaseAddress () + Address, + AndData, + OrData + ); +} + +/** + Reads a bit field of a PCI configuration register. + + Reads the bit field in a 32-bit PCI configuration register. The bit fiel= d is + specified by the StartBit and the EndBit. The value of the bit field is + returned. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param Address The PCI configuration register to read. + @param StartBit The ordinal of the least significant bit in the bit fi= eld. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit fie= ld. + Range 0..31. + + @return The value of the bit field read from the PCI configuration regis= ter. + +**/ +UINT32 +EFIAPI +PciExpressBitFieldRead32 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + if (IgnoreBusDeviceFunction (Address)) { + return 0xffffffff; + } + return MmioBitFieldRead32 ( + (UINTN) GetPciExpressBaseAddress () + Address, + StartBit, + EndBit + ); +} + +/** + Writes a bit field to a PCI configuration register. + + Writes Value to the bit field of the PCI configuration register. The bit + field is specified by the StartBit and the EndBit. All other bits in the + destination PCI configuration register are preserved. The new value of t= he + 32-bit register is returned. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If Value is larger than the bitmask value range specified by StartBit an= d EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit fi= eld. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit fie= ld. + Range 0..31. + @param Value The new value of the bit field. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciExpressBitFieldWrite32 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 Value + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + if (IgnoreBusDeviceFunction (Address)) { + return 0xffffffff; + } + return MmioBitFieldWrite32 ( + (UINTN) GetPciExpressBaseAddress () + Address, + StartBit, + EndBit, + Value + ); +} + +/** + Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, = and + writes the result back to the bit field in the 32-bit port. + + Reads the 32-bit PCI configuration register specified by Address, perfor= ms a + bitwise OR between the read result and the value specified by + OrData, and writes the result to the 32-bit PCI configuration register + specified by Address. The value written to the PCI configuration registe= r is + returned. This function must guarantee that all PCI read and write opera= tions + are serialized. Extra left bits in OrData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit a= nd EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit fi= eld. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit fie= ld. + Range 0..31. + @param OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciExpressBitFieldOr32 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 OrData + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + if (IgnoreBusDeviceFunction (Address)) { + return 0xffffffff; + } + return MmioBitFieldOr32 ( + (UINTN) GetPciExpressBaseAddress () + Address, + StartBit, + EndBit, + OrData + ); +} + +/** + Reads a bit field in a 32-bit PCI configuration register, performs a bit= wise + AND, and writes the result back to the bit field in the 32-bit register. + + Reads the 32-bit PCI configuration register specified by Address, perfor= ms a + bitwise AND between the read result and the value specified by AndData, = and + writes the result to the 32-bit PCI configuration register specified by + Address. The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are + serialized. Extra left bits in AndData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit = and EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit fi= eld. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit fie= ld. + Range 0..31. + @param AndData The value to AND with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciExpressBitFieldAnd32 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 AndData + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + if (IgnoreBusDeviceFunction (Address)) { + return 0xffffffff; + } + return MmioBitFieldAnd32 ( + (UINTN) GetPciExpressBaseAddress () + Address, + StartBit, + EndBit, + AndData + ); +} + +/** + Reads a bit field in a 32-bit port, performs a bitwise AND followed by a + bitwise OR, and writes the result back to the bit field in the + 32-bit port. + + Reads the 32-bit PCI configuration register specified by Address, perfor= ms a + bitwise AND followed by a bitwise OR between the read result and + the value specified by AndData, and writes the result to the 32-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that al= l PCI + read and write operations are serialized. Extra left bits in both AndDat= a and + OrData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit = and EndBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit a= nd EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit fi= eld. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit fie= ld. + Range 0..31. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciExpressBitFieldAndThenOr32 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 AndData, + IN UINT32 OrData + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + if (IgnoreBusDeviceFunction (Address)) { + return 0xffffffff; + } + return MmioBitFieldAndThenOr32 ( + (UINTN) GetPciExpressBaseAddress () + Address, + StartBit, + EndBit, + AndData, + OrData + ); +} + +/** + Reads a range of PCI configuration registers into a caller supplied buff= er. + + Reads the range of PCI configuration registers specified by StartAddress= and + Size into the buffer specified by Buffer. This function only allows the = PCI + configuration registers from a single PCI function to be read. Size is + returned. When possible 32-bit PCI configuration read cycles are used to= read + from StartAddress to StartAddress + Size. Due to alignment restrictions,= 8-bit + and 16-bit PCI configuration read cycles may be used at the beginning an= d the + end of the range. + + If StartAddress > 0x0FFFFFFF, then ASSERT(). + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). + If Size > 0 and Buffer is NULL, then ASSERT(). + + @param StartAddress The starting address that encodes the PCI Bus, Dev= ice, + Function and Register. + @param Size The size in bytes of the transfer. + @param Buffer The pointer to a buffer receiving the data read. + + @return Size read data from StartAddress. + +**/ +UINTN +EFIAPI +PciExpressReadBuffer ( + IN UINTN StartAddress, + IN UINTN Size, + OUT VOID *Buffer + ) +{ + UINTN ReturnValue; + + ASSERT_INVALID_PCI_ADDRESS (StartAddress); + ASSERT (((StartAddress & 0xFFF) + Size) <=3D 0x1000); + + if (Size =3D=3D 0) { + return Size; + } + + ASSERT (Buffer !=3D NULL); + + // + // Save Size for return + // + ReturnValue =3D Size; + + if ((StartAddress & 1) !=3D 0) { + // + // Read a byte if StartAddress is byte aligned + // + *(volatile UINT8 *)Buffer =3D PciExpressRead8 (StartAddress); + StartAddress +=3D sizeof (UINT8); + Size -=3D sizeof (UINT8); + Buffer =3D (UINT8*)Buffer + 1; + } + + if (Size >=3D sizeof (UINT16) && (StartAddress & 2) !=3D 0) { + // + // Read a word if StartAddress is word aligned + // + WriteUnaligned16 ((UINT16 *) Buffer, (UINT16) PciExpressRead16 (StartA= ddress)); + + StartAddress +=3D sizeof (UINT16); + Size -=3D sizeof (UINT16); + Buffer =3D (UINT16*)Buffer + 1; + } + + while (Size >=3D sizeof (UINT32)) { + // + // Read as many double words as possible + // + WriteUnaligned32 ((UINT32 *) Buffer, (UINT32) PciExpressRead32 (StartA= ddress)); + + StartAddress +=3D sizeof (UINT32); + Size -=3D sizeof (UINT32); + Buffer =3D (UINT32*)Buffer + 1; + } + + if (Size >=3D sizeof (UINT16)) { + // + // Read the last remaining word if exist + // + WriteUnaligned16 ((UINT16 *) Buffer, (UINT16) PciExpressRead16 (StartA= ddress)); + StartAddress +=3D sizeof (UINT16); + Size -=3D sizeof (UINT16); + Buffer =3D (UINT16*)Buffer + 1; + } + + if (Size >=3D sizeof (UINT8)) { + // + // Read the last remaining byte if exist + // + *(volatile UINT8 *)Buffer =3D PciExpressRead8 (StartAddress); + } + + return ReturnValue; +} + +/** + Copies the data in a caller supplied buffer to a specified range of PCI + configuration space. + + Writes the range of PCI configuration registers specified by StartAddres= s and + Size from the buffer specified by Buffer. This function only allows the = PCI + configuration registers from a single PCI function to be written. Size is + returned. When possible 32-bit PCI configuration write cycles are used to + write from StartAddress to StartAddress + Size. Due to alignment restric= tions, + 8-bit and 16-bit PCI configuration write cycles may be used at the begin= ning + and the end of the range. + + If StartAddress > 0x0FFFFFFF, then ASSERT(). + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). + If Size > 0 and Buffer is NULL, then ASSERT(). + + @param StartAddress The starting address that encodes the PCI Bus, Dev= ice, + Function and Register. + @param Size The size in bytes of the transfer. + @param Buffer The pointer to a buffer containing the data to wri= te. + + @return Size written to StartAddress. + +**/ +UINTN +EFIAPI +PciExpressWriteBuffer ( + IN UINTN StartAddress, + IN UINTN Size, + IN VOID *Buffer + ) +{ + UINTN ReturnValue; + + ASSERT_INVALID_PCI_ADDRESS (StartAddress); + ASSERT (((StartAddress & 0xFFF) + Size) <=3D 0x1000); + + if (Size =3D=3D 0) { + return 0; + } + + ASSERT (Buffer !=3D NULL); + + // + // Save Size for return + // + ReturnValue =3D Size; + + if ((StartAddress & 1) !=3D 0) { + // + // Write a byte if StartAddress is byte aligned + // + PciExpressWrite8 (StartAddress, *(UINT8*)Buffer); + StartAddress +=3D sizeof (UINT8); + Size -=3D sizeof (UINT8); + Buffer =3D (UINT8*)Buffer + 1; + } + + if (Size >=3D sizeof (UINT16) && (StartAddress & 2) !=3D 0) { + // + // Write a word if StartAddress is word aligned + // + PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer)); + StartAddress +=3D sizeof (UINT16); + Size -=3D sizeof (UINT16); + Buffer =3D (UINT16*)Buffer + 1; + } + + while (Size >=3D sizeof (UINT32)) { + // + // Write as many double words as possible + // + PciExpressWrite32 (StartAddress, ReadUnaligned32 ((UINT32*)Buffer)); + StartAddress +=3D sizeof (UINT32); + Size -=3D sizeof (UINT32); + Buffer =3D (UINT32*)Buffer + 1; + } + + if (Size >=3D sizeof (UINT16)) { + // + // Write the last remaining word if exist + // + PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer)); + StartAddress +=3D sizeof (UINT16); + Size -=3D sizeof (UINT16); + Buffer =3D (UINT16*)Buffer + 1; + } + + if (Size >=3D sizeof (UINT8)) { + // + // Write the last remaining byte if exist + // + PciExpressWrite8 (StartAddress, *(UINT8*)Buffer); + } + + return ReturnValue; +} --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id l25sm276668lfk.57.2019.05.09.02.54.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 09 May 2019 02:54:03 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com, Jici.Gao@arm.com, rebecca@bluestop.org, kettenis@jive.eu Subject: [edk2-devel] [edk2-platforms: PATCH 07/14] Marvell/Armada7k8k: Implement PciHostBridgeLib Date: Thu, 9 May 2019 11:53:35 +0200 Message-Id: <1557395622-32425-8-git-send-email-mw@semihalf.com> In-Reply-To: <1557395622-32425-1-git-send-email-mw@semihalf.com> References: <1557395622-32425-1-git-send-email-mw@semihalf.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1557395647; bh=AQH0pSn2ofZkUtYOihi5wrS5rVA88z3FBfYN0X6PSts=; h=Cc:Date:From:Reply-To:Subject:To; b=kxp4P4O0hKGmKZZ7Uw4F3xuX2rkE6fe0m65/rKf5NGdsPAHClyoz0QNw3zIegFWCPOr laO98xib0I2iyqaWJRSGgm2Fg6fAb6aFRLcmG2poF/8n9Zot7TSeOMON3X66brbfgTlNK nD0BK7OjVrn3LIE8JrVMm01XCNDdzIX74QY= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add an implementation of the PciHostBridgeLib glue library that describes the PCIe RC on this SoC so that the generic PCI host bridge driver can attach to it. This includes a constructor which performs the SoC specific init and training sequences. This patch is based on work of Ard Biesheuvel and Jing Hua / Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridg= eLib.inf | 52 +++ Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridg= eLibConstructor.h | 95 ++++++ Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridg= eLib.c | 244 +++++++++++++++ Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridg= eLibConstructor.c | 330 ++++++++++++++++++++ 4 files changed, 721 insertions(+) create mode 100644 Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBri= dgeLib/PciHostBridgeLib.inf create mode 100644 Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBri= dgeLib/PciHostBridgeLibConstructor.h create mode 100644 Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBri= dgeLib/PciHostBridgeLib.c create mode 100644 Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBri= dgeLib/PciHostBridgeLibConstructor.c diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/= PciHostBridgeLib.inf b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHost= BridgeLib/PciHostBridgeLib.inf new file mode 100644 index 0000000..e46f71d --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHost= BridgeLib.inf @@ -0,0 +1,52 @@ +## @file +# PCI Host Bridge Library instance for Marvell Armada 7k/8k SOC +# +# Copyright (c) 2017, Linaro Ltd. All rights reserved.
+# Copyright (c) 2019 Marvell International Ltd. All rights reserved.
+# +# This program and the accompanying materials are licensed and made avail= able +# under the terms and conditions of the BSD License which accompanies this +# distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR +# IMPLIED. +# +# +## + +[Defines] + INF_VERSION =3D 0x0001001B + BASE_NAME =3D Armada7k8kPciHostBridgeLib + FILE_GUID =3D 7f989c9d-02a0-4348-8aeb-ab2e1566fb18 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D PciHostBridgeLib|DXE_DRIVER + CONSTRUCTOR =3D Armada7k8kPciHostBridgeLibConstructor + +[Sources] + PciHostBridgeLib.c + PciHostBridgeLibConstructor.c + +[Packages] + ArmPkg/ArmPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Marvell/Marvell.dec + +[LibraryClasses] + ArmLib + ArmadaSoCDescLib + DebugLib + DevicePathLib + MemoryAllocationLib + MvGpioLib + UefiBootServicesTableLib + +[Protocols] + gEmbeddedGpioProtocolGuid + gMarvellBoardDescProtocolGuid + +[Depex] + gMarvellPlatformInitCompleteProtocolGuid diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/= PciHostBridgeLibConstructor.h b/Silicon/Marvell/Armada7k8k/Library/Armada7k= 8kPciHostBridgeLib/PciHostBridgeLibConstructor.h new file mode 100644 index 0000000..ff9d919 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHost= BridgeLibConstructor.h @@ -0,0 +1,95 @@ +/** @file + PCI Host Bridge Library instance for Marvell 70x0/80x0 + + Copyright (c) 2017, Linaro Ltd. All rights reserved.
+ Copyright (c) 2019 Marvell International Ltd. All rights reserved.
+ + This program and the accompanying materials are licensed and made availa= ble + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WI= THOUT + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef __PCI_HOST_BRIDGE_LIB_CONSTRUCTOR_H__ +#define __PCI_HOST_BRIDGE_LIB_CONSTRUCTOR_H__ + +#define IATU_VIEWPORT_OFF 0x900 +#define IATU_VIEWPORT_INBOUND BIT31 +#define IATU_VIEWPORT_OUTBOUND 0 +#define IATU_VIEWPORT_REGION_INDEX(Idx) ((Idx) & 7) + +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0 0x904 +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM 0x0 +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_IO 0x2 +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG0 0x4 +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG1 0x5 + +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0 0x908 +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN BIT31 +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE BIT28 + +#define IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0 0x90C +#define IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0 0x910 +#define IATU_LIMIT_ADDR_OFF_OUTBOUND_0 0x914 +#define IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0 0x918 +#define IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0 0x91C + +#define PORT_LINK_CTRL_OFF 0x710 +#define PORT_LINK_CTRL_OFF_LINK_CAPABLE_x1 (0x01 << 16) +#define PORT_LINK_CTRL_OFF_LINK_CAPABLE_x2 (0x03 << 16) +#define PORT_LINK_CTRL_OFF_LINK_CAPABLE_x4 (0x07 << 16) +#define PORT_LINK_CTRL_OFF_LINK_CAPABLE_x8 (0x0f << 16) +#define PORT_LINK_CTRL_OFF_LINK_CAPABLE_x16 (0x1f << 16) +#define PORT_LINK_CTRL_OFF_LINK_CAPABLE_MASK (0x3f << 16) + +#define GEN2_CTRL_OFF 0x80c +#define GEN2_CTRL_OFF_NUM_OF_LANES(n) (((n) & 0x1f) = << 8) +#define GEN2_CTRL_OFF_NUM_OF_LANES_MASK (0x1f << 8) +#define GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE BIT17 + +#define PCIE_GLOBAL_CTRL_OFFSET 0x8000 +#define PCIE_GLOBAL_APP_LTSSM_EN BIT2 +#define PCIE_GLOBAL_CTRL_DEVICE_TYPE_RC (0x4 << 4) +#define PCIE_GLOBAL_CTRL_DEVICE_TYPE_MASK (0xF << 4) + +#define PCIE_GLOBAL_STATUS_REG 0x8008 +#define PCIE_GLOBAL_STATUS_RDLH_LINK_UP BIT1 +#define PCIE_GLOBAL_STATUS_PHY_LINK_UP BIT9 + +#define PCIE_PM_STATUS 0x8014 +#define PCIE_PM_LTSSM_STAT_MASK (0x3f << 3) + +#define PCIE_GLOBAL_INT_MASK1_REG 0x8020 +#define PCIE_INT_A_ASSERT_MASK BIT9 +#define PCIE_INT_B_ASSERT_MASK BIT10 +#define PCIE_INT_C_ASSERT_MASK BIT11 +#define PCIE_INT_D_ASSERT_MASK BIT12 + +#define PCIE_ARCACHE_TRC_REG 0x8050 +#define PCIE_AWCACHE_TRC_REG 0x8054 +#define PCIE_ARUSER_REG 0x805C +#define PCIE_AWUSER_REG 0x8060 + +#define ARCACHE_DEFAULT_VALUE 0x3511 +#define AWCACHE_DEFAULT_VALUE 0x5311 + +#define AX_USER_DOMAIN_INNER_SHAREABLE (0x1 << 4) +#define AX_USER_DOMAIN_OUTER_SHAREABLE (0x2 << 4) +#define AX_USER_DOMAIN_MASK (0x3 << 4) + +#define PCIE_LINK_CAPABILITY 0x7C +#define PCIE_LINK_CTL_2 0xA0 +#define TARGET_LINK_SPEED_MASK 0xF +#define LINK_SPEED_GEN_1 0x1 +#define LINK_SPEED_GEN_2 0x2 +#define LINK_SPEED_GEN_3 0x3 + +#define PCIE_GEN3_EQU_CTRL 0x8A8 +#define GEN3_EQU_EVAL_2MS_DISABLE BIT5 + +#define PCIE_LINK_UP_TIMEOUT_US 40000 + +#endif diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/= PciHostBridgeLib.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBr= idgeLib/PciHostBridgeLib.c new file mode 100644 index 0000000..ff6288c --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHost= BridgeLib.c @@ -0,0 +1,244 @@ +/** @file + PCI Host Bridge Library instance for Marvell Armada 70x0/80x0 + + Copyright (c) 2017, Linaro Ltd. All rights reserved.
+ Copyright (c) 2019 Marvell International Ltd. All rights reserved.
+ + This program and the accompanying materials are licensed and made availa= ble + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WI= THOUT + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#pragma pack(1) +typedef struct { + ACPI_HID_DEVICE_PATH AcpiDevicePath; + EFI_DEVICE_PATH_PROTOCOL EndDevicePath; +} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH; +#pragma pack () + +STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath =3D { + { + { + ACPI_DEVICE_PATH, + ACPI_DP, + { + (UINT8) (sizeof (ACPI_HID_DEVICE_PATH)), + (UINT8) ((sizeof (ACPI_HID_DEVICE_PATH)) >> 8) + } + }, + EISA_PNP_ID(0x0A08), // PCI Express + 0 + }, + + { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { + END_DEVICE_PATH_LENGTH, + 0 + } + } +}; + +GLOBAL_REMOVE_IF_UNREFERENCED +CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] =3D { + L"Mem", L"I/O", L"Bus" +}; + +/** + Return all the root bridge instances in an array. + + @param Count Return the count of root bridge instances. + + @return All the root bridge instances in an array. + The array should be passed into PciHostBridgeFreeRootBridges() + when it's not used. + +**/ +PCI_ROOT_BRIDGE * +EFIAPI +PciHostBridgeGetRootBridges ( + UINTN *Count + ) +{ + MARVELL_BOARD_DESC_PROTOCOL *BoardDescriptionProtocol; + MV_BOARD_PCIE_DESCRIPTION *BoardPcieDescription; + MV_PCIE_CONTROLLER *PcieController; + PCI_ROOT_BRIDGE *PciRootBridges; + PCI_ROOT_BRIDGE *RootBridge; + EFI_STATUS Status; + UINTN Index; + + *Count =3D 0; + + /* Obtain list of available controllers */ + Status =3D gBS->LocateProtocol (&gMarvellBoardDescProtocolGuid, + NULL, + (VOID **)&BoardDescriptionProtocol); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, + "%a: Cannot locate BoardDesc protocol\n", + __FUNCTION__)); + return NULL; + } + + Status =3D BoardDescriptionProtocol->PcieDescriptionGet ( + BoardDescriptionProtocol, + &BoardPcieDescription); + if (Status =3D=3D EFI_NOT_FOUND) { + /* No controllers used on the platform, exit silently */ + return NULL; + } else if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, + "%a: Cannot get Pcie board desc from BoardDesc protocol\n", + __FUNCTION__)); + return NULL; + } + + /* Assign return values */ + PciRootBridges =3D AllocateZeroPool (BoardPcieDescription->PcieControlle= rCount * + sizeof (PCI_ROOT_BRIDGE)); + if (PciRootBridges =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Fail to allocate resources\n", __FUNCTION__)= ); + return NULL; + } + + *Count =3D BoardPcieDescription->PcieControllerCount; + RootBridge =3D PciRootBridges; + + /* Fill information of all root bridge instances */ + for (Index =3D 0; Index < *Count; Index++, RootBridge++) { + + PcieController =3D &(BoardPcieDescription->PcieControllers[Index]); + + RootBridge->Segment =3D 0; + RootBridge->Supports =3D 0; + RootBridge->Attributes =3D RootBridge->Supports; + + RootBridge->DmaAbove4G =3D FALSE; + + RootBridge->AllocationAttributes =3D EFI_PCI_HOST_BRIDGE_COMBINE_MEM_= PMEM | + EFI_PCI_HOST_BRIDGE_MEM64_DECODE; + + RootBridge->Bus.Base =3D PcieController->PcieBusMin; + RootBridge->Bus.Limit =3D PcieController->PcieBusMax; + RootBridge->Io.Base =3D PcieController->PcieIoWinBase; + RootBridge->Io.Limit =3D PcieController->PcieIoWinBase + + PcieController->PcieIoWinSize - 1; + RootBridge->Mem.Base =3D PcieController->PcieMmio32WinBase; + RootBridge->Mem.Limit =3D PcieController->PcieMmio32WinBase + + PcieController->PcieMmio32WinSize - 1; + RootBridge->MemAbove4G.Base =3D PcieController->PcieMmio64WinBase; + RootBridge->MemAbove4G.Limit =3D PcieController->PcieMmio64WinBase + + PcieController->PcieMmio64WinSize - 1; + + /* No separate ranges for prefetchable and non-prefetchable BARs */ + RootBridge->PMem.Base =3D MAX_UINT64; + RootBridge->PMem.Limit =3D 0; + RootBridge->PMemAbove4G.Base =3D MAX_UINT64; + RootBridge->PMemAbove4G.Limit =3D 0; + + ASSERT (PcieController->PcieMmio64Translation =3D=3D 0); + ASSERT (PcieController->PcieMmio32Translation =3D=3D 0); + + RootBridge->NoExtendedConfigSpace =3D FALSE; + + RootBridge->DevicePath =3D (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBri= dgeDevicePath; + } + + return PciRootBridges; +} + +/** + Free the root bridge instances array returned from PciHostBridgeGetRootB= ridges(). + + @param Bridges The root bridge instances array. + @param Count The count of the array. + +**/ +VOID +EFIAPI +PciHostBridgeFreeRootBridges ( + PCI_ROOT_BRIDGE *Bridges, + UINTN Count + ) +{ + FreePool (Bridges); +} + +/** + Inform the platform that the resource conflict happens. + + @param HostBridgeHandle Handle of the Host Bridge. + @param Configuration Pointer to PCI I/O and PCI memory resource + descriptors. The Configuration contains the reso= urces + for all the root bridges. The resource for each = root + bridge is terminated with END descriptor and an + additional END is appended indicating the end of= the + entire resources. The resource descriptor field + values follow the description in + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL + .SubmitResources(). + +**/ +VOID +EFIAPI +PciHostBridgeResourceConflict ( + EFI_HANDLE HostBridgeHandle, + VOID *Configuration + ) +{ + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor; + UINTN RootBridgeIndex; + + DEBUG ((DEBUG_ERROR, "PciHostBridge: Resource conflict happens!\n")); + + RootBridgeIndex =3D 0; + Descriptor =3D (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration; + + while (Descriptor->Desc =3D=3D ACPI_ADDRESS_SPACE_DESCRIPTOR) { + + DEBUG ((DEBUG_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++)); + + for (; Descriptor->Desc =3D=3D ACPI_ADDRESS_SPACE_DESCRIPTOR; Descript= or++) { + ASSERT (Descriptor->ResType < + (sizeof (mPciHostBridgeLibAcpiAddressSpaceTypeStr) / + sizeof (mPciHostBridgeLibAcpiAddressSpaceTypeStr[0]))); + + DEBUG ((DEBUG_ERROR, + " %s: Length/Alignment =3D 0x%lx / 0x%lx\n", + mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType], + Descriptor->AddrLen, Descriptor->AddrRangeMax)); + + if (Descriptor->ResType =3D=3D ACPI_ADDRESS_SPACE_TYPE_MEM) { + DEBUG ((DEBUG_ERROR, + " Granularity/SpecificFlag =3D %ld / %02x%s\n", + Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag, + ((Descriptor->SpecificFlag & + EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE)= !=3D 0) ? + L" (Prefetchable)" : L"")); + } + } + /* Skip the END descriptor for root bridge */ + ASSERT (Descriptor->Desc =3D=3D ACPI_END_TAG_DESCRIPTOR); + Descriptor =3D (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)( + (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1); + } +} diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/= PciHostBridgeLibConstructor.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k= 8kPciHostBridgeLib/PciHostBridgeLibConstructor.c new file mode 100644 index 0000000..ced2c12 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHost= BridgeLibConstructor.c @@ -0,0 +1,330 @@ +/** @file + PCI Host Bridge Library instance for Marvell 70x0/80x0 + + Copyright (c) 2017, Linaro Ltd. All rights reserved.
+ Copyright (c) 2019 Marvell International Ltd. All rights reserved.
+ + This program and the accompanying materials are licensed and made availa= ble + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WI= THOUT + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include + +#include + +#include +#include +#include +#include +#include + +#include + +#include "PciHostBridgeLibConstructor.h" + +/** + This function configures PCIE controllers IATU windows. + + @param [in] PcieBaseAddress PCIE controller base address. + @param [in] Index IATU window index. + @param [in] CpuBase Address from the CPU perspective. + @param [in] PciBase Target PCIE address. + @param [in] Size IATU window size. + @param [in] Type IATU window type. + @param [in] EnableFlags Extra configuration flags. + + @retval none + +**/ +STATIC +VOID +ConfigureWindow ( + IN EFI_PHYSICAL_ADDRESS PcieBaseAddress, + IN UINTN Index, + IN UINT64 CpuBase, + IN UINT64 PciBase, + IN UINT64 Size, + IN UINTN Type, + IN UINTN EnableFlags + ) +{ + ArmDataMemoryBarrier (); + + MmioWrite32 (PcieBaseAddress + IATU_VIEWPORT_OFF, + IATU_VIEWPORT_OUTBOUND | IATU_VIEWPORT_REGION_INDEX (Index)); + + ArmDataMemoryBarrier (); + + MmioWrite32 (PcieBaseAddress + IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0, + (UINT32)(CpuBase & 0xFFFFFFFF)); + MmioWrite32 (PcieBaseAddress + IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0, + (UINT32)(CpuBase >> 32)); + MmioWrite32 (PcieBaseAddress + IATU_LIMIT_ADDR_OFF_OUTBOUND_0, + (UINT32)(CpuBase + Size - 1)); + MmioWrite32 (PcieBaseAddress + IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0, + (UINT32)(PciBase & 0xFFFFFFFF)); + MmioWrite32 (PcieBaseAddress + IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0, + (UINT32)(PciBase >> 32)); + MmioWrite32 (PcieBaseAddress + IATU_REGION_CTRL_1_OFF_OUTBOUND_0, + Type); + MmioWrite32 (PcieBaseAddress + IATU_REGION_CTRL_2_OFF_OUTBOUND_0, + IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN | EnableFlags); +} + +/** + Perform PCIE slot reset using external GPIO pin. + + @param [in] PcieBaseAddress PCIE controller base address. + + @retval none + +**/ +STATIC +VOID +WaitForLink ( + IN EFI_PHYSICAL_ADDRESS PcieBaseAddress + ) +{ + UINT32 Mask; + UINT32 Status; + UINT32 Timeout; + + if (!(MmioRead32 (PcieBaseAddress + PCIE_PM_STATUS) & PCIE_PM_LTSSM_STAT= _MASK)) { + DEBUG ((DEBUG_INIT, "%a: no PCIE device detected\n", __FUNCTION__)); + return; + } + + /* Wait for the link to establish itself */ + DEBUG ((DEBUG_INIT, "%a: waiting for PCIE link\n", __FUNCTION__)); + + Mask =3D PCIE_GLOBAL_STATUS_RDLH_LINK_UP | PCIE_GLOBAL_STATUS_PHY_LINK_U= P; + Timeout =3D PCIE_LINK_UP_TIMEOUT_US / 10; + do { + Status =3D MmioRead32 (PcieBaseAddress + PCIE_GLOBAL_STATUS_REG); + if ((Status & Mask) =3D=3D Mask) { + DEBUG ((DEBUG_ERROR, "pcie@0x%x link UP\n", PcieBaseAddress)); + break; + } + gBS->Stall (10); + } while (Timeout--); +} + +/** + Perform PCIE slot reset using external GPIO pin. + + @param [in] *PcieResetGpio GPIO pin description. + + @retval EFI_SUCEESS PCIE slot reset succeeded. + @retval Other Return error status. + +**/ +STATIC +EFI_STATUS +ResetPcieSlot ( + IN MV_GPIO_PIN *PcieResetGpio + ) +{ + EMBEDDED_GPIO_MODE Mode; + EMBEDDED_GPIO_PIN GpioPin; + EMBEDDED_GPIO *GpioProtocol; + EFI_STATUS Status; + + /* Get GPIO protocol */ + Status =3D MvGpioGetProtocol (PcieResetGpio->ControllerType, &GpioProtoc= ol); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Unable to find GPIO protocol\n", __FUNCTION_= _)); + return Status; + } + + GpioPin =3D GPIO (PcieResetGpio->ControllerId, PcieResetGpio->PinNumber), + + /* Reset the slot by toggling the GPIO pin */ + Mode =3D PcieResetGpio->ActiveHigh ? GPIO_MODE_OUTPUT_1 : GPIO_MODE_OUTP= UT_0; + Status =3D GpioProtocol->Set (GpioProtocol, GpioPin, Mode); + gBS->Stall (10 * 1000); + + Mode =3D PcieResetGpio->ActiveHigh ? GPIO_MODE_OUTPUT_0 : GPIO_MODE_OUTP= UT_1; + Status =3D GpioProtocol->Set (GpioProtocol, GpioPin, Mode); + gBS->Stall (20 * 1000); + + return EFI_SUCCESS; +} + +/** + Obtain resources and perform a low-level PCIE controllers + configuration. + + @param [in] ImageHandle The image handle. + @param [in] *SystemTable The system table. + + @retval EFI_SUCEESS PCIE configuration successful. + @retval Other Return error status. + +**/ +EFI_STATUS +EFIAPI +Armada7k8kPciHostBridgeLibConstructor ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + MARVELL_BOARD_DESC_PROTOCOL *BoardDescriptionProtocol; + MV_BOARD_PCIE_DESCRIPTION *BoardPcieDescription; + MV_PCIE_CONTROLLER *PcieController; + EFI_PHYSICAL_ADDRESS PcieBaseAddress; + EFI_STATUS Status; + UINTN Index; + + /* Obtain list of available controllers */ + Status =3D gBS->LocateProtocol (&gMarvellBoardDescProtocolGuid, + NULL, + (VOID **)&BoardDescriptionProtocol); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, + "%a: Cannot locate BoardDesc protocol\n", + __FUNCTION__)); + return EFI_DEVICE_ERROR; + } + + Status =3D BoardDescriptionProtocol->PcieDescriptionGet ( + BoardDescriptionProtocol, + &BoardPcieDescription); + if (Status =3D=3D EFI_NOT_FOUND) { + /* No controllers used on the platform, exit silently */ + return EFI_SUCCESS; + } else if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, + "%a: Cannot get Pcie board desc from BoardDesc protocol\n", + __FUNCTION__)); + return EFI_DEVICE_ERROR; + } + + for (Index =3D 0; Index < BoardPcieDescription->PcieControllerCount; Ind= ex++) { + + PcieController =3D &(BoardPcieDescription->PcieControllers[Index]); + + ASSERT (PcieController->PcieBusMin =3D=3D 0); + ASSERT (PcieController->ConfigSpaceAddress % SIZE_256MB =3D=3D 0); + + if (PcieController->HaveResetGpio =3D=3D TRUE) { + /* Reset PCIE slot */ + Status =3D ResetPcieSlot (&PcieController->PcieResetGpio); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, + "%a: Cannot reset Pcie Slot\n", + __FUNCTION__)); + return EFI_DEVICE_ERROR; + } + } + + /* Low level PCIE controller configuration */ + PcieBaseAddress =3D PcieController->PcieBaseAddress; + + MmioAndThenOr32 (PcieBaseAddress + PORT_LINK_CTRL_OFF, + ~PORT_LINK_CTRL_OFF_LINK_CAPABLE_MASK, + PORT_LINK_CTRL_OFF_LINK_CAPABLE_x4); + + MmioAndThenOr32 (PcieBaseAddress + GEN2_CTRL_OFF, + ~GEN2_CTRL_OFF_NUM_OF_LANES_MASK, + GEN2_CTRL_OFF_NUM_OF_LANES(4) | GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE); + + MmioAndThenOr32 (PcieBaseAddress + PCIE_GLOBAL_CTRL_OFFSET, + ~(PCIE_GLOBAL_CTRL_DEVICE_TYPE_MASK | PCIE_GLOBAL_APP_LTSSM_EN), + PCIE_GLOBAL_CTRL_DEVICE_TYPE_RC); + + MmioWrite32 (PcieBaseAddress + PCIE_ARCACHE_TRC_REG, + ARCACHE_DEFAULT_VALUE); + + MmioWrite32 (PcieBaseAddress + PCIE_AWCACHE_TRC_REG, + AWCACHE_DEFAULT_VALUE); + + MmioAndThenOr32 (PcieBaseAddress + PCIE_ARUSER_REG, + ~AX_USER_DOMAIN_MASK, + AX_USER_DOMAIN_OUTER_SHAREABLE); + + MmioAndThenOr32 (PcieBaseAddress + PCIE_AWUSER_REG, + ~AX_USER_DOMAIN_MASK, + AX_USER_DOMAIN_OUTER_SHAREABLE); + + MmioAndThenOr32 (PcieBaseAddress + PCIE_LINK_CTL_2, + ~TARGET_LINK_SPEED_MASK, + LINK_SPEED_GEN_3); + + MmioAndThenOr32 (PcieBaseAddress + PCIE_LINK_CAPABILITY, + ~TARGET_LINK_SPEED_MASK, + LINK_SPEED_GEN_3); + + MmioOr32 (PcieBaseAddress + PCIE_GEN3_EQU_CTRL, + GEN3_EQU_EVAL_2MS_DISABLE); + + MmioOr32 (PcieBaseAddress + PCIE_GLOBAL_CTRL_OFFSET, + PCIE_GLOBAL_APP_LTSSM_EN); + + /* Region 0: MMIO32 range */ + ConfigureWindow (PcieBaseAddress, + 0, + PcieController->PcieMmio32WinBase, + PcieController->PcieMmio32WinBase, + PcieController->PcieMmio32WinSize, + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM, + 0); + + /* Region 1: Type 0 config space */ + ConfigureWindow (PcieBaseAddress, + 1, + PcieController->ConfigSpaceAddress, + 0x0, + SIZE_64KB, + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG0, + IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE); + + /* Region 2: Type 1 config space */ + ConfigureWindow (PcieBaseAddress, + 2, + PcieController->ConfigSpaceAddress + SIZE_64KB, + 0x0, + PcieController->PcieBusMax * SIZE_1MB, + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG1, + IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE); + + /* Region 3: port I/O range */ + ConfigureWindow (PcieBaseAddress, + 3, + PcieController->PcieIoTranslation, + PcieController->PcieIoWinBase, + PcieController->PcieIoWinSize, + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_IO, + 0); + + /* Region 4: MMIO64 range */ + ConfigureWindow (PcieBaseAddress, + 4, + PcieController->PcieMmio64WinBase, + PcieController->PcieMmio64WinBase, + PcieController->PcieMmio64WinSize, + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM, + 0); + + MmioOr32 (PcieBaseAddress + PCIE_GLOBAL_INT_MASK1_REG, + PCIE_INT_A_ASSERT_MASK | + PCIE_INT_B_ASSERT_MASK | + PCIE_INT_C_ASSERT_MASK | + PCIE_INT_D_ASSERT_MASK); + + WaitForLink (PcieBaseAddress); + + /* Enable the RC */ + MmioOr32 (PcieBaseAddress + PCI_COMMAND_OFFSET, + EFI_PCI_COMMAND_IO_SPACE | + EFI_PCI_COMMAND_MEMORY_SPACE | + EFI_PCI_COMMAND_BUS_MASTER); + } + + return EFI_SUCCESS; +} --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id l25sm276668lfk.57.2019.05.09.02.54.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 09 May 2019 02:54:05 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com, Jici.Gao@arm.com, rebecca@bluestop.org, kettenis@jive.eu Subject: [edk2-devel] [edk2-platforms: PATCH 08/14] Marvell/Armada7k8k: Enable PCIE support Date: Thu, 9 May 2019 11:53:36 +0200 Message-Id: <1557395622-32425-9-git-send-email-mw@semihalf.com> In-Reply-To: <1557395622-32425-1-git-send-email-mw@semihalf.com> References: <1557395622-32425-1-git-send-email-mw@semihalf.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1557395649; bh=4LI6lh1FBuo+EkvwYWLYe8K2ry/fE1fJahEuKRot8+4=; h=Cc:Date:From:Reply-To:Subject:To; b=DoX3GI/MnMTXPu/J6P5N2fg/ikl3AsB2t/Xmad/Yt1uIYWPxhyInJ/f/xMrsj4UCZBQ 7S7dlcwDxkxDeLzqZwUtggZmFASXJUOkAxCoVfziGKf2GREZsKyaQLS5jC0DiguJWzzYl Zchr/ZXsEdkXPW+Qo5rB7ac86g8Zxp09Qmo= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Wire up the platform libraries to the generic drivers so that we can use PCI devices and UEFI, and leave the controller initialized so that the OS can boot it using a generic driver of its own. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 17 +++++++++++++++-- Silicon/Marvell/Armada7k8k/Armada7k8k.fdf | 5 +++++ 2 files changed, 20 insertions(+), 2 deletions(-) diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc b/Silicon/Marvel= l/Armada7k8k/Armada7k8k.dsc.inc index 545b369..f78a76b 100644 --- a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc +++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc @@ -70,8 +70,10 @@ IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompres= sLib.inf CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf - PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf - PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf + PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf + PciHostBridgeLib|Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBri= dgeLib/PciHostBridgeLib.inf + PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.i= nf + PciExpressLib|Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciExpressLib= /PciExpressLib.inf =20 # Basic UEFI services libraries UefiLib|MdePkg/Library/UefiLib/UefiLib.inf @@ -407,6 +409,12 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x00010000 gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00010000 =20 + # PCIE + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 + + # SoC Configuration Space + gMarvellTokenSpaceGuid.PcdConfigSpaceBaseAddress|0xE0000000 + !if $(CAPSULE_ENABLE) [PcdsDynamicExDefault.common.DEFAULT] gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareImageDescriptor= |{0x0}|VOID*|0x100 @@ -520,6 +528,11 @@ MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.inf Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonDxe.inf =20 + # PCI + ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf + MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf + MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + # Console packages MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.fdf b/Silicon/Marvell/Ar= mada7k8k/Armada7k8k.fdf index 3a320ba..e22f514 100644 --- a/Silicon/Marvell/Armada7k8k/Armada7k8k.fdf +++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.fdf @@ -174,6 +174,11 @@ FvNameGuid =3D 5eda4200-2c5f-43cb-9da3-0baf74b= 1b30c INF MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.inf INF Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonDxe.inf =20 + # PCI + INF ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf + INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf + INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + # Multiple Console IO support INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#40322): https://edk2.groups.io/g/devel/message/40322 Mute This Topic: https://groups.io/mt/31553481/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat May 4 20:05:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+40323+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+40323+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1557395650; cv=none; d=zoho.com; s=zohoarc; b=iG1Q8IK0i4862yc4Pnjhb47gDIQS8jmLgoXghwOGpxHVOTX57Luq81MagqS5My6JYQRLetyjcMiR0JNtetlFMm7ZO0hQ+W8eZPOIIkPGAsqwaog9a8eYewP2dZno64SRBa46KgOsyRnoJI102bRxR+SImhLXGthUhK6s9AVO1gs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557395650; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=TIwDtWb2Dg+psQRdNOrixZmZCTahDQ5ivJc8gR1ycAw=; b=ikIjS8s2obX6HlpMI3dQ8sIErNN9hdb2AYn/B7xYmBqVEk3/BvJEROPOae859JNCQV2BDGhhmg/vz/T1DLtdYZkSbo0S6vo7oKKScU3mrTJ7xLYKsBLAjA+dudYuu84x9rwb8jl8NNQexNMudqQ2RNnut2hytBbEzkBqc61c2k4= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+40323+1787277+3901457@groups.io Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1557395650722748.5663882067493; Thu, 9 May 2019 02:54:10 -0700 (PDT) Return-Path: X-Received: from mail-lj1-f196.google.com (mail-lj1-f196.google.com [209.85.208.196]) by groups.io with SMTP; Thu, 09 May 2019 02:54:09 -0700 X-Received: by mail-lj1-f196.google.com with SMTP id j24so665699ljg.1 for ; Thu, 09 May 2019 02:54:08 -0700 (PDT) X-Gm-Message-State: APjAAAVZaP2PuWcCsZLbSAAcCouL2UkrEX5qzLK+OM8i8g0u8skze53k UPAMI6GBMi8jVpdgyFgI0hO/TsZsmj4= X-Google-Smtp-Source: APXvYqxogNa2qc5QsIqj8abTYBfFQZFT3fUxZ84w3ZwEMfvgOwo9tCbkts5XBWkygb2gkv1XnXlycg== X-Received: by 2002:a2e:1508:: with SMTP id s8mr1718874ljd.87.1557395646993; Thu, 09 May 2019 02:54:06 -0700 (PDT) X-Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id l25sm276668lfk.57.2019.05.09.02.54.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 09 May 2019 02:54:06 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com, Jici.Gao@arm.com, rebecca@bluestop.org, kettenis@jive.eu Subject: [edk2-devel] [edk2-platforms: PATCH 09/14] Marvell/Armada80x0McBin: Enable ACPI PCIE support Date: Thu, 9 May 2019 11:53:37 +0200 Message-Id: <1557395622-32425-10-git-send-email-mw@semihalf.com> In-Reply-To: <1557395622-32425-1-git-send-email-mw@semihalf.com> References: <1557395622-32425-1-git-send-email-mw@semihalf.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1557395650; bh=o9IXC/UkPxhEG+7aLAZB46uYf1LRRSTeUHRRcLWSjhQ=; h=Cc:Date:From:Reply-To:Subject:To; b=llY6dLpU4L6xMZXLTMwJDF2V/ug3N6sqWz6OFiXrmq77i2M90x/8y8HqebNDAsnarZm e7qFoNmeg8hun5QW5ooJoew9kNvVYZX/4Uu3fiTfGdG67oPLIloMtzau5KPYn7U2SJA/X Wf/xOKqGGir6sStfng/pd0qmZSt6FDaYg08= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch adds description of the PCIE controller in ACPI tables of MacchiatoBin community board. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin.inf | 1 + Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Pcie.h | 25 +++ Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl | 217 ++++= ++++++++++++++++ Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Mcfg.aslc | 47 +++++ 4 files changed, 290 insertions(+) create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/P= cie.h create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/M= cfg.aslc diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin.inf b/Si= licon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin.inf index 9e52281..e627932 100644 --- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin.inf +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin.inf @@ -25,6 +25,7 @@ =20 [Sources] Armada80x0McBin/Dsdt.asl + Armada80x0McBin/Mcfg.aslc Fadt.aslc Gtdt.aslc Madt.aslc diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Pcie.h b= /Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Pcie.h new file mode 100644 index 0000000..93631c2 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Pcie.h @@ -0,0 +1,25 @@ +/** + + Copyright (C) 2019, Marvell International Ltd. and its affiliates. + + This program and the accompanying materials are licensed and made availa= ble + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#define PCI_BUS_MIN 0x0 +#define PCI_BUS_MAX 0x0 +#define PCI_BUS_COUNT 0x1 +#define PCI_MMIO32_BASE 0xC0000000 +#define PCI_MMIO32_SIZE 0x20000000 +#define PCI_MMIO64_BASE 0x800000000 +#define PCI_MMIO64_SIZE 0x100000000 +#define PCI_IO_BASE 0x0 +#define PCI_IO_SIZE 0x10000 +#define PCI_IO_TRANSLATION 0xEFF00000 +#define PCI_ECAM_BASE 0xE0008000 diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl= b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl index 87cb93a..caf5cb9 100644 --- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl @@ -14,6 +14,7 @@ =20 **/ =20 +#include "Armada80x0McBin/Pcie.h" #include "IcuInterrupts.h" =20 DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) @@ -306,5 +307,221 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "AR= MADA8K", 3) } }) } + + // + // PCIe Root Bus + // + Device (PCI0) + { + Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardwar= e ID + Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID + Name (_SEG, 0x00) // _SEG: PCI Segment + Name (_BBN, 0x00) // _BBN: BIOS Bus Number + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Name (_PRT, Package () // _PRT: PCI Routing Table + { + Package () { 0xFFFF, 0x0, 0x0, 0x40 }, + Package () { 0xFFFF, 0x1, 0x0, 0x40 }, + Package () { 0xFFFF, 0x2, 0x0, 0x40 }, + Package () { 0xFFFF, 0x3, 0x0, 0x40 } + }) + + Method (_CRS, 0, Serialized) // _CRS: Current Resource Settin= gs + { + Name (RBUF, ResourceTemplate () + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, P= osDecode, + 0x0000, // Granularity + PCI_BUS_MIN, // Range Minim= um + PCI_BUS_MAX, // Range Maxim= um + 0x0000, // Translation= Offset + PCI_BUS_COUNT // Length + ) + DWordMemory (ResourceProducer, PosDecode, MinFixed, Ma= xFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + PCI_MMIO32_BASE, // Range Minim= um + 0xDFFFFFFF, // Range Maxim= um + 0x00000000, // Translation= Offset + PCI_MMIO32_SIZE // Length + ) + QWordMemory (ResourceProducer, PosDecode, MinFixed, Ma= xFixed, NonCacheable, ReadWrite, + 0x0000000000000000, // Granularity + PCI_MMIO64_BASE, // Range Minim= um + 0x8FFFFFFFF, // Range Maxim= um + 0x00000000, // Translation= Offset + PCI_MMIO64_SIZE // Length + ) + DWordIo (ResourceProducer, MinFixed, MaxFixed, PosDeco= de, EntireRange, + 0x00000000, // Granularity + PCI_IO_BASE, // Range Minim= um + 0x0000FFFF, // Range Maxim= um + PCI_IO_TRANSLATION, // Translation= Address + PCI_IO_SIZE, // Length + , + , + , + TypeTranslation + ) + }) + Return (RBUF) /* \_SB_.PCI0._CRS.RBUF */ + } // Method(_CRS) + + Device (RES0) + { + Name (_HID, "PNP0C02") + Name (_CRS, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + PCI_ECAM_BASE, + 0x10000000 + ) + }) + } + Name (SUPP, 0x00) + Name (CTRL, 0x00) + Method (_OSC, 4, NotSerialized) // _OSC: Operating System Cap= abilities + { + CreateDWordField (Arg3, 0x00, CDW1) + If (LEqual (Arg0, ToUUID ("33db4d5b-1ff7-401c-9657-7441c03= dd766") /* PCI Host Bridge Device */)) + { + CreateDWordField (Arg3, 0x04, CDW2) + CreateDWordField (Arg3, 0x08, CDW3) + Store (CDW2, SUPP) /* \_SB_.PCI0.SUPP */ + Store (CDW3, CTRL) /* \_SB_.PCI0.CTRL */ + If (LNotEqual (And (SUPP, 0x16), 0x16)) + { + And (CTRL, 0x1E, CTRL) /* \_SB_.PCI0.CTRL */ + } + + And (CTRL, 0x1D, CTRL) /* \_SB_.PCI0.CTRL */ + If (LNotEqual (Arg1, One)) + { + Or (CDW1, 0x08, CDW1) /* \_SB_.PCI0._OSC.CDW1 */ + } + + If (LNotEqual (CDW3, CTRL)) + { + Or (CDW1, 0x10, CDW1) /* \_SB_.PCI0._OSC.CDW1 */ + } + + Store (CTRL, CDW3) /* \_SB_.PCI0._OSC.CDW3 */ + Return (Arg3) + } + Else + { + Or (CDW1, 0x04, CDW1) /* \_SB_.PCI0._OSC.CDW1 */ + Return (Arg3) + } + } // Method(_OSC) + + // + // Device-Specific Methods + // + Method(_DSM, 0x4, NotSerialized) { + If (LEqual(Arg0, ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434= D"))) { + switch (ToInteger(Arg2)) { + // + // Function 0: Return supported functions + // + case(0) { + Return (Buffer() {0xFF}) + } + + // + // Function 1: Return PCIe Slot Information + // + case(1) { + Return (Package(2) { + One, // Success + Package(3) { + 0x1, // x1 PCIe link + 0x1, // PCI express card slot + 0x1 // WAKE# signal supported + } + }) + } + + // + // Function 2: Return PCIe Slot Number. + // + case(2) { + Return (Package(1) { + Package(4) { + 2, // Source ID + 4, // Token ID: ID refers to a slot + 0, // Start bit of the field to use. + 7 // End bit of the field to use. + } + }) + } + + // + // Function 4: Return PCI Bus Capabilities + // + case(4) { + Return (Package(2) { + One, // Success + Buffer() { + 1,0, // Version + 0,0, // Status, 0:Success + 24,0,0,0, // Length + 1,0, // PCI + 16,0, // Length + 0, // Attributes + 0x0D, // Current Speed/Mode + 0x3F,0, // Supported Speeds/Modes + 0, // Voltage + 0,0,0,0,0,0,0 // Reserved + } + }) + } + + // + // Function 5: Return Ignore PCI Boot Configuration + // + case(5) { + Return (Package(1) {1}) + } + + // + // Function 6: Return LTR Maximum Latency + // + case(6) { + Return (Package(4) { + Package(1){0}, // Maximum Snoop Latency Scale + Package(1){0}, // Maximum Snoop Latency Value + Package(1){0}, // Maximum No-Snoop Latency Scale + Package(1){0} // Maximum No-Snoop Latency Value + }) + } + + // + // Function 7: Return PCI Express Naming + // + case(7) { + Return (Package(2) { + Package(1) {0}, + Package(1) {Unicode("PCI0")} + }) + } + + // + // Not supported + // + default { + } + } + } + Return (Buffer(){0}) + } // Method(_DSM) + + // + // Root-Complex 0 + // + Device (RP0) + { + Name (_ADR, PCI_ECAM_BASE) // _ADR: Bus 0, Dev 0, Func 0 + } + } } } diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Mcfg.asl= c b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Mcfg.aslc new file mode 100644 index 0000000..bda5800 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Mcfg.aslc @@ -0,0 +1,47 @@ +/** @file + + Memory mapped config space base address table (MCFG) + + Copyright (c) 2017, Linaro Ltd. All rights reserved.
+ Copyright (c) 2019, Marvell International Ltd. and its affiliates.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include + +#include "AcpiHeader.h" +#include "Armada80x0McBin/Pcie.h" + +#include + +#pragma pack(1) +typedef struct { + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER Header; + EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCAT= ION_STRUCTURE Structure; +} ACPI_6_0_MCFG_STRUCTURE; +#pragma pack() + +STATIC ACPI_6_0_MCFG_STRUCTURE Mcfg =3D { + { + __ACPI_HEADER (EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SP= ACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE, + ACPI_6_0_MCFG_STRUCTURE, + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE= _REVISION), + EFI_ACPI_RESERVED_QWORD + }, { + PCI_ECAM_BASE, // BaseAddress + 0, // PciSegmentGroupNumber + PCI_BUS_MIN, // StartBusNumber + PCI_BUS_MAX, // EndBusNumber + EFI_ACPI_RESERVED_DWORD // Reserved + } +}; + +VOID CONST * CONST ReferenceAcpiTable =3D &Mcfg; --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id l25sm276668lfk.57.2019.05.09.02.54.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 09 May 2019 02:54:07 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com, Jici.Gao@arm.com, rebecca@bluestop.org, kettenis@jive.eu Subject: [edk2-devel] [edk2-platforms: PATCH 10/14] Marvell/Armada80x0Db: Enable ACPI PCIE support Date: Thu, 9 May 2019 11:53:38 +0200 Message-Id: <1557395622-32425-11-git-send-email-mw@semihalf.com> In-Reply-To: <1557395622-32425-1-git-send-email-mw@semihalf.com> References: <1557395622-32425-1-git-send-email-mw@semihalf.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1557395651; bh=eZ2+Y2Xh0YMo0THGg+S82jSlTX/NP7PFUyy5IFTrL/Q=; h=Cc:Date:From:Reply-To:Subject:To; b=f5/rbwYEuBpubLM0ByWAQaNwgFt45pCIxxaUghHusH6PAuBV6Ypb6OJbKSW8WSBf1te zCzWOk0jEwH97SB4mer813XxLnTBsHl3de+iuNH5+IEFYwk3WS9Q76Soab9u/avtjcMtD nNKxY6q7xu+0wCWIp6oLKgXM6WK+fg1CYMY= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch adds description of the PCIE controller in ACPI tables of Armada 8040 DB board. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db.inf | 1 + Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Pcie.h | 25 +++ Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl | 217 +++++++= +++++++++++++ Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Mcfg.aslc | 47 +++++ 4 files changed, 290 insertions(+) create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Pcie= .h create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Mcfg= .aslc diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db.inf b/Silic= on/Marvell/Armada7k8k/AcpiTables/Armada80x0Db.inf index 35a679b..9b37eb7 100644 --- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db.inf +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db.inf @@ -25,6 +25,7 @@ =20 [Sources] Armada80x0Db/Dsdt.asl + Armada80x0Db/Mcfg.aslc Fadt.aslc Gtdt.aslc Madt.aslc diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Pcie.h b/Si= licon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Pcie.h new file mode 100644 index 0000000..93631c2 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Pcie.h @@ -0,0 +1,25 @@ +/** + + Copyright (C) 2019, Marvell International Ltd. and its affiliates. + + This program and the accompanying materials are licensed and made availa= ble + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#define PCI_BUS_MIN 0x0 +#define PCI_BUS_MAX 0x0 +#define PCI_BUS_COUNT 0x1 +#define PCI_MMIO32_BASE 0xC0000000 +#define PCI_MMIO32_SIZE 0x20000000 +#define PCI_MMIO64_BASE 0x800000000 +#define PCI_MMIO64_SIZE 0x100000000 +#define PCI_IO_BASE 0x0 +#define PCI_IO_SIZE 0x10000 +#define PCI_IO_TRANSLATION 0xEFF00000 +#define PCI_ECAM_BASE 0xE0008000 diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl b/= Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl index 7c65949..0f78e39 100644 --- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl @@ -15,6 +15,7 @@ =20 **/ =20 +#include "Armada80x0Db/Pcie.h" #include "IcuInterrupts.h" =20 DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) @@ -326,5 +327,221 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "AR= MADA8K", 3) } }) } + + // + // PCIe Root Bus + // + Device (PCI0) + { + Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardwar= e ID + Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID + Name (_SEG, 0x00) // _SEG: PCI Segment + Name (_BBN, 0x00) // _BBN: BIOS Bus Number + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Name (_PRT, Package () // _PRT: PCI Routing Table + { + Package () { 0xFFFF, 0x0, 0x0, 0x40 }, + Package () { 0xFFFF, 0x1, 0x0, 0x40 }, + Package () { 0xFFFF, 0x2, 0x0, 0x40 }, + Package () { 0xFFFF, 0x3, 0x0, 0x40 } + }) + + Method (_CRS, 0, Serialized) // _CRS: Current Resource Settin= gs + { + Name (RBUF, ResourceTemplate () + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, P= osDecode, + 0x0000, // Granularity + PCI_BUS_MIN, // Range Minim= um + PCI_BUS_MAX, // Range Maxim= um + 0x0000, // Translation= Offset + PCI_BUS_COUNT // Length + ) + DWordMemory (ResourceProducer, PosDecode, MinFixed, Ma= xFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + PCI_MMIO32_BASE, // Range Minim= um + 0xDFFFFFFF, // Range Maxim= um + 0x00000000, // Translation= Offset + PCI_MMIO32_SIZE // Length + ) + QWordMemory (ResourceProducer, PosDecode, MinFixed, Ma= xFixed, NonCacheable, ReadWrite, + 0x0000000000000000, // Granularity + PCI_MMIO64_BASE, // Range Minim= um + 0x8FFFFFFFF, // Range Maxim= um + 0x00000000, // Translation= Offset + PCI_MMIO64_SIZE // Length + ) + DWordIo (ResourceProducer, MinFixed, MaxFixed, PosDeco= de, EntireRange, + 0x00000000, // Granularity + PCI_IO_BASE, // Range Minim= um + 0x0000FFFF, // Range Maxim= um + PCI_IO_TRANSLATION, // Translation= Address + PCI_IO_SIZE, // Length + , + , + , + TypeTranslation + ) + }) + Return (RBUF) /* \_SB_.PCI0._CRS.RBUF */ + } // Method(_CRS) + + Device (RES0) + { + Name (_HID, "PNP0C02") + Name (_CRS, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + PCI_ECAM_BASE, + 0x10000000 + ) + }) + } + Name (SUPP, 0x00) + Name (CTRL, 0x00) + Method (_OSC, 4, NotSerialized) // _OSC: Operating System Cap= abilities + { + CreateDWordField (Arg3, 0x00, CDW1) + If (LEqual (Arg0, ToUUID ("33db4d5b-1ff7-401c-9657-7441c03= dd766") /* PCI Host Bridge Device */)) + { + CreateDWordField (Arg3, 0x04, CDW2) + CreateDWordField (Arg3, 0x08, CDW3) + Store (CDW2, SUPP) /* \_SB_.PCI0.SUPP */ + Store (CDW3, CTRL) /* \_SB_.PCI0.CTRL */ + If (LNotEqual (And (SUPP, 0x16), 0x16)) + { + And (CTRL, 0x1E, CTRL) /* \_SB_.PCI0.CTRL */ + } + + And (CTRL, 0x1D, CTRL) /* \_SB_.PCI0.CTRL */ + If (LNotEqual (Arg1, One)) + { + Or (CDW1, 0x08, CDW1) /* \_SB_.PCI0._OSC.CDW1 */ + } + + If (LNotEqual (CDW3, CTRL)) + { + Or (CDW1, 0x10, CDW1) /* \_SB_.PCI0._OSC.CDW1 */ + } + + Store (CTRL, CDW3) /* \_SB_.PCI0._OSC.CDW3 */ + Return (Arg3) + } + Else + { + Or (CDW1, 0x04, CDW1) /* \_SB_.PCI0._OSC.CDW1 */ + Return (Arg3) + } + } // Method(_OSC) + + // + // Device-Specific Methods + // + Method(_DSM, 0x4, NotSerialized) { + If (LEqual(Arg0, ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434= D"))) { + switch (ToInteger(Arg2)) { + // + // Function 0: Return supported functions + // + case(0) { + Return (Buffer() {0xFF}) + } + + // + // Function 1: Return PCIe Slot Information + // + case(1) { + Return (Package(2) { + One, // Success + Package(3) { + 0x1, // x1 PCIe link + 0x1, // PCI express card slot + 0x1 // WAKE# signal supported + } + }) + } + + // + // Function 2: Return PCIe Slot Number. + // + case(2) { + Return (Package(1) { + Package(4) { + 2, // Source ID + 4, // Token ID: ID refers to a slot + 0, // Start bit of the field to use. + 7 // End bit of the field to use. + } + }) + } + + // + // Function 4: Return PCI Bus Capabilities + // + case(4) { + Return (Package(2) { + One, // Success + Buffer() { + 1,0, // Version + 0,0, // Status, 0:Success + 24,0,0,0, // Length + 1,0, // PCI + 16,0, // Length + 0, // Attributes + 0x0D, // Current Speed/Mode + 0x3F,0, // Supported Speeds/Modes + 0, // Voltage + 0,0,0,0,0,0,0 // Reserved + } + }) + } + + // + // Function 5: Return Ignore PCI Boot Configuration + // + case(5) { + Return (Package(1) {1}) + } + + // + // Function 6: Return LTR Maximum Latency + // + case(6) { + Return (Package(4) { + Package(1){0}, // Maximum Snoop Latency Scale + Package(1){0}, // Maximum Snoop Latency Value + Package(1){0}, // Maximum No-Snoop Latency Scale + Package(1){0} // Maximum No-Snoop Latency Value + }) + } + + // + // Function 7: Return PCI Express Naming + // + case(7) { + Return (Package(2) { + Package(1) {0}, + Package(1) {Unicode("PCI0")} + }) + } + + // + // Not supported + // + default { + } + } + } + Return (Buffer(){0}) + } // Method(_DSM) + + // + // Root-Complex 0 + // + Device (RP0) + { + Name (_ADR, PCI_ECAM_BASE) // _ADR: Bus 0, Dev 0, Func 0 + } + } } } diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Mcfg.aslc b= /Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Mcfg.aslc new file mode 100644 index 0000000..da152b7 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Mcfg.aslc @@ -0,0 +1,47 @@ +/** @file + + Memory mapped config space base address table (MCFG) + + Copyright (c) 2017, Linaro Ltd. All rights reserved.
+ Copyright (c) 2019, Marvell International Ltd. and its affiliates.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include + +#include "AcpiHeader.h" +#include "Armada80x0Db/Pcie.h" + +#include + +#pragma pack(1) +typedef struct { + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER Header; + EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCAT= ION_STRUCTURE Structure; +} ACPI_6_0_MCFG_STRUCTURE; +#pragma pack() + +STATIC ACPI_6_0_MCFG_STRUCTURE Mcfg =3D { + { + __ACPI_HEADER (EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SP= ACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE, + ACPI_6_0_MCFG_STRUCTURE, + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE= _REVISION), + EFI_ACPI_RESERVED_QWORD + }, { + PCI_ECAM_BASE, // BaseAddress + 0, // PciSegmentGroupNumber + PCI_BUS_MIN, // StartBusNumber + PCI_BUS_MAX, // EndBusNumber + EFI_ACPI_RESERVED_DWORD // Reserved + } +}; + +VOID CONST * CONST ReferenceAcpiTable =3D &Mcfg; --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#40324): https://edk2.groups.io/g/devel/message/40324 Mute This Topic: https://groups.io/mt/31553483/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat May 4 20:05:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+40325+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+40325+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1557395653; cv=none; d=zoho.com; s=zohoarc; b=nLfa/gDnn4AAxu06vlKwPjYsz1w32ARyE457tP6bAM0nAON/XiWeH/E8x8kXP3ULglbjRyKW7w7HItYEPYfrMkIkXCb+rnI0mud6ieWwoa3Fy3IuO5aPfxymOfsUpEGNn+HtnuZGXpQn20mw6Yf6ZwmEE4M8BJ7swkFTuT9TVeM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557395653; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=w8yt0YFILH1DdLSoJdF50ABsLE5n69KzRVZhhgZCcLk=; b=iYeWIzhCZEpUZecYImoB61qzhYBREQ7yJ0EqOUtaj9tlpvUa0SAxCLXJZzp3Zlj6CvZvnVic3E/QDB1jhcMT76igrcnPW0tMeghoWoArnp9pQbTH3joKP4T6ProtoKlrPUDovCueaa7EOKsy83vGyiSzPYppq2uxeocyQpNJ4js= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+40325+1787277+3901457@groups.io Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1557395653306853.4911871818634; Thu, 9 May 2019 02:54:13 -0700 (PDT) Return-Path: X-Received: from mail-lj1-f196.google.com (mail-lj1-f196.google.com [209.85.208.196]) by groups.io with SMTP; Thu, 09 May 2019 02:54:12 -0700 X-Received: by mail-lj1-f196.google.com with SMTP id e13so1431378ljl.11 for ; Thu, 09 May 2019 02:54:11 -0700 (PDT) X-Gm-Message-State: APjAAAVutEou+x4fGi9wnY0FRUS5gS9+p88T8w1FEUdk8ynuJybEDyFm M3LQ2YbamBaC4YgA9NAIr0eFe+Ic5ps= X-Google-Smtp-Source: APXvYqx42aVKJ2faaVxNbJ3WJpV9WdHO8DWVvxsFxh1VDoqV2tlwv/sTkWvJRSym3l6friT2qWUOOw== X-Received: by 2002:a2e:9c0a:: with SMTP id s10mr1765797lji.162.1557395649729; Thu, 09 May 2019 02:54:09 -0700 (PDT) X-Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id l25sm276668lfk.57.2019.05.09.02.54.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 09 May 2019 02:54:08 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com, Jici.Gao@arm.com, rebecca@bluestop.org, kettenis@jive.eu Subject: [edk2-devel] [edk2-platforms: PATCH 11/14] Marvell/Armada70x0Db: Enable ACPI PCIE support Date: Thu, 9 May 2019 11:53:39 +0200 Message-Id: <1557395622-32425-12-git-send-email-mw@semihalf.com> In-Reply-To: <1557395622-32425-1-git-send-email-mw@semihalf.com> References: <1557395622-32425-1-git-send-email-mw@semihalf.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1557395652; bh=zV//Ne8FDAuaAvm+JXsXug/BtDVq8IFTKJaDAs+nn+w=; h=Cc:Date:From:Reply-To:Subject:To; b=t9trNzCE7kTwssSBBfo585VsdTG0rZ6LNAQZyBYh7Cfkav8j8u3BQT5QrlceG4yFOi3 aDlMm1w/G5NqSrwfVSZt50B8PrFtcOe56BjKWx5EF3HbErLqSFZh2oyDvchyPbc7AO+Iu ju396hyiLW9mWv8s1rXiGRpsdhcC1TtF0hI= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch adds description of the PCIE controller in ACPI tables of Armada 7040 DB board. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db.inf | 1 + Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Pcie.h | 25 +++ Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl | 217 +++++++= +++++++++++++ Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Mcfg.aslc | 47 +++++ 4 files changed, 290 insertions(+) create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Pcie= .h create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Mcfg= .aslc diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db.inf b/Silic= on/Marvell/Armada7k8k/AcpiTables/Armada70x0Db.inf index 659c333..96bcdf0 100644 --- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db.inf +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db.inf @@ -25,6 +25,7 @@ =20 [Sources] Armada70x0Db/Dsdt.asl + Armada70x0Db/Mcfg.aslc Fadt.aslc Gtdt.aslc Madt.aslc diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Pcie.h b/Si= licon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Pcie.h new file mode 100644 index 0000000..93631c2 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Pcie.h @@ -0,0 +1,25 @@ +/** + + Copyright (C) 2019, Marvell International Ltd. and its affiliates. + + This program and the accompanying materials are licensed and made availa= ble + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#define PCI_BUS_MIN 0x0 +#define PCI_BUS_MAX 0x0 +#define PCI_BUS_COUNT 0x1 +#define PCI_MMIO32_BASE 0xC0000000 +#define PCI_MMIO32_SIZE 0x20000000 +#define PCI_MMIO64_BASE 0x800000000 +#define PCI_MMIO64_SIZE 0x100000000 +#define PCI_IO_BASE 0x0 +#define PCI_IO_SIZE 0x10000 +#define PCI_IO_TRANSLATION 0xEFF00000 +#define PCI_ECAM_BASE 0xE0008000 diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl b/= Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl index 621b688..a23bd70 100644 --- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl @@ -15,6 +15,7 @@ =20 **/ =20 +#include "Armada70x0Db/Pcie.h" #include "IcuInterrupts.h" =20 DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) @@ -225,5 +226,221 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "AR= MADA7K", 3) } }) } + + // + // PCIe Root Bus + // + Device (PCI0) + { + Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardwar= e ID + Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID + Name (_SEG, 0x00) // _SEG: PCI Segment + Name (_BBN, 0x00) // _BBN: BIOS Bus Number + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Name (_PRT, Package () // _PRT: PCI Routing Table + { + Package () { 0xFFFF, 0x0, 0x0, 0x40 }, + Package () { 0xFFFF, 0x1, 0x0, 0x40 }, + Package () { 0xFFFF, 0x2, 0x0, 0x40 }, + Package () { 0xFFFF, 0x3, 0x0, 0x40 } + }) + + Method (_CRS, 0, Serialized) // _CRS: Current Resource Settin= gs + { + Name (RBUF, ResourceTemplate () + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, P= osDecode, + 0x0000, // Granularity + PCI_BUS_MIN, // Range Minim= um + PCI_BUS_MAX, // Range Maxim= um + 0x0000, // Translation= Offset + PCI_BUS_COUNT // Length + ) + DWordMemory (ResourceProducer, PosDecode, MinFixed, Ma= xFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + PCI_MMIO32_BASE, // Range Minim= um + 0xDFFFFFFF, // Range Maxim= um + 0x00000000, // Translation= Offset + PCI_MMIO32_SIZE // Length + ) + QWordMemory (ResourceProducer, PosDecode, MinFixed, Ma= xFixed, NonCacheable, ReadWrite, + 0x0000000000000000, // Granularity + PCI_MMIO64_BASE, // Range Minim= um + 0x8FFFFFFFF, // Range Maxim= um + 0x00000000, // Translation= Offset + PCI_MMIO64_SIZE // Length + ) + DWordIo (ResourceProducer, MinFixed, MaxFixed, PosDeco= de, EntireRange, + 0x00000000, // Granularity + PCI_IO_BASE, // Range Minim= um + 0x0000FFFF, // Range Maxim= um + PCI_IO_TRANSLATION, // Translation= Address + PCI_IO_SIZE, // Length + , + , + , + TypeTranslation + ) + }) + Return (RBUF) /* \_SB_.PCI0._CRS.RBUF */ + } // Method(_CRS) + + Device (RES0) + { + Name (_HID, "PNP0C02") + Name (_CRS, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + PCI_ECAM_BASE, + 0x10000000 + ) + }) + } + Name (SUPP, 0x00) + Name (CTRL, 0x00) + Method (_OSC, 4, NotSerialized) // _OSC: Operating System Cap= abilities + { + CreateDWordField (Arg3, 0x00, CDW1) + If (LEqual (Arg0, ToUUID ("33db4d5b-1ff7-401c-9657-7441c03= dd766") /* PCI Host Bridge Device */)) + { + CreateDWordField (Arg3, 0x04, CDW2) + CreateDWordField (Arg3, 0x08, CDW3) + Store (CDW2, SUPP) /* \_SB_.PCI0.SUPP */ + Store (CDW3, CTRL) /* \_SB_.PCI0.CTRL */ + If (LNotEqual (And (SUPP, 0x16), 0x16)) + { + And (CTRL, 0x1E, CTRL) /* \_SB_.PCI0.CTRL */ + } + + And (CTRL, 0x1D, CTRL) /* \_SB_.PCI0.CTRL */ + If (LNotEqual (Arg1, One)) + { + Or (CDW1, 0x08, CDW1) /* \_SB_.PCI0._OSC.CDW1 */ + } + + If (LNotEqual (CDW3, CTRL)) + { + Or (CDW1, 0x10, CDW1) /* \_SB_.PCI0._OSC.CDW1 */ + } + + Store (CTRL, CDW3) /* \_SB_.PCI0._OSC.CDW3 */ + Return (Arg3) + } + Else + { + Or (CDW1, 0x04, CDW1) /* \_SB_.PCI0._OSC.CDW1 */ + Return (Arg3) + } + } // Method(_OSC) + + // + // Device-Specific Methods + // + Method(_DSM, 0x4, NotSerialized) { + If (LEqual(Arg0, ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434= D"))) { + switch (ToInteger(Arg2)) { + // + // Function 0: Return supported functions + // + case(0) { + Return (Buffer() {0xFF}) + } + + // + // Function 1: Return PCIe Slot Information + // + case(1) { + Return (Package(2) { + One, // Success + Package(3) { + 0x1, // x1 PCIe link + 0x1, // PCI express card slot + 0x1 // WAKE# signal supported + } + }) + } + + // + // Function 2: Return PCIe Slot Number. + // + case(2) { + Return (Package(1) { + Package(4) { + 2, // Source ID + 4, // Token ID: ID refers to a slot + 0, // Start bit of the field to use. + 7 // End bit of the field to use. + } + }) + } + + // + // Function 4: Return PCI Bus Capabilities + // + case(4) { + Return (Package(2) { + One, // Success + Buffer() { + 1,0, // Version + 0,0, // Status, 0:Success + 24,0,0,0, // Length + 1,0, // PCI + 16,0, // Length + 0, // Attributes + 0x0D, // Current Speed/Mode + 0x3F,0, // Supported Speeds/Modes + 0, // Voltage + 0,0,0,0,0,0,0 // Reserved + } + }) + } + + // + // Function 5: Return Ignore PCI Boot Configuration + // + case(5) { + Return (Package(1) {1}) + } + + // + // Function 6: Return LTR Maximum Latency + // + case(6) { + Return (Package(4) { + Package(1){0}, // Maximum Snoop Latency Scale + Package(1){0}, // Maximum Snoop Latency Value + Package(1){0}, // Maximum No-Snoop Latency Scale + Package(1){0} // Maximum No-Snoop Latency Value + }) + } + + // + // Function 7: Return PCI Express Naming + // + case(7) { + Return (Package(2) { + Package(1) {0}, + Package(1) {Unicode("PCI0")} + }) + } + + // + // Not supported + // + default { + } + } + } + Return (Buffer(){0}) + } // Method(_DSM) + + // + // Root-Complex 0 + // + Device (RP0) + { + Name (_ADR, PCI_ECAM_BASE) // _ADR: Bus 0, Dev 0, Func 0 + } + } } } diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Mcfg.aslc b= /Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Mcfg.aslc new file mode 100644 index 0000000..90bf163 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Mcfg.aslc @@ -0,0 +1,47 @@ +/** @file + + Memory mapped config space base address table (MCFG) + + Copyright (c) 2017, Linaro Ltd. All rights reserved.
+ Copyright (c) 2019, Marvell International Ltd. and its affiliates.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include + +#include "AcpiHeader.h" +#include "Armada70x0Db/Pcie.h" + +#include + +#pragma pack(1) +typedef struct { + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER Header; + EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCAT= ION_STRUCTURE Structure; +} ACPI_6_0_MCFG_STRUCTURE; +#pragma pack() + +STATIC ACPI_6_0_MCFG_STRUCTURE Mcfg =3D { + { + __ACPI_HEADER (EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SP= ACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE, + ACPI_6_0_MCFG_STRUCTURE, + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE= _REVISION), + EFI_ACPI_RESERVED_QWORD + }, { + PCI_ECAM_BASE, // BaseAddress + 0, // PciSegmentGroupNumber + PCI_BUS_MIN, // StartBusNumber + PCI_BUS_MAX, // EndBusNumber + EFI_ACPI_RESERVED_DWORD // Reserved + } +}; + +VOID CONST * CONST ReferenceAcpiTable =3D &Mcfg; --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#40325): https://edk2.groups.io/g/devel/message/40325 Mute This Topic: https://groups.io/mt/31553484/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat May 4 20:05:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+40326+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+40326+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1557395654; cv=none; d=zoho.com; s=zohoarc; b=PE78XCyDLQTSaeJuhm/6iALlBXs2m0ZbMuZ284VwqXDe4dvq1EvCQY6eA4u+phOQUJYHwSeUcxHcjxijh1376hFltU4EXw1LNWYNVdK3Sz6jrjcuEOcsWEVgs246kJrriHyLc181LAO8V+da+muAoaIjQbf08bGY2Gr0RU7GJQk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557395654; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=/NygPHSDwfWY2BANoIQti8tsQRBGu7Lw7quUDdskV20=; b=GjMs4uHICsDR5jptWSwrPlRaxtm9VGupO+yQhdzuTuhc2ULPGKTZtdYJONPYabWUugnyzdgHcpFv0VaAdcmR7CFMR5lBJvqeUnldUFgKgRQvmdAvxYAA5H5ImvZKWoVaQEUtX5jzSkYYBzDw6rVilHsld3465nJiBCloggSrFfM= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+40326+1787277+3901457@groups.io Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1557395654341822.2996190001479; Thu, 9 May 2019 02:54:14 -0700 (PDT) Return-Path: X-Received: from mail-lf1-f67.google.com (mail-lf1-f67.google.com [209.85.167.67]) by groups.io with SMTP; Thu, 09 May 2019 02:54:13 -0700 X-Received: by mail-lf1-f67.google.com with SMTP id h13so1094518lfc.7 for ; Thu, 09 May 2019 02:54:12 -0700 (PDT) X-Gm-Message-State: APjAAAX34DAwtZ2y0/bv1mSfjmXyJMruAMOI3JI/XAY+HtJ8kLU5r0/R 9dJnGpavmVTuns+pUh6l1X4QM+8ILvE= X-Google-Smtp-Source: APXvYqzUWTfnqN1Zwif+QECJYxiKpyg4tOmLpGvgR/gJgey6Upqx8g1MUMhyauTp1idJ2JOXcoTIeA== X-Received: by 2002:ac2:51d1:: with SMTP id u17mr1877945lfm.151.1557395650904; Thu, 09 May 2019 02:54:10 -0700 (PDT) X-Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id l25sm276668lfk.57.2019.05.09.02.54.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 09 May 2019 02:54:10 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com, Jici.Gao@arm.com, rebecca@bluestop.org, kettenis@jive.eu Subject: [edk2-devel] [edk2-platforms: PATCH 12/14] Marvell/Armada80x0McBin: DeviceTree: Use pci-host-generic driver Date: Thu, 9 May 2019 11:53:40 +0200 Message-Id: <1557395622-32425-13-git-send-email-mw@semihalf.com> In-Reply-To: <1557395622-32425-1-git-send-email-mw@semihalf.com> References: <1557395622-32425-1-git-send-email-mw@semihalf.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1557395653; bh=6mmy9LxXsI/RUJe+pz3s3CGBZ5+1qnmb6VJtgr+jV64=; h=Cc:Date:From:Reply-To:Subject:To; b=eZyMWEzCv+KKYMTvmjxEz13meIWBx1iLO74HTiSJ6orpZ/t66lDPJFmmOb5bpMsxsJ4 k2EEv8KBB7AqnFhFF1NKqGGCDi/4suE5i+XDVJXq4HSJzvT/bWpPuLp1OUGLX+jhTeohv aJ1Cl6HTAjRMYj0TgR9tNzPcUjwfnDnx9Qc= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Now as the OS clock configuration is inherited from the firmware, and PCIE is also configured, switch safely MacchiatoBin board to use the pci-host-generic driver. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts b/= Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts index b86e27e..d9c9348 100644 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts @@ -180,6 +180,9 @@ }; =20 &cp0_pcie0 { + compatible =3D "marvell,armada8k-pcie-ecam", "snps,dw-pcie-ecam"; + reg =3D <0 0xe0000000 0 0xff00000>; + bus-range =3D <0 0xfe>; pinctrl-names =3D "default"; pinctrl-0 =3D <&cp0_pcie_pins>; num-lanes =3D <4>; --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id l25sm276668lfk.57.2019.05.09.02.54.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 09 May 2019 02:54:11 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com, Jici.Gao@arm.com, rebecca@bluestop.org, kettenis@jive.eu Subject: [edk2-devel] [edk2-platforms: PATCH 13/14] Marvell/Armada7k8k: Remove duplication in .dsc files Date: Thu, 9 May 2019 11:53:41 +0200 Message-Id: <1557395622-32425-14-git-send-email-mw@semihalf.com> In-Reply-To: <1557395622-32425-1-git-send-email-mw@semihalf.com> References: <1557395622-32425-1-git-send-email-mw@semihalf.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1557395655; bh=ZkTBEdux8YuGuM9IBVedceHJGjv+ktQ1ChvxtdQ4Ga4=; h=Cc:Date:From:Reply-To:Subject:To; b=hfoWO2OuKdQilpCwJpAb8mUYb4ye6FHml6maycwtAGz6t4Q3jBCREGzZQybMDGbmEj1 oEmm5JAIIrPhlXXrGxRQcOMqUyo8dE81PrM8pMLRBcKA+LL32byGs2nziX35h+c8gtyB1 S8tQYGCqZgsiVlzlUwrkzYuqxinXTyfq2l8= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Mistakenly in all Marvell Armada7k8k .dsc files '[LibraryClasses.common]' section was split. Merge entries into one for each platform. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc | 4 +--- Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc | 4 +--- Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc | 4 +--- 3 files changed, 3 insertions(+), 9 deletions(-) diff --git a/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc b/Platform/Marv= ell/Armada70x0Db/Armada70x0Db.dsc index 01532b4..9ceb872 100644 --- a/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc +++ b/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc @@ -48,9 +48,6 @@ =20 !include Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc =20 -[LibraryClasses.common] - NonDiscoverableInitLib|Platform/Marvell/Armada70x0Db/NonDiscoverableInit= Lib/NonDiscoverableInitLib.inf - [Components.common] Silicon/Marvell/Armada7k8k/DeviceTree/Armada70x0Db.inf =20 @@ -59,6 +56,7 @@ =20 [LibraryClasses.common] ArmadaBoardDescLib|Platform/Marvell/Armada70x0Db/Armada70x0DbBoardDescLi= b/Armada70x0DbBoardDescLib.inf + NonDiscoverableInitLib|Platform/Marvell/Armada70x0Db/NonDiscoverableInit= Lib/NonDiscoverableInitLib.inf =20 ##########################################################################= ###### # diff --git a/Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc b/Platform/Marv= ell/Armada80x0Db/Armada80x0Db.dsc index c6510bb..6487321 100644 --- a/Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc +++ b/Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc @@ -48,9 +48,6 @@ =20 !include Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc =20 -[LibraryClasses.common] - NonDiscoverableInitLib|Platform/Marvell/Armada80x0Db/NonDiscoverableInit= Lib/NonDiscoverableInitLib.inf - [Components.common] Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0Db.inf =20 @@ -59,6 +56,7 @@ =20 [LibraryClasses.common] ArmadaBoardDescLib|Platform/Marvell/Armada80x0Db/Armada80x0DbBoardDescLi= b/Armada80x0DbBoardDescLib.inf + NonDiscoverableInitLib|Platform/Marvell/Armada80x0Db/NonDiscoverableInit= Lib/NonDiscoverableInitLib.inf =20 ##########################################################################= ###### # diff --git a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc b/Platfo= rm/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc index d080136..cb41f4e 100644 --- a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc +++ b/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc @@ -49,9 +49,6 @@ =20 !include Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc =20 -[LibraryClasses.common] - NonDiscoverableInitLib|Platform/SolidRun/Armada80x0McBin/NonDiscoverable= InitLib/NonDiscoverableInitLib.inf - [Components.common] Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0McBin.inf =20 @@ -60,6 +57,7 @@ =20 [LibraryClasses.common] ArmadaBoardDescLib|Platform/SolidRun/Armada80x0McBin/Armada80x0McBinBoar= dDescLib/Armada80x0McBinBoardDescLib.inf + NonDiscoverableInitLib|Platform/SolidRun/Armada80x0McBin/NonDiscoverable= InitLib/NonDiscoverableInitLib.inf =20 ##########################################################################= ###### # --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id l25sm276668lfk.57.2019.05.09.02.54.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 09 May 2019 02:54:12 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com, Jici.Gao@arm.com, rebecca@bluestop.org, kettenis@jive.eu Subject: [edk2-devel] [edk2-platforms: PATCH 14/14] Marvell/Armada7k8: Add 'acpiview' shell command to build Date: Thu, 9 May 2019 11:53:42 +0200 Message-Id: <1557395622-32425-15-git-send-email-mw@semihalf.com> In-Reply-To: <1557395622-32425-1-git-send-email-mw@semihalf.com> References: <1557395622-32425-1-git-send-email-mw@semihalf.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1557395656; bh=7F0gzYx+FBEgXE96Pb3KR+PVAsWy/IjQPPo65j5G7C0=; h=Cc:Date:From:Reply-To:Subject:To; b=oD1dh2LdGFNdaxXkRcEfYr9yBMf7sQ+C52ny2l2q9shcA5qTYf+cAUVDGoTFwE0F+a5 hOS4lccx1U5oL+d2SDou10hj9lPqTPcRV0GQhArcV3363toMqL3Pua7wuPt3bX48X4vrM 61dyDCjKtMqLgxDjrfjMzLcNyrNyJu0/cIE= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" To help diagnose ACPI related boot problems, include the 'acpiview' builtin shell command to Armada7k8k build of the UEFI Shell. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc b/Silicon/Marvel= l/Armada7k8k/Armada7k8k.dsc.inc index f78a76b..af58ce9 100644 --- a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc +++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc @@ -592,6 +592,7 @@ ShellPkg/Application/Shell/Shell.inf { ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellComman= dLib.inf + NULL|ShellPkg/Library/UefiShellAcpiViewCommandLib/UefiShellAcpiViewC= ommandLib.inf NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2Comm= andsLib.inf NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1Comm= andsLib.inf NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3Comm= andsLib.inf --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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