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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id c7sm5448111lja.90.2019.04.25.04.29.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 25 Apr 2019 04:29:32 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com, Jici.Gao@arm.com, Hanna Hawa Subject: [edk2-devel] [edk2-platforms: PATCH v3 1/4] Marvell/Drivers: MvFvbDxe: Change Pcd parameters to be 64 bit Date: Thu, 25 Apr 2019 13:28:21 +0200 Message-Id: <1556191704-28834-2-git-send-email-mw@semihalf.com> In-Reply-To: <1556191704-28834-1-git-send-email-mw@semihalf.com> References: <1556191704-28834-1-git-send-email-mw@semihalf.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1556191776; bh=hB2tSO1ybjWY37HGe8+em916Nj/0pRg9d/T5BhZK3P4=; h=Cc:Date:From:Reply-To:Subject:To; b=o86MNOQ4AKbl1ePulZG5BTqZgvYBypYIjg+ZrkXPQ7sEgsZIRKsfdLm7DjcgEy7AYOW lvrpgMYSICr/cQgFQSYGAmGPnnEILhdDjWKeErKZjzcM924LadKO88MoXlvJyLFkmKoFm 5Z21ykmxg77XYbHqY8dvkxZGWr0i5taB+fw= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Hanna Hawa Update PCD paramters to be 64 bit, so that to add more flexibility for the platforms in terms of configuring memory-mapped SPI access. Signed-off-by: Marcin Wojtas Reviewed-by: Ard Biesheuvel --- Silicon/Marvell/Marvell.dec | 2 +- Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 6 +++--- Silicon/Marvell/Drivers/Spi/MvFvbDxe/MvFvbDxe.inf | 6 +++--- Silicon/Marvell/Drivers/Spi/MvFvbDxe/MvFvbDxe.c | 18 +++++++++--------- 4 files changed, 16 insertions(+), 16 deletions(-) diff --git a/Silicon/Marvell/Marvell.dec b/Silicon/Marvell/Marvell.dec index c927078..7210ba2 100644 --- a/Silicon/Marvell/Marvell.dec +++ b/Silicon/Marvell/Marvell.dec @@ -139,7 +139,7 @@ =20 #SPI gMarvellTokenSpaceGuid.PcdSpiRegBase|0|UINT32|0x3000051 - gMarvellTokenSpaceGuid.PcdSpiMemoryBase|0|UINT32|0x3000059 + gMarvellTokenSpaceGuid.PcdSpiMemoryBase|0|UINT64|0x3000059 gMarvellTokenSpaceGuid.PcdSpiMaxFrequency|0|UINT32|0x30000052 gMarvellTokenSpaceGuid.PcdSpiClockFrequency|0|UINT32|0x30000053 =20 diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc b/Silicon/Marvel= l/Armada7k8k/Armada7k8k.dsc.inc index 0ced400..a1ebb81 100644 --- a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc +++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc @@ -396,11 +396,11 @@ # Variable store - default values # gMarvellTokenSpaceGuid.PcdSpiMemoryBase|0xF9000000 - gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|0xF93C0000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0xF93C0000 gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x00010000 - gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0xF93D0000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|0xF93D0= 000 gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x00010000 - gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0xF93E0000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|0xF93E0000 gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00010000 =20 !if $(CAPSULE_ENABLE) diff --git a/Silicon/Marvell/Drivers/Spi/MvFvbDxe/MvFvbDxe.inf b/Silicon/Ma= rvell/Drivers/Spi/MvFvbDxe/MvFvbDxe.inf index fd3f2f7..ef10bfd 100644 --- a/Silicon/Marvell/Drivers/Spi/MvFvbDxe/MvFvbDxe.inf +++ b/Silicon/Marvell/Drivers/Spi/MvFvbDxe/MvFvbDxe.inf @@ -76,11 +76,11 @@ gMarvellSpiMasterProtocolGuid =20 [FixedPcd] - gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64 gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize - gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64 gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize - gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64 gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize gMarvellTokenSpaceGuid.PcdSpiMemoryBase =20 diff --git a/Silicon/Marvell/Drivers/Spi/MvFvbDxe/MvFvbDxe.c b/Silicon/Marv= ell/Drivers/Spi/MvFvbDxe/MvFvbDxe.c index 1a41a4f..cb006cd 100644 --- a/Silicon/Marvell/Drivers/Spi/MvFvbDxe/MvFvbDxe.c +++ b/Silicon/Marvell/Drivers/Spi/MvFvbDxe/MvFvbDxe.c @@ -145,12 +145,12 @@ MvFvbInitFvAndVariableStoreHeaders ( // FirmwareVolumeHeader->FvLength is declared to have the Variable area // AND the FTW working area AND the FTW Spare contiguous. // - ASSERT (PcdGet32 (PcdFlashNvStorageVariableBase) + + ASSERT (PcdGet64 (PcdFlashNvStorageVariableBase64) + PcdGet32 (PcdFlashNvStorageVariableSize) =3D=3D - PcdGet32 (PcdFlashNvStorageFtwWorkingBase)); - ASSERT (PcdGet32 (PcdFlashNvStorageFtwWorkingBase) + + PcdGet64 (PcdFlashNvStorageFtwWorkingBase64)); + ASSERT (PcdGet64 (PcdFlashNvStorageFtwWorkingBase64) + PcdGet32 (PcdFlashNvStorageFtwWorkingSize) =3D=3D - PcdGet32 (PcdFlashNvStorageFtwSpareBase)); + PcdGet64 (PcdFlashNvStorageFtwSpareBase64)); =20 // Check if the size of the area is at least one block size ASSERT ((PcdGet32 (PcdFlashNvStorageVariableSize) > 0) && @@ -161,9 +161,9 @@ MvFvbInitFvAndVariableStoreHeaders ( (PcdGet32 (PcdFlashNvStorageFtwSpareSize) / BlockSize > 0)); =20 // Ensure the Variable areas are aligned on block size boundaries - ASSERT ((PcdGet32 (PcdFlashNvStorageVariableBase) % BlockSize) =3D=3D 0); - ASSERT ((PcdGet32 (PcdFlashNvStorageFtwWorkingBase) % BlockSize) =3D=3D = 0); - ASSERT ((PcdGet32 (PcdFlashNvStorageFtwSpareBase) % BlockSize) =3D=3D 0); + ASSERT ((PcdGet64 (PcdFlashNvStorageVariableBase64) % BlockSize) =3D=3D = 0); + ASSERT ((PcdGet64 (PcdFlashNvStorageFtwWorkingBase64) % BlockSize) =3D= =3D 0); + ASSERT ((PcdGet64 (PcdFlashNvStorageFtwSpareBase64) % BlockSize) =3D=3D = 0); =20 // // EFI_FIRMWARE_VOLUME_HEADER @@ -1009,8 +1009,8 @@ MvFvbConfigureFlashInstance ( } =20 // Fill remaining flash description - FlashInstance->DeviceBaseAddress =3D PcdGet32 (PcdSpiMemoryBase); - FlashInstance->RegionBaseAddress =3D FixedPcdGet32 (PcdFlashNvStorageVar= iableBase); + FlashInstance->DeviceBaseAddress =3D PcdGet64 (PcdSpiMemoryBase); + FlashInstance->RegionBaseAddress =3D FixedPcdGet64 (PcdFlashNvStorageVar= iableBase64); FlashInstance->FvbOffset =3D FlashInstance->RegionBaseAddress - FlashInstance->DeviceBaseAddress; FlashInstance->FvbSize =3D PcdGet32(PcdFlashNvStorageVariableSize) + --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id c7sm5448111lja.90.2019.04.25.04.29.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 25 Apr 2019 04:29:33 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com, Jici.Gao@arm.com Subject: [edk2-devel] [edk2-platforms: PATCH v3 2/4] Marvell/Armada7k8k: Cleanup PEI phase FV Date: Thu, 25 Apr 2019 13:28:22 +0200 Message-Id: <1556191704-28834-3-git-send-email-mw@semihalf.com> In-Reply-To: <1556191704-28834-1-git-send-email-mw@semihalf.com> References: <1556191704-28834-1-git-send-email-mw@semihalf.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1556191777; bh=wGwZNVocBtd/DtRQ3SZBFcap9JvtejVEcvFK2Te3lWQ=; h=Cc:Date:From:Reply-To:Subject:To; b=ESBXvvW5wtY9A12ehW4fFvCPWIh9zHO0/qNdRKz3TMZU4wmDBqJsPAEFX8BKGeWSx5J 0VdB2zvsJyDtYF9wbgVUM3HFZ7j5PUc6WcwPZR06/ZFTWpEr+vmTSyVle2GY4tXGPjDV4 SsgUbN1zvPssK3rxsjqmWElzn2Yq99uYOvg= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Currently supported the capsule update scenarios on Armada platforms require only the SystemFirmwareDescriptor to be installed in the PEI phase. Remove redundant components and reduce PEI phase FV footprint. Signed-off-by: Marcin Wojtas Reviewed-by: Ard Biesheuvel --- Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 3 --- Silicon/Marvell/Armada7k8k/Armada7k8k.fdf | 3 --- 2 files changed, 6 deletions(-) diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc b/Silicon/Marvel= l/Armada7k8k/Armada7k8k.dsc.inc index a1ebb81..ca3de2e 100644 --- a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc +++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc @@ -427,10 +427,7 @@ ArmPlatformPkg/PlatformPei/PlatformPeim.inf ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf ArmPkg/Drivers/CpuPei/CpuPei.inf - MdeModulePkg/Universal/Variable/Pei/VariablePei.inf !if $(CAPSULE_ENABLE) - MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf - MdeModulePkg/Universal/CapsulePei/CapsulePei.inf Silicon/Marvell/Armada7k8k/Feature/Capsule/SystemFirmwareDescriptor/Syst= emFirmwareDescriptor.inf !endif MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf { diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.fdf b/Silicon/Marvell/Ar= mada7k8k/Armada7k8k.fdf index 5ee7889..3a320ba 100644 --- a/Silicon/Marvell/Armada7k8k/Armada7k8k.fdf +++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.fdf @@ -254,10 +254,7 @@ READ_LOCK_STATUS =3D TRUE INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf INF ArmPkg/Drivers/CpuPei/CpuPei.inf - INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf !if $(CAPSULE_ENABLE) - INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.i= nf - INF MdeModulePkg/Universal/CapsulePei/CapsulePei.inf INF RuleOverride =3D FMP_IMAGE_DESC Silicon/Marvell/Armada7k8k/Feature/C= apsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf !endif INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id c7sm5448111lja.90.2019.04.25.04.29.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 25 Apr 2019 04:29:34 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com, Jici.Gao@arm.com Subject: [edk2-devel] [edk2-platforms: PATCH v3 3/4] Marvell/Drivers/Spi: Improve modules dependencies Date: Thu, 25 Apr 2019 13:28:23 +0200 Message-Id: <1556191704-28834-4-git-send-email-mw@semihalf.com> In-Reply-To: <1556191704-28834-1-git-send-email-mw@semihalf.com> References: <1556191704-28834-1-git-send-email-mw@semihalf.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1556191778; bh=9B5qqqPkYI/cMB7AFiTeG1nztsq9EiEH3UHQ0Jmj14Y=; h=Cc:Date:From:Reply-To:Subject:To; b=gxS3on2/m2HKw7YGglKUsVChmlCtHAqitIYfwDJFgKnbixh1u17suMFKJV0wPHkBm7j wOXwpE2xnLw3PU+FfnT1r/Gk1a1jXz7+gV+G6vbdnEWW5GdPxbaiMQZ45vJZu59fWm1dB YOjgqlgYl132rfekcwjct9EG9NzjuUYEYmQ= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Currently the Marvell SPI DXE drivers depexes are specified with explicit modules' GUIDs and BEFORE/AFTER expressions. Replace it with the actual protocol dependencies. Signed-off-by: Marcin Wojtas Reviewed-by: Ard Biesheuvel --- Silicon/Marvell/Marvell.dec | 3 --- Silicon/Marvell/Drivers/Spi/MvFvbDxe/MvFvbDxe.inf | 4 +++- Silicon/Marvell/Drivers/Spi/MvSpiFlashDxe/MvSpiFlashDxe.inf | 5 +---- Silicon/Marvell/Drivers/Spi/MvSpiOrionDxe/MvSpiOrionDxe.inf | 5 +---- 4 files changed, 5 insertions(+), 12 deletions(-) diff --git a/Silicon/Marvell/Marvell.dec b/Silicon/Marvell/Marvell.dec index 7210ba2..641c53b 100644 --- a/Silicon/Marvell/Marvell.dec +++ b/Silicon/Marvell/Marvell.dec @@ -56,9 +56,6 @@ gShellFUpdateHiiGuid =3D { 0x9b5d2176, 0x590a, 0x49db, { 0x89, 0x5d, 0x4= a, 0x70, 0xfe, 0xad, 0xbe, 0x24 } } gShellSfHiiGuid =3D { 0x03a67756, 0x8cde, 0x4638, { 0x82, 0x34, 0x4a, 0x= 0f, 0x6d, 0x58, 0x81, 0x39 } } =20 - gMarvellFvbDxeGuid =3D { 0x42903750, 0x7e61, 0x4aaf, { 0x83, 0x29, 0xbf,= 0x42, 0x36, 0x4e, 0x24, 0x85 } } - gMarvellSpiFlashDxeGuid =3D { 0x49d7fb74, 0x306d, 0x42bd, { 0x94, 0xc8, = 0xc0, 0xc5, 0x4b, 0x18, 0x1d, 0xd7 } } - [LibraryClasses] ArmadaBoardDescLib|Include/Library/ArmadaBoardDescLib.h ArmadaIcuLib|Include/Library/ArmadaIcuLib.h diff --git a/Silicon/Marvell/Drivers/Spi/MvFvbDxe/MvFvbDxe.inf b/Silicon/Ma= rvell/Drivers/Spi/MvFvbDxe/MvFvbDxe.inf index ef10bfd..e222075 100644 --- a/Silicon/Marvell/Drivers/Spi/MvFvbDxe/MvFvbDxe.inf +++ b/Silicon/Marvell/Drivers/Spi/MvFvbDxe/MvFvbDxe.inf @@ -85,4 +85,6 @@ gMarvellTokenSpaceGuid.PcdSpiMemoryBase =20 [Depex] - gEfiCpuArchProtocolGuid + gEfiCpuArchProtocolGuid AND + gMarvellSpiMasterProtocolGuid AND + gMarvellSpiFlashProtocolGuid diff --git a/Silicon/Marvell/Drivers/Spi/MvSpiFlashDxe/MvSpiFlashDxe.inf b/= Silicon/Marvell/Drivers/Spi/MvSpiFlashDxe/MvSpiFlashDxe.inf index 20939bf..ce843e9 100644 --- a/Silicon/Marvell/Drivers/Spi/MvSpiFlashDxe/MvSpiFlashDxe.inf +++ b/Silicon/Marvell/Drivers/Spi/MvSpiFlashDxe/MvSpiFlashDxe.inf @@ -64,7 +64,4 @@ gMarvellSpiMasterProtocolGuid =20 [Depex] - # - # MvSpiFlashDxe must be loaded prior to variables driver MvFvbDxe - # - BEFORE gMarvellFvbDxeGuid + gMarvellSpiMasterProtocolGuid diff --git a/Silicon/Marvell/Drivers/Spi/MvSpiOrionDxe/MvSpiOrionDxe.inf b/= Silicon/Marvell/Drivers/Spi/MvSpiOrionDxe/MvSpiOrionDxe.inf index 4779371..628ab39 100644 --- a/Silicon/Marvell/Drivers/Spi/MvSpiOrionDxe/MvSpiOrionDxe.inf +++ b/Silicon/Marvell/Drivers/Spi/MvSpiOrionDxe/MvSpiOrionDxe.inf @@ -67,7 +67,4 @@ gMarvellSpiMasterProtocolGuid =20 [Depex] - # - # MvSpiDxe must be loaded prior to MvSpiFlash driver - # - BEFORE gMarvellSpiFlashDxeGuid + TRUE --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#39545): https://edk2.groups.io/g/devel/message/39545 Mute This Topic: https://groups.io/mt/31341164/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon May 13 10:33:05 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+39546+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+39546+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1556191780; cv=none; d=zoho.com; s=zohoarc; b=gz+XtNg1juFvZqoQDBGRjgkE42Mx+ht1brTqVMvuXF1Ons0A4XFB0veYwUMDnwmUxGMr5JJLU6Co0BwUYPK1IQlMuLH/3S2BpLy2h0Rb0INmODcSxfaLIXt9Af+sGeF0gGpaLPrthbu9HH38g6s7TgUbmSLE1UdXuVY4ovhoyvU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1556191780; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=0bJYcoKLNdp9YSGrGqclknePuPKFgaP7bU6jXHX6+J8=; b=DOxC1uv96N9BSvAswuRAIGEav7KbhQNEEVaVQ8omJX/snYsHO5P5u0YBbN4io+/pKmNEcoqyqk4d/mCUXI0uhxvXEj/OIYZ0Ot7bLuYYwlzsts4QYD2KWm21YJkmJAoAVH5FYf9TJSgjWXqv3oSaynGSXADPyNPAnEQXspCHAMM= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+39546+1787277+3901457@groups.io Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 15561917800611016.4176811279082; Thu, 25 Apr 2019 04:29:40 -0700 (PDT) Return-Path: X-Received: from mail-lf1-f66.google.com (mail-lf1-f66.google.com [209.85.167.66]) by groups.io with SMTP; Thu, 25 Apr 2019 04:29:39 -0700 X-Received: by mail-lf1-f66.google.com with SMTP id t30so17226721lfd.8 for ; Thu, 25 Apr 2019 04:29:38 -0700 (PDT) X-Gm-Message-State: APjAAAUMebzSvTO6ftCEuX6gWKvDgaWG2xSKNDOhaQFZ7zaDpehFFdtP qacdovr9qgBb+xrcUiCUJ4P2XkR2TJM= X-Google-Smtp-Source: APXvYqxWtxsjP1bWt0W+giaHtEF3GFBaMEg6O1f/MC+mdJyCACyFUIBsxezO2/Y0BEaKyhSBffmcZA== X-Received: by 2002:ac2:48bb:: with SMTP id u27mr20542732lfg.17.1556191776730; Thu, 25 Apr 2019 04:29:36 -0700 (PDT) X-Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id c7sm5448111lja.90.2019.04.25.04.29.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 25 Apr 2019 04:29:36 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com, Jici.Gao@arm.com, Kornel Duleba Subject: [edk2-devel] [edk2-platforms: PATCH v3 4/4] Marvell/Drivers: MvFvbDxe: Introduce non-mmio mode Date: Thu, 25 Apr 2019 13:28:24 +0200 Message-Id: <1556191704-28834-5-git-send-email-mw@semihalf.com> In-Reply-To: <1556191704-28834-1-git-send-email-mw@semihalf.com> References: <1556191704-28834-1-git-send-email-mw@semihalf.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1556191779; bh=Er3dn4tw/vvFmQni0Pskj8k3gNZQAEEqHcc2voQIx9s=; h=Cc:Date:From:Reply-To:Subject:To; b=FNJNipm4y5OqQgeIM25zxViwsE6DUXN8AW7VJeHGJboDCuCVs8XWtzTPDTrrZXC3X/W Frld2POED187/U9mOHHgiNGs0NWrWGYszf6Bv5L5/V4qvTLkQjY/e9FXSE5Jj49RgHheq R/vFjNAeiSb0WaNuPuAQLKupii0Wp/BKens= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Kornel Duleba This path enables support for reading variables directly from flash without relying on it to be memory mapped. It adds PcdSpiMemoryMapped PCD that allows to switch between the modes. When in non-memory-mapped mode the driver will copy the variables from flash to previously allocated buffer and set PcdFlashNvStorageVariableBase64, PcdFlashNvStorageFtwWorkingBase64 and PcdFlashNvStorageFtwSpareBase64 accordingly. Because of that satisfy a depex dependency with the FTW driver by hooking NvVarStoreFormattedLib. Signed-off-by: Marcin Wojtas Reviewed-by: Ard Biesheuvel --- Silicon/Marvell/Marvell.dec | 2 + Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 15 ++- Silicon/Marvell/Drivers/Spi/MvFvbDxe/MvFvbDxe.inf | 10 +- Silicon/Marvell/Drivers/Spi/MvFvbDxe/MvFvbDxe.h | 1 + Silicon/Marvell/Drivers/Spi/MvFvbDxe/MvFvbDxe.c | 135 +++++++++++++++---= -- 5 files changed, 127 insertions(+), 36 deletions(-) diff --git a/Silicon/Marvell/Marvell.dec b/Silicon/Marvell/Marvell.dec index 641c53b..2b25ae9 100644 --- a/Silicon/Marvell/Marvell.dec +++ b/Silicon/Marvell/Marvell.dec @@ -137,6 +137,8 @@ #SPI gMarvellTokenSpaceGuid.PcdSpiRegBase|0|UINT32|0x3000051 gMarvellTokenSpaceGuid.PcdSpiMemoryBase|0|UINT64|0x3000059 + gMarvellTokenSpaceGuid.PcdSpiMemoryMapped|TRUE|BOOLEAN|0x3000060 + gMarvellTokenSpaceGuid.PcdSpiVariableOffset|0|UINT32|0x3000061 gMarvellTokenSpaceGuid.PcdSpiMaxFrequency|0|UINT32|0x30000052 gMarvellTokenSpaceGuid.PcdSpiClockFrequency|0|UINT32|0x30000053 =20 diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc b/Silicon/Marvel= l/Armada7k8k/Armada7k8k.dsc.inc index ca3de2e..545b369 100644 --- a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc +++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc @@ -256,6 +256,11 @@ # USB support gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE =20 +[PcdsDynamicDefault.common] + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0xF93C0000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|0xF93E0000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|0xF93D0= 000 + [PcdsFixedAtBuild.common] gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"MARVELL_EFI" gArmPlatformTokenSpaceGuid.PcdCoreCount|4 @@ -396,11 +401,10 @@ # Variable store - default values # gMarvellTokenSpaceGuid.PcdSpiMemoryBase|0xF9000000 - gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0xF93C0000 + gMarvellTokenSpaceGuid.PcdSpiMemoryMapped|TRUE + gMarvellTokenSpaceGuid.PcdSpiVariableOffset|0x3C0000 gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x00010000 - gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|0xF93D0= 000 gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x00010000 - gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|0xF93E0000 gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00010000 =20 !if $(CAPSULE_ENABLE) @@ -558,7 +562,10 @@ # Variable services # Silicon/Marvell/Drivers/Spi/MvFvbDxe/MvFvbDxe.inf - MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf + MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf { + + NULL|EmbeddedPkg/Library/NvVarStoreFormattedLib/NvVarStoreFormattedL= ib.inf + } MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf { AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariabl= eLibNull.inf diff --git a/Silicon/Marvell/Drivers/Spi/MvFvbDxe/MvFvbDxe.inf b/Silicon/Ma= rvell/Drivers/Spi/MvFvbDxe/MvFvbDxe.inf index e222075..128c538 100644 --- a/Silicon/Marvell/Drivers/Spi/MvFvbDxe/MvFvbDxe.inf +++ b/Silicon/Marvell/Drivers/Spi/MvFvbDxe/MvFvbDxe.inf @@ -76,13 +76,17 @@ gMarvellSpiMasterProtocolGuid =20 [FixedPcd] - gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64 gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize - gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64 gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize - gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64 gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize gMarvellTokenSpaceGuid.PcdSpiMemoryBase + gMarvellTokenSpaceGuid.PcdSpiMemoryMapped + gMarvellTokenSpaceGuid.PcdSpiVariableOffset + +[Pcd] + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64 =20 [Depex] gEfiCpuArchProtocolGuid AND diff --git a/Silicon/Marvell/Drivers/Spi/MvFvbDxe/MvFvbDxe.h b/Silicon/Marv= ell/Drivers/Spi/MvFvbDxe/MvFvbDxe.h index 31e6e44..e8df9a5 100644 --- a/Silicon/Marvell/Drivers/Spi/MvFvbDxe/MvFvbDxe.h +++ b/Silicon/Marvell/Drivers/Spi/MvFvbDxe/MvFvbDxe.h @@ -55,6 +55,7 @@ typedef struct { =20 UINT32 Signature; =20 + BOOLEAN IsMemoryMapped; UINTN DeviceBaseAddress; UINTN RegionBaseAddress; UINTN Size; diff --git a/Silicon/Marvell/Drivers/Spi/MvFvbDxe/MvFvbDxe.c b/Silicon/Marv= ell/Drivers/Spi/MvFvbDxe/MvFvbDxe.c index cb006cd..b4fd29c 100644 --- a/Silicon/Marvell/Drivers/Spi/MvFvbDxe/MvFvbDxe.c +++ b/Silicon/Marvell/Drivers/Spi/MvFvbDxe/MvFvbDxe.c @@ -52,6 +52,7 @@ STATIC CONST FVB_DEVICE mMvFvbFlashInstanceTemplate =3D { =20 FVB_FLASH_SIGNATURE, // Signature =20 + FALSE, // IsMemoryMapped ... NEED TO BE FILLED 0, // DeviceBaseAddress ... NEED TO BE FILLED 0, // RegionBaseAddress ... NEED TO BE FILLED SIZE_256KB, // Size @@ -175,11 +176,14 @@ MvFvbInitFvAndVariableStoreHeaders ( FirmwareVolumeHeader->Attributes =3D EFI_FVB2_READ_ENABLED_CAP | EFI_FVB2_READ_STATUS | EFI_FVB2_STICKY_WRITE | - EFI_FVB2_MEMORY_MAPPED | EFI_FVB2_ERASE_POLARITY | EFI_FVB2_WRITE_STATUS | EFI_FVB2_WRITE_ENABLED_CAP; =20 + if (FlashInstance->IsMemoryMapped) { + FirmwareVolumeHeader->Attributes |=3D EFI_FVB2_MEMORY_MAPPED; + } + FirmwareVolumeHeader->HeaderLength =3D sizeof (EFI_FIRMWARE_VOLUME_HEADE= R) + sizeof (EFI_FV_BLOCK_MAP_ENTRY); FirmwareVolumeHeader->Revision =3D EFI_FVH_REVISION; @@ -349,10 +353,13 @@ MvFvbSetAttributes ( EFI_FVB_ATTRIBUTES_2 OldAttributes; EFI_FVB_ATTRIBUTES_2 FlashFvbAttributes; EFI_FVB_ATTRIBUTES_2 UnchangedAttributes; + FVB_DEVICE *FlashInstance; UINT32 Capabilities; UINT32 OldStatus; UINT32 NewStatus; =20 + FlashInstance =3D INSTANCE_FROM_FVB_THIS (This); + // // Obtain attributes from FVB header // @@ -369,12 +376,15 @@ MvFvbSetAttributes ( EFI_FVB2_WRITE_ENABLED_CAP | \ EFI_FVB2_LOCK_CAP | \ EFI_FVB2_STICKY_WRITE | \ - EFI_FVB2_MEMORY_MAPPED | \ EFI_FVB2_ERASE_POLARITY | \ EFI_FVB2_READ_LOCK_CAP | \ EFI_FVB2_WRITE_LOCK_CAP | \ EFI_FVB2_ALIGNMENT; =20 + if (FlashInstance->IsMemoryMapped) { + UnchangedAttributes |=3D EFI_FVB2_MEMORY_MAPPED; + } + // // Some attributes of FV is read only can *not* be set // @@ -692,6 +702,7 @@ MvFvbWrite ( IN UINT8 *Buffer ) { + EFI_STATUS Status; FVB_DEVICE *FlashInstance; UINTN DataOffset; =20 @@ -701,10 +712,27 @@ MvFvbWrite ( FlashInstance->StartLba + Lba, FlashInstance->Media.BlockSize); =20 - return FlashInstance->SpiFlashProtocol->Write (&FlashInstance->SpiDevice, - DataOffset, - *NumBytes, - Buffer); + Status =3D FlashInstance->SpiFlashProtocol->Write (&FlashInstance->SpiDe= vice, + DataOffset, + *NumBytes, + Buffer); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, + "%a: Failed to write to Spi device\n", + __FUNCTION__)); + return Status; + } + + // Update shadow buffer + if (!FlashInstance->IsMemoryMapped) { + DataOffset =3D GET_DATA_OFFSET (FlashInstance->RegionBaseAddress + Off= set, + FlashInstance->StartLba + Lba, + FlashInstance->Media.BlockSize); + + CopyMem ((UINTN *)DataOffset, Buffer, *NumBytes); + } + + return EFI_SUCCESS; } =20 /** @@ -975,6 +1003,9 @@ MvFvbConfigureFlashInstance ( ) { EFI_STATUS Status; + UINTN *NumBytes; + UINTN DataOffset; + UINTN VariableSize, FtwWorkingSize, FtwSpareSize, MemorySize; =20 =20 // Locate SPI protocols @@ -1009,25 +1040,62 @@ MvFvbConfigureFlashInstance ( } =20 // Fill remaining flash description - FlashInstance->DeviceBaseAddress =3D PcdGet64 (PcdSpiMemoryBase); - FlashInstance->RegionBaseAddress =3D FixedPcdGet64 (PcdFlashNvStorageVar= iableBase64); - FlashInstance->FvbOffset =3D FlashInstance->RegionBaseAddress - - FlashInstance->DeviceBaseAddress; - FlashInstance->FvbSize =3D PcdGet32(PcdFlashNvStorageVariableSize) + - PcdGet32(PcdFlashNvStorageFtwWorkingSize) + - PcdGet32(PcdFlashNvStorageFtwSpareSize); + VariableSize =3D PcdGet32 (PcdFlashNvStorageVariableSize); + FtwWorkingSize =3D PcdGet32 (PcdFlashNvStorageFtwWorkingSize); + FtwSpareSize =3D PcdGet32 (PcdFlashNvStorageFtwSpareSize); + + FlashInstance->IsMemoryMapped =3D PcdGetBool (PcdSpiMemoryMapped); + FlashInstance->FvbSize =3D VariableSize + FtwWorkingSize + FtwSpareSize; + FlashInstance->FvbOffset =3D PcdGet32 (PcdSpiVariableOffset); =20 FlashInstance->Media.MediaId =3D 0; FlashInstance->Media.BlockSize =3D FlashInstance->SpiDevice.Info->Sector= Size; FlashInstance->Media.LastBlock =3D FlashInstance->Size / FlashInstance->Media.BlockSize - 1; =20 + if (FlashInstance->IsMemoryMapped) { + FlashInstance->DeviceBaseAddress =3D PcdGet64 (PcdSpiMemoryBase); + FlashInstance->RegionBaseAddress =3D PcdGet64 (PcdFlashNvStorageVariab= leBase64); + } else { + MemorySize =3D EFI_SIZE_TO_PAGES (FlashInstance->FvbSize); + + // FaultTolerantWriteDxe requires memory to be aligned to FtwWorkingSi= ze + FlashInstance->RegionBaseAddress =3D (UINTN) AllocateAlignedRuntimePag= es (MemorySize, + SIZE_64KB); + if (FlashInstance->RegionBaseAddress =3D=3D (UINTN) NULL) { + return EFI_OUT_OF_RESOURCES; + } + + PcdSet64 (PcdFlashNvStorageVariableBase64, + (UINT64) FlashInstance->RegionBaseAddress); + PcdSet64 (PcdFlashNvStorageFtwWorkingBase64, + (UINT64) FlashInstance->RegionBaseAddress + + VariableSize); + PcdSet64 (PcdFlashNvStorageFtwSpareBase64, + (UINT64) FlashInstance->RegionBaseAddress + + VariableSize + + FtwWorkingSize); + + // Fill the buffer with data from flash + DataOffset =3D GET_DATA_OFFSET (FlashInstance->FvbOffset, + FlashInstance->StartLba, + FlashInstance->Media.BlockSize); + *NumBytes =3D FlashInstance->FvbSize; + Status =3D FlashInstance->SpiFlashProtocol->Read (&FlashInstance->SpiD= evice, + DataOffset, + *NumBytes, + (VOID *)FlashInstance->Reg= ionBaseAddress); + if (EFI_ERROR (Status)) { + goto ErrorFreeAllocatedPages; + } + } + Status =3D gBS->InstallMultipleProtocolInterfaces (&FlashInstance->Handl= e, &gEfiDevicePathProtocolGuid, &FlashInstance->DevicePath, &gEfiFirmwareVolumeBlockProtocolGuid, &FlashInstance->Fv= bProtocol, NULL); if (EFI_ERROR (Status)) { - return Status; + goto ErrorFreeAllocatedPages; } =20 Status =3D MvFvbPrepareFvHeader (FlashInstance); @@ -1043,6 +1111,12 @@ ErrorPrepareFvbHeader: &gEfiFirmwareVolumeBlockProtocolGuid, NULL); =20 +ErrorFreeAllocatedPages: + if (!FlashInstance->IsMemoryMapped) { + FreeAlignedPages ((VOID *)FlashInstance->RegionBaseAddress, + MemorySize); + } + return Status; } =20 @@ -1094,24 +1168,27 @@ MvFvbEntryPoint ( // // Declare the Non-Volatile storage as EFI_MEMORY_RUNTIME // - RuntimeMmioRegionSize =3D mFvbDevice->FvbSize; RegionBaseAddress =3D mFvbDevice->RegionBaseAddress; =20 - Status =3D gDS->AddMemorySpace (EfiGcdMemoryTypeMemoryMappedIo, - RegionBaseAddress, - RuntimeMmioRegionSize, - EFI_MEMORY_UC | EFI_MEMORY_RUNTIME); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "%a: Failed to add memory space\n", __FUNCTION__)= ); - goto ErrorAddSpace; - } + if (mFvbDevice->IsMemoryMapped) { + RuntimeMmioRegionSize =3D mFvbDevice->FvbSize; + Status =3D gDS->AddMemorySpace (EfiGcdMemoryTypeMemoryMappedIo, + RegionBaseAddress, + RuntimeMmioRegionSize, + EFI_MEMORY_UC | EFI_MEMORY_RUNTIME); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Failed to add memory space\n", __FUNCTION_= _)); + goto ErrorAddSpace; + } =20 - Status =3D gDS->SetMemorySpaceAttributes (RegionBaseAddress, - RuntimeMmioRegionSize, - EFI_MEMORY_UC | EFI_MEMORY_RUNTIME); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "%a: Failed to set memory attributes\n", __FUNCTI= ON__)); - goto ErrorSetMemAttr; + + Status =3D gDS->SetMemorySpaceAttributes (RegionBaseAddress, + RuntimeMmioRegionSize, + EFI_MEMORY_UC | EFI_MEMORY_RUNTIME); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Failed to set memory attributes\n", __FUNCT= ION__)); + goto ErrorSetMemAttr; + } } =20 // --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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