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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id v136-v6sm1861994lfa.10.2018.08.05.16.28.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 05 Aug 2018 16:28:45 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4864:20::243; helo=mail-lj1-x243.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=kt7ZgfMM5rQH2izJ/B/u4LWPkXJ5eLO/lz6xnOVPFsk=; b=oB8NnY+hqLNAZ1m+bbPwOQ+p9HtS6nUeEOrn9cZh27PYFqPxEJ4YCJaxvzNBCSJoqO xuUDfVqMYvd6oEEKCvG/aLACUNsZrWUPmsVaMli+H0QqzO2ldT5X0Q5uAebreQi79//7 TfpLOyQ04IIoxJSMFZXajbp7caSsyHYX2u5hGPUAYvykd6eis5qB54XYB0oPKW84QcTs hQxd6OTP6sBX3hJlRV5WBmE+MH7pG+on7/hnPB0WLiQ+5HpZ4ACQbco7ElTjlm0mbc5Z OVEXM9Pb8vvotThQiUvPC2ZsjDyQCugMXESSxkw2KGfeFY6TsCOlyyDb9dmLF0Da/EMA kxfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=kt7ZgfMM5rQH2izJ/B/u4LWPkXJ5eLO/lz6xnOVPFsk=; b=RimTpvdaJXf/KsKxsrcDXSou71NmgLBNzppViLnsvXvD1oxxkBLju8QOizClL+TRme yYxD+C9zt52lp4BzkcZv973UZqOMT6Oco/ZFeGUy1VWw5J77iT83SdA926RJ0lPrtUZy sckT8qHc6GXJhn0XPbnIrU2nYNPQ1b+KnaH7dH5emyQxr2lXxxT2rEukyI4UrcFHeKMG 9VgZLzarImR8TlDO2R6Ob5R3e7bNxdetHxcDf1uuBhDlHHNnbVPHxOZX+tuk3mpfXuYl LwqM0psqc1ourAm6BhNG5demlALNRv/kcHgnI7AGPMDiYV/xaYK6VBtjbw5+nrEka4qP MLAA== X-Gm-Message-State: AOUpUlGjsZHYfFOqC19vwb8SIZTM2xip4DTUK7AcNOOPO3dd3pGwGTye Ca35anBYAIfUF1G/AlxVLcmGIgwdm+SfxQ== X-Google-Smtp-Source: AAOMgpfQMnYiLPnLUUB8OCkcWTAqSQpLdwtGcWCenz6erWeUMty9EV8NC6Q9IE/JRE+bNFepcYq0+g== X-Received: by 2002:a2e:3c1a:: with SMTP id j26-v6mr10542904lja.149.1533511726198; Sun, 05 Aug 2018 16:28:46 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Mon, 6 Aug 2018 01:28:18 +0200 Message-Id: <1533511706-9344-2-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1533511706-9344-1-git-send-email-mw@semihalf.com> References: <1533511706-9344-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 1/9] Marvell/Armada7k8k: Import device tree X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jaz@semihalf.com, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Add a device tree description of the Armada7k8k SoCs, whose sources are aligned to the Linux v4.18-rc7. Enablement for each board will be done in the follow-up commits. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Armada7k8k/DeviceTree/armada-7020.dtsi | 16 + Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040-db.dts | 267 +++++++= ++++ Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040.dtsi | 16 + Silicon/Marvell/Armada7k8k/DeviceTree/armada-70x0.dtsi | 64 +++ Silicon/Marvell/Armada7k8k/DeviceTree/armada-8020.dtsi | 26 + Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-db.dts | 336 +++++++= ++++++ Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts | 371 +++++++= ++++++++ Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040.dtsi | 25 + Silicon/Marvell/Armada7k8k/DeviceTree/armada-80x0.dtsi | 108 +++++ Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-dual.dtsi | 31 ++ Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-quad.dtsi | 43 ++ Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806.dtsi | 264 +++++++= +++ Silicon/Marvell/Armada7k8k/DeviceTree/armada-common.dtsi | 10 + Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp110.dtsi | 503 +++++++= +++++++++++++ 14 files changed, 2080 insertions(+) create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-7020.dtsi create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040-db.dts create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040.dtsi create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-70x0.dtsi create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-8020.dtsi create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-db.dts create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin= .dts create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040.dtsi create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-80x0.dtsi create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-dual= .dtsi create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-quad= .dtsi create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806.dtsi create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-common.dtsi create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp110.dtsi diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7020.dtsi b/Silic= on/Marvell/Armada7k8k/DeviceTree/armada-7020.dtsi new file mode 100644 index 0000000..e2edc26 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7020.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2016 Marvell Technology Group Ltd. + * + * Device Tree file for the Armada 7020 SoC, made of an AP806 Dual and + * one CP110. + */ + +#include "armada-ap806-dual.dtsi" +#include "armada-70x0.dtsi" + +/ { + model =3D "Marvell Armada 7020"; + compatible =3D "marvell,armada7020", "marvell,armada-ap806-dual", + "marvell,armada-ap806"; +}; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040-db.dts b/Sil= icon/Marvell/Armada7k8k/DeviceTree/armada-7040-db.dts new file mode 100644 index 0000000..6b28bbe --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040-db.dts @@ -0,0 +1,267 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2016 Marvell Technology Group Ltd. + * + * Device Tree file for Marvell Armada 7040 Development board platform + */ + +#include "armada-7040.dtsi" + +#define GPIO_ACTIVE_HIGH 0 +#define GPIO_ACTIVE_LOW 1 + +/ { + model =3D "Marvell Armada 7040 DB board"; + compatible =3D "marvell,armada7040-db", "marvell,armada7040", + "marvell,armada-ap806-quad", "marvell,armada-ap806"; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + memory@0 { + device_type =3D "memory"; + reg =3D <0x0 0x0 0x0 0x80000000>; + }; + + aliases { + ethernet0 =3D &cp0_eth0; + ethernet1 =3D &cp0_eth1; + ethernet2 =3D &cp0_eth2; + }; + + cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus { + compatible =3D "regulator-fixed"; + regulator-name =3D "usb3h0-vbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + enable-active-high; + gpio =3D <&expander0 0 GPIO_ACTIVE_HIGH>; + }; + + cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus { + compatible =3D "regulator-fixed"; + regulator-name =3D "usb3h1-vbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + enable-active-high; + gpio =3D <&expander0 1 GPIO_ACTIVE_HIGH>; + }; + + cp0_usb3_0_phy: cp0-usb3-0-phy { + compatible =3D "usb-nop-xceiv"; + vcc-supply =3D <&cp0_reg_usb3_0_vbus>; + }; + + cp0_usb3_1_phy: cp0-usb3-1-phy { + compatible =3D "usb-nop-xceiv"; + vcc-supply =3D <&cp0_reg_usb3_1_vbus>; + }; +}; + +&i2c0 { + status =3D "okay"; + clock-frequency =3D <100000>; +}; + +&spi0 { + status =3D "okay"; + + spi-flash@0 { + #address-cells =3D <1>; + #size-cells =3D <1>; + compatible =3D "jedec,spi-nor"; + reg =3D <0>; + spi-max-frequency =3D <10000000>; + + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + partition@0 { + label =3D "U-Boot"; + reg =3D <0 0x200000>; + }; + partition@400000 { + label =3D "Filesystem"; + reg =3D <0x200000 0xce0000>; + }; + }; + }; +}; + +&uart0 { + status =3D "okay"; + pinctrl-0 =3D <&uart0_pins>; + pinctrl-names =3D "default"; +}; + + +&cp0_pcie2 { + status =3D "okay"; +}; + +&cp0_i2c0 { + status =3D "okay"; + clock-frequency =3D <100000>; + + expander0: pca9555@21 { + compatible =3D "nxp,pca9555"; + pinctrl-names =3D "default"; + gpio-controller; + #gpio-cells =3D <2>; + reg =3D <0x21>; + /* + * IO0_0: USB3_PWR_EN0 IO1_0: USB_3_1_Dev_Detect + * IO0_1: USB3_PWR_EN1 IO1_1: USB2_1_current_limit + * IO0_2: DDR3_4_Detect IO1_2: Hcon_IO_RstN + * IO0_3: USB2_DEVICE_DETECT + * IO0_4: GPIO_0 IO1_4: SD_Status + * IO0_5: GPIO_1 IO1_5: LDO_5V_Enable + * IO0_6: IHB_5V_Enable IO1_6: PWR_EN_eMMC + * IO0_7: IO1_7: SDIO_Vcntrl + */ + }; +}; + +&cp0_nand_controller { + /* + * SPI on CPM and NAND have common pins on this board. We can + * use only one at a time. To enable the NAND (which will + * disable the SPI), the "status =3D "okay";" line have to be + * added here. + */ + pinctrl-0 =3D <&nand_pins>, <&nand_rb>; + pinctrl-names =3D "default"; + + nand@0 { + reg =3D <0>; + label =3D "pxa3xx_nand-0"; + nand-rb =3D <0>; + nand-on-flash-bbt; + nand-ecc-strength =3D <4>; + nand-ecc-step-size =3D <512>; + + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + partition@0 { + label =3D "U-Boot"; + reg =3D <0 0x200000>; + }; + + partition@200000 { + label =3D "Linux"; + reg =3D <0x200000 0xe00000>; + }; + + partition@1000000 { + label =3D "Filesystem"; + reg =3D <0x1000000 0x3f000000>; + }; + + }; + }; +}; + +&cp0_spi1 { + status =3D "okay"; + + spi-flash@0 { + #address-cells =3D <0x1>; + #size-cells =3D <0x1>; + compatible =3D "jedec,spi-nor"; + reg =3D <0x0>; + spi-max-frequency =3D <20000000>; + + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + partition@0 { + label =3D "U-Boot"; + reg =3D <0x0 0x200000>; + }; + + partition@400000 { + label =3D "Filesystem"; + reg =3D <0x200000 0xe00000>; + }; + }; + }; +}; + +&cp0_sata0 { + status =3D "okay"; +}; + +&cp0_usb3_0 { + usb-phy =3D <&cp0_usb3_0_phy>; + status =3D "okay"; +}; + +&cp0_usb3_1 { + usb-phy =3D <&cp0_usb3_1_phy>; + status =3D "okay"; +}; + +&ap_sdhci0 { + status =3D "okay"; + bus-width =3D <4>; + no-1-8-v; + non-removable; +}; + +&cp0_sdhci0 { + status =3D "okay"; + bus-width =3D <4>; + no-1-8-v; + cd-gpios =3D <&expander0 12 GPIO_ACTIVE_LOW>; +}; + +&cp0_mdio { + status =3D "okay"; + + phy0: ethernet-phy@0 { + reg =3D <0>; + }; + phy1: ethernet-phy@1 { + reg =3D <1>; + }; +}; + +&cp0_ethernet { + status =3D "okay"; +}; + +&cp0_eth0 { + status =3D "okay"; + /* Network PHY */ + phy-mode =3D "10gbase-kr"; + /* Generic PHY, providing serdes lanes */ + phys =3D <&cp0_comphy2 0>; + + fixed-link { + speed =3D <10000>; + full-duplex; + }; +}; + +&cp0_eth1 { + status =3D "okay"; + /* Network PHY */ + phy =3D <&phy0>; + phy-mode =3D "sgmii"; + /* Generic PHY, providing serdes lanes */ + phys =3D <&cp0_comphy0 1>; +}; + +&cp0_eth2 { + status =3D "okay"; + phy =3D <&phy1>; + phy-mode =3D "rgmii-id"; +}; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040.dtsi b/Silic= on/Marvell/Armada7k8k/DeviceTree/armada-7040.dtsi new file mode 100644 index 0000000..03109b2 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2016 Marvell Technology Group Ltd. + * + * Device Tree file for the Armada 7040 SoC, made of an AP806 Quad and + * one CP110. + */ + +#include "armada-ap806-quad.dtsi" +#include "armada-70x0.dtsi" + +/ { + model =3D "Marvell Armada 7040"; + compatible =3D "marvell,armada7040", "marvell,armada-ap806-quad", + "marvell,armada-ap806"; +}; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-70x0.dtsi b/Silic= on/Marvell/Armada7k8k/DeviceTree/armada-70x0.dtsi new file mode 100644 index 0000000..78f9d87 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-70x0.dtsi @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2017 Marvell Technology Group Ltd. + * + * Device Tree file for the Armada 70x0 SoC + */ + +/ { + aliases { + gpio1 =3D &cp0_gpio1; + gpio2 =3D &cp0_gpio2; + spi1 =3D &cp0_spi0; + spi2 =3D &cp0_spi1; + }; +}; + +/* + * Instantiate the CP110 + */ +#define CP110_NAME cp0 +#define CP110_BASE f2000000 +#define CP110_PCIE_IO_BASE 0xf9000000 +#define CP110_PCIE_MEM_BASE 0xf6000000 +#define CP110_PCIE0_BASE f2600000 +#define CP110_PCIE1_BASE f2620000 +#define CP110_PCIE2_BASE f2640000 + +#include "armada-cp110.dtsi" + +#undef CP110_NAME +#undef CP110_BASE +#undef CP110_PCIE_IO_BASE +#undef CP110_PCIE_MEM_BASE +#undef CP110_PCIE0_BASE +#undef CP110_PCIE1_BASE +#undef CP110_PCIE2_BASE + +&cp0_gpio1 { + status =3D "okay"; +}; + +&cp0_gpio2 { + status =3D "okay"; +}; + +&cp0_syscon0 { + cp0_pinctrl: pinctrl { + compatible =3D "marvell,armada-7k-pinctrl"; + + nand_pins: nand-pins { + marvell,pins =3D + "mpp15", "mpp16", "mpp17", "mpp18", + "mpp19", "mpp20", "mpp21", "mpp22", + "mpp23", "mpp24", "mpp25", "mpp26", + "mpp27"; + marvell,function =3D "dev"; + }; + + nand_rb: nand-rb { + marvell,pins =3D "mpp13"; + marvell,function =3D "nf"; + }; + }; +}; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8020.dtsi b/Silic= on/Marvell/Armada7k8k/DeviceTree/armada-8020.dtsi new file mode 100644 index 0000000..5d76345 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8020.dtsi @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2016 Marvell Technology Group Ltd. + * + * Device Tree file for the Armada 8020 SoC, made of an AP806 Dual and + * two CP110. + */ + +#include "armada-ap806-dual.dtsi" +#include "armada-80x0.dtsi" + +/ { + model =3D "Marvell Armada 8020"; + compatible =3D "marvell,armada8020", "marvell,armada-ap806-dual", + "marvell,armada-ap806"; +}; + +/* The RTC requires external oscillator. But on Aramda 80x0, the RTC clock + * in CP master is not connected (by package) to the oscillator. So + * disable it. However, the RTC clock in CP slave is connected to the + * oscillator so this one is let enabled. + */ + +&cp0_rtc { + status =3D "disabled"; +}; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-db.dts b/Sil= icon/Marvell/Armada7k8k/DeviceTree/armada-8040-db.dts new file mode 100644 index 0000000..7518029 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-db.dts @@ -0,0 +1,336 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2016 Marvell Technology Group Ltd. + * + * Device Tree file for Marvell Armada 8040 Development board platform + */ + +#include "armada-8040.dtsi" + +#define GPIO_ACTIVE_HIGH 0 +#define GPIO_ACTIVE_LOW 1 + +/ { + model =3D "Marvell Armada 8040 DB board"; + compatible =3D "marvell,armada8040-db", "marvell,armada8040", + "marvell,armada-ap806-quad", "marvell,armada-ap806"; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + memory@0 { + device_type =3D "memory"; + reg =3D <0x0 0x0 0x0 0x80000000>; + }; + + aliases { + ethernet0 =3D &cp0_eth0; + ethernet1 =3D &cp0_eth2; + ethernet2 =3D &cp1_eth0; + ethernet3 =3D &cp1_eth1; + }; + + cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus { + compatible =3D "regulator-fixed"; + regulator-name =3D "cp0-usb3h0-vbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + enable-active-high; + gpio =3D <&expander0 0 GPIO_ACTIVE_HIGH>; + }; + + cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus { + compatible =3D "regulator-fixed"; + regulator-name =3D "cp0-usb3h1-vbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + enable-active-high; + gpio =3D <&expander0 1 GPIO_ACTIVE_HIGH>; + }; + + cp0_usb3_0_phy: cp0-usb3-0-phy { + compatible =3D "usb-nop-xceiv"; + vcc-supply =3D <&cp0_reg_usb3_0_vbus>; + }; + + cp0_usb3_1_phy: cp0-usb3-1-phy { + compatible =3D "usb-nop-xceiv"; + vcc-supply =3D <&cp0_reg_usb3_1_vbus>; + }; + + cp1_reg_usb3_0_vbus: cp1-usb3-0-vbus { + compatible =3D "regulator-fixed"; + regulator-name =3D "cp1-usb3h0-vbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + enable-active-high; + gpio =3D <&expander1 0 GPIO_ACTIVE_HIGH>; + }; + + cp1_usb3_0_phy: cp1-usb3-0-phy { + compatible =3D "usb-nop-xceiv"; + vcc-supply =3D <&cp1_reg_usb3_0_vbus>; + }; +}; + +&i2c0 { + status =3D "okay"; + clock-frequency =3D <100000>; +}; + +&spi0 { + status =3D "okay"; + + spi-flash@0 { + #address-cells =3D <1>; + #size-cells =3D <1>; + compatible =3D "jedec,spi-nor"; + reg =3D <0>; + spi-max-frequency =3D <10000000>; + + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + partition@0 { + label =3D "U-Boot"; + reg =3D <0 0x200000>; + }; + partition@400000 { + label =3D "Filesystem"; + reg =3D <0x200000 0xce0000>; + }; + }; + }; +}; + +/* Accessible over the mini-USB CON9 connector on the main board */ +&uart0 { + status =3D "okay"; + pinctrl-0 =3D <&uart0_pins>; + pinctrl-names =3D "default"; +}; + +/* CON6 on CP0 expansion */ +&cp0_pcie0 { + status =3D "okay"; +}; + +/* CON5 on CP0 expansion */ +&cp0_pcie2 { + status =3D "okay"; +}; + +&cp0_i2c0 { + status =3D "okay"; + clock-frequency =3D <100000>; + + /* U31 */ + expander0: pca9555@21 { + compatible =3D "nxp,pca9555"; + pinctrl-names =3D "default"; + gpio-controller; + #gpio-cells =3D <2>; + reg =3D <0x21>; + }; + + /* U25 */ + expander1: pca9555@25 { + compatible =3D "nxp,pca9555"; + pinctrl-names =3D "default"; + gpio-controller; + #gpio-cells =3D <2>; + reg =3D <0x25>; + }; + +}; + +/* CON4 on CP0 expansion */ +&cp0_sata0 { + status =3D "okay"; +}; + +/* CON9 on CP0 expansion */ +&cp0_usb3_0 { + usb-phy =3D <&cp0_usb3_0_phy>; + status =3D "okay"; +}; + +/* CON10 on CP0 expansion */ +&cp0_usb3_1 { + usb-phy =3D <&cp0_usb3_1_phy>; + status =3D "okay"; +}; + +&cp0_mdio { + status =3D "okay"; + + phy1: ethernet-phy@1 { + reg =3D <1>; + }; +}; + +&cp0_ethernet { + status =3D "okay"; +}; + +&cp0_eth0 { + status =3D "okay"; + phy-mode =3D "10gbase-kr"; + + fixed-link { + speed =3D <10000>; + full-duplex; + }; +}; + +&cp0_eth2 { + status =3D "okay"; + phy =3D <&phy1>; + phy-mode =3D "rgmii-id"; +}; + +/* CON6 on CP1 expansion */ +&cp1_pcie0 { + status =3D "okay"; +}; + +/* CON7 on CP1 expansion */ +&cp1_pcie1 { + status =3D "okay"; +}; + +/* CON5 on CP1 expansion */ +&cp1_pcie2 { + status =3D "okay"; +}; + +&cp1_i2c0 { + status =3D "okay"; + clock-frequency =3D <100000>; +}; + +&cp1_spi1 { + status =3D "okay"; + + spi-flash@0 { + #address-cells =3D <0x1>; + #size-cells =3D <0x1>; + compatible =3D "jedec,spi-nor"; + reg =3D <0x0>; + spi-max-frequency =3D <20000000>; + + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + partition@0 { + label =3D "Boot"; + reg =3D <0x0 0x200000>; + }; + partition@200000 { + label =3D "Filesystem"; + reg =3D <0x200000 0xd00000>; + }; + partition@f00000 { + label =3D "Boot_2nd"; + reg =3D <0xf00000 0x100000>; + }; + }; + }; +}; + +/* + * Proper NAND usage will require DPR-76 to be in position 1-2, which disa= bles + * MDIO signal of CP1. + */ +&cp1_nand_controller { + pinctrl-0 =3D <&nand_pins>, <&nand_rb>; + pinctrl-names =3D "default"; + + nand@0 { + reg =3D <0>; + nand-rb =3D <0>; + nand-on-flash-bbt; + nand-ecc-strength =3D <4>; + nand-ecc-step-size =3D <512>; + + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + partition@0 { + label =3D "U-Boot"; + reg =3D <0 0x200000>; + }; + partition@200000 { + label =3D "Linux"; + reg =3D <0x200000 0xe00000>; + }; + partition@1000000 { + label =3D "Filesystem"; + reg =3D <0x1000000 0x3f000000>; + }; + }; + }; +}; + +/* CON4 on CP1 expansion */ +&cp1_sata0 { + status =3D "okay"; +}; + +/* CON9 on CP1 expansion */ +&cp1_usb3_0 { + usb-phy =3D <&cp1_usb3_0_phy>; + status =3D "okay"; +}; + +/* CON10 on CP1 expansion */ +&cp1_usb3_1 { + status =3D "okay"; +}; + +&cp1_mdio { + status =3D "okay"; + + phy0: ethernet-phy@0 { + reg =3D <0>; + }; +}; + +&cp1_ethernet { + status =3D "okay"; +}; + +&cp1_eth0 { + status =3D "okay"; + phy-mode =3D "10gbase-kr"; + + fixed-link { + speed =3D <10000>; + full-duplex; + }; +}; + +&cp1_eth1 { + status =3D "okay"; + phy =3D <&phy0>; + phy-mode =3D "rgmii-id"; +}; + +&ap_sdhci0 { + status =3D "okay"; + bus-width =3D <4>; + non-removable; +}; + +&cp0_sdhci0 { + status =3D "okay"; + bus-width =3D <8>; + non-removable; +}; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts b/= Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts new file mode 100644 index 0000000..0e20e70 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts @@ -0,0 +1,371 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2016 Marvell Technology Group Ltd. + * + * Device Tree file for MACCHIATOBin Armada 8040 community board platform + */ + +#include "armada-8040.dtsi" + +#define GPIO_ACTIVE_HIGH 0 +#define GPIO_ACTIVE_LOW 1 + +/ { + model =3D "Marvell 8040 MACCHIATOBin"; + compatible =3D "marvell,armada8040-mcbin", "marvell,armada8040", + "marvell,armada-ap806-quad", "marvell,armada-ap806= "; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + memory@0 { + device_type =3D "memory"; + reg =3D <0x0 0x0 0x0 0x80000000>; + }; + + aliases { + ethernet0 =3D &cp0_eth0; + ethernet1 =3D &cp1_eth0; + ethernet2 =3D &cp1_eth1; + ethernet3 =3D &cp1_eth2; + }; + + /* Regulator labels correspond with schematics */ + v_3_3: regulator-3-3v { + compatible =3D "regulator-fixed"; + regulator-name =3D "v_3_3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + status =3D "okay"; + }; + + v_vddo_h: regulator-1-8v { + compatible =3D "regulator-fixed"; + regulator-name =3D "v_vddo_h"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-always-on; + status =3D "okay"; + }; + + v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 { + compatible =3D "regulator-fixed"; + enable-active-high; + gpio =3D <&cp0_gpio2 15 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cp0_xhci_vbus_pins>; + regulator-name =3D "v_5v0_usb3_hst_vbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + status =3D "okay"; + }; + + usb3h0_phy: usb3_phy0 { + compatible =3D "usb-nop-xceiv"; + vcc-supply =3D <&v_5v0_usb3_hst_vbus>; + }; + + sfp_eth0: sfp-eth0 { + /* CON15,16 - CPM lane 4 */ + compatible =3D "sff,sfp"; + i2c-bus =3D <&sfpp0_i2c>; + los-gpio =3D <&cp1_gpio1 28 GPIO_ACTIVE_HIGH>; + mod-def0-gpio =3D <&cp1_gpio1 27 GPIO_ACTIVE_LOW>; + tx-disable-gpio =3D <&cp1_gpio1 29 GPIO_ACTIVE_HIGH>; + tx-fault-gpio =3D <&cp1_gpio1 26 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cp1_sfpp0_pins>; + }; + + sfp_eth1: sfp-eth1 { + /* CON17,18 - CPS lane 4 */ + compatible =3D "sff,sfp"; + i2c-bus =3D <&sfpp1_i2c>; + los-gpio =3D <&cp1_gpio1 8 GPIO_ACTIVE_HIGH>; + mod-def0-gpio =3D <&cp1_gpio1 11 GPIO_ACTIVE_LOW>; + tx-disable-gpio =3D <&cp1_gpio1 10 GPIO_ACTIVE_HIGH>; + tx-fault-gpio =3D <&cp0_gpio2 30 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cp1_sfpp1_pins &cp0_sfpp1_pins>; + }; + + sfp_eth3: sfp-eth3 { + /* CON3,4 - CPS lane 5 */ + compatible =3D "sff,sfp"; + i2c-bus =3D <&sfp_1g_i2c>; + los-gpio =3D <&cp0_gpio2 22 GPIO_ACTIVE_HIGH>; + mod-def0-gpio =3D <&cp0_gpio2 21 GPIO_ACTIVE_LOW>; + tx-disable-gpio =3D <&cp1_gpio1 24 GPIO_ACTIVE_HIGH>; + tx-fault-gpio =3D <&cp0_gpio2 19 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cp0_sfp_1g_pins &cp1_sfp_1g_pins>; + }; +}; + +&uart0 { + status =3D "okay"; + pinctrl-0 =3D <&uart0_pins>; + pinctrl-names =3D "default"; +}; + +&ap_sdhci0 { + bus-width =3D <8>; + /* + * Not stable in HS modes - phy needs "more calibration", so add + * the "slow-mode" and disable SDR104, SDR50 and DDR50 modes. + */ + marvell,xenon-phy-slow-mode; + no-1-8-v; + no-sd; + no-sdio; + non-removable; + status =3D "okay"; + vqmmc-supply =3D <&v_vddo_h>; +}; + +&cp0_i2c0 { + clock-frequency =3D <100000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cp0_i2c0_pins>; + status =3D "okay"; +}; + +&cp0_i2c1 { + clock-frequency =3D <100000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cp0_i2c1_pins>; + status =3D "okay"; + + i2c-switch@70 { + compatible =3D "nxp,pca9548"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x70>; + + sfpp0_i2c: i2c@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + }; + sfpp1_i2c: i2c@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + }; + sfp_1g_i2c: i2c@2 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <2>; + }; + }; +}; + +/* J25 UART header */ +&cp0_uart1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cp0_uart1_pins>; + status =3D "okay"; +}; + +&cp0_mdio { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cp0_ge_mdio_pins>; + status =3D "okay"; + + ge_phy: ethernet-phy@0 { + reg =3D <0>; + }; +}; + +&cp0_pcie0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cp0_pcie_pins>; + num-lanes =3D <4>; + num-viewport =3D <8>; + reset-gpio =3D <&cp0_gpio1 20 GPIO_ACTIVE_LOW>; + status =3D "okay"; +}; + +&cp0_pinctrl { + cp0_ge_mdio_pins: ge-mdio-pins { + marvell,pins =3D "mpp32", "mpp34"; + marvell,function =3D "ge"; + }; + cp0_i2c1_pins: i2c1-pins { + marvell,pins =3D "mpp35", "mpp36"; + marvell,function =3D "i2c1"; + }; + cp0_i2c0_pins: i2c0-pins { + marvell,pins =3D "mpp37", "mpp38"; + marvell,function =3D "i2c0"; + }; + cp0_uart1_pins: uart1-pins { + marvell,pins =3D "mpp40", "mpp41"; + marvell,function =3D "uart1"; + }; + cp0_xhci_vbus_pins: xhci0-vbus-pins { + marvell,pins =3D "mpp47"; + marvell,function =3D "gpio"; + }; + cp0_sfp_1g_pins: sfp-1g-pins { + marvell,pins =3D "mpp51", "mpp53", "mpp54"; + marvell,function =3D "gpio"; + }; + cp0_pcie_pins: pcie-pins { + marvell,pins =3D "mpp52"; + marvell,function =3D "gpio"; + }; + cp0_sdhci_pins: sdhci-pins { + marvell,pins =3D "mpp55", "mpp56", "mpp57", "mpp58", "mpp5= 9", + "mpp60", "mpp61"; + marvell,function =3D "sdio"; + }; + cp0_sfpp1_pins: sfpp1-pins { + marvell,pins =3D "mpp62"; + marvell,function =3D "gpio"; + }; +}; + +&cp0_xmdio { + status =3D "okay"; + + phy0: ethernet-phy@0 { + compatible =3D "ethernet-phy-ieee802.3-c45"; + reg =3D <0>; + sfp =3D <&sfp_eth0>; + }; + + phy8: ethernet-phy@8 { + compatible =3D "ethernet-phy-ieee802.3-c45"; + reg =3D <8>; + sfp =3D <&sfp_eth1>; + }; +}; + +&cp0_ethernet { + status =3D "okay"; +}; + +&cp0_eth0 { + status =3D "okay"; + /* Network PHY */ + phy =3D <&phy0>; + phy-mode =3D "10gbase-kr"; + /* Generic PHY, providing serdes lanes */ + phys =3D <&cp0_comphy4 0>; +}; + +&cp0_sata0 { + /* CPM Lane 0 - U29 */ + status =3D "okay"; +}; + +&cp0_sdhci0 { + /* U6 */ + broken-cd; + bus-width =3D <4>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cp0_sdhci_pins>; + status =3D "okay"; + vqmmc-supply =3D <&v_3_3>; +}; + +&cp0_usb3_0 { + /* J38? - USB2.0 only */ + status =3D "okay"; +}; + +&cp0_usb3_1 { + /* J38? - USB2.0 only */ + status =3D "okay"; +}; + +&cp1_ethernet { + status =3D "okay"; +}; + +&cp1_eth0 { + status =3D "okay"; + /* Network PHY */ + phy =3D <&phy8>; + phy-mode =3D "10gbase-kr"; + /* Generic PHY, providing serdes lanes */ + phys =3D <&cp1_comphy4 0>; +}; + +&cp1_eth1 { + /* CPS Lane 0 - J5 (Gigabit RJ45) */ + status =3D "okay"; + /* Network PHY */ + phy =3D <&ge_phy>; + phy-mode =3D "sgmii"; + /* Generic PHY, providing serdes lanes */ + phys =3D <&cp1_comphy0 1>; +}; + +&cp1_eth2 { + /* CPS Lane 5 */ + status =3D "okay"; + /* Network PHY */ + phy-mode =3D "2500base-x"; + managed =3D "in-band-status"; + /* Generic PHY, providing serdes lanes */ + phys =3D <&cp1_comphy5 2>; + sfp =3D <&sfp_eth3>; +}; + +&cp1_pinctrl { + cp1_sfpp1_pins: sfpp1-pins { + marvell,pins =3D "mpp8", "mpp10", "mpp11"; + marvell,function =3D "gpio"; + }; + cp1_spi1_pins: spi1-pins { + marvell,pins =3D "mpp12", "mpp13", "mpp14", "mpp15", "mpp1= 6"; + marvell,function =3D "spi1"; + }; + cp1_uart0_pins: uart0-pins { + marvell,pins =3D "mpp6", "mpp7"; + marvell,function =3D "uart0"; + }; + cp1_sfp_1g_pins: sfp-1g-pins { + marvell,pins =3D "mpp24"; + marvell,function =3D "gpio"; + }; + cp1_sfpp0_pins: sfpp0-pins { + marvell,pins =3D "mpp26", "mpp27", "mpp28", "mpp29"; + marvell,function =3D "gpio"; + }; +}; + +/* J27 UART header */ +&cp1_uart0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cp1_uart0_pins>; + status =3D "okay"; +}; + +&cp1_sata0 { + /* CPS Lane 1 - U32 */ + /* CPS Lane 3 - U31 */ + status =3D "okay"; +}; + +&cp1_spi1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cp1_spi1_pins>; + status =3D "okay"; + + spi-flash@0 { + compatible =3D "st,w25q32"; + spi-max-frequency =3D <50000000>; + reg =3D <0>; + }; +}; + +&cp1_usb3_0 { + /* CPS Lane 2 - CON7 */ + usb-phy =3D <&usb3h0_phy>; + status =3D "okay"; +}; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040.dtsi b/Silic= on/Marvell/Armada7k8k/DeviceTree/armada-8040.dtsi new file mode 100644 index 0000000..784ef3f --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040.dtsi @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2016 Marvell Technology Group Ltd. + * + * Device Tree file for the Armada 8040 SoC, made of an AP806 Quad and + * two CP110. + */ + +#include "armada-ap806-quad.dtsi" +#include "armada-80x0.dtsi" + +/ { + model =3D "Marvell Armada 8040"; + compatible =3D "marvell,armada8040", "marvell,armada-ap806-quad", + "marvell,armada-ap806"; +}; + +/* The RTC requires external oscillator. But on Aramda 80x0, the RTC clock + * in CP master is not connected (by package) to the oscillator. So + * disable it. However, the RTC clock in CP slave is connected to the + * oscillator so this one is let enabled. + */ +&cp0_rtc { + status =3D "disabled"; +}; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-80x0.dtsi b/Silic= on/Marvell/Armada7k8k/DeviceTree/armada-80x0.dtsi new file mode 100644 index 0000000..81967e2 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-80x0.dtsi @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2017 Marvell Technology Group Ltd. + * + * Device Tree file for the Armada 80x0 SoC family + */ + +/ { + aliases { + gpio1 =3D &cp1_gpio1; + gpio2 =3D &cp0_gpio2; + spi1 =3D &cp0_spi0; + spi2 =3D &cp0_spi1; + spi3 =3D &cp1_spi0; + spi4 =3D &cp1_spi1; + }; +}; + +/* + * Instantiate the master CP110 + */ +#define CP110_NAME cp0 +#define CP110_BASE f2000000 +#define CP110_PCIE_IO_BASE 0xf9000000 +#define CP110_PCIE_MEM_BASE 0xf6000000 +#define CP110_PCIE0_BASE f2600000 +#define CP110_PCIE1_BASE f2620000 +#define CP110_PCIE2_BASE f2640000 + +#include "armada-cp110.dtsi" + +#undef CP110_NAME +#undef CP110_BASE +#undef CP110_PCIE_IO_BASE +#undef CP110_PCIE_MEM_BASE +#undef CP110_PCIE0_BASE +#undef CP110_PCIE1_BASE +#undef CP110_PCIE2_BASE + +/* + * Instantiate the slave CP110 + */ +#define CP110_NAME cp1 +#define CP110_BASE f4000000 +#define CP110_PCIE_IO_BASE 0xfd000000 +#define CP110_PCIE_MEM_BASE 0xfa000000 +#define CP110_PCIE0_BASE f4600000 +#define CP110_PCIE1_BASE f4620000 +#define CP110_PCIE2_BASE f4640000 + +#include "armada-cp110.dtsi" + +#undef CP110_NAME +#undef CP110_BASE +#undef CP110_PCIE_IO_BASE +#undef CP110_PCIE_MEM_BASE +#undef CP110_PCIE0_BASE +#undef CP110_PCIE1_BASE +#undef CP110_PCIE2_BASE + +/* The 80x0 has two CP blocks, but uses only one block from each. */ +&cp1_gpio1 { + status =3D "okay"; +}; + +&cp0_gpio2 { + status =3D "okay"; +}; + +&cp0_syscon0 { + cp0_pinctrl: pinctrl { + compatible =3D "marvell,armada-8k-cpm-pinctrl"; + }; +}; + +&cp1_syscon0 { + cp1_pinctrl: pinctrl { + compatible =3D "marvell,armada-8k-cps-pinctrl"; + + nand_pins: nand-pins { + marvell,pins =3D + "mpp0", "mpp1", "mpp2", "mpp3", + "mpp4", "mpp5", "mpp6", "mpp7", + "mpp8", "mpp9", "mpp10", "mpp11", + "mpp15", "mpp16", "mpp17", "mpp18", + "mpp19", "mpp20", "mpp21", "mpp22", + "mpp23", "mpp24", "mpp25", "mpp26", + "mpp27"; + marvell,function =3D "dev"; + }; + + nand_rb: nand-rb { + marvell,pins =3D "mpp13", "mpp12"; + marvell,function =3D "nf"; + }; + }; +}; + +&cp1_crypto { + /* + * The cryptographic engine found on the cp110 + * master is enabled by default at the SoC + * level. Because it is not possible as of now + * to enable two cryptographic engines in + * parallel, disable this one by default. + */ + status =3D "disabled"; +}; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-dual.dtsi b= /Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-dual.dtsi new file mode 100644 index 0000000..5985843 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-dual.dtsi @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2016 Marvell Technology Group Ltd. + * + * Device Tree file for Marvell Armada AP806. + */ + +#include "armada-ap806.dtsi" + +/ { + model =3D "Marvell Armada AP806 Dual"; + compatible =3D "marvell,armada-ap806-dual", "marvell,armada-ap806"; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72", "arm,armv8"; + reg =3D <0x000>; + enable-method =3D "psci"; + }; + cpu@1 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72", "arm,armv8"; + reg =3D <0x001>; + enable-method =3D "psci"; + }; + }; +}; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-quad.dtsi b= /Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-quad.dtsi new file mode 100644 index 0000000..bae0ed9 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-quad.dtsi @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2016 Marvell Technology Group Ltd. + * + * Device Tree file for Marvell Armada AP806. + */ + +#include "armada-ap806.dtsi" + +/ { + model =3D "Marvell Armada AP806 Quad"; + compatible =3D "marvell,armada-ap806-quad", "marvell,armada-ap806"; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72", "arm,armv8"; + reg =3D <0x000>; + enable-method =3D "psci"; + }; + cpu@1 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72", "arm,armv8"; + reg =3D <0x001>; + enable-method =3D "psci"; + }; + cpu@100 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72", "arm,armv8"; + reg =3D <0x100>; + enable-method =3D "psci"; + }; + cpu@101 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72", "arm,armv8"; + reg =3D <0x101>; + enable-method =3D "psci"; + }; + }; +}; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806.dtsi b/Sili= con/Marvell/Armada7k8k/DeviceTree/armada-ap806.dtsi new file mode 100644 index 0000000..66124bf --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806.dtsi @@ -0,0 +1,264 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2016 Marvell Technology Group Ltd. + * + * Device Tree file for Marvell Armada AP806. + */ + +#define IRQ_TYPE_LEVEL_HIGH (1 << 2) +#define IRQ_TYPE_LEVEL_LOW (1 << 3) + +#define GIC_SPI 0 +#define GIC_PPI 1 + +#define GIC_CPU_MASK_RAW(x) ((x) << 8) +#define GIC_CPU_MASK_SIMPLE(num) GIC_CPU_MASK_RAW((1 << (num)) - 1) + +/dts-v1/; + +/ { + model =3D "Marvell Armada AP806"; + compatible =3D "marvell,armada-ap806"; + #address-cells =3D <2>; + #size-cells =3D <2>; + + aliases { + serial0 =3D &uart0; + serial1 =3D &uart1; + gpio0 =3D &ap_gpio; + spi0 =3D &spi0; + }; + + psci { + compatible =3D "arm,psci-0.2"; + method =3D "smc"; + }; + + ap806 { + #address-cells =3D <2>; + #size-cells =3D <2>; + compatible =3D "simple-bus"; + interrupt-parent =3D <&gic>; + ranges; + + config-space@f0000000 { + #address-cells =3D <1>; + #size-cells =3D <1>; + compatible =3D "simple-bus"; + ranges =3D <0x0 0x0 0xf0000000 0x1000000>; + + gic: interrupt-controller@210000 { + compatible =3D "arm,gic-400"; + #interrupt-cells =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + interrupt-controller; + interrupts =3D ; + reg =3D <0x210000 0x10000>, + <0x220000 0x20000>, + <0x240000 0x20000>, + <0x260000 0x20000>; + + gic_v2m0: v2m@280000 { + compatible =3D "arm,gic-v2m-frame"; + msi-controller; + reg =3D <0x280000 0x1000>; + arm,msi-base-spi =3D <160>; + arm,msi-num-spis =3D <32>; + }; + gic_v2m1: v2m@290000 { + compatible =3D "arm,gic-v2m-frame"; + msi-controller; + reg =3D <0x290000 0x1000>; + arm,msi-base-spi =3D <192>; + arm,msi-num-spis =3D <32>; + }; + gic_v2m2: v2m@2a0000 { + compatible =3D "arm,gic-v2m-frame"; + msi-controller; + reg =3D <0x2a0000 0x1000>; + arm,msi-base-spi =3D <224>; + arm,msi-num-spis =3D <32>; + }; + gic_v2m3: v2m@2b0000 { + compatible =3D "arm,gic-v2m-frame"; + msi-controller; + reg =3D <0x2b0000 0x1000>; + arm,msi-base-spi =3D <256>; + arm,msi-num-spis =3D <32>; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + }; + + pmu { + compatible =3D "arm,cortex-a72-pmu"; + interrupt-parent =3D <&pic>; + interrupts =3D <17>; + }; + + odmi: odmi@300000 { + compatible =3D "marvell,odmi-controller"; + interrupt-controller; + msi-controller; + marvell,odmi-frames =3D <4>; + reg =3D <0x300000 0x4000>, + <0x304000 0x4000>, + <0x308000 0x4000>, + <0x30C000 0x4000>; + marvell,spi-base =3D <128>, <136>, <144>, = <152>; + }; + + gicp: gicp@3f0040 { + compatible =3D "marvell,ap806-gicp"; + reg =3D <0x3f0040 0x10>; + marvell,spi-ranges =3D <64 64>, <288 64>; + msi-controller; + }; + + pic: interrupt-controller@3f0100 { + compatible =3D "marvell,armada-8k-pic"; + reg =3D <0x3f0100 0x10>; + #interrupt-cells =3D <1>; + interrupt-controller; + interrupts =3D ; + }; + + xor@400000 { + compatible =3D "marvell,armada-7k-xor", "m= arvell,xor-v2"; + reg =3D <0x400000 0x1000>, + <0x410000 0x1000>; + msi-parent =3D <&gic_v2m0>; + clocks =3D <&ap_clk 3>; + dma-coherent; + }; + + xor@420000 { + compatible =3D "marvell,armada-7k-xor", "m= arvell,xor-v2"; + reg =3D <0x420000 0x1000>, + <0x430000 0x1000>; + msi-parent =3D <&gic_v2m0>; + clocks =3D <&ap_clk 3>; + dma-coherent; + }; + + xor@440000 { + compatible =3D "marvell,armada-7k-xor", "m= arvell,xor-v2"; + reg =3D <0x440000 0x1000>, + <0x450000 0x1000>; + msi-parent =3D <&gic_v2m0>; + clocks =3D <&ap_clk 3>; + dma-coherent; + }; + + xor@460000 { + compatible =3D "marvell,armada-7k-xor", "m= arvell,xor-v2"; + reg =3D <0x460000 0x1000>, + <0x470000 0x1000>; + msi-parent =3D <&gic_v2m0>; + clocks =3D <&ap_clk 3>; + dma-coherent; + }; + + spi0: spi@510600 { + compatible =3D "marvell,armada-380-spi"; + reg =3D <0x510600 0x50>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D ; + clocks =3D <&ap_clk 3>; + status =3D "disabled"; + }; + + i2c0: i2c@511000 { + compatible =3D "marvell,mv78230-i2c"; + reg =3D <0x511000 0x20>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D ; + timeout-ms =3D <1000>; + clocks =3D <&ap_clk 3>; + status =3D "disabled"; + }; + + uart0: serial@512000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x512000 0x100>; + reg-shift =3D <2>; + interrupts =3D ; + reg-io-width =3D <1>; + clocks =3D <&ap_clk 3>; + status =3D "disabled"; + }; + + uart1: serial@512100 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x512100 0x100>; + reg-shift =3D <2>; + interrupts =3D ; + reg-io-width =3D <1>; + clocks =3D <&ap_clk 3>; + status =3D "disabled"; + + }; + + watchdog: watchdog@610000 { + compatible =3D "arm,sbsa-gwdt"; + reg =3D <0x610000 0x1000>, <0x600000 0x100= 0>; + interrupts =3D ; + }; + + ap_sdhci0: sdhci@6e0000 { + compatible =3D "marvell,armada-ap806-sdhci= "; + reg =3D <0x6e0000 0x300>; + interrupts =3D ; + clock-names =3D "core"; + clocks =3D <&ap_clk 4>; + dma-coherent; + marvell,xenon-phy-slow-mode; + status =3D "disabled"; + }; + + ap_syscon: system-controller@6f4000 { + compatible =3D "syscon", "simple-mfd"; + reg =3D <0x6f4000 0x2000>; + + ap_clk: clock { + compatible =3D "marvell,ap806-cloc= k"; + #clock-cells =3D <1>; + }; + + ap_pinctrl: pinctrl { + compatible =3D "marvell,ap806-pinc= trl"; + + uart0_pins: uart0-pins { + marvell,pins =3D "mpp11", = "mpp19"; + marvell,function =3D "uart= 0"; + }; + }; + + ap_gpio: gpio@1040 { + compatible =3D "marvell,armada-8k-= gpio"; + offset =3D <0x1040>; + ngpios =3D <20>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&ap_pinctrl 0 0 2= 0>; + }; + }; + + ap_thermal: thermal@6f808c { + compatible =3D "marvell,armada-ap806-therm= al"; + reg =3D <0x6f808c 0x4>, + <0x6f8084 0x8>; + }; + }; + }; +}; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-common.dtsi b/Sil= icon/Marvell/Armada7k8k/DeviceTree/armada-common.dtsi new file mode 100644 index 0000000..8b610fd --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-common.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2016 Marvell Technology Group Ltd. + */ + +/* Common definitions used by Armada 7K/8K DTs */ +#define PASTER(x, y) x ## y +#define EVALUATOR(x, y) PASTER(x, y) +#define CP110_LABEL(name) EVALUATOR(CP110_NAME, EVALUATOR(_, name)) +#define ADDRESSIFY(addr) EVALUATOR(0x, addr) diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp110.dtsi b/Sili= con/Marvell/Armada7k8k/DeviceTree/armada-cp110.dtsi new file mode 100644 index 0000000..b9504a3 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp110.dtsi @@ -0,0 +1,503 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2016 Marvell Technology Group Ltd. + * + * Device Tree file for Marvell Armada CP110. + */ + +#include "armada-common.dtsi" + +#define ICU_GRP_NSR 0x0 +#define ICU_GRP_SR 0x1 +#define ICU_GRP_SEI 0x4 +#define ICU_GRP_REI 0x5 + +#define CP110_PCIEx_IO_BASE(iface) (CP110_PCIE_IO_BASE + (iface * = 0x10000)) +#define CP110_PCIEx_MEM_BASE(iface) (CP110_PCIE_MEM_BASE + (iface *= 0x1000000)) +#define CP110_PCIEx_CONF_BASE(iface) (CP110_PCIEx_MEM_BASE(iface) += 0xf00000) + +/ { + /* + * The contents of the node are defined below, in order to + * save one indentation level + */ + CP110_NAME: CP110_NAME { }; +}; + +&CP110_NAME { + #address-cells =3D <2>; + #size-cells =3D <2>; + compatible =3D "simple-bus"; + interrupt-parent =3D <&CP110_LABEL(icu)>; + ranges; + + config-space@CP110_BASE { + #address-cells =3D <1>; + #size-cells =3D <1>; + compatible =3D "simple-bus"; + ranges =3D <0x0 0x0 ADDRESSIFY(CP110_BASE) 0x2000000>; + + CP110_LABEL(ethernet): ethernet@0 { + compatible =3D "marvell,armada-7k-pp22"; + reg =3D <0x0 0x100000>, <0x129000 0xb000>; + clocks =3D <&CP110_LABEL(clk) 1 3>, <&CP110_LABEL(= clk) 1 9>, + <&CP110_LABEL(clk) 1 5>, <&CP110_LABEL(cl= k) 1 6>, + <&CP110_LABEL(clk) 1 18>; + clock-names =3D "pp_clk", "gop_clk", + "mg_clk", "mg_core_clk", "axi_clk"; + marvell,system-controller =3D <&CP110_LABEL(syscon= 0)>; + status =3D "disabled"; + dma-coherent; + + CP110_LABEL(eth0): eth0 { + interrupts =3D , + , + , + , + , + ; + interrupt-names =3D "tx-cpu0", "tx-cpu1", = "tx-cpu2", + "tx-cpu3", "rx-shared", "link"; + port-id =3D <0>; + gop-port-id =3D <0>; + status =3D "disabled"; + }; + + CP110_LABEL(eth1): eth1 { + interrupts =3D , + , + , + , + , + ; + interrupt-names =3D "tx-cpu0", "tx-cpu1", = "tx-cpu2", + "tx-cpu3", "rx-shared", "link"; + port-id =3D <1>; + gop-port-id =3D <2>; + status =3D "disabled"; + }; + + CP110_LABEL(eth2): eth2 { + interrupts =3D , + , + , + , + , + ; + interrupt-names =3D "tx-cpu0", "tx-cpu1", = "tx-cpu2", + "tx-cpu3", "rx-shared", "link"; + port-id =3D <2>; + gop-port-id =3D <3>; + status =3D "disabled"; + }; + }; + + CP110_LABEL(comphy): phy@120000 { + compatible =3D "marvell,comphy-cp110"; + reg =3D <0x120000 0x6000>; + marvell,system-controller =3D <&CP110_LABEL(syscon= 0)>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + CP110_LABEL(comphy0): phy@0 { + reg =3D <0>; + #phy-cells =3D <1>; + }; + + CP110_LABEL(comphy1): phy@1 { + reg =3D <1>; + #phy-cells =3D <1>; + }; + + CP110_LABEL(comphy2): phy@2 { + reg =3D <2>; + #phy-cells =3D <1>; + }; + + CP110_LABEL(comphy3): phy@3 { + reg =3D <3>; + #phy-cells =3D <1>; + }; + + CP110_LABEL(comphy4): phy@4 { + reg =3D <4>; + #phy-cells =3D <1>; + }; + + CP110_LABEL(comphy5): phy@5 { + reg =3D <5>; + #phy-cells =3D <1>; + }; + }; + + CP110_LABEL(mdio): mdio@12a200 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "marvell,orion-mdio"; + reg =3D <0x12a200 0x10>; + clocks =3D <&CP110_LABEL(clk) 1 9>, <&CP110_LABEL(= clk) 1 5>, + <&CP110_LABEL(clk) 1 6>, <&CP110_LABEL(cl= k) 1 18>; + status =3D "disabled"; + }; + + CP110_LABEL(xmdio): mdio@12a600 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "marvell,xmdio"; + reg =3D <0x12a600 0x10>; + clocks =3D <&CP110_LABEL(clk) 1 5>, + <&CP110_LABEL(clk) 1 6>, <&CP110_LABEL(cl= k) 1 18>; + status =3D "disabled"; + }; + + CP110_LABEL(icu): interrupt-controller@1e0000 { + compatible =3D "marvell,cp110-icu"; + reg =3D <0x1e0000 0x440>; + #interrupt-cells =3D <3>; + interrupt-controller; + msi-parent =3D <&gicp>; + }; + + CP110_LABEL(rtc): rtc@284000 { + compatible =3D "marvell,armada-8k-rtc"; + reg =3D <0x284000 0x20>, <0x284080 0x24>; + reg-names =3D "rtc", "rtc-soc"; + interrupts =3D ; + }; + + CP110_LABEL(thermal): thermal@400078 { + compatible =3D "marvell,armada-cp110-thermal"; + reg =3D <0x400078 0x4>, + <0x400070 0x8>; + }; + + CP110_LABEL(syscon0): system-controller@440000 { + compatible =3D "syscon", "simple-mfd"; + reg =3D <0x440000 0x2000>; + + CP110_LABEL(clk): clock { + compatible =3D "marvell,cp110-clock"; + #clock-cells =3D <2>; + }; + + CP110_LABEL(gpio1): gpio@100 { + compatible =3D "marvell,armada-8k-gpio"; + offset =3D <0x100>; + ngpios =3D <32>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&CP110_LABEL(pinctrl) 0 0= 32>; + interrupt-controller; + interrupts =3D , + , + , + ; + status =3D "disabled"; + }; + + CP110_LABEL(gpio2): gpio@140 { + compatible =3D "marvell,armada-8k-gpio"; + offset =3D <0x140>; + ngpios =3D <31>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&CP110_LABEL(pinctrl) 0 3= 2 31>; + interrupt-controller; + interrupts =3D , + , + , + ; + status =3D "disabled"; + }; + }; + + CP110_LABEL(usb3_0): usb3@500000 { + compatible =3D "marvell,armada-8k-xhci", + "generic-xhci"; + reg =3D <0x500000 0x4000>; + dma-coherent; + interrupts =3D ; + clock-names =3D "core", "reg"; + clocks =3D <&CP110_LABEL(clk) 1 22>, + <&CP110_LABEL(clk) 1 16>; + status =3D "disabled"; + }; + + CP110_LABEL(usb3_1): usb3@510000 { + compatible =3D "marvell,armada-8k-xhci", + "generic-xhci"; + reg =3D <0x510000 0x4000>; + dma-coherent; + interrupts =3D ; + clock-names =3D "core", "reg"; + clocks =3D <&CP110_LABEL(clk) 1 23>, + <&CP110_LABEL(clk) 1 16>; + status =3D "disabled"; + }; + + CP110_LABEL(sata0): sata@540000 { + compatible =3D "marvell,armada-8k-ahci", + "generic-ahci"; + reg =3D <0x540000 0x30000>; + dma-coherent; + interrupts =3D ; + clocks =3D <&CP110_LABEL(clk) 1 15>, + <&CP110_LABEL(clk) 1 16>; + status =3D "disabled"; + }; + + CP110_LABEL(xor0): xor@6a0000 { + compatible =3D "marvell,armada-7k-xor", "marvell,x= or-v2"; + reg =3D <0x6a0000 0x1000>, <0x6b0000 0x1000>; + dma-coherent; + msi-parent =3D <&gic_v2m0>; + clock-names =3D "core", "reg"; + clocks =3D <&CP110_LABEL(clk) 1 8>, + <&CP110_LABEL(clk) 1 14>; + }; + + CP110_LABEL(xor1): xor@6c0000 { + compatible =3D "marvell,armada-7k-xor", "marvell,x= or-v2"; + reg =3D <0x6c0000 0x1000>, <0x6d0000 0x1000>; + dma-coherent; + msi-parent =3D <&gic_v2m0>; + clock-names =3D "core", "reg"; + clocks =3D <&CP110_LABEL(clk) 1 7>, + <&CP110_LABEL(clk) 1 14>; + }; + + CP110_LABEL(spi0): spi@700600 { + compatible =3D "marvell,armada-380-spi"; + reg =3D <0x700600 0x50>; + #address-cells =3D <0x1>; + #size-cells =3D <0x0>; + clock-names =3D "core", "axi"; + clocks =3D <&CP110_LABEL(clk) 1 21>, + <&CP110_LABEL(clk) 1 17>; + status =3D "disabled"; + }; + + CP110_LABEL(spi1): spi@700680 { + compatible =3D "marvell,armada-380-spi"; + reg =3D <0x700680 0x50>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clock-names =3D "core", "axi"; + clocks =3D <&CP110_LABEL(clk) 1 21>, + <&CP110_LABEL(clk) 1 17>; + status =3D "disabled"; + }; + + CP110_LABEL(i2c0): i2c@701000 { + compatible =3D "marvell,mv78230-i2c"; + reg =3D <0x701000 0x20>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D ; + clock-names =3D "core", "reg"; + clocks =3D <&CP110_LABEL(clk) 1 21>, + <&CP110_LABEL(clk) 1 17>; + status =3D "disabled"; + }; + + CP110_LABEL(i2c1): i2c@701100 { + compatible =3D "marvell,mv78230-i2c"; + reg =3D <0x701100 0x20>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D ; + clock-names =3D "core", "reg"; + clocks =3D <&CP110_LABEL(clk) 1 21>, + <&CP110_LABEL(clk) 1 17>; + status =3D "disabled"; + }; + + CP110_LABEL(uart0): serial@702000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x702000 0x100>; + reg-shift =3D <2>; + interrupts =3D ; + reg-io-width =3D <1>; + clock-names =3D "baudclk", "apb_pclk"; + clocks =3D <&CP110_LABEL(clk) 1 21>, + <&CP110_LABEL(clk) 1 17>; + status =3D "disabled"; + }; + + CP110_LABEL(uart1): serial@702100 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x702100 0x100>; + reg-shift =3D <2>; + interrupts =3D ; + reg-io-width =3D <1>; + clock-names =3D "baudclk", "apb_pclk"; + clocks =3D <&CP110_LABEL(clk) 1 21>, + <&CP110_LABEL(clk) 1 17>; + status =3D "disabled"; + }; + + CP110_LABEL(uart2): serial@702200 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x702200 0x100>; + reg-shift =3D <2>; + interrupts =3D ; + reg-io-width =3D <1>; + clock-names =3D "baudclk", "apb_pclk"; + clocks =3D <&CP110_LABEL(clk) 1 21>, + <&CP110_LABEL(clk) 1 17>; + status =3D "disabled"; + }; + + CP110_LABEL(uart3): serial@702300 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x702300 0x100>; + reg-shift =3D <2>; + interrupts =3D ; + reg-io-width =3D <1>; + clock-names =3D "baudclk", "apb_pclk"; + clocks =3D <&CP110_LABEL(clk) 1 21>, + <&CP110_LABEL(clk) 1 17>; + status =3D "disabled"; + }; + + CP110_LABEL(nand_controller): nand@720000 { + /* + * Due to the limitation of the pins available + * this controller is only usable on the CPM + * for A7K and on the CPS for A8K. + */ + compatible =3D "marvell,armada-8k-nand-controller", + "marvell,armada370-nand-controller"; + reg =3D <0x720000 0x54>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D ; + clock-names =3D "core", "reg"; + clocks =3D <&CP110_LABEL(clk) 1 2>, + <&CP110_LABEL(clk) 1 17>; + marvell,system-controller =3D <&CP110_LABEL(syscon= 0)>; + status =3D "disabled"; + }; + + CP110_LABEL(trng): trng@760000 { + compatible =3D "marvell,armada-8k-rng", + "inside-secure,safexcel-eip76"; + reg =3D <0x760000 0x7d>; + interrupts =3D ; + clock-names =3D "core", "reg"; + clocks =3D <&CP110_LABEL(clk) 1 25>, + <&CP110_LABEL(clk) 1 17>; + status =3D "okay"; + }; + + CP110_LABEL(sdhci0): sdhci@780000 { + compatible =3D "marvell,armada-cp110-sdhci"; + reg =3D <0x780000 0x300>; + interrupts =3D ; + clock-names =3D "core", "axi"; + clocks =3D <&CP110_LABEL(clk) 1 4>, <&CP110_LABEL(= clk) 1 18>; + dma-coherent; + status =3D "disabled"; + }; + + CP110_LABEL(crypto): crypto@800000 { + compatible =3D "inside-secure,safexcel-eip197"; + reg =3D <0x800000 0x200000>; + interrupts =3D , + , + , + , + , + ; + interrupt-names =3D "mem", "ring0", "ring1", + "ring2", "ring3", "eip"; + clock-names =3D "core", "reg"; + clocks =3D <&CP110_LABEL(clk) 1 26>, + <&CP110_LABEL(clk) 1 17>; + dma-coherent; + }; + }; + + CP110_LABEL(pcie0): pcie@CP110_PCIE0_BASE { + compatible =3D "marvell,armada8k-pcie", "snps,dw-pcie"; + reg =3D <0 ADDRESSIFY(CP110_PCIE0_BASE) 0 0x10000>, + <0 CP110_PCIEx_CONF_BASE(0) 0 0x80000>; + reg-names =3D "ctrl", "config"; + #address-cells =3D <3>; + #size-cells =3D <2>; + #interrupt-cells =3D <1>; + device_type =3D "pci"; + dma-coherent; + msi-parent =3D <&gic_v2m0>; + + bus-range =3D <0 0xff>; + ranges =3D + /* downstream I/O */ + <0x81000000 0 CP110_PCIEx_IO_BASE(0) 0 CP110_PCIEx_IO_BAS= E(0) 0 0x10000 + /* non-prefetchable memory */ + 0x82000000 0 CP110_PCIEx_MEM_BASE(0) 0 CP110_PCIEx_MEM_BA= SE(0) 0 0xf00000>; + interrupt-map-mask =3D <0 0 0 0>; + interrupt-map =3D <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 2= 2 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; + num-lanes =3D <1>; + clock-names =3D "core", "reg"; + clocks =3D <&CP110_LABEL(clk) 1 13>, <&CP110_LABEL(clk) 1 = 14>; + status =3D "disabled"; + }; + + CP110_LABEL(pcie1): pcie@CP110_PCIE1_BASE { + compatible =3D "marvell,armada8k-pcie", "snps,dw-pcie"; + reg =3D <0 ADDRESSIFY(CP110_PCIE1_BASE) 0 0x10000>, + <0 CP110_PCIEx_CONF_BASE(1) 0 0x80000>; + reg-names =3D "ctrl", "config"; + #address-cells =3D <3>; + #size-cells =3D <2>; + #interrupt-cells =3D <1>; + device_type =3D "pci"; + dma-coherent; + msi-parent =3D <&gic_v2m0>; + + bus-range =3D <0 0xff>; + ranges =3D + /* downstream I/O */ + <0x81000000 0 CP110_PCIEx_IO_BASE(1) 0 CP110_PCIEx_IO_BAS= E(1) 0 0x10000 + /* non-prefetchable memory */ + 0x82000000 0 CP110_PCIEx_MEM_BASE(1) 0 CP110_PCIEx_MEM_BA= SE(1) 0 0xf00000>; + interrupt-map-mask =3D <0 0 0 0>; + interrupt-map =3D <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 2= 4 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; + + num-lanes =3D <1>; + clock-names =3D "core", "reg"; + clocks =3D <&CP110_LABEL(clk) 1 11>, <&CP110_LABEL(clk) 1 = 14>; + status =3D "disabled"; + }; + + CP110_LABEL(pcie2): pcie@CP110_PCIE2_BASE { + compatible =3D "marvell,armada8k-pcie", "snps,dw-pcie"; + reg =3D <0 ADDRESSIFY(CP110_PCIE2_BASE) 0 0x10000>, + <0 CP110_PCIEx_CONF_BASE(2) 0 0x80000>; + reg-names =3D "ctrl", "config"; + #address-cells =3D <3>; + #size-cells =3D <2>; + #interrupt-cells =3D <1>; + device_type =3D "pci"; + dma-coherent; + msi-parent =3D <&gic_v2m0>; + + bus-range =3D <0 0xff>; + ranges =3D + /* downstream I/O */ + <0x81000000 0 CP110_PCIEx_IO_BASE(2) 0 CP110_PCIEx_IO_BAS= E(2) 0 0x10000 + /* non-prefetchable memory */ + 0x82000000 0 CP110_PCIEx_MEM_BASE(2) 0 CP110_PCIEx_MEM_BA= SE(2) 0 0xf00000>; + interrupt-map-mask =3D <0 0 0 0>; + interrupt-map =3D <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 2= 3 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; + + num-lanes =3D <1>; + clock-names =3D "core", "reg"; + clocks =3D <&CP110_LABEL(clk) 1 12>, <&CP110_LABEL(clk) 1 = 14>; + status =3D "disabled"; + }; +}; --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Fri May 3 05:48:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id v136-v6sm1861994lfa.10.2018.08.05.16.28.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 05 Aug 2018 16:28:46 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4864:20::243; helo=mail-lj1-x243.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ZHqnu4oMYFJmLowjaOsi2idNa2BsHbaygk8Zq6YxEls=; b=xrwcZYYM3Oe8VGe3C9aob+jICr+bsvTtlHjXZK7yAIfx7+FLpmEcoN0DRV6FssO8TS yWq/BTIzbHR/wR5e+Qjr1lgE2CTcAH/weZy25Z4BVO1izVdEFoHbhI6oRgYDX6DV9LYo JvN/J93qAEgyuKZWgOzJtB3dSMb9wTFk+YHW47QYHPy5uZIxsquqDc8T3uLsvvdWUaEO rwsJ9aa3Lmej28SmCrNaMU+gjL73uiBBTssSjvOwAOtbZ9BUu2o8HC/7+8bWUHvqx9bk MZPjnhPVdi2PHO3D5XWb2s3DClzSbZqD/nDTq/bAk9zGSodOjng0sXYQimtXJgjjPSBy QBjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ZHqnu4oMYFJmLowjaOsi2idNa2BsHbaygk8Zq6YxEls=; b=YJGGc5878QrTdp4GPnmfs7x4pt5nMn/GgLFWiDGc6GHQm8DN22J/POyigUaf3ijL4p Kwe2VeDAg93bNDXAU+OAbIZfIuKC/RI7wCfbjvMQWBNLqrqpDkN8Jo8qRmExH6ASF1NZ xECzZB3ymu2FU/fhhpmkZz07N3YVURmaNViRsI+j5ZRq0p/RohzWQhBvdUbwl4Ui5Wrl mgWqNzj365wbhirIfIEPE7EdhyXoCURiHIDvyGi3+zPrmtnfeLDFnf9WKZW3QfnNoi9z wBOWI5RHWrV1dVtUy05We1y71gBoTh269UYTE1LVTW6+S5u/5y5mcZ4/WuYDAuht5jdu gUXA== X-Gm-Message-State: AOUpUlGh8/dpONB8bVaRMOzASwJg4KdyETIPBAuR4qPgcshTy5E1f3sM 6W0eVRt1TSPYWntyc4bCBwrGGuz3qxOzeQ== X-Google-Smtp-Source: AAOMgpeS+TCRdivBbVP2qn8AqfjVZ9gUJpqqj3MYfWDcfDmsGlD+Jy1f4fnhlRE/7wNz+GV6dffNsQ== X-Received: by 2002:a2e:557:: with SMTP id 84-v6mr11526462ljf.152.1533511727228; Sun, 05 Aug 2018 16:28:47 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Mon, 6 Aug 2018 01:28:19 +0200 Message-Id: <1533511706-9344-3-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1533511706-9344-1-git-send-email-mw@semihalf.com> References: <1533511706-9344-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 2/9] Marvell/Armada7k8k: Enable including additional DXE FV components X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jaz@semihalf.com, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Unified .fdf file allows to update all Armada7k8k-based boards at the same time. However there may be a need to add unique DXE firmware volume contents like DTB or ACPI. For this purpose create empty files for existing boards that are included as defined in BOARD_DXE_FV_COMPONENTS macro. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc | 1 + Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc | 1 + Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc | 1 + Silicon/Marvell/Armada7k8k/Armada7k8k.fdf | 2 ++ Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf.inc | 13 +++++++++++= ++ Platform/Marvell/Armada80x0Db/Armada80x0Db.fdf.inc | 13 +++++++++++= ++ Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.fdf.inc | 13 +++++++++++= ++ 7 files changed, 44 insertions(+) create mode 100644 Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf.inc create mode 100644 Platform/Marvell/Armada80x0Db/Armada80x0Db.fdf.inc create mode 100644 Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.fdf.i= nc diff --git a/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc b/Platform/Marv= ell/Armada70x0Db/Armada70x0Db.dsc index 2240a57..0c08328 100644 --- a/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc +++ b/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc @@ -44,6 +44,7 @@ BUILD_TARGETS =3D DEBUG|RELEASE|NOOPT SKUID_IDENTIFIER =3D DEFAULT FLASH_DEFINITION =3D Silicon/Marvell/Armada7k8k/Armada7k8k= .fdf + BOARD_DXE_FV_COMPONENTS =3D Platform/Marvell/Armada70x0Db/Armada7= 0x0Db.fdf.inc =20 !include Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc =20 diff --git a/Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc b/Platform/Marv= ell/Armada80x0Db/Armada80x0Db.dsc index 2425c45..2d4523f2 100644 --- a/Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc +++ b/Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc @@ -44,6 +44,7 @@ BUILD_TARGETS =3D DEBUG|RELEASE|NOOPT SKUID_IDENTIFIER =3D DEFAULT FLASH_DEFINITION =3D Silicon/Marvell/Armada7k8k/Armada7k8k= .fdf + BOARD_DXE_FV_COMPONENTS =3D Platform/Marvell/Armada80x0Db/Armada8= 0x0Db.fdf.inc =20 !include Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc =20 diff --git a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc b/Platfo= rm/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc index 1baed88..e1f5827 100644 --- a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc +++ b/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc @@ -44,6 +44,7 @@ BUILD_TARGETS =3D DEBUG|RELEASE|NOOPT SKUID_IDENTIFIER =3D DEFAULT FLASH_DEFINITION =3D Silicon/Marvell/Armada7k8k/Armada7k8k= .fdf + BOARD_DXE_FV_COMPONENTS =3D Platform/SolidRun/Armada80x0McBin/Arm= ada80x0McBin.fdf.inc CAPSULE_ENABLE =3D TRUE =20 !include Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.fdf b/Silicon/Marvell/Ar= mada7k8k/Armada7k8k.fdf index 18d5d06..0f38978 100644 --- a/Silicon/Marvell/Armada7k8k/Armada7k8k.fdf +++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.fdf @@ -212,6 +212,8 @@ FvNameGuid =3D 5eda4200-2c5f-43cb-9da3-0baf74b1= b30c } !endif =20 +!include $(BOARD_DXE_FV_COMPONENTS) + # PEI phase firmware volume [FV.FVMAIN_COMPACT] FvAlignment =3D 8 diff --git a/Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf.inc b/Platform/= Marvell/Armada70x0Db/Armada70x0Db.fdf.inc new file mode 100644 index 0000000..984cf7e --- /dev/null +++ b/Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf.inc @@ -0,0 +1,13 @@ +# +# Copyright (C) 2018 Marvell International Ltd. and its affiliates +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# + +# Per-board additional content of the DXE phase firmware volume diff --git a/Platform/Marvell/Armada80x0Db/Armada80x0Db.fdf.inc b/Platform/= Marvell/Armada80x0Db/Armada80x0Db.fdf.inc new file mode 100644 index 0000000..984cf7e --- /dev/null +++ b/Platform/Marvell/Armada80x0Db/Armada80x0Db.fdf.inc @@ -0,0 +1,13 @@ +# +# Copyright (C) 2018 Marvell International Ltd. and its affiliates +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# + +# Per-board additional content of the DXE phase firmware volume diff --git a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.fdf.inc b/Pl= atform/SolidRun/Armada80x0McBin/Armada80x0McBin.fdf.inc new file mode 100644 index 0000000..984cf7e --- /dev/null +++ b/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.fdf.inc @@ -0,0 +1,13 @@ +# +# Copyright (C) 2018 Marvell International Ltd. and its affiliates +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# + +# Per-board additional content of the DXE phase firmware volume --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Fri May 3 05:48:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1533511739321151.3595185008071; Sun, 5 Aug 2018 16:28:59 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 7B908210DA14B; Sun, 5 Aug 2018 16:28:52 -0700 (PDT) Received: from mail-lf1-x141.google.com (mail-lf1-x141.google.com [IPv6:2a00:1450:4864:20::141]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id A4DE4210DA140 for ; Sun, 5 Aug 2018 16:28:50 -0700 (PDT) Received: by mail-lf1-x141.google.com with SMTP id v22-v6so7721534lfe.8 for ; Sun, 05 Aug 2018 16:28:50 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id v136-v6sm1861994lfa.10.2018.08.05.16.28.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 05 Aug 2018 16:28:47 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4864:20::141; helo=mail-lf1-x141.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=7iZ8A3OdRvSWpSyGu6Yp4S30g19XWiMC7XU6ONgoB6U=; b=wVIjRzvUrtn/WexuU74ZQT8aepiB9J+Ju6LkCve5it37hydxovmP+m3FsH97/wtP/u z1ZvOeUVfs4LFiMi9/bw8pEU+VlLBntIKgc4GkLw8r80kLRfzFE5vLi3wiQyayaAUkU2 9liRdwvbFH10YJ2IcNcpTsCIW7TH7a3q/5oY01/h/nbvZaz/ozz16L2eKdx5GxC7/Qd5 7oIC77QZUX4ol+korEExz1YMYXvT6MIUQ/x0fpiikvPJo7OIwhrK6FI43IdTpF/hYKLm lk3RJk+MmvbwepM7hGyOrYLKLOqESSqswAq67iGiNjJRqhoGl8KmLih0Zfeka9Xh3MBL KHyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=7iZ8A3OdRvSWpSyGu6Yp4S30g19XWiMC7XU6ONgoB6U=; b=fgYHQLDWAua2YXHUv6fXPIUYGU9MEZekvn+y+piCwpdpkZjWu2UC5OrdkflcLyLvxA A554VdY8dQrTvdwRouENhGnZtmAEXoDWRmO+bJ5+2MLyP3P/Aa6+b6m2oEPsrlP4AdAq VM/MJxUvsEMf757FqOLHzOM/lAAOAr3hyXn5VkHj0enbb8mPZz0Tm0uzCV5bVdJdtwaT MQkNpcV5YM2iF0Lm4g8ED/Sy8FyQPhECI27Wz7MTRG2Mpq0gn6vf7JCNkvtdDnVFnSRz mBsFvUfKiX704UDb6YgeoioECkwCzoyVoLAG3Qm9nB/XcISJHF2pZu3aBSlZRSjgiko/ l/3w== X-Gm-Message-State: AOUpUlHM+YxEuwhzIbXy1KhiQwh3v9HjxlLoZrBRH0914paKc5nt5m5H 7602w5XjHj8lCIZG5h4tk8suiaod7U6Jig== X-Google-Smtp-Source: AAOMgpeigarkwIr1uQCVOvct8yafp1CpWvZl5wWMqHl8zHYQiy5g496Gsw33yGMcwODzZ0jCepc6kg== X-Received: by 2002:a19:1510:: with SMTP id l16-v6mr9256634lfi.88.1533511728319; Sun, 05 Aug 2018 16:28:48 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Mon, 6 Aug 2018 01:28:20 +0200 Message-Id: <1533511706-9344-4-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1533511706-9344-1-git-send-email-mw@semihalf.com> References: <1533511706-9344-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 3/9] Marvell/Armada70x0Db: Enable device tree support X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jaz@semihalf.com, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This patch enables compilation of the Armada 7040 DB device tree. Necessary adjustments are added, so that the OS can use efi-rtc and has no access to the SPI flash Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 4 +++ Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc | 3 +++ Silicon/Marvell/Armada7k8k/Armada7k8k.fdf | 8 ++++++ Silicon/Marvell/Armada7k8k/DeviceTree/Armada70x0Db.inf | 28 ++++++++++++= ++++++++ Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf.inc | 3 +++ Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040-db.dts | 2 +- Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp110.dtsi | 1 + 7 files changed, 48 insertions(+), 1 deletion(-) create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/Armada70x0Db.inf diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc b/Silicon/Marvel= l/Armada7k8k/Armada7k8k.dsc.inc index 2d38ea4..f1ccda0 100644 --- a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc +++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc @@ -200,6 +200,7 @@ PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.= inf MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf NonDiscoverableDeviceRegistrationLib|MdeModulePkg/Library/NonDiscoverabl= eDeviceRegistrationLib/NonDiscoverableDeviceRegistrationLib.inf + DtPlatformDtbLoaderLib|EmbeddedPkg/Library/DxeDtPlatformDtbLoaderLibDefa= ult/DxeDtPlatformDtbLoaderLibDefault.inf =20 [LibraryClasses.common.UEFI_APPLICATION] UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDec= ompressLib/BaseUefiTianoCustomDecompressLib.inf @@ -585,6 +586,9 @@ gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000 } =20 + # DTB + EmbeddedPkg/Drivers/DtPlatformDxe/DtPlatformDxe.inf + !ifdef $(INCLUDE_TFTP_COMMAND) ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf !endif #$(INCLUDE_TFTP_COMMAND) diff --git a/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc b/Platform/Marv= ell/Armada70x0Db/Armada70x0Db.dsc index 0c08328..d3dffb0 100644 --- a/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc +++ b/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc @@ -48,6 +48,9 @@ =20 !include Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc =20 +[Components.common] + Silicon/Marvell/Armada7k8k/DeviceTree/Armada70x0Db.inf + ##########################################################################= ###### # # Pcd Section - list of all EDK II PCD Entries defined by this Platform diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.fdf b/Silicon/Marvell/Ar= mada7k8k/Armada7k8k.fdf index 0f38978..909ad3e 100644 --- a/Silicon/Marvell/Armada7k8k/Armada7k8k.fdf +++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.fdf @@ -212,6 +212,9 @@ FvNameGuid =3D 5eda4200-2c5f-43cb-9da3-0baf74b1= b30c } !endif =20 + # DTB + INF EmbeddedPkg/Drivers/DtPlatformDxe/DtPlatformDxe.inf + !include $(BOARD_DXE_FV_COMPONENTS) =20 # PEI phase firmware volume @@ -400,3 +403,8 @@ READ_LOCK_STATUS =3D TRUE UI STRING=3D"$(MODULE_NAME)" Optional VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R) } + +[Rule.Common.USER_DEFINED.DTB] + FILE FREEFORM =3D $(NAMED_GUID) { + RAW BIN |.dtb + } diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/Armada70x0Db.inf b/Silic= on/Marvell/Armada7k8k/DeviceTree/Armada70x0Db.inf new file mode 100644 index 0000000..1f2d9ea --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/Armada70x0Db.inf @@ -0,0 +1,28 @@ +## @file +# +# Device tree description of the Marvell Armada 7040 DB platform +# +# Copyright (c) 2018, Marvell International Ltd. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +## + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D Armada70x0DbDeviceTree + FILE_GUID =3D 25462CDA-221F-47DF-AC1D-259CFAA4E326 # gDtPlatformDef= aultDtbFileGuid + MODULE_TYPE =3D USER_DEFINED + VERSION_STRING =3D 1.0 + +[Sources] + armada-7040-db.dts + +[Packages] + MdePkg/MdePkg.dec diff --git a/Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf.inc b/Platform/= Marvell/Armada70x0Db/Armada70x0Db.fdf.inc index 984cf7e..b4c3e20 100644 --- a/Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf.inc +++ b/Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf.inc @@ -11,3 +11,6 @@ # =20 # Per-board additional content of the DXE phase firmware volume + + # DTB + INF RuleOverride =3D DTB Silicon/Marvell/Armada7k8k/DeviceTree/Armada70x= 0Db.inf diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040-db.dts b/Sil= icon/Marvell/Armada7k8k/DeviceTree/armada-7040-db.dts index 6b28bbe..f5878ef 100644 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040-db.dts +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040-db.dts @@ -168,7 +168,7 @@ }; =20 &cp0_spi1 { - status =3D "okay"; + status =3D "disabled"; =20 spi-flash@0 { #address-cells =3D <0x1>; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp110.dtsi b/Sili= con/Marvell/Armada7k8k/DeviceTree/armada-cp110.dtsi index b9504a3..3337034 100644 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp110.dtsi +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp110.dtsi @@ -163,6 +163,7 @@ reg =3D <0x284000 0x20>, <0x284080 0x24>; reg-names =3D "rtc", "rtc-soc"; interrupts =3D ; + status =3D "disabled"; }; =20 CP110_LABEL(thermal): thermal@400078 { --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Fri May 3 05:48:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1533511742797321.4055319391764; Sun, 5 Aug 2018 16:29:02 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id B211B210DA150; Sun, 5 Aug 2018 16:28:52 -0700 (PDT) Received: from mail-lf1-x143.google.com (mail-lf1-x143.google.com [IPv6:2a00:1450:4864:20::143]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 24BCB210DA149 for ; Sun, 5 Aug 2018 16:28:52 -0700 (PDT) Received: by mail-lf1-x143.google.com with SMTP id f18-v6so7742450lfc.2 for ; Sun, 05 Aug 2018 16:28:52 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id v136-v6sm1861994lfa.10.2018.08.05.16.28.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 05 Aug 2018 16:28:48 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4864:20::143; helo=mail-lf1-x143.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=fRuwGCcKthuIvPa6Ig7Ixg95TpZUl4ceaxT5AKBx0yA=; b=V7nwiHkkYOJ5L4yXdE7WmFDqYZaPTLUXIFMZurKqkCBYPIJDNe2vYKS4UfVmOKX3Xs Kv7eH7lHKLZZGg03SCvwa6IpTDK4TWhM7nAZ4Tp6KAxJ0XiTC5w8B6bRGt0t1E+lQHO0 57ayhZrHbUI2RaKnshRKydvRDM/aksnWKOjDXq4ppbPrZ2ruuq+fe9iC6UtVONZhgK9B E0BFeR0/NKVSP3ePXOE4rIIUJF6v7p22P2Ck7XtVAkNCr7UCVVbu2EI3sKmZcxdoaca2 lokKv0yDKnb5CyZSO6ZGH6T9JZ8kkvVjzN0oiX7i2pBBt9MGTHZyYHLqMGrS1xTndQs1 HNJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=fRuwGCcKthuIvPa6Ig7Ixg95TpZUl4ceaxT5AKBx0yA=; b=I6Sa3QXt+tFCTqqFMAtFhePCGpQvL9/9X1a/+Cq5wCGhFuJetL/8BqXF3PMjbQttfU WxLtLH9tLiKNKLvExDOqjPRqwBXsJyyxQSiaGcGJHFU60BlN/idu6yIG1ccIVfwGOuZ+ iFVRG5INjkpSeDW3FD5oFadmfXnW6/Aqggg59ViW5o8N9yVXVXGLwKpxmtlJV0loI1Gk 4Xd+GYDQBwY+8qiRM/VG9kf+t5u3bbaGGT7u1DQi/piYooxawAQo+HG0zkpPjeIwvJsm HivOQOjnT+SkmtKm2aweKix38lFyo1//sytANtGxKn0Iwf5Gq7vo21QWg60FtLpi7vL9 suYQ== X-Gm-Message-State: AOUpUlEZsaZrXLLkU2Qn76VulaF9s6d8Q4+HkZexWHyQ+PNAPFFaNVRe p+pzCBB6qHy8O92CHQTMlBkiwfw0Db/q2Q== X-Google-Smtp-Source: AAOMgpfD9RDzO3cXFbGPEigJFk7n9lVVVFFuW0d2Pl25GP0tZDMu14R4NaooUi3fdCnJWKzbiLnFRw== X-Received: by 2002:a19:4c57:: with SMTP id z84-v6mr9271078lfa.67.1533511729469; Sun, 05 Aug 2018 16:28:49 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Mon, 6 Aug 2018 01:28:21 +0200 Message-Id: <1533511706-9344-5-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1533511706-9344-1-git-send-email-mw@semihalf.com> References: <1533511706-9344-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 4/9] Marvell/Armada80x0Db: Enable device tree support X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jaz@semihalf.com, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This patch enables compilation of the Armada 8040 DB device tree. Also disable OS access to the SPI flash. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc | 3 +++ Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0Db.inf | 28 ++++++++++++= ++++++++ Platform/Marvell/Armada80x0Db/Armada80x0Db.fdf.inc | 3 +++ Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-db.dts | 2 +- 4 files changed, 35 insertions(+), 1 deletion(-) create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0Db.inf diff --git a/Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc b/Platform/Marv= ell/Armada80x0Db/Armada80x0Db.dsc index 2d4523f2..3fc33d4 100644 --- a/Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc +++ b/Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc @@ -48,6 +48,9 @@ =20 !include Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc =20 +[Components.common] + Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0Db.inf + ##########################################################################= ###### # # Pcd Section - list of all EDK II PCD Entries defined by this Platform diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0Db.inf b/Silic= on/Marvell/Armada7k8k/DeviceTree/Armada80x0Db.inf new file mode 100644 index 0000000..e4dd41c --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0Db.inf @@ -0,0 +1,28 @@ +## @file +# +# Device tree description of the Marvell Armada 8040 DB platform +# +# Copyright (c) 2018, Marvell International Ltd. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +## + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D Armada80x0DbDeviceTree + FILE_GUID =3D 25462CDA-221F-47DF-AC1D-259CFAA4E326 # gDtPlatformDef= aultDtbFileGuid + MODULE_TYPE =3D USER_DEFINED + VERSION_STRING =3D 1.0 + +[Sources] + armada-8040-db.dts + +[Packages] + MdePkg/MdePkg.dec diff --git a/Platform/Marvell/Armada80x0Db/Armada80x0Db.fdf.inc b/Platform/= Marvell/Armada80x0Db/Armada80x0Db.fdf.inc index 984cf7e..99e1a11 100644 --- a/Platform/Marvell/Armada80x0Db/Armada80x0Db.fdf.inc +++ b/Platform/Marvell/Armada80x0Db/Armada80x0Db.fdf.inc @@ -11,3 +11,6 @@ # =20 # Per-board additional content of the DXE phase firmware volume + + # DTB + INF RuleOverride =3D DTB Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x= 0Db.inf diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-db.dts b/Sil= icon/Marvell/Armada7k8k/DeviceTree/armada-8040-db.dts index 7518029..e813922 100644 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-db.dts +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-db.dts @@ -213,7 +213,7 @@ }; =20 &cp1_spi1 { - status =3D "okay"; + status =3D "disabled"; =20 spi-flash@0 { #address-cells =3D <0x1>; --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Fri May 3 05:48:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1533511746296705.9692053817203; Sun, 5 Aug 2018 16:29:06 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id DE96C210DA14F; Sun, 5 Aug 2018 16:28:54 -0700 (PDT) Received: from mail-lf1-x141.google.com (mail-lf1-x141.google.com [IPv6:2a00:1450:4864:20::141]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 70C80210D978F for ; Sun, 5 Aug 2018 16:28:52 -0700 (PDT) Received: by mail-lf1-x141.google.com with SMTP id u14-v6so7753811lfu.0 for ; Sun, 05 Aug 2018 16:28:52 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id v136-v6sm1861994lfa.10.2018.08.05.16.28.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 05 Aug 2018 16:28:49 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4864:20::141; helo=mail-lf1-x141.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=GiYxA0lZ05JqSmIXcPmjKXMKfgR33aj2/GNiDHQSgNY=; b=Y5Rw+LUikHfPQIACvNCE1C1hcbtWcIwLNVTuJiG5iAX4iWpI+fg4rApQ+wy6Bbxeln vbg0gavKKsEaE4kl11mqkOZZqQ/GqZ+/m3hUaZwTng007z4eOUKKzbEvGdxHjRcCR2NV 6ipkmL25RBGRXWDbu8MoLhsD98vlTFs1iNC1dZP+YPrGLXcrwFdYkgSRvDFt4rt1beaq cvuFQTXvSn7bBh30fAF739nFdZJVu/r9LhIJr38awUqNlDZPgtfSg9l1XUwsChn4BkeQ ZYJmRUuKKEqXn+igeKpCVPp+YviurHbLPlyiTzrTBLIpQxD8iRS2twRchPaDDOtSzmOX Qung== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=GiYxA0lZ05JqSmIXcPmjKXMKfgR33aj2/GNiDHQSgNY=; b=NBEk+t1hVBQ5+zCgqBmNNahn1/kTSBnvaZheehGhzhXsihfaBuvuzwLpsVH6R/PI5C /ZMkmyIP0RhV5nMCtN+kICa8O0J6ffeXZHLt65bMxPZqPN3Nz0c+sUBs3AdpcbZBnOQn tS0Jl/X+i62aLyvBcsNbfqjdxbITXZ2Zp2fVhIXMWErfuL4WRLr2k4RFAsZk5LPnttk0 Q0568ECZGxAfGUuQB2IYkQFMye1nIJTs5mqge+LewUx6lxEidG5VWRLdI/kc+gVW1hGO QzoOjaFKlHT56omaWDVqOiGgish8lzuZxXiavODd0Hs2BiizWV26cdprKVUNipQuQyQP nvzg== X-Gm-Message-State: AOUpUlEmE1KH4Tb62yvqsqf8pK3xho9qVcTO52TY1FsU1Uw1eVCTynMi Gdj3PzSL0KuykP/lcJ52LuR13ZwsrwS4VA== X-Google-Smtp-Source: AAOMgpduZ8/gzYjVmU0xR4OZoU+ic7Ekxk3NeYj7VPYXYcimPwT3H1tZ9cA6fIFNEIbQ14oiR5Wbyg== X-Received: by 2002:a19:e9d7:: with SMTP id j84-v6mr9992088lfk.115.1533511730539; Sun, 05 Aug 2018 16:28:50 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Mon, 6 Aug 2018 01:28:22 +0200 Message-Id: <1533511706-9344-6-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1533511706-9344-1-git-send-email-mw@semihalf.com> References: <1533511706-9344-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 5/9] Marvell/Armada80x0McBin: Enable device tree support X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jaz@semihalf.com, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This patch enables compilation of the Armada 8040 MacchiatoBin device tree. Dsable OS acccess to the SPI flash and extend PCI ranges to use 256MB mmio32 and 4GB mmio64. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc | 3 +++ Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0McBin.inf | 28 +++++++++= +++++++++++ Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.fdf.inc | 3 +++ Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts | 5 +++- 4 files changed, 38 insertions(+), 1 deletion(-) create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0McBin.i= nf diff --git a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc b/Platfo= rm/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc index e1f5827..e6cb0d6 100644 --- a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc +++ b/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc @@ -49,6 +49,9 @@ =20 !include Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc =20 +[Components.common] + Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0McBin.inf + ##########################################################################= ###### # # Pcd Section - list of all EDK II PCD Entries defined by this Platform diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0McBin.inf b/Si= licon/Marvell/Armada7k8k/DeviceTree/Armada80x0McBin.inf new file mode 100644 index 0000000..810a52b --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0McBin.inf @@ -0,0 +1,28 @@ +## @file +# +# Device tree description of the Marvell Armada 8040 MacchiatoBin platform +# +# Copyright (c) 2018, Marvell International Ltd. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +## + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D Armada80x0McBinDeviceTree + FILE_GUID =3D 25462CDA-221F-47DF-AC1D-259CFAA4E326 # gDtPlatformDef= aultDtbFileGuid + MODULE_TYPE =3D USER_DEFINED + VERSION_STRING =3D 1.0 + +[Sources] + armada-8040-mcbin.dts + +[Packages] + MdePkg/MdePkg.dec diff --git a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.fdf.inc b/Pl= atform/SolidRun/Armada80x0McBin/Armada80x0McBin.fdf.inc index 984cf7e..4eb1496 100644 --- a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.fdf.inc +++ b/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.fdf.inc @@ -11,3 +11,6 @@ # =20 # Per-board additional content of the DXE phase firmware volume + + # DTB + INF RuleOverride =3D DTB Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x= 0McBin.inf diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts b/= Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts index 0e20e70..b86e27e 100644 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts @@ -185,6 +185,9 @@ num-lanes =3D <4>; num-viewport =3D <8>; reset-gpio =3D <&cp0_gpio1 20 GPIO_ACTIVE_LOW>; + ranges =3D <0x1000000 0x0 0x00000000 0x0 0xeff00000 0x0 0x00010000= >, + <0x2000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000>, + <0x3000000 0x8 0x00000000 0x8 0x00000000 0x1 0x00000000>; status =3D "okay"; }; =20 @@ -355,7 +358,7 @@ &cp1_spi1 { pinctrl-names =3D "default"; pinctrl-0 =3D <&cp1_spi1_pins>; - status =3D "okay"; + status =3D "disabled"; =20 spi-flash@0 { compatible =3D "st,w25q32"; --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Fri May 3 05:48:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1533511749493421.7697513963609; Sun, 5 Aug 2018 16:29:09 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 1599C210DA159; Sun, 5 Aug 2018 16:28:56 -0700 (PDT) Received: from mail-lf1-x134.google.com (mail-lf1-x134.google.com [IPv6:2a00:1450:4864:20::134]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 4DEBC211F887A for ; Sun, 5 Aug 2018 16:28:54 -0700 (PDT) Received: by mail-lf1-x134.google.com with SMTP id u202-v6so7712056lff.9 for ; Sun, 05 Aug 2018 16:28:54 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id v136-v6sm1861994lfa.10.2018.08.05.16.28.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 05 Aug 2018 16:28:51 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4864:20::134; helo=mail-lf1-x134.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jWs0jsn1KBz7f6KWj9PD/o0zN2Q060UXQcjdwjkkBc8=; b=sfTFcsSDKJUS3f8PeDwDlmY0Xw+zOorO+mn14EDj8l3i0IkYp7WTordhyky05XauK9 6toxc/OZ53MzV3y1PedNZvg5qc8A6CmlZosbkLzk3egSj6fX6RtQN/M+C0aw5cLSX36n DUubbdt9Tu3nv4bKGMGEVNWrh+jd+rV3QbTOn8wOXsGezd17kizS2Zp75nmyXvf/vrIh 056Ahc86p0nTGXSoRjfYgT7Ubnv/4Wqy3nI2CZDk4Ztkr202VjlfqlCr9rjW7wzl2pTN EJ+Q4ldNtFfqD7m6gwLue2yd3RHlosmvUFBH5NHWeFyAXnne5ZFQYU0M2X4yr3YT3LLB IBAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jWs0jsn1KBz7f6KWj9PD/o0zN2Q060UXQcjdwjkkBc8=; b=VK3cW8SKg6o48KtpyZRdnwBsx6A3vn5BwqxVM+DiorCVaAvKvxyWr+WPy9abWgzyh5 E5nfbQ2y9tyIL9fXtR+QNWRgFGxa5zWbwvE2y9p+omcXP94UTT4r8CKgq8mcRtbF/QDi uAFp4WqIhpRmCUmIIyo4VPCYL+vZliUpJdG3NV8Bmw5skOSDgvOqPf+dWR+EUi6YczVv qo4b+ukppixQ4XEDuk9rdLCvhpTllGM2f3+CM1gYXY6LZAYAHnKR7K5YWImaIYCcByhC U3K0eLjKGY4hnhk9n1epWZqqK9NYJvcwQvpPNdOXcs9/vFrAyok77A74TMqquyElFErm d1rg== X-Gm-Message-State: AOUpUlGMT2CQUi3qiws4F1zz/Nj360NuBqFB/a9sBawupO/Tl4ZmcoL1 5p8nL/eUFperMSsbJYc4EpJq5gnVqEKzNg== X-Google-Smtp-Source: AAOMgpfezl7ICN7eQ+mpAYBlWEsqVcCuS47wvptAPdaKHP27Nve1kwEqInFJAeZo/MkcSCjZblZ5bg== X-Received: by 2002:a19:be54:: with SMTP id o81-v6mr9541195lff.31.1533511731793; Sun, 05 Aug 2018 16:28:51 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Mon, 6 Aug 2018 01:28:23 +0200 Message-Id: <1533511706-9344-7-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1533511706-9344-1-git-send-email-mw@semihalf.com> References: <1533511706-9344-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 6/9] Marvell/Armada7k8k: Add common ACPI tables X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jaz@semihalf.com, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This patch adds ACPI tables and necessary headers, which are common for Armada7k8k SoCs. Per-board tables and wiring up of support will be done in the follow-up commits. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Armada7k8k/AcpiTables/AcpiHeader.h | 45 ++++ Silicon/Marvell/Armada7k8k/AcpiTables/IcuInterrupts.h | 42 ++++ Silicon/Marvell/Armada7k8k/AcpiTables/Fadt.aslc | 86 ++++++++ Silicon/Marvell/Armada7k8k/AcpiTables/Gtdt.aslc | 64 ++++++ Silicon/Marvell/Armada7k8k/AcpiTables/Madt.aslc | 139 +++++++++++++ Silicon/Marvell/Armada7k8k/AcpiTables/Pptt.aslc | 216 ++++++++++++++= ++++++ Silicon/Marvell/Armada7k8k/AcpiTables/Spcr.aslc | 53 +++++ 7 files changed, 645 insertions(+) create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/AcpiHeader.h create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/IcuInterrupts.h create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Fadt.aslc create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Gtdt.aslc create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Madt.aslc create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Pptt.aslc create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Spcr.aslc diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/AcpiHeader.h b/Silicon/M= arvell/Armada7k8k/AcpiTables/AcpiHeader.h new file mode 100644 index 0000000..f5ebd27 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/AcpiHeader.h @@ -0,0 +1,45 @@ +/** @file + + Multiple APIC Description Table (MADT) + + Copyright (c) 2017, Linaro Ltd. All rights reserved.
+ Copyright (C) 2018, Marvell International Ltd. and its affiliates.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include + +#define ACPI_OEM_ID_ARRAY {'M','V','E','B','U',' '} +#define ACPI_OEM_REVISION 0 +#define ACPI_CREATOR_ID SIGNATURE_32('L','N','R','O') +#define ACPI_CREATOR_REVISION 0 + +#if defined(ARMADA7K) +#define ACPI_OEM_TABLE_ID SIGNATURE_64('A','R','M','A','D','A','7',= 'K') +#elif defined (ARMADA8K) +#define ACPI_OEM_TABLE_ID SIGNATURE_64('A','R','M','A','D','A','8',= 'K') +#endif + +/** + * A macro to initialize the common header part of EFI ACPI tables + * as defined by EFI_ACPI_DESCRIPTION_HEADER structure. + **/ +#define __ACPI_HEADER(sign, type, rev) { \ + sign, /* UINT32 Signature */ \ + sizeof (type), /* UINT32 Length */ \ + rev, /* UINT8 Revision */ \ + 0, /* UINT8 Checksum */ \ + ACPI_OEM_ID_ARRAY, /* UINT8 OemId[6] */ \ + ACPI_OEM_TABLE_ID, /* UINT64 OemTableId */ \ + ACPI_OEM_REVISION, /* UINT32 OemRevision */ \ + ACPI_CREATOR_ID, /* UINT32 CreatorId */ \ + ACPI_CREATOR_REVISION /* UINT32 CreatorRevision */ \ + } diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/IcuInterrupts.h b/Silico= n/Marvell/Armada7k8k/AcpiTables/IcuInterrupts.h new file mode 100644 index 0000000..5746ad4 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/IcuInterrupts.h @@ -0,0 +1,42 @@ +/** + + Copyright (C) 2018, Marvell International Ltd. and its affiliates. + + This program and the accompanying materials are licensed and made availa= ble + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + + Glossary - abbreviations used in Marvell SampleAtReset library implement= ation: + ICU - Interrupt Consolidation Unit + AP - Application Processor hardware block (Armada 7k8k incorporates AP80= 6) + CP - South Bridge hardware blocks (Armada 7k8k incorporates CP110) + +**/ + +#define CP_GIC_SPI_CP0_PCI0 64 +#define CP_GIC_SPI_CP0_PCI1 65 +#define CP_GIC_SPI_CP0_PCI2 66 +#define CP_GIC_SPI_CP0_SDMMC 67 +#define CP_GIC_SPI_PP2_CP0_PORT0 69, 72, 75, 78, 81, 127 +#define CP_GIC_SPI_PP2_CP0_PORT1 70, 73, 76, 79, 82, 126 +#define CP_GIC_SPI_PP2_CP0_PORT2 71, 74, 77, 80, 83, 125 +#define CP_GIC_SPI_CP0_EIP_RNG0 105 +#define CP_GIC_SPI_CP0_USB_H1 112 +#define CP_GIC_SPI_CP0_USB_H0 113 +#define CP_GIC_SPI_CP0_SATA_H0 114 + +#define CP_GIC_SPI_CP1_PCI0 288 +#define CP_GIC_SPI_CP1_PCI1 289 +#define CP_GIC_SPI_CP1_PCI2 290 +#define CP_GIC_SPI_CP1_SDMMC 291 +#define CP_GIC_SPI_PP2_CP1_PORT0 293, 296, 299, 302, 305, 351 +#define CP_GIC_SPI_PP2_CP1_PORT1 294, 297, 300, 303, 306, 350 +#define CP_GIC_SPI_PP2_CP1_PORT2 295, 298, 301, 304, 307, 349 +#define CP_GIC_SPI_CP1_EIP_RNG0 329 +#define CP_GIC_SPI_CP1_USB_H1 336 +#define CP_GIC_SPI_CP1_USB_H0 337 +#define CP_GIC_SPI_CP1_SATA_H0 338 diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Fadt.aslc b/Silicon/Marv= ell/Armada7k8k/AcpiTables/Fadt.aslc new file mode 100644 index 0000000..de88210 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Fadt.aslc @@ -0,0 +1,86 @@ +/** @file + + Fixed ACPI Description Table (FADT) + + Copyright (c) 2017, Linaro Ltd. All rights reserved.
+ Copyright (C) 2018, Marvell International Ltd. and its affiliates.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include + +#include "AcpiHeader.h" + +#define FADT_FLAGS EFI_ACPI_6_0_HW_REDUCED_ACPI | \ + EFI_ACPI_6_0_LOW_POWER_S0_IDLE_CAPABLE | \ + EFI_ACPI_6_0_HEADLESS + +EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE Fadt =3D { + __ACPI_HEADER (EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE, + EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION), + 0, // UINT32 FirmwareCtrl + 0, // UINT32 Dsdt + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0 + EFI_ACPI_6_0_PM_PROFILE_ENTERPRISE_SERVER, // UINT8 PreferredPmP= rofile + 0, // UINT16 SciInt + 0, // UINT32 SmiCmd + 0, // UINT8 AcpiEnable + 0, // UINT8 AcpiDisable + 0, // UINT8 S4BiosReq + 0, // UINT8 PstateCnt + 0, // UINT32 Pm1aEvtBlk + 0, // UINT32 Pm1bEvtBlk + 0, // UINT32 Pm1aCntBlk + 0, // UINT32 Pm1bCntBlk + 0, // UINT32 Pm2CntBlk + 0, // UINT32 PmTmrBlk + 0, // UINT32 Gpe0Blk + 0, // UINT32 Gpe1Blk + 0, // UINT8 Pm1EvtLen + 0, // UINT8 Pm1CntLen + 0, // UINT8 Pm2CntLen + 0, // UINT8 PmTmrLen + 0, // UINT8 Gpe0BlkLen + 0, // UINT8 Gpe1BlkLen + 0, // UINT8 Gpe1Base + 0, // UINT8 CstCnt + 0, // UINT16 PLvl2Lat + 0, // UINT16 PLvl3Lat + 0, // UINT16 FlushSize + 0, // UINT16 FlushStride + 0, // UINT8 DutyOffset + 0, // UINT8 DutyWidth + 0, // UINT8 DayAlrm + 0, // UINT8 MonAlrm + 0, // UINT8 Century + 0, // UINT16 IaPcBootArch + 0, // UINT8 Reserved1 + FADT_FLAGS, // UINT32 Flags + NULL_GAS, // EFI_ACPI_6_0_GENERIC_AD= DRESS_STRUCTURE ResetReg + 0, // UINT8 ResetValue + EFI_ACPI_6_0_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArch + EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, // UINT8 = MinorVersion + 0, // UINT64 XFirmwareCtrl + 0, // UINT64 XDsdt + NULL_GAS, // EFI_ACPI_6_0_GENERIC_AD= DRESS_STRUCTURE XPm1aEvtBlk + NULL_GAS, // EFI_ACPI_6_0_GENERIC_AD= DRESS_STRUCTURE XPm1bEvtBlk + NULL_GAS, // EFI_ACPI_6_0_GENERIC_AD= DRESS_STRUCTURE XPm1aCntBlk + NULL_GAS, // EFI_ACPI_6_0_GENERIC_AD= DRESS_STRUCTURE XPm1bCntBlk + NULL_GAS, // EFI_ACPI_6_0_GENERIC_AD= DRESS_STRUCTURE XPm2CntBlk + NULL_GAS, // EFI_ACPI_6_0_GENERIC_AD= DRESS_STRUCTURE XPmTmrBlk + NULL_GAS, // EFI_ACPI_6_0_GENERIC_AD= DRESS_STRUCTURE XGpe0Blk + NULL_GAS, // EFI_ACPI_6_0_GENERIC_AD= DRESS_STRUCTURE XGpe1Blk + NULL_GAS, // EFI_ACPI_6_0_GENERIC_AD= DRESS_STRUCTURE SleepControlReg + NULL_GAS // EFI_ACPI_6_0_GENERIC_AD= DRESS_STRUCTURE SleepStatusReg +}; + +VOID CONST * CONST ReferenceAcpiTable =3D &Fadt; diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Gtdt.aslc b/Silicon/Marv= ell/Armada7k8k/AcpiTables/Gtdt.aslc new file mode 100644 index 0000000..16a8806 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Gtdt.aslc @@ -0,0 +1,64 @@ +/** @file + + Multiple APIC Description Table (MADT) + + Copyright (c) 2017, Linaro Ltd. All rights reserved.
+ Copyright (C) 2018, Marvell International Ltd. and its affiliates.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include + +#include "AcpiHeader.h" + +// active low, level triggered +#define GTDT_GTIMER_FLAGS EFI_ACPI_6_0_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILI= TY + +// active high, level triggered +#define GTDT_WDG_FLAGS 0x0 + +#pragma pack(1) +typedef struct { + EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE Header; + EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE SbsaWatchdog; +} ACPI_6_0_GTDT_STRUCTURE; +#pragma pack() + +ACPI_6_0_GTDT_STRUCTURE Gtdt =3D { + { + __ACPI_HEADER (EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE, + ACPI_6_0_GTDT_STRUCTURE, + EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION), + 0xFFFFFFFFFFFFFFFF, // UINT64 PhysicalAdd= ress + 0, // UINT32 Reserved + FixedPcdGet32 (PcdArmArchTimerSecIntrNum), // UINT32 SecureEL1Ti= merGSIV + GTDT_GTIMER_FLAGS, // UINT32 SecureEL1Ti= merFlags + FixedPcdGet32 (PcdArmArchTimerIntrNum), // UINT32 NonSecureEL= 1TimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 NonSecureEL= 1TimerFlags + FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), // UINT32 VirtualTime= rGSIV + GTDT_GTIMER_FLAGS, // UINT32 VirtualTime= rFlags + FixedPcdGet32 (PcdArmArchTimerHypIntrNum), // UINT32 NonSecureEL= 2TimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 NonSecureEL= 2TimerFlags + 0xFFFFFFFFFFFFFFFF, // UINT64 CntReadBase= Address + 0x1, // UINT32 PlatformTim= erCount + sizeof (Gtdt.Header) // UINT32 PlatformTim= erOffset + }, { + EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG, // UINT8 Type + sizeof (Gtdt.SbsaWatchdog), // UINT16 Length + 0x0, // UINT8 Reserved + FixedPcdGet64 (PcdGenericWatchdogRefreshBase), // UINT64 RefreshFram= ePhysicalAddress + FixedPcdGet64 (PcdGenericWatchdogControlBase), // UINT64 WatchdogCon= trolFramePhysicalAddress + FixedPcdGet32 (PcdGenericWatchdogEl2IntrNum), // UINT32 WatchdogTim= erGSIV + GTDT_WDG_FLAGS // UINT32 WatchdogTim= erFlags + }, +}; + +VOID CONST * CONST ReferenceAcpiTable =3D &Gtdt; diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Madt.aslc b/Silicon/Marv= ell/Armada7k8k/AcpiTables/Madt.aslc new file mode 100644 index 0000000..3dae5d3 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Madt.aslc @@ -0,0 +1,139 @@ +/** @file + + Multiple APIC Description Table (MADT) + + Copyright (c) 2017, Linaro Ltd. All rights reserved.
+ Copyright (C) 2018, Marvell International Ltd. and its affiliates.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include + +#include "AcpiHeader.h" + +#define GICC_BASE FixedPcdGet64 (PcdGicInterruptInterfaceB= ase) +#define GICD_BASE FixedPcdGet64 (PcdGicDistributorBase) +#define GICH_BASE 0xF0240000 +#define GICV_BASE 0xF0260000 +#define VGIC_MAINT_INT 25 // SPI #9 + +#define GIC_MSI_FRAME0 0xF0280000 +#define GIC_MSI_FRAME1 0xF0290000 +#define GIC_MSI_FRAME2 0xF02A0000 +#define GIC_MSI_FRAME3 0xF02B0000 + +#define PMU_INTERRUPT_CPU0 130 +#define PMU_INTERRUPT_CPU1 131 +#define PMU_INTERRUPT_CPU2 132 +#define PMU_INTERRUPT_CPU3 133 + +#pragma pack(push, 1) +typedef struct { + EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; + EFI_ACPI_6_0_GIC_STRUCTURE GicC[4]; + EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE GicD; + EFI_ACPI_6_0_GIC_MSI_FRAME_STRUCTURE GicM[4]; +} ACPI_6_0_MADT_STRUCTURE; +#pragma pack(pop) + + +ACPI_6_0_MADT_STRUCTURE Madt =3D { + { + __ACPI_HEADER (EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, + ACPI_6_0_MADT_STRUCTURE, + EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION), + 0, // UINT32 LocalApicAddress + 0 // UINT32 Flags + }, + { + EFI_ACPI_6_0_GICC_STRUCTURE_INIT(0, // GicId + 0x000, // AcpiCpu= Uid + 0x000, // Mpidr + EFI_ACPI_6_0_GIC_ENABLED, // Flags + PMU_INTERRUPT_CPU0, // PmuIrq + GICC_BASE, // GicBase + GICV_BASE, // GicVBase + GICH_BASE, // GicHBase + VGIC_MAINT_INT, // GsivId + 0, // GicRBase + 0 // Efficie= ncy + ), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT(1, // GicId + 0x001, // AcpiCpu= Uid + 0x001, // Mpidr + EFI_ACPI_6_0_GIC_ENABLED, // Flags + PMU_INTERRUPT_CPU1, // PmuIrq + GICC_BASE, // GicBase + GICV_BASE, // GicVBase + GICH_BASE, // GicHBase + VGIC_MAINT_INT, // GsivId + 0, // GicRBase + 0 // Efficie= ncy + ), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT(2, // GicId + 0x100, // AcpiCpu= Uid + 0x100, // Mpidr + EFI_ACPI_6_0_GIC_ENABLED, // Flags + PMU_INTERRUPT_CPU2, // PmuIrq + GICC_BASE, // GicBase + GICV_BASE, // GicVBase + GICH_BASE, // GicHBase + VGIC_MAINT_INT, // GsivId + 0, // GicRBase + 0 // Efficie= ncy + ), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT(3, // GicId + 0x101, // AcpiCpu= Uid + 0x101, // Mpidr + EFI_ACPI_6_0_GIC_ENABLED, // Flags + PMU_INTERRUPT_CPU3, // PmuIrq + GICC_BASE, // GicBase + GICV_BASE, // GicVBase + GICH_BASE, // GicHBase + VGIC_MAINT_INT, // GsivId + 0, // GicRBase + 0 // Efficie= ncy + ), + }, + EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT(0x0, // GicDist= HwId + GICD_BASE, // GicDist= Base + 0x0, // GicDist= Vector + EFI_ACPI_6_0_GIC_V2 // GicVers= ion + ), + { + EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(0x0, // GicMsiF= rameId + GIC_MSI_FRAME0, // BaseAdd= ress + 0, // Flags + 0, // SPICount + 0 // SPIBase + ), + EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(0x1, // GicMsiF= rameId + GIC_MSI_FRAME1, // BaseAdd= ress + 0, // Flags + 0, // SPICount + 0 // SPIBase + ), + EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(0x2, // GicMsiF= rameId + GIC_MSI_FRAME2, // BaseAdd= ress + 0, // Flags + 0, // SPICount + 0 // SPIBase + ), + EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(0x3, // GicMsiF= rameId + GIC_MSI_FRAME3, // BaseAdd= ress + 0, // Flags + 0, // SPICount + 0 // SPIBase + ), + } +}; + +VOID CONST * CONST ReferenceAcpiTable =3D &Madt; diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Pptt.aslc b/Silicon/Marv= ell/Armada7k8k/AcpiTables/Pptt.aslc new file mode 100644 index 0000000..8de29bd3 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Pptt.aslc @@ -0,0 +1,216 @@ +/** @file + + Copyright (c) 2018, Linaro Ltd. All rights reserved.
+ Copyright (c) 2018, Marvell International Ltd. All rights reserved.
+ + This program and the accompanying materials are licensed and made availa= ble + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include + +#include "AcpiHeader.h" + +#define NUM_CORES FixedPcdGet64 (PcdCoreCount) + +#define FIELD_OFFSET(type, name) __builtin_offsetof(type, name) + +#pragma pack(1) +typedef struct { + EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR Core; + UINT32 Offset[2]; + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE DCache; + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE ICache; +} ACPI_6_2_PPTT_CORE; + +typedef struct { + EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR Cluster; + UINT32 Offset[1]; + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE L2Cache; + ACPI_6_2_PPTT_CORE Cores[2]; +} ACPI_6_2_PPTT_CLUSTER; + +typedef struct { + EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR Package; + UINT32 Offset[1]; + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE L3Cache; + ACPI_6_2_PPTT_CLUSTER Clusters[NUM_C= ORES / 2]; +} ACPI_6_2_PPTT_PACKAGE; + +typedef struct { + EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Pptt; + ACPI_6_2_PPTT_PACKAGE Packages[1]; +} ACPI_6_2_PPTT_STRUCTURE; +#pragma pack() + +#define PPTT_CORE(pid, cid, id) { = \ + { = \ + EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR, = \ + FIELD_OFFSET (ACPI_6_2_PPTT_CORE, DCache), = \ + {}, = \ + { = \ + 0, /* PhysicalPackage */ = \ + EFI_ACPI_6_2_PPTT_PROCESSOR_ID_VALID, /* AcpiProcessorIdValid */= \ + }, = \ + FIELD_OFFSET (ACPI_6_2_PPTT_STRUCTURE, = \ + Packages[pid].Clusters[cid]), /* Parent */ = \ + 256 * (cid) + (id), /* AcpiProcessorId */ = \ + 2, /* NumberOfPrivateResource= s */ \ + }, { = \ + FIELD_OFFSET (ACPI_6_2_PPTT_STRUCTURE, = \ + Packages[pid].Clusters[cid].Cores[id].DCache), = \ + FIELD_OFFSET (ACPI_6_2_PPTT_STRUCTURE, = \ + Packages[pid].Clusters[cid].Cores[id].ICache), = \ + }, { = \ + EFI_ACPI_6_2_PPTT_TYPE_CACHE, = \ + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), = \ + {}, = \ + { = \ + 1, /* SizePropertyValid */ = \ + 1, /* NumberOfSetsValid */ = \ + 1, /* AssociativityValid */ = \ + 1, /* AllocationTypeValid */ = \ + 1, /* CacheTypeValid */ = \ + 1, /* WritePolicyValid */ = \ + 1, /* LineSizeValid */ = \ + }, = \ + 0, /* NextLevelOfCache */ = \ + SIZE_32KB, /* Size */ = \ + 256, /* NumberOfSets */ = \ + 2, /* Associativity */ = \ + { = \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, = \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_DATA, = \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, = \ + }, = \ + 64 /* LineSize */ = \ + }, { = \ + EFI_ACPI_6_2_PPTT_TYPE_CACHE, = \ + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), = \ + {}, = \ + { = \ + 1, /* SizePropertyValid */ = \ + 1, /* NumberOfSetsValid */ = \ + 1, /* AssociativityValid */ = \ + 1, /* AllocationTypeValid */ = \ + 1, /* CacheTypeValid */ = \ + 0, /* WritePolicyValid */ = \ + 1, /* LineSizeValid */ = \ + }, = \ + 0, /* NextLevelOfCache */ = \ + 3 * SIZE_16KB, /* Size */ = \ + 256, /* NumberOfSets */ = \ + 3, /* Associativity */ = \ + { = \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ, /* AllocationType = */ \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION, = \ + 0, /* WritePolicy */ = \ + }, = \ + 64 /* LineSize */ = \ + } = \ +} + +#define PPTT_CLUSTER(pid, cid) { = \ + { = \ + EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR, = \ + FIELD_OFFSET (ACPI_6_2_PPTT_CLUSTER, L2Cache), = \ + {}, = \ + { = \ + 0, /* PhysicalPackage */ = \ + EFI_ACPI_6_2_PPTT_PROCESSOR_ID_INVALID, /* AcpiProcessorIdValid */ = \ + }, = \ + FIELD_OFFSET (ACPI_6_2_PPTT_STRUCTURE, Packages[pid]), /* Parent */ = \ + 0, /* AcpiProcessorId */ = \ + 1, /* NumberOfPrivateResources = */ \ + }, { = \ + FIELD_OFFSET (ACPI_6_2_PPTT_STRUCTURE, Packages[pid].Clusters[cid].L2C= ache), \ + }, { = \ + EFI_ACPI_6_2_PPTT_TYPE_CACHE, = \ + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), = \ + {}, = \ + { = \ + 1, /* SizePropertyValid */ = \ + 1, /* NumberOfSetsValid */ = \ + 1, /* AssociativityValid */ = \ + 1, /* AllocationTypeValid */ = \ + 1, /* CacheTypeValid */ = \ + 1, /* WritePolicyValid */ = \ + 1, /* LineSizeValid */ = \ + }, = \ + 0, /* NextLevelOfCache */ = \ + SIZE_512KB, /* Size */ = \ + 256, /* NumberOfSets */ = \ + 16, /* Associativity */ = \ + { = \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, = \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, = \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, = \ + }, = \ + 64 /* LineSize */ = \ + }, { = \ + PPTT_CORE(pid, cid, 0), = \ + PPTT_CORE(pid, cid, 1), = \ + } = \ +} + +ACPI_6_2_PPTT_STRUCTURE Pptt =3D { + { + __ACPI_HEADER(EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTU= RE_SIGNATURE, + ACPI_6_2_PPTT_STRUCTURE, + EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVIS= ION), + }, + { + { + { + EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR, + FIELD_OFFSET (ACPI_6_2_PPTT_PACKAGE, L3Cache), + {}, + { + 1, /* PhysicalPackage */ + EFI_ACPI_6_2_PPTT_PROCESSOR_ID_INVALID, /* AcpiProcessorIdValid = */ + }, + 0, /* Parent */ + 0, /* AcpiProcessorId */ + 1, /* NumberOfPrivateResour= ces */ + }, { + FIELD_OFFSET (ACPI_6_2_PPTT_STRUCTURE, Packages[0].L3Cache), + }, { + EFI_ACPI_6_2_PPTT_TYPE_CACHE, + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), + {}, + { + 1, /* SizePropertyValid */ + 1, /* NumberOfSetsValid */ + 1, /* AssociativityValid */ + 1, /* AllocationTypeValid */ + 1, /* CacheTypeValid */ + 1, /* WritePolicyValid */ + 1, /* LineSizeValid */ + }, + 0, /* NextLevelOfCache */ + SIZE_1MB, /* Size */ + 2048, /* NumberOfSets */ + 8, /* Associativity */ + { + 0, /* AllocationType */ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, + EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, + }, + 64 /* LineSize */ + }, { + PPTT_CLUSTER (0, 0), +#if NUM_CORES > 3 + PPTT_CLUSTER (0, 1), +#endif + } + } + } +}; + +VOID * CONST ReferenceAcpiTable =3D &Pptt; diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Spcr.aslc b/Silicon/Marv= ell/Armada7k8k/AcpiTables/Spcr.aslc new file mode 100644 index 0000000..e78bb90 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Spcr.aslc @@ -0,0 +1,53 @@ +/** @file + Serial Port Console Redirection Table (SPCR) + + Copyright (c) 2017, Linaro Limited. All rights reserved. + Copyright (C) 2018, Marvell International Ltd. and its affiliates. + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + + Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ + +**/ + +#include +#include + +#include "AcpiHeader.h" + +EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr =3D { + __ACPI_HEADER(EFI_ACPI_6_1_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATU= RE, + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE, + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_REVISION + ), + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_16550, //= InterfaceType + { EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE }, //= Reserved1[3] + ARM_GAS32 (FixedPcdGet64(PcdSerialRegisterBase)), //= BaseAddress + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_GIC, //= InterruptType + 0, //= Irq + 51, //= GlobalSystemInterrupt + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_115200, //= BaudRate + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_PARITY_NO_PARITY, //= Parity + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_STOP_BITS_1, //= StopBits + 0, //= FlowControl + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_ANSI, //= TerminalType + EFI_ACPI_RESERVED_BYTE, //= Language + 0xFFFF, //= PciDeviceId + 0xFFFF, //= PciVendorId + 0, //= PciBusNumber + 0, //= PciDeviceNumber + 0, //= PciFunctionNumber + 0, //= PciFlags + 0, //= PciSegment + EFI_ACPI_RESERVED_DWORD //= Reserved2 +}; + +VOID CONST * CONST ReferenceAcpiTable =3D &Spcr; --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Fri May 3 05:48:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1533511752880843.7657943575302; Sun, 5 Aug 2018 16:29:12 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 41E44210DA160; Sun, 5 Aug 2018 16:28:57 -0700 (PDT) Received: from mail-lf1-x143.google.com (mail-lf1-x143.google.com [IPv6:2a00:1450:4864:20::143]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 00DDE210DA155 for ; Sun, 5 Aug 2018 16:28:54 -0700 (PDT) Received: by mail-lf1-x143.google.com with SMTP id a134-v6so7740063lfe.6 for ; Sun, 05 Aug 2018 16:28:54 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id v136-v6sm1861994lfa.10.2018.08.05.16.28.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 05 Aug 2018 16:28:52 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4864:20::143; helo=mail-lf1-x143.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=OhIpMqMGfSnk890q9bbeUANr77waTVGw3XXvMhXvdC4=; b=PQPp/Ii9wZgR+93Q47qwkpo+H//3JuC3CHdqNXyiN3y1M8rlCg2084KV8AHsqHEQ+5 dnPTlxNi8gRXiqG3db8PPyXdmkEyAoRoo60obIK/hQSwv00VGaAEQTyQMIprvf0Ipx/H JqysR+YCaXunpLlWjkFRCr5BIbgJYrrYNV/IFR3ZITe7+GUq2S3hbRFkB3Gnk/b4ECQv esG2XwtwYX1xpt/Bo2Qwfb43GEUdSKHmkppcjAQV4/SBl639jyWTGGiNM2oDFzq6SKtl HFpSLTKq0nrkAAyestYmmHcGuhxzV8uX5LdSOmkyMAQWzDCeFPWqC6U+5YZXeH8nmgMn Wb0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=OhIpMqMGfSnk890q9bbeUANr77waTVGw3XXvMhXvdC4=; b=g0U3YMY6js9KnlsYFtwIWHlCjcz4HPWUcD2l9KywHtEzNcxSc0wIFrESJGRjAkAZe5 7nACKE1KkECYkwH9Gj2GcGsIzPpcF3uoUEXVgm0zxbHHC+C4H9pwD9LGjR1V7xw8ctay rGB+9mqZQoiFwrkenIxo/eEQBVaGqjyc6AO5GTB+jPrcMushu6H1dmGkHzZAOZY1+a4m RK9Dwle1UbEvEo3ExIJDf56O3cbhuWaUimtXuVY2AUnTtA2Laulg8sENywIKNWOFQ4RF jVaJJMnmbEnjeWs6R5E7cGou9HSwftfEACO4Bgp0rWwd0HabhfvyMhZNMZRjuS7HxA/X cDXQ== X-Gm-Message-State: AOUpUlH5ACS1XTohQOlXgQRLjsWstUMi3Wh2WS3njKNLwF7Iidax8mW4 D2i5V+TVLHbCV7vDf8wwuFhG+Ia1CGu42g== X-Google-Smtp-Source: AAOMgpfRBMPoPBYbJi608EQV5dJE8ekANCX2gF64cIz3TF0EKyQVR5Xv+6eS70xwPynywQqoWLNA9Q== X-Received: by 2002:a19:9710:: with SMTP id z16-v6mr9219039lfd.17.1533511732875; Sun, 05 Aug 2018 16:28:52 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Mon, 6 Aug 2018 01:28:24 +0200 Message-Id: <1533511706-9344-8-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1533511706-9344-1-git-send-email-mw@semihalf.com> References: <1533511706-9344-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 7/9] Marvell/Armada70x0Db: Enable ACPI support X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jaz@semihalf.com, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This patch introduces DSDT table and adds necessary wiring in order to enable ACPI support on Armada 7040 DB. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 14 ++ Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc | 3 + Silicon/Marvell/Armada7k8k/Armada7k8k.fdf | 12 + Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/AcpiTables.inf | 61 ++= ++++ Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf.inc | 5 + Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl | 229 ++= ++++++++++++++++++ Silicon/Marvell/Documentation/PortingGuide.txt | 22 ++ 7 files changed, 346 insertions(+) create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Acpi= Tables.inf create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt= .asl diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc b/Silicon/Marvel= l/Armada7k8k/Armada7k8k.dsc.inc index f1ccda0..d4c67a2 100644 --- a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc +++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc @@ -593,6 +593,20 @@ ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf !endif #$(INCLUDE_TFTP_COMMAND) =20 +[Components.AARCH64] + # + # Generic ACPI modules + # + MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf + MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf { + + PlatformHasAcpiLib|EmbeddedPkg/Library/PlatformHasAcpiLib/PlatformHa= sAcpiLib.inf + + + # support ACPI v5.0 or later + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20 + } + [BuildOptions.common.EDKII.DXE_CORE,BuildOptions.common.EDKII.DXE_DRIVER,B= uildOptions.common.EDKII.UEFI_DRIVER,BuildOptions.common.EDKII.UEFI_APPLICA= TION] GCC:*_*_*_DLINK_FLAGS =3D -z common-page-size=3D0x1000 =20 diff --git a/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc b/Platform/Marv= ell/Armada70x0Db/Armada70x0Db.dsc index d3dffb0..f6faff1 100644 --- a/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc +++ b/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc @@ -51,6 +51,9 @@ [Components.common] Silicon/Marvell/Armada7k8k/DeviceTree/Armada70x0Db.inf =20 +[Components.AARCH64] + Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/AcpiTables.inf + ##########################################################################= ###### # # Pcd Section - list of all EDK II PCD Entries defined by this Platform diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.fdf b/Silicon/Marvell/Ar= mada7k8k/Armada7k8k.fdf index 909ad3e..c064a43 100644 --- a/Silicon/Marvell/Armada7k8k/Armada7k8k.fdf +++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.fdf @@ -215,6 +215,12 @@ FvNameGuid =3D 5eda4200-2c5f-43cb-9da3-0baf74b= 1b30c # DTB INF EmbeddedPkg/Drivers/DtPlatformDxe/DtPlatformDxe.inf =20 +!if $(ARCH) =3D=3D AARCH64 + # ACPI support + INF MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf + INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf +!endif + !include $(BOARD_DXE_FV_COMPONENTS) =20 # PEI phase firmware volume @@ -408,3 +414,9 @@ READ_LOCK_STATUS =3D TRUE FILE FREEFORM =3D $(NAMED_GUID) { RAW BIN |.dtb } + +[Rule.Common.USER_DEFINED.ACPITABLE] + FILE FREEFORM =3D $(NAMED_GUID) { + RAW ASL |.aml + RAW ACPI |.acpi + } diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/AcpiTables.= inf b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/AcpiTables.inf new file mode 100644 index 0000000..8732e10 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/AcpiTables.inf @@ -0,0 +1,61 @@ +## @file +# Component description file for PlatformAcpiTables module. +# +# ACPI table data and ASL sources required to boot the platform. +# +# Copyright (c) 2018, Linaro, Ltd. All rights reserved.
+# Copyright (C) 2018, Marvell International Ltd. and its affiliates.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +## + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D PlatformAcpiTables + FILE_GUID =3D 7E374E25-8E01-4FEE-87F2-390C23C606CD + MODULE_TYPE =3D USER_DEFINED + VERSION_STRING =3D 1.0 + +[Sources] + Dsdt.asl + ../Fadt.aslc + ../Gtdt.aslc + ../Madt.aslc + ../Pptt.aslc + ../Spcr.aslc + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Marvell/Marvell.dec + +[FixedPcd] + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase + gArmTokenSpaceGuid.PcdGicDistributorBase + + gArmPlatformTokenSpaceGuid.PcdCoreCount + + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum + + gArmTokenSpaceGuid.PcdGenericWatchdogControlBase + gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase + gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum + + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate + +[BuildOptions] + *_*_*_ASLCC_FLAGS =3D -DARMADA7K diff --git a/Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf.inc b/Platform/= Marvell/Armada70x0Db/Armada70x0Db.fdf.inc index b4c3e20..0610fdb 100644 --- a/Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf.inc +++ b/Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf.inc @@ -14,3 +14,8 @@ =20 # DTB INF RuleOverride =3D DTB Silicon/Marvell/Armada7k8k/DeviceTree/Armada70x= 0Db.inf + +!if $(ARCH) =3D=3D AARCH64 + # ACPI support + INF RuleOverride =3D ACPITABLE Silicon/Marvell/Armada7k8k/AcpiTables/Arm= ada70x0Db/AcpiTables.inf +!endif diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl b/= Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl new file mode 100644 index 0000000..621b688 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl @@ -0,0 +1,229 @@ +/** @file + + Differentiated System Description Table Fields (DSDT) + + Copyright (c) 2018, Linaro Ltd. All rights reserved.
+ Copyright (C) 2018, Marvell International Ltd. and its affiliates.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include "IcuInterrupts.h" + +DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) +{ + Scope (_SB) + { + Device (CPU0) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID + Name (_UID, 0x000) // _UID: Unique ID + } + Device (CPU1) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID + Name (_UID, 0x001) // _UID: Unique ID + } + Device (CPU2) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID + Name (_UID, 0x100) // _UID: Unique ID + } + Device (CPU3) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID + Name (_UID, 0x101) // _UID: Unique ID + } + + Device (AHC0) + { + Name (_HID, "LNRO001E") // _HID: Hardware ID + Name (_UID, 0x00) // _UID: Unique ID + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Name (_CLS, Package (0x03) // _CLS: Class Code + { + 0x01, + 0x06, + 0x01 + }) + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings + { + Memory32Fixed (ReadWrite, + 0xF2540000, // Address Base (MMIO) + 0x00030000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,= ,, ) + { + CP_GIC_SPI_CP0_SATA_H0 + } + }) + } + + Device (XHC0) + { + Name (_HID, "PNP0D10") // _HID: Hardware ID + Name (_UID, 0x00) // _UID: Unique ID + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings + { + Memory32Fixed (ReadWrite, + 0xF2500000, // Address Base (MMIO) + 0x00004000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,= ,, ) + { + CP_GIC_SPI_CP0_USB_H0 + } + }) + } + + Device (XHC1) + { + Name (_HID, "PNP0D10") // _HID: Hardware ID + Name (_UID, 0x01) // _UID: Unique ID + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings + { + Memory32Fixed (ReadWrite, + 0xF2510000, // Address Base (MMIO) + 0x00004000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,= ,, ) + { + CP_GIC_SPI_CP0_USB_H1 + } + }) + } + + Device (COM1) + { + Name (_HID, "HISI0031") // _HID: H= ardware ID + Name (_CID, "8250dw") // _CID: C= ompatible ID + Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: A= ddress + Name (_CRS, ResourceTemplate () // _CRS: C= urrent Resource Settings + { + Memory32Fixed (ReadWrite, + FixedPcdGet64(PcdSerialRegisterBase), // Address= Base + 0x00000100, // Address= Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,= ,, ) + { + 51 + } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "clock-frequency", FixedPcdGet32 (PcdSe= rialClockRate) }, + Package () { "reg-io-width", 1 }, + Package () { "reg-shift", 2 }, + } + }) + } + + Device (PP20) + { + Name (_HID, "MRVL0110") // _HID: H= ardware ID + Name (_CCA, 0x01) // Cache-c= oherent controller + Name (_UID, 0x00) // _UID: U= nique ID + Name (_CRS, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000) + Memory32Fixed (ReadWrite, 0xf2129000 , 0xb000) + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "clock-frequency", 333333333 }, + } + }) + Device (ETH0) + { + Name (_ADR, 0x0) + Name (_CRS, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusiv= e, ,, ) + { + CP_GIC_SPI_PP2_CP0_PORT0 + } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "port-id", 0 }, + Package () { "gop-port-id", 0 }, + Package () { "phy-mode", "10gbase-kr"}, + } + }) + } + Device (ETH1) + { + Name (_ADR, 0x0) + Name (_CRS, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusiv= e, ,, ) + { + CP_GIC_SPI_PP2_CP0_PORT1 + } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "port-id", 1 }, + Package () { "gop-port-id", 2 }, + Package () { "phy-mode", "sgmii"}, + } + }) + } + Device (ETH2) + { + Name (_ADR, 0x0) + Name (_CRS, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusiv= e, ,, ) + { + CP_GIC_SPI_PP2_CP0_PORT2 + } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "port-id", 2 }, + Package () { "gop-port-id", 3 }, + Package () { "phy-mode", "rgmii-id"}, + } + }) + } + } + + Device (RNG0) + { + Name (_HID, "PRP0001") // _HID= : Hardware ID + Name (_UID, 0x00) // _UID= : Unique ID + Name (_CRS, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0xF2760000, 0x7D) + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared) + { + CP_GIC_SPI_CP0_EIP_RNG0 + } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "compatible", "inside-secure,safexcel-eip= 76" }, + } + }) + } + } +} diff --git a/Silicon/Marvell/Documentation/PortingGuide.txt b/Silicon/Marve= ll/Documentation/PortingGuide.txt index d5deed5..2603980 100644 --- a/Silicon/Marvell/Documentation/PortingGuide.txt +++ b/Silicon/Marvell/Documentation/PortingGuide.txt @@ -43,6 +43,28 @@ board. For the sake of simplicity new Marvell board will= be called "new_board". - Output files (and among others FD file, which may be used by ATF) are generated under directory pointed by "OUTPUT_DIRECTORY" entry (see poin= t 1.2). =20 +5. ACPI support (optional) + - The tables can be enabled as in A70x0Db example: + + /Platforms/Marvell/Armada/AcpiTables/Armada70= x0Db/ + + - Enable compilation of the tables in the board's .dsc file. Add it to the + output flash image contents via .fdf.inc file - path to it defined as + BOARD_DXE_FV_COMPONENTS. Example: + Armada70x0Db.dsc: + + BOARD_DXE_FV_COMPONENTS =3D Platform/Marvell/Armada70x0Db/Armada70x0D= b.fdf.inc + + [Components.AARCH64] + Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/AcpiTables.inf + + Armada70x0Db.fdf.inc: + + !if $(ARCH) =3D=3D AARCH64 + # ACPI support + INF RuleOverride =3D ACPITABLE Silicon/Marvell/Armada7k8k/AcpiTable= s/Armada70x0Db/AcpiTables.inf + !endif + =20 COMPHY configuration =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Fri May 3 05:48:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1533511756281951.351536329012; Sun, 5 Aug 2018 16:29:16 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 71049210DA162; Sun, 5 Aug 2018 16:28:58 -0700 (PDT) Received: from mail-lj1-x241.google.com (mail-lj1-x241.google.com [IPv6:2a00:1450:4864:20::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 16FF9210C669A for ; Sun, 5 Aug 2018 16:28:57 -0700 (PDT) Received: by mail-lj1-x241.google.com with SMTP id y17-v6so9071223ljy.8 for ; Sun, 05 Aug 2018 16:28:56 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id v136-v6sm1861994lfa.10.2018.08.05.16.28.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 05 Aug 2018 16:28:53 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4864:20::241; helo=mail-lj1-x241.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=GMJQnim2lQjH27Pj9dTfbndkuME5sk26Iap4jDDXRtA=; b=oiMChOLYWi51hmuJP6c8b/+b1xioKeH9uWjaqNIqbl3+hJMycpant6azsy+5tQKQfU catHsjLJx1fy6khR7tp4DYD1zf9wVGSiKXymOiieKbMeQjPQ1fHN7il1mz/rp/iW2k9U 7hH1PjEERivThJogQ8MH/CNwYX4pkRJrTgyBK92hyPYslG0l/wOuVNCnbRPpM0sGZjrg hQAcniqq8GiWar12joGJiid6aqvl4RInsrbI80h0IGPz4QpIZLiH1WZD1kYSqDnJArvu pcpQorWJZuGJmsTVaBRDMCCmcgnpQLSIy4Rdzu+LwAbPh6GYWx6h9FY5GWuACHbxTgeZ d+Zw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=GMJQnim2lQjH27Pj9dTfbndkuME5sk26Iap4jDDXRtA=; b=pRnMvI44hGgowfdXeLbpnR66WkzPWE2FoDtusSvFVyAiLIQVHYei5EaLArW9KqrOll oa7pyacj2GEUUsqnTRkoAz6N5CuE4Nmg9DyPXQcWujC0XTOGGQvwL183zz80slPktV8u ASlMiRp8/CVWtCldoAzZZiuEnKQtdsbCHY1AArYp5jabU2Os4HAqJuOHL93mXw8W2GYZ xDsjvd5YAeVAb+WLn2BW8tKd46xZOip9VTaw4Lwd6vrRvaYSfRIGLkK4LXpNKnGF790H bFgUWZJ9c2B66NcDawYirfaWMbRwxd4RzodBU4Tk+coCJWbO+3Gz9SgHoEmQ7rRRZg6f qYDg== X-Gm-Message-State: AOUpUlFzB69FMwv9REanJwNL13gOYnGLHLTw92SQscweahRUouahUIlX bliwB7NVvCzJ3KjArr9PYGZrxRbfwcqZJw== X-Google-Smtp-Source: AAOMgpdQmLoZIJVIzW/PmhsPsgVWEt5vy7elcyErCfYz1E//MOsz2WFvMWQMl7ejiI5mpfsQHsSqaQ== X-Received: by 2002:a2e:84c6:: with SMTP id q6-v6mr11519102ljh.65.1533511733937; Sun, 05 Aug 2018 16:28:53 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Mon, 6 Aug 2018 01:28:25 +0200 Message-Id: <1533511706-9344-9-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1533511706-9344-1-git-send-email-mw@semihalf.com> References: <1533511706-9344-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 8/9] Marvell/Armada80x0Db: Enable ACPI support X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jaz@semihalf.com, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This patch introduces DSDT table and adds necessary wiring in order to enable ACPI support on Armada 8040 DB. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc | 3 + Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/AcpiTables.inf | 61 ++= ++ Platform/Marvell/Armada80x0Db/Armada80x0Db.fdf.inc | 5 + Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl | 330 ++= ++++++++++++++++++ 4 files changed, 399 insertions(+) create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Acpi= Tables.inf create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt= .asl diff --git a/Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc b/Platform/Marv= ell/Armada80x0Db/Armada80x0Db.dsc index 3fc33d4..e2b1156 100644 --- a/Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc +++ b/Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc @@ -51,6 +51,9 @@ [Components.common] Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0Db.inf =20 +[Components.AARCH64] + Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/AcpiTables.inf + ##########################################################################= ###### # # Pcd Section - list of all EDK II PCD Entries defined by this Platform diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/AcpiTables.= inf b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/AcpiTables.inf new file mode 100644 index 0000000..1e440f7 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/AcpiTables.inf @@ -0,0 +1,61 @@ +## @file +# Component description file for PlatformAcpiTables module. +# +# ACPI table data and ASL sources required to boot the platform. +# +# Copyright (c) 2018, Linaro, Ltd. All rights reserved.
+# Copyright (C) 2018, Marvell International Ltd. and its affiliates.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +## + +[Defines] + INF_VERSION =3D 0x00010019 + BASE_NAME =3D PlatformAcpiTables + FILE_GUID =3D 7E374E25-8E01-4FEE-87F2-390C23C606CD + MODULE_TYPE =3D USER_DEFINED + VERSION_STRING =3D 1.0 + +[Sources] + Dsdt.asl + ../Fadt.aslc + ../Gtdt.aslc + ../Madt.aslc + ../Pptt.aslc + ../Spcr.aslc + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Marvell/Marvell.dec + +[FixedPcd] + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase + gArmTokenSpaceGuid.PcdGicDistributorBase + + gArmPlatformTokenSpaceGuid.PcdCoreCount + + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum + + gArmTokenSpaceGuid.PcdGenericWatchdogControlBase + gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase + gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum + + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate + +[BuildOptions] + *_*_*_ASLCC_FLAGS =3D -DARMADA8K diff --git a/Platform/Marvell/Armada80x0Db/Armada80x0Db.fdf.inc b/Platform/= Marvell/Armada80x0Db/Armada80x0Db.fdf.inc index 99e1a11..e902e9f 100644 --- a/Platform/Marvell/Armada80x0Db/Armada80x0Db.fdf.inc +++ b/Platform/Marvell/Armada80x0Db/Armada80x0Db.fdf.inc @@ -14,3 +14,8 @@ =20 # DTB INF RuleOverride =3D DTB Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x= 0Db.inf + +!if $(ARCH) =3D=3D AARCH64 + # ACPI support + INF RuleOverride =3D ACPITABLE Silicon/Marvell/Armada7k8k/AcpiTables/Arm= ada80x0Db/AcpiTables.inf +!endif diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl b/= Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl new file mode 100644 index 0000000..7c65949 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl @@ -0,0 +1,330 @@ +/** @file + + Differentiated System Description Table Fields (DSDT) + + Copyright (c) 2018, Linaro Ltd. All rights reserved.
+ Copyright (C) 2018, Marvell International Ltd. and its affiliates.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include "IcuInterrupts.h" + +DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) +{ + Scope (_SB) + { + Device (CPU0) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID + Name (_UID, 0x000) // _UID: Unique ID + } + Device (CPU1) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID + Name (_UID, 0x001) // _UID: Unique ID + } + Device (CPU2) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID + Name (_UID, 0x100) // _UID: Unique ID + } + Device (CPU3) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID + Name (_UID, 0x101) // _UID: Unique ID + } + + Device (AHC0) + { + Name (_HID, "LNRO001E") // _HID: Hardware ID + Name (_UID, 0x00) // _UID: Unique ID + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Name (_CLS, Package (0x03) // _CLS: Class Code + { + 0x01, + 0x06, + 0x01 + }) + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings + { + Memory32Fixed (ReadWrite, + 0xF2540000, // Address Base (MMIO) + 0x00002000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,= ,, ) + { + CP_GIC_SPI_CP0_SATA_H0 + } + }) + } + + Device (AHC1) + { + Name (_HID, "LNRO001E") // _HID: Hardware ID + Name (_UID, 0x01) // _UID: Unique ID + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Name (_CLS, Package (0x03) // _CLS: Class Code + { + 0x01, + 0x06, + 0x01 + }) + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings + { + Memory32Fixed (ReadWrite, + 0xF4540000, // Address Base (MMIO) + 0x00002000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,= ,, ) + { + CP_GIC_SPI_CP1_SATA_H0 + } + }) + } + + Device (XHC0) + { + Name (_HID, "PNP0D10") // _HID: Hardware ID + Name (_UID, 0x00) // _UID: Unique ID + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings + { + Memory32Fixed (ReadWrite, + 0xF2500000, // Address Base (MMIO) + 0x00004000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,= ,, ) + { + CP_GIC_SPI_CP0_USB_H0 + } + }) + } + + Device (XHC1) + { + Name (_HID, "PNP0D10") // _HID: Hardware ID + Name (_UID, 0x01) // _UID: Unique ID + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings + { + Memory32Fixed (ReadWrite, + 0xF2510000, // Address Base (MMIO) + 0x00004000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,= ,, ) + { + CP_GIC_SPI_CP0_USB_H1 + } + }) + } + + Device (XHC2) + { + Name (_HID, "PNP0D10") // _HID: Hardware ID + Name (_UID, 0x02) // _UID: Unique ID + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings + { + Memory32Fixed (ReadWrite, + 0xF4500000, // Address Base (MMIO) + 0x00004000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,= ,, ) + { + CP_GIC_SPI_CP1_USB_H0 + } + }) + } + + Device (COM1) + { + Name (_HID, "HISI0031") // _HID: H= ardware ID + Name (_CID, "8250dw") // _CID: C= ompatible ID + Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: A= ddress + Name (_CRS, ResourceTemplate () // _CRS: C= urrent Resource Settings + { + Memory32Fixed (ReadWrite, + FixedPcdGet64(PcdSerialRegisterBase), // Address= Base + 0x00000100, // Address= Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,= ,, ) + { + 51 + } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "clock-frequency", FixedPcdGet32 (PcdSe= rialClockRate) }, + Package () { "reg-io-width", 1 }, + Package () { "reg-shift", 2 }, + } + }) + } + + Device (PP20) + { + Name (_HID, "MRVL0110") // _HID: H= ardware ID + Name (_CCA, 0x01) // Cache-c= oherent controller + Name (_UID, 0x00) // _UID: U= nique ID + Name (_CRS, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000) + Memory32Fixed (ReadWrite, 0xf2129000 , 0xb000) + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "clock-frequency", 333333333 }, + } + }) + Device (ETH0) + { + Name (_ADR, 0x0) + Name (_CRS, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusiv= e, ,, ) + { + CP_GIC_SPI_PP2_CP0_PORT0 + } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "port-id", 0 }, + Package () { "gop-port-id", 0 }, + Package () { "phy-mode", "10gbase-kr"}, + } + }) + } + Device (ETH2) + { + Name (_ADR, 0x0) + Name (_CRS, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusiv= e, ,, ) + { + CP_GIC_SPI_PP2_CP0_PORT2 + } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "port-id", 2 }, + Package () { "gop-port-id", 3 }, + Package () { "phy-mode", "rgmii-id"}, + } + }) + } + } + + Device (PP21) + { + Name (_HID, "MRVL0110") // _HID: H= ardware ID + Name (_CCA, 0x01) // Cache-c= oherent controller + Name (_UID, 0x01) // _UID: U= nique ID + Name (_CRS, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000) + Memory32Fixed (ReadWrite, 0xf4129000 , 0xb000) + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "clock-frequency", 333333333 }, + } + }) + Device (ETH0) + { + Name (_ADR, 0x0) + Name (_CRS, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusiv= e, ,, ) + { + CP_GIC_SPI_PP2_CP1_PORT0 + } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "port-id", 0 }, + Package () { "gop-port-id", 0 }, + Package () { "phy-mode", "10gbase-kr"}, + } + }) + } + Device (ETH1) + { + Name (_ADR, 0x0) + Name (_CRS, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusiv= e, ,, ) + { + CP_GIC_SPI_PP2_CP1_PORT1 + } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "port-id", 1 }, + Package () { "gop-port-id", 2 }, + Package () { "phy-mode", "rgmii-id"}, + } + }) + } + } + + Device (RNG0) + { + Name (_HID, "PRP0001") // _HID= : Hardware ID + Name (_UID, 0x00) // _UID= : Unique ID + Name (_CRS, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0xF2760000, 0x7D) + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared) + { + CP_GIC_SPI_CP0_EIP_RNG0 + } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "compatible", "inside-secure,safexcel-eip= 76" }, + } + }) + } + + Device (RNG1) + { + Name (_HID, "PRP0001") // _HID= : Hardware ID + Name (_UID, 0x01) // _UID= : Unique ID + Name (_CRS, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0xF4760000, 0x7D) + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared) + { + CP_GIC_SPI_CP1_EIP_RNG0 + } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "compatible", "inside-secure,safexcel-eip= 76" }, + } + }) + } + } +} --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Fri May 3 05:48:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id v136-v6sm1861994lfa.10.2018.08.05.16.28.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 05 Aug 2018 16:28:54 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4864:20::242; helo=mail-lj1-x242.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=qMVIG+8X0ZaU41zLJOuvbDiW/M+OpiWIP/+vHb6aJGw=; b=uPrUtaVQigcpFSA2OWM00KADAda8J12U0EQGYAbQJLE+vmPrMcqanfGrbEtw9PNmsS ayu0CvcRcKglTtto2iL2/OEHW7o5MWnKE6PyY4jLiKRnxYCnmE+PruNeD1w6fMLBMbkA eUCyUQUiYl9WZBHoPEbrI4CFnL0oEQ7OWGaDuMZIOSRB2WZRerIRMuktLT/gUDldXhuX zbkMcpmam05kYpOa79rvwdUEqmODRuPjzwnO7ideUtPh/hmZoTpHmu39jd1os9QVkKkD +HaPzS5q8uKe2Km1Wg53kkG9QK3yTLJbVf4N6Wka0HWr9FDzIy3SoOd87YOXcJbdEYHC xkmg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=qMVIG+8X0ZaU41zLJOuvbDiW/M+OpiWIP/+vHb6aJGw=; b=UIXs04zs/t2/apmtr7Gvi1/NL0ezXyzzAoJknH2oIxCDUCUPGWvlzc7I/oWQLMkC7G 9Pano+riWWlS+ieMj/VgtKnJ/gr52FghEI8UaFHyNuKjLL1LnrQ1VPasEGfkN0/xbe8j vyCIvGUZaC9n0DaDazMUZrbI9cLD7SyKT+aRhXNnND6/mlYmyvhjP0ebWpx2Srk4oRXd Z2QMf4ny3r9738RYGNiqyKX8lMtKiB5Vg5sCDwPXb2LsXPjtPwaz2UyC0POBI4EUeBpY fQjGpMKqNVyw3hIqq/ODAW+ySU2cgYn0bfdczGxMcMTocryllZf+n7Y3bz40wCkdTMBN X3gA== X-Gm-Message-State: AOUpUlGHXzySJW83Bb9su1FRfGDNQQ0/OUWUt4g5ba3tvYrAoeAR08Sz vc1K1bjJDfkHQIZvjeHYeK/ms/+UsfXNNA== X-Google-Smtp-Source: AAOMgpdN7v/EaBmrequuIcm0ZSRijseLQGJYPpnAjIjlOfQ8PDyeeeLxMkY83W+UUVTfMXC3+Z/agA== X-Received: by 2002:a2e:4557:: with SMTP id s84-v6mr10580324lja.47.1533511735007; Sun, 05 Aug 2018 16:28:55 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Mon, 6 Aug 2018 01:28:26 +0200 Message-Id: <1533511706-9344-10-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1533511706-9344-1-git-send-email-mw@semihalf.com> References: <1533511706-9344-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 9/9] Marvell/Armada80x0McBin: Enable ACPI support X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jaz@semihalf.com, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This patch introduces DSDT table and adds necessary wiring in order to enable ACPI support on Armada 8040 MacchiatoBin. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc | 3= + Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/AcpiTables.inf | 61= ++++ Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.fdf.inc | 4= + Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl | 310= ++++++++++++++++++++ 4 files changed, 378 insertions(+) create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/A= cpiTables.inf create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/D= sdt.asl diff --git a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc b/Platfo= rm/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc index e6cb0d6..bb96e4c 100644 --- a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc +++ b/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc @@ -52,6 +52,9 @@ [Components.common] Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0McBin.inf =20 +[Components.AARCH64] + Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/AcpiTables.inf + ##########################################################################= ###### # # Pcd Section - list of all EDK II PCD Entries defined by this Platform diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/AcpiTabl= es.inf b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/AcpiTables.i= nf new file mode 100644 index 0000000..66b1124 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/AcpiTables.inf @@ -0,0 +1,61 @@ +## @file +# Component description file for PlatformAcpiTables module. +# +# ACPI table data and ASL sources required to boot the platform. +# +# Copyright (c) 2018, Linaro, Ltd. All rights reserved.
+# Copyright (C) 2018, Marvell International Ltd. and its affiliates.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +## + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D PlatformAcpiTables + FILE_GUID =3D 7E374E25-8E01-4FEE-87F2-390C23C606CD + MODULE_TYPE =3D USER_DEFINED + VERSION_STRING =3D 1.0 + +[Sources] + Dsdt.asl + ../Fadt.aslc + ../Gtdt.aslc + ../Madt.aslc + ../Pptt.aslc + ../Spcr.aslc + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Marvell/Marvell.dec + +[FixedPcd] + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase + gArmTokenSpaceGuid.PcdGicDistributorBase + + gArmPlatformTokenSpaceGuid.PcdCoreCount + + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum + + gArmTokenSpaceGuid.PcdGenericWatchdogControlBase + gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase + gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum + + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate + +[BuildOptions] + *_*_*_ASLCC_FLAGS =3D -DARMADA8K diff --git a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.fdf.inc b/Pl= atform/SolidRun/Armada80x0McBin/Armada80x0McBin.fdf.inc index 4eb1496..3a6e945 100644 --- a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.fdf.inc +++ b/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.fdf.inc @@ -14,3 +14,7 @@ =20 # DTB INF RuleOverride =3D DTB Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x= 0McBin.inf + +!if $(ARCH) =3D=3D AARCH64 + INF RuleOverride =3D ACPITABLE Silicon/Marvell/Armada7k8k/AcpiTables/Arm= ada80x0McBin/AcpiTables.inf +!endif diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl= b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl new file mode 100644 index 0000000..87cb93a --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl @@ -0,0 +1,310 @@ +/** @file + + Differentiated System Description Table Fields (DSDT) + + Copyright (c) 2018, Linaro Ltd. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include "IcuInterrupts.h" + +DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) +{ + Scope (_SB) + { + Device (CPU0) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID + Name (_UID, 0x000) // _UID: Unique ID + } + Device (CPU1) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID + Name (_UID, 0x001) // _UID: Unique ID + } + Device (CPU2) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID + Name (_UID, 0x100) // _UID: Unique ID + } + Device (CPU3) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID + Name (_UID, 0x101) // _UID: Unique ID + } + + Device (AHC0) + { + Name (_HID, "LNRO001E") // _HID: Hardware ID + Name (_UID, 0x00) // _UID: Unique ID + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Name (_CLS, Package (0x03) // _CLS: Class Code + { + 0x01, + 0x06, + 0x01 + }) + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings + { + Memory32Fixed (ReadWrite, + 0xF2540000, // Address Base (MMIO) + 0x00002000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,= ,, ) + { + CP_GIC_SPI_CP0_SATA_H0 + } + }) + } + + Device (AHC1) + { + Name (_HID, "LNRO001E") // _HID: Hardware ID + Name (_UID, 0x01) // _UID: Unique ID + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Name (_CLS, Package (0x03) // _CLS: Class Code + { + 0x01, + 0x06, + 0x01 + }) + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings + { + Memory32Fixed (ReadWrite, + 0xF4540000, // Address Base (MMIO) + 0x00002000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,= ,, ) + { + CP_GIC_SPI_CP1_SATA_H0 + } + }) + } + + Device (XHC0) + { + Name (_HID, "PNP0D10") // _HID: Hardware ID + Name (_UID, 0x00) // _UID: Unique ID + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings + { + Memory32Fixed (ReadWrite, + 0xF2500000, // Address Base (MMIO) + 0x00004000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,= ,, ) + { + CP_GIC_SPI_CP0_USB_H0 + } + }) + } + + Device (XHC1) + { + Name (_HID, "PNP0D10") // _HID: Hardware ID + Name (_UID, 0x01) // _UID: Unique ID + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings + { + Memory32Fixed (ReadWrite, + 0xF2510000, // Address Base (MMIO) + 0x00004000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,= ,, ) + { + CP_GIC_SPI_CP0_USB_H1 + } + }) + } + + Device (XHC2) + { + Name (_HID, "PNP0D10") // _HID: Hardware ID + Name (_UID, 0x02) // _UID: Unique ID + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings + { + Memory32Fixed (ReadWrite, + 0xF4500000, // Address Base (MMIO) + 0x00004000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,= ,, ) + { + CP_GIC_SPI_CP1_USB_H0 + } + }) + } + + Device (COM1) + { + Name (_HID, "HISI0031") // _HID: H= ardware ID + Name (_CID, "8250dw") // _CID: C= ompatible ID + Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: A= ddress + Name (_CRS, ResourceTemplate () // _CRS: C= urrent Resource Settings + { + Memory32Fixed (ReadWrite, + FixedPcdGet64(PcdSerialRegisterBase), // Address= Base + 0x00000100, // Address= Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,= ,, ) + { + 51 + } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "clock-frequency", FixedPcdGet32 (PcdSe= rialClockRate) }, + Package () { "reg-io-width", 1 }, + Package () { "reg-shift", 2 }, + } + }) + } + + Device (PP20) + { + Name (_HID, "MRVL0110") // _HID: H= ardware ID + Name (_CCA, 0x01) // Cache-c= oherent controller + Name (_UID, 0x00) // _UID: U= nique ID + Name (_CRS, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000) + Memory32Fixed (ReadWrite, 0xf2129000 , 0xb000) + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "clock-frequency", 333333333 }, + } + }) + Device (ETH0) + { + Name (_ADR, 0x0) + Name (_CRS, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusiv= e, ,, ) + { + CP_GIC_SPI_PP2_CP0_PORT0 + } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "port-id", 0 }, + Package () { "gop-port-id", 0 }, + Package () { "phy-mode", "10gbase-kr"}, + } + }) + } + } + + Device (PP21) + { + Name (_HID, "MRVL0110") // _HID: H= ardware ID + Name (_CCA, 0x01) // Cache-c= oherent controller + Name (_UID, 0x01) // _UID: U= nique ID + Name (_CRS, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000) + Memory32Fixed (ReadWrite, 0xf4129000 , 0xb000) + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "clock-frequency", 333333333 }, + } + }) + Device (ETH0) + { + Name (_ADR, 0x0) + Name (_CRS, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusiv= e, ,, ) + { + CP_GIC_SPI_PP2_CP1_PORT0 + } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "port-id", 0 }, + Package () { "gop-port-id", 0 }, + Package () { "phy-mode", "10gbase-kr"}, + } + }) + } + Device (ETH1) + { + Name (_ADR, 0x0) + Name (_CRS, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusiv= e, ,, ) + { + CP_GIC_SPI_PP2_CP1_PORT1 + } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "port-id", 1 }, + Package () { "gop-port-id", 2 }, + Package () { "phy-mode", "sgmii"}, + } + }) + } + } + + Device (RNG0) + { + Name (_HID, "PRP0001") // _HID= : Hardware ID + Name (_UID, 0x00) // _UID= : Unique ID + Name (_CRS, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0xF2760000, 0x7D) + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared) + { + CP_GIC_SPI_CP0_EIP_RNG0 + } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "compatible", "inside-secure,safexcel-eip= 76" }, + } + }) + } + + Device (RNG1) + { + Name (_HID, "PRP0001") // _HID= : Hardware ID + Name (_UID, 0x01) // _UID= : Unique ID + Name (_CRS, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0xF4760000, 0x7D) + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared) + { + CP_GIC_SPI_CP1_EIP_RNG0 + } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "compatible", "inside-secure,safexcel-eip= 76" }, + } + }) + } + } +} --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel