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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id h136-v6sm3020754lfe.23.2018.06.18.15.59.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 18 Jun 2018 15:59:12 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::241; helo=mail-lf0-x241.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=txk09sTQqre3aTdKy7V2FLnLT1pZhZIKmidgp+MAtio=; b=XNTliJbjnQaPcHGRkw8/vIHWnIRTNHTv0GiuUcexOKMMR8gs8af695mIQXt1Y8yr/+ jI3D/+EIJaq35Uwj/FTx3r4HsWjVMFgSfgh9rou3STM/mstgnyDuKTzHvfhKbIEUGvPG bcFbtjqQwttLAyQiMzT3abQnxLnvEqMjV06eVorvIbpbdmBzA/iagajtJlQvJuIBd5lR KKaaGk8pXk4FVDaz42C4geoxrvzLPBJ8MQrqevl0OKK9lZ312VMr5QAE4sWHD+v7SWWL GbMoeCr4mBxGTHFAgTnuSP+3JuL8z0wRV/38KDeUV1SrzAsk74tgMtkCgGN7dpSBZTnq ww9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=txk09sTQqre3aTdKy7V2FLnLT1pZhZIKmidgp+MAtio=; b=Hbq5YlZDX4oapVsfuwY+OGNz0WBo8atMEpkD5vHX5CILRG+77I0qVpKkytuEgfGyCW 8hGMzimqkvIrSMRzyiy1pwh/NFnBdqt0MvfaAl8G/7OMnfUrpgxHXntPPRoztFwTQCZO lq9/Du/o60Uso5ug3/wNc/Utw0qvisTglyqGISf3JpBcw+16lqUJfMHLdDzrG/Tt5KEz CuUZLpUnd0fyMjW2CDMr9JBG3htAjk8iiiSECD9RJRe5Vpnys+xumNO8nuK5fuk+hzHl 7gGl0UvHpMHudKHHpmD+3o1BEPhP+Sz1g6qSDrKSmAFuAFOqXeubkYKubal+LP0JPfP3 6fAA== X-Gm-Message-State: APt69E0PvFAbK5vpfZubOT1KjAl8XFv3WJn86nEPsyzPHl4/DaWoH6fC JkIs8G/ZMHp2jY9GujJGYa7xK2kVQ+I= X-Google-Smtp-Source: ADUXVKKDTc720DpAJl+02caa+AOMvFbVgpo0nM37mGrLdfs01nqghqXuVe9w/c3cHKxXlrOkfyUruA== X-Received: by 2002:a2e:428e:: with SMTP id h14-v6mr9850719ljf.136.1529362752844; Mon, 18 Jun 2018 15:59:12 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Tue, 19 Jun 2018 00:58:30 +0200 Message-Id: <1529362724-9244-12-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529362724-9244-1-git-send-email-mw@semihalf.com> References: <1529362724-9244-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v3 11/25] Marvell/Armada7k8k: Extend ArmadaSoCDescLib with AHCI/SDMMC/XHCI X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This patch introduces new library callbacks for NonDiscoverable devices i.e. AHCI/XHCI/SDMMC. They dynamically allocate and fill according structures with the SoC description of the devices. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescL= ib.h | 18 ++++ Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h = | 48 ++++++++++ Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescL= ib.c | 92 ++++++++++++++++++++ 3 files changed, 158 insertions(+) diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada= 7k8kSoCDescLib.h b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/= Armada7k8kSoCDescLib.h index b899d29..d7557e8 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.h +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.h @@ -24,12 +24,24 @@ #define MV_SOC_CP_BASE(Cp) (0xF2000000 + ((Cp) * 0x2000000)) =20 // +// Platform description of AHCI controllers +// +#define MV_SOC_AHCI_BASE(Cp) (MV_SOC_CP_BASE (Cp) + 0x540000) +#define MV_SOC_AHCI_ID(Cp) ((Cp) % 2) + +// // Platform description of PP2 NIC // #define MV_SOC_PP2_BASE(Cp) MV_SOC_CP_BASE (Cp) #define MV_SOC_PP2_CLK_FREQ 333333333 =20 // +// Platform description of SDMMC controllers +// +#define MV_SOC_MAX_SDMMC_COUNT 2 +#define MV_SOC_SDMMC_BASE(Index) ((Index) =3D=3D 0 ? 0xF06E0000 : = 0xF2780000) + +// // Platform description of UTMI PHY's // #define MV_SOC_UTMI_PER_CP_COUNT 2 @@ -38,4 +50,10 @@ #define MV_SOC_UTMI_CFG_BASE 0x440440 #define MV_SOC_UTMI_USB_CFG_BASE 0x440420 =20 +// +// Platform description of XHCI controllers +// +#define MV_SOC_XHCI_PER_CP_COUNT 2 +#define MV_SOC_XHCI_BASE(Xhci) (0x500000 + ((Xhci) * 0x10000)) + #endif diff --git a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h b/Silicon/M= arvell/Include/Library/ArmadaSoCDescLib.h index cafcc0f..3b29d78 100644 --- a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h +++ b/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h @@ -14,6 +14,54 @@ #ifndef __ARMADA_SOC_DESC_LIB_H__ #define __ARMADA_SOC_DESC_LIB_H__ =20 +#include + +// +// NonDiscoverable devices SoC description +// +// AHCI +typedef struct { + UINTN AhciId; + UINTN AhciBaseAddress; + UINTN AhciMemSize; + NON_DISCOVERABLE_DEVICE_DMA_TYPE AhciDmaType; +} MV_SOC_AHCI_DESC; + +EFI_STATUS +EFIAPI +ArmadaSoCDescAhciGet ( + IN OUT MV_SOC_AHCI_DESC **AhciDesc, + IN OUT UINTN *DescCount + ); + +// SDMMC +typedef struct { + UINTN SdMmcBaseAddress; + UINTN SdMmcMemSize; + NON_DISCOVERABLE_DEVICE_DMA_TYPE SdMmcDmaType; +} MV_SOC_SDMMC_DESC; + +EFI_STATUS +EFIAPI +ArmadaSoCDescSdMmcGet ( + IN OUT MV_SOC_SDMMC_DESC **SdMmcDesc, + IN OUT UINTN *DescCount + ); + +// XHCI +typedef struct { + UINTN XhciBaseAddress; + UINTN XhciMemSize; + NON_DISCOVERABLE_DEVICE_DMA_TYPE XhciDmaType; +} MV_SOC_XHCI_DESC; + +EFI_STATUS +EFIAPI +ArmadaSoCDescXhciGet ( + IN OUT MV_SOC_XHCI_DESC **XhciDesc, + IN OUT UINTN *DescCount + ); + // // PP2 NIC devices SoC description // diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada= 7k8kSoCDescLib.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/= Armada7k8kSoCDescLib.c index 61b4e30..97fe3f8 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.c +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.c @@ -30,6 +30,37 @@ =20 EFI_STATUS EFIAPI +ArmadaSoCDescAhciGet ( + IN OUT MV_SOC_AHCI_DESC **AhciDesc, + IN OUT UINTN *DescCount + ) +{ + MV_SOC_AHCI_DESC *Desc; + UINTN CpCount, CpIndex; + + CpCount =3D FixedPcdGet8 (PcdMaxCpCount); + + Desc =3D AllocateZeroPool (CpCount * sizeof (MV_SOC_AHCI_DESC)); + if (Desc =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + for (CpIndex =3D 0; CpIndex < CpCount; CpIndex++) { + Desc[CpIndex].AhciId =3D MV_SOC_AHCI_ID (CpIndex); + Desc[CpIndex].AhciBaseAddress =3D MV_SOC_AHCI_BASE (CpIndex); + Desc[CpIndex].AhciMemSize =3D SIZE_8KB; + Desc[CpIndex].AhciDmaType =3D NonDiscoverableDeviceDmaTypeCoherent; + } + + *AhciDesc =3D Desc; + *DescCount =3D CpCount; + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI ArmadaSoCDescPp2Get ( IN OUT MV_SOC_PP2_DESC **Pp2Desc, IN OUT UINTN *DescCount @@ -59,6 +90,34 @@ ArmadaSoCDescPp2Get ( =20 EFI_STATUS EFIAPI +ArmadaSoCDescSdMmcGet ( + IN OUT MV_SOC_SDMMC_DESC **SdMmcDesc, + IN OUT UINTN *DescCount + ) +{ + MV_SOC_SDMMC_DESC *Desc; + UINTN Index; + + Desc =3D AllocateZeroPool (MV_SOC_MAX_SDMMC_COUNT * sizeof (MV_SOC_SDMMC= _DESC)); + if (Desc =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + for (Index =3D 0; Index < MV_SOC_MAX_SDMMC_COUNT; Index++) { + Desc[Index].SdMmcBaseAddress =3D MV_SOC_SDMMC_BASE (Index); + Desc[Index].SdMmcMemSize =3D SIZE_1KB; + Desc[Index].SdMmcDmaType =3D NonDiscoverableDeviceDmaTypeCoherent; + } + + *SdMmcDesc =3D Desc; + *DescCount =3D MV_SOC_MAX_SDMMC_COUNT; + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI ArmadaSoCDescUtmiGet ( IN OUT MV_SOC_UTMI_DESC **UtmiDesc, IN OUT UINTN *DescCount @@ -92,3 +151,36 @@ ArmadaSoCDescUtmiGet ( =20 return EFI_SUCCESS; } + +EFI_STATUS +EFIAPI +ArmadaSoCDescXhciGet ( + IN OUT MV_SOC_XHCI_DESC **XhciDesc, + IN OUT UINTN *DescCount + ) +{ + MV_SOC_XHCI_DESC *Desc; + UINTN CpCount, CpIndex, Index; + + CpCount =3D FixedPcdGet8 (PcdMaxCpCount); + + *DescCount =3D CpCount * MV_SOC_XHCI_PER_CP_COUNT; + Desc =3D AllocateZeroPool (*DescCount * sizeof (MV_SOC_XHCI_DESC)); + if (Desc =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + *XhciDesc =3D Desc; + + for (CpIndex =3D 0; CpIndex < CpCount; CpIndex++) { + for (Index =3D 0; Index < MV_SOC_XHCI_PER_CP_COUNT; Index++) { + Desc->XhciBaseAddress =3D MV_SOC_CP_BASE (CpIndex) + MV_SOC_XHCI_BAS= E (Index); + Desc->XhciMemSize =3D SIZE_16KB; + Desc->XhciDmaType =3D NonDiscoverableDeviceDmaTypeCoherent; + Desc++; + } + } + + return EFI_SUCCESS; +} --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel