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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id p5-v6sm65156ljh.3.2018.06.12.07.06.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 12 Jun 2018 07:06:49 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::244; helo=mail-lf0-x244.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=zbw3s3AG39f7gmn2DfOrKwD8ynlgUjdRHbmpooQhXsY=; b=PbkfazIYSSxNYD9huntJL2iY2TZI7olBiTBrs9PZCsMf8qOZtKTXH3/eUsTBUreB6p mBw5LDIgFnNhFDuq8eFxTIJu2WolO0bLvpeyHFmfHAbNacm/GS+9kkn9lxmkLEz/4K+5 9wwo9WTKQEOm9niCBJhR6AJ8nLmDlaCTArJX/t/pavwAo62hds+9FU1TzonKRmeOFkcV 2GZpSM0utUST0Igt07F4CEdRySt9ET1ZEuU8AyCxb1dWcLbl7fO3k9kEaqYqvwpepY6a v4kDwybqMaHLu/y9Q98A1Sy5EVa5pKOcIo0EMqEnBegvrwfWhtX+l9+bhjzdI2nZ/seN inRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=zbw3s3AG39f7gmn2DfOrKwD8ynlgUjdRHbmpooQhXsY=; b=BH/nJCBryYE2XaJ+1/6kNuoWa9nrBoTeupbkGIP96Am43oz7VnydCIWZ+63NW6ceHV CMhj6kwYtysmU1+anfEek5Fw4xsPh9s+tBT7kkxtDL8eh7SvKti3eKpeAXH4kWogFhUi yr6hL679QvxdHSjjlCWnewkk9PNIzCFkIdHIC6/O1wnu5b3R6NMXtc9I/fX9Qq3KkFMv tzJdGh01glIOEC9j6v/ZuEam873DIU3vXcTMV6m3hqy9geAZAFRDQT4XfvMrV6s/BqtB TJSURITNRV2JWHFpQwq+NOqyKratmny7OLccpQiZlWFebGwHVzovoe7qHO2m2aIHsf5R Sg1g== X-Gm-Message-State: APt69E1CdtqsUVhLUF/+qUPkEi4DxJMJuY1WDYqqarsTQL8EXPih+jET JUSBReV2fwKlH6z5NLsGeekvVBgWYLg= X-Google-Smtp-Source: ADUXVKLf+KIaSwf+qCEAkdhD8Gyso2DQQK5w3b4VT/QwMKWCv1UbpIldWDslVUVjo0Y3blMNOZN7dw== X-Received: by 2002:a2e:889a:: with SMTP id k26-v6mr381733lji.54.1528812410450; Tue, 12 Jun 2018 07:06:50 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Tue, 12 Jun 2018 16:06:33 +0200 Message-Id: <1528812395-2716-2-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1528812395-2716-1-git-send-email-mw@semihalf.com> References: <1528812395-2716-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 1/3] Marvell/Armada7k8k: Use common .fdf file X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" As for the preparation for adding multiple boards support, move common part of the .fdf file to the SoC family directory and change output FD file name to more generic. Once needed, possible per-board differences will be resolved by including custom .fdf.inc file. This way adding new common changes for entire SoC family won't require any duplication and at the same time the per-board .fdf.inc will allow better suiting the .FD file contents. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc = | 2 +- Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf =3D> Silicon/Marvell/Armada= 7k8k/Armada7k8k.fdf | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) rename Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf =3D> Silicon/Marvell= /Armada7k8k/Armada7k8k.fdf (97%) diff --git a/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc b/Platform/Marv= ell/Armada70x0Db/Armada70x0Db.dsc index 46a1ea9..eedb025 100644 --- a/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc +++ b/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc @@ -43,7 +43,7 @@ SUPPORTED_ARCHITECTURES =3D AARCH64|ARM BUILD_TARGETS =3D DEBUG|RELEASE SKUID_IDENTIFIER =3D DEFAULT - FLASH_DEFINITION =3D Platform/Marvell/Armada70x0Db/Armada7= 0x0Db.fdf + FLASH_DEFINITION =3D Silicon/Marvell/Armada7k8k/Armada7k8k= .fdf =20 !include Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc =20 diff --git a/Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf b/Silicon/Marve= ll/Armada7k8k/Armada7k8k.fdf similarity index 97% rename from Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf rename to Silicon/Marvell/Armada7k8k/Armada7k8k.fdf index e5e5443..180b6c9 100644 --- a/Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf +++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.fdf @@ -24,7 +24,7 @@ # ##########################################################################= ###### =20 -[FD.Armada70x0Db_EFI] +[FD.Armada_EFI] BaseAddress =3D 0x00000000|gArmTokenSpaceGuid.PcdFdBaseAddress # The ba= se address of the Firmware in NOR Flash. Size =3D 0x00400000|gArmTokenSpaceGuid.PcdFdSize # The si= ze in bytes of the FLASH Device ErasePolarity =3D 1 --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu May 2 21:17:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1528812421930352.331916247658; Tue, 12 Jun 2018 07:07:01 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id C6E41212746F5; Tue, 12 Jun 2018 07:06:55 -0700 (PDT) Received: from mail-lf0-x242.google.com (mail-lf0-x242.google.com [IPv6:2a00:1450:4010:c07::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 17DA5212733F3 for ; Tue, 12 Jun 2018 07:06:54 -0700 (PDT) Received: by mail-lf0-x242.google.com with SMTP id n15-v6so36212935lfn.10 for ; Tue, 12 Jun 2018 07:06:53 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id p5-v6sm65156ljh.3.2018.06.12.07.06.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 12 Jun 2018 07:06:51 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::242; helo=mail-lf0-x242.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=5QouF+58ZRtwClUNU+FtOANeiOFsIif9TxiyAb2sm1A=; b=IEjV4UKKylCYgGPj8a8WBHDKRlIzV3ZgLgbozpRE9OiHguU9y8ENNbqa9RVv80Bu1H Z/Sujrs7tFp/M6qc0+l/MyBzsZxRZOmgR+zyI0MFCfXueoRce5VRTIAgfw48NP6ac7me T6VElLrmBkv17ChhHSwfxovQiWyZonlTKiBn19a8zCaaWNNV/e0ojublYFmtbFkpiUmv X8A2mm2UAKBmppfO4GXvnuya752L0/CVbGe68NKpPWd5QNWBycJfIsEtDGQM6ak1za0r xtgV6Yc0Q0R1EQ14bl2+XOteeQ82nuU/HJ3OaOwSdza8G8UnxDPy2XBTEBCnBYK+O1i2 yHAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=5QouF+58ZRtwClUNU+FtOANeiOFsIif9TxiyAb2sm1A=; b=RKlCYQE9LVGtvEt6hLxk0cZOUSrSUmSy6LJM8JHuoWJFLtQHdk//DbwDANlLrcBsGc H24P1gZpD8UAvy2i17T5dG9Z2XAMrwDx4XKYeiiXY2hcryz5ldMTH0pbbROH9xZ0lEyg m/RRk2r70CLdkGK9HVLNwDhLcKjJJQUYdR783Q0td+FTIQKYMxEZqVkeB6tsxhVFa/lj N8hyx66utEr6Plf+oGOFp9vbcS/BYN2iFLSBsOuFX2ffDuRit249i7Euf0RgqNzEEGJf wkiKzmaV4kZBxzkUEzPdIhe4l8TpXIKdeNcwHgapMBrVLRt63qyUutgMpj27w0gzQhlV 56WA== X-Gm-Message-State: APt69E0TMu2/TsjFbUpWYlmZ0FLoPmAPuWZGo11xon8fCtTwvTRMl7pB KTBrdTOBmKkFlbSjW3j19XcgbtwMDFY= X-Google-Smtp-Source: ADUXVKJZebNXXvQs0JEM54MUOYyLFPvqoQUJ4rwu8uLWVvN6aW/xENfuURDQRgGRw5xs7+rf3bnZ9A== X-Received: by 2002:a19:e544:: with SMTP id c65-v6mr345029lfh.134.1528812411924; Tue, 12 Jun 2018 07:06:51 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Tue, 12 Jun 2018 16:06:34 +0200 Message-Id: <1528812395-2716-3-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1528812395-2716-1-git-send-email-mw@semihalf.com> References: <1528812395-2716-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 2/3] Marvell/Armada7k8k: Introduce support for Armada-8040-McBin X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Add new board description file Armada80x0McBin.dsc, which uses common Armada7k8k.fdf file. By default build capsule components. Most of the interfaces are fully functional, except for: - USB ports - it requires merging GPIO support and VBUS power supply enabling - SdMmc ports - they are kept enabled, as no issues were observed on v1.3 board so far. However higher speed modes (HS200) and full stability will be gained after Xenon driver improvements merge. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc | 149 ++++++++++++++= ++++++ 1 file changed, 149 insertions(+) create mode 100644 Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc diff --git a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc b/Platfo= rm/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc new file mode 100644 index 0000000..1a811d5 --- /dev/null +++ b/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc @@ -0,0 +1,149 @@ +#Copyright (C) 2017 Marvell International Ltd. +# +#Marvell BSD License Option +# +#If you received this File from Marvell, you may opt to use, redistribute = and/or +#modify this File under the following licensing terms. +#Redistribution and use in source and binary forms, with or without modifi= cation, +#are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# +# * Neither the name of Marvell nor the names of its contributors may be +# used to endorse or promote products derived from this software without +# specific prior written permission. +# +#THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS I= S" AND +#ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMP= LIED +#WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +#DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIAB= LE FOR +#ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DA= MAGES +#(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVIC= ES; +#LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED A= ND ON +#ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +#(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF = THIS +#SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +##########################################################################= ###### +# +# Defines Section - statements that will be processed to create a Makefile. +# +##########################################################################= ###### +[Defines] + PLATFORM_NAME =3D Armada80x0McBin + PLATFORM_GUID =3D 256e46dc-bff2-4e83-8ab3-6d2a3bec3f62 + PLATFORM_VERSION =3D 0.1 + DSC_SPECIFICATION =3D 0x00010019 + OUTPUT_DIRECTORY =3D Build/$(PLATFORM_NAME)-$(ARCH) + SUPPORTED_ARCHITECTURES =3D AARCH64|ARM + BUILD_TARGETS =3D DEBUG|RELEASE + SKUID_IDENTIFIER =3D DEFAULT + FLASH_DEFINITION =3D Silicon/Marvell/Armada7k8k/Armada7k8k= .fdf + CAPSULE_ENABLE =3D TRUE + +!include Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc + +##########################################################################= ###### +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +##########################################################################= ###### +[PcdsFixedAtBuild.common] + #MPP + gMarvellTokenSpaceGuid.PcdMppChipCount|3 + + # APN806-A0 MPP SET + gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE + gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000 + gMarvellTokenSpaceGuid.PcdChip0MppPinCount|20 + gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0= x1, 0x1, 0x1, 0x1 } + gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x3 } + + # CP110 MPP SET - master + gMarvellTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE + gMarvellTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000 + gMarvellTokenSpaceGuid.PcdChip1MppPinCount|64 + gMarvellTokenSpaceGuid.PcdChip1MppSel0|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0= xFF, 0xFF, 0xFF, 0xFF, 0xFF } + gMarvellTokenSpaceGuid.PcdChip1MppSel1|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0= xFF, 0xFF, 0xFF, 0xFF, 0xFF } + gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0= xFF, 0xFF, 0xFF, 0xFF, 0xFF } + gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0xFF, 0x0, 0x7, 0xA, 0x7, 0x2, = 0x2, 0x2, 0x2, 0xA } + gMarvellTokenSpaceGuid.PcdChip1MppSel4|{ 0x7, 0x7, 0x8, 0x8, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdChip1MppSel5|{ 0x0, 0x0, 0x9, 0x0, 0x0, 0x0, 0= xE, 0xE, 0xE, 0xE } + gMarvellTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 } + + # CP110 MPP SET - slave + gMarvellTokenSpaceGuid.PcdChip2MppReverseFlag|FALSE + gMarvellTokenSpaceGuid.PcdChip2MppBaseAddress|0xF4440000 + gMarvellTokenSpaceGuid.PcdChip2MppPinCount|64 + gMarvellTokenSpaceGuid.PcdChip2MppSel0|{ 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0= x8, 0x8, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdChip2MppSel1|{ 0x0, 0x0, 0x3, 0x3, 0x3, 0x3, 0= x3, 0xFF, 0xFF, 0xFF } + gMarvellTokenSpaceGuid.PcdChip2MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, 0x0, 0x= FF, 0x0, 0x0, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdChip2MppSel3|{ 0x0, 0x0, 0xFF, 0xFF, 0xFF, 0xF= F, 0xFF, 0xFF, 0xFF, 0xFF } + gMarvellTokenSpaceGuid.PcdChip2MppSel4|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0= xFF, 0xFF, 0xFF, 0xFF, 0xFF } + gMarvellTokenSpaceGuid.PcdChip2MppSel5|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0= xFF, 0xFF, 0xFF, 0xFF, 0xFF } + gMarvellTokenSpaceGuid.PcdChip2MppSel6|{ 0xFF, 0xFF, 0xFF, 0x0, 0x0, 0x0= , 0x0, 0x0, 0x0, 0x0 } + + #SPI + gMarvellTokenSpaceGuid.PcdSpiRegBase|0xF4700680 + gMarvellTokenSpaceGuid.PcdSpiMaxFrequency|10000000 + gMarvellTokenSpaceGuid.PcdSpiClockFrequency|200000000 + + gMarvellTokenSpaceGuid.PcdSpiFlashMode|3 + gMarvellTokenSpaceGuid.PcdSpiFlashCs|0 + + #ComPhy + gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1 } + # ComPhy0 + # 0: PCIE0 5 Gbps + # 1: PCIE0 5 Gbps + # 2: PCIE0 5 Gbps + # 3: PCIE0 5 Gbps + # 4: SFI 10.31 Gbps + # 5: SATA1 5 Gbps + gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), $= (CP_PCIE0), $(CP_PCIE0), $(CP_SFI), $(CP_SATA1)} + gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5= G), $(CP_5G), $(CP_10_3125G), $(CP_5G) } + # ComPhy1 + # 0: SGMII1 1.25 Gbps + # 1: SATA0 5 Gbps + # 2: USB3_HOST0 5 Gbps + # 3: SATA1 5 Gbps + # 4: SFI 10.31 Gbps + # 5: SGMII2 3.125 Gbps + gMarvellTokenSpaceGuid.PcdChip1ComPhyTypes|{ $(CP_SGMII1), $(CP_SATA2), = $(CP_USB3_HOST0), $(CP_SATA3), $(CP_SFI), $(CP_SGMII2) } + gMarvellTokenSpaceGuid.PcdChip1ComPhySpeeds|{ $(CP_1_25G), $(CP_5G), $(C= P_5G), $(CP_5G), $(CP_10_3125G), $(CP_3_125G) } + + #UtmiPhy + gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x1, 0x0 } + gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_H= OST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) } + + #MDIO + gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 } + + #PHY + gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0 } + gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0 } + gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0 } + gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE + + #NET + gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x0, 0x2, 0x3 } + gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_= SPEED_10000), $(PHY_SPEED_1000), $(PHY_SPEED_2500) } + gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_SFI)= , $(PHY_SGMII), $(PHY_SGMII) } + gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0xFF, 0x0, 0xFF } + gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x1, 0x1, 0x1 } + gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x0, 0x1, 0x2 } + gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1 } + + #PciEmulation + gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x1, 0x0 } + gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x1 } + gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 } + + #RTC + gMarvellTokenSpaceGuid.PcdRtcEnabled|{ 0x0, 0x1 } --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu May 2 21:17:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1528812426874100.87049798218027; Tue, 12 Jun 2018 07:07:06 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id F0FFA21276751; Tue, 12 Jun 2018 07:06:56 -0700 (PDT) Received: from mail-lf0-x243.google.com (mail-lf0-x243.google.com [IPv6:2a00:1450:4010:c07::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 7AE34212746CD for ; Tue, 12 Jun 2018 07:06:55 -0700 (PDT) Received: by mail-lf0-x243.google.com with SMTP id n15-v6so36213085lfn.10 for ; Tue, 12 Jun 2018 07:06:55 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id p5-v6sm65156ljh.3.2018.06.12.07.06.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 12 Jun 2018 07:06:52 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::243; helo=mail-lf0-x243.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4jOW8D6Mqv1dUr5KL7OEoXXWyhrUYWgAPtEXWLrWu8E=; b=tSWEH4HS4b/gOv3PrTAS13FQg6NhdrrXFuLQk6zBQ7QR0LWMku1BSva+Yt8wT1rMKP 2JtXAHqjUt90TLXQ6yqc25HjWsDHFEBGybsS/2gdCgrx6l7aPCrz15neJ/qxasfW4IqS ObGcqQgN3syY7B+tEZpoYlu4EQqvbviL/Prvg4cbbFHV8jNe0Dr2geIiunG8P7f71HTj NjHTIcpjBhouZqscJNROZJ3fhRSmVfkBQV3YXL6YCtWSpizrwWATe5LJmniyDKXZ5DpL KGT7T1l8LLOYl8vgUQ9mALeKwrlIJLOYxbHTOiNhVfA+btl9zuRoyrmKysxBsU05bZuN 07ig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4jOW8D6Mqv1dUr5KL7OEoXXWyhrUYWgAPtEXWLrWu8E=; b=aMqGUOH7AI8pW83smM2VFbYgujs2ZHawjvSVWwLJvUZEnC1cKuJfscFe3jHSXR/AVv wN7vOQ+qL2ZZkluUJa29VbaFAhnXRBBGIMCSoErdou0wxo8fkCoyEQp7iZ85LAjJLW/Z H3ROsodHz5xBP7LwGlRGly1sLNPthSFBx/xne5KZCV1dA1CvNRoiP/1439agq5ItpnlK Y3QcQjerfpE5+yu79EaEHEaZp9p2v6QO+Ce+FzEB7+d+U6Nc3iF0MhSnrbE/J0HqGKKY F9qYzoTYWxMBQQV7Ge/LbaoUNlOz0KHcc4em5tBrbQsdKAgilxecWBkf9mZyMMDDfmjR wlwQ== X-Gm-Message-State: APt69E06zl3T6DqlS/F4u019gikvlCgbG45Jr+RcS55Wy2LPR3t+LSEp ddgSHAjktedJyfR4TdHiSGdevOvYDnA= X-Google-Smtp-Source: ADUXVKKfhBRIDt2Oaxa/1j+kqj9rAcPoq2Lk55BHtFrMoj1qBoX4bmlS3QTtzkFWo+b/pHE/0Uo4Rw== X-Received: by 2002:a19:cd08:: with SMTP id d8-v6mr339828lfg.41.1528812413375; Tue, 12 Jun 2018 07:06:53 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Tue, 12 Jun 2018 16:06:35 +0200 Message-Id: <1528812395-2716-4-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1528812395-2716-1-git-send-email-mw@semihalf.com> References: <1528812395-2716-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 3/3] Marvell/Armada7k8k: Introduce support for Armada-8040-Db X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Add new board description file Armada80x0Db.dsc, which uses common Armada7k8k.fdf file. Most of the interfaces are fully functional, except for: - USB ports - it requires merging GPIO support and VBUS power supply enabling Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc | 158 ++++++++++++++++++++ 1 file changed, 158 insertions(+) create mode 100644 Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc diff --git a/Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc b/Platform/Marv= ell/Armada80x0Db/Armada80x0Db.dsc new file mode 100644 index 0000000..0fc00c1 --- /dev/null +++ b/Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc @@ -0,0 +1,158 @@ +#Copyright (C) 2017 Marvell International Ltd. +# +#Marvell BSD License Option +# +#If you received this File from Marvell, you may opt to use, redistribute = and/or +#modify this File under the following licensing terms. +#Redistribution and use in source and binary forms, with or without modifi= cation, +#are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# +# * Neither the name of Marvell nor the names of its contributors may be +# used to endorse or promote products derived from this software without +# specific prior written permission. +# +#THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS I= S" AND +#ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMP= LIED +#WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +#DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIAB= LE FOR +#ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DA= MAGES +#(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVIC= ES; +#LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED A= ND ON +#ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +#(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF = THIS +#SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +##########################################################################= ###### +# +# Defines Section - statements that will be processed to create a Makefile. +# +##########################################################################= ###### +[Defines] + PLATFORM_NAME =3D Armada80x0Db + PLATFORM_GUID =3D 5cc803a0-9c42-498e-9086-e176d4a1f598 + PLATFORM_VERSION =3D 0.1 + DSC_SPECIFICATION =3D 0x00010019 + OUTPUT_DIRECTORY =3D Build/$(PLATFORM_NAME)-$(ARCH) + SUPPORTED_ARCHITECTURES =3D AARCH64|ARM + BUILD_TARGETS =3D DEBUG|RELEASE + SKUID_IDENTIFIER =3D DEFAULT + FLASH_DEFINITION =3D Silicon/Marvell/Armada7k8k/Armada7k8k= .fdf + +!include Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc + +##########################################################################= ###### +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +##########################################################################= ###### +[PcdsFixedAtBuild.common] + #MPP + gMarvellTokenSpaceGuid.PcdMppChipCount|3 + + # APN806-A0 MPP SET + gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE + gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000 + gMarvellTokenSpaceGuid.PcdChip0MppPinCount|20 + gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0= x1, 0x1, 0x1, 0x1 } + gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x3 } + + # CP110 MPP SET - master + gMarvellTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE + gMarvellTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000 + gMarvellTokenSpaceGuid.PcdChip1MppPinCount|64 + gMarvellTokenSpaceGuid.PcdChip1MppSel0|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0= xFF, 0xFF, 0xFF, 0xFF, 0xFF } + gMarvellTokenSpaceGuid.PcdChip1MppSel1|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0= xFF, 0xFF, 0xFF, 0xFF, 0xFF } + gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0= xFF, 0xFF, 0xFF, 0xFF, 0xFF } + gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0xFF, 0xFF, 0x7, 0x0, 0x7, 0= xA, 0xA, 0x2, 0x2, 0x5 } + gMarvellTokenSpaceGuid.PcdChip1MppSel4|{ 0x9, 0x9, 0x8, 0x8, 0x1, 0= x1, 0x1, 0x1, 0x1, 0x1 } + gMarvellTokenSpaceGuid.PcdChip1MppSel5|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0= x1, 0xE, 0xE, 0xE, 0xE } + gMarvellTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0xE, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0, 0x0 } + + # CP110 MPP SET - slave + gMarvellTokenSpaceGuid.PcdChip2MppReverseFlag|FALSE + gMarvellTokenSpaceGuid.PcdChip2MppBaseAddress|0xF4440000 + gMarvellTokenSpaceGuid.PcdChip2MppPinCount|64 + gMarvellTokenSpaceGuid.PcdChip2MppSel0|{ 0x3, 0x3, 0x3, 0x3, 0x3, 0= x3, 0x3, 0x3, 0x3, 0x3 } + gMarvellTokenSpaceGuid.PcdChip2MppSel1|{ 0x3, 0x3, 0x3, 0x3, 0x3, 0= x3, 0x3, 0xFF, 0xFF, 0xFF } + gMarvellTokenSpaceGuid.PcdChip2MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0= xFF, 0xFF, 0x8, 0x9, 0xA } + gMarvellTokenSpaceGuid.PcdChip2MppSel3|{ 0xA, 0x8, 0xFF, 0xFF, 0xFF, 0= xFF, 0xFF, 0xFF, 0xFF, 0xFF } + gMarvellTokenSpaceGuid.PcdChip2MppSel4|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0= xFF, 0xFF, 0xFF, 0xFF, 0xFF } + gMarvellTokenSpaceGuid.PcdChip2MppSel5|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0= xFF, 0xFF, 0xFF, 0xFF, 0xFF } + gMarvellTokenSpaceGuid.PcdChip2MppSel6|{ 0xFF, 0xFF, 0xFF, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0, 0x0 } + + # I2C + gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x50, 0x57, 0x50, 0x57, 0x= 21, 0x25 } + gMarvellTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x1, 0x1, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x1, 0x0, 0x1 } + gMarvellTokenSpaceGuid.PcdEepromI2cAddresses|{ 0x50, 0x57, 0x50, 0x57 } + gMarvellTokenSpaceGuid.PcdEepromI2cBuses|{ 0x0, 0x0, 0x1, 0x1 } + gMarvellTokenSpaceGuid.PcdI2cClockFrequency|250000000 + gMarvellTokenSpaceGuid.PcdI2cBaudRate|100000 + gMarvellTokenSpaceGuid.PcdI2cBusCount|2 + + #SPI + gMarvellTokenSpaceGuid.PcdSpiRegBase|0xF4700680 + gMarvellTokenSpaceGuid.PcdSpiMaxFrequency|10000000 + gMarvellTokenSpaceGuid.PcdSpiClockFrequency|200000000 + + gMarvellTokenSpaceGuid.PcdSpiFlashMode|3 + gMarvellTokenSpaceGuid.PcdSpiFlashCs|0 + + #ComPhy + gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1 } + # ComPhy0 + # 0: PCIE0 5 Gbps + # 1: SATA0 5 Gbps + # 2: SFI 10.31 Gbps + # 3: SATA1 5 Gbps + # 4: USB_HOST1 5 Gbps + # 5: PCIE2 5 Gbps + gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_PCIE0), $(CP_SATA0), $= (CP_SFI), $(CP_SATA1), $(CP_USB3_HOST1), $(CP_PCIE2) } + gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_1= 0_3125G), $(CP_5G), $(CP_5G), $(CP_5G) } + # ComPhy1 + # 0: PCIE0 5 Gbps + # 1: SATA0 5 Gbps + # 2: SFI 10.31 Gbps + # 3: SATA1 5 Gbps + # 4: PCIE1 5 Gbps + # 5: PCIE2 5 Gbps + gMarvellTokenSpaceGuid.PcdChip1ComPhyTypes|{ $(CP_PCIE0), $(CP_SATA2), $= (CP_SFI), $(CP_SATA3), $(CP_PCIE1), $(CP_PCIE2) } + gMarvellTokenSpaceGuid.PcdChip1ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5= _15625G), $(CP_5G), $(CP_5G), $(CP_5G) } + + #UtmiPhy + gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x1, 0x0 } + gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_H= OST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) } + + #MDIO + gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x1 } + + #PHY + gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0, 0x1 } + gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x1, 0x0 } + gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE + + #NET + gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x3, 0x0, 0x2 } + gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_= SPEED_1000), $(PHY_SPEED_10000), $(PHY_SPEED_1000) } + gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMI= I), $(PHY_SFI), $(PHY_RGMII) } + gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0xFF, 0x1 } + gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x1, 0x1 } + gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x2, 0x0, 0x1 } + gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1 } + + #PciEmulation + gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x1, 0x0 } + gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x1 } + gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 } + + #RTC + gMarvellTokenSpaceGuid.PcdRtcEnabled|{ 0x0, 0x1 } --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel