From nobody Mon Apr 29 11:01:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1519376030944275.7717822983317; Fri, 23 Feb 2018 00:53:50 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 270BC22436952; Fri, 23 Feb 2018 00:47:48 -0800 (PST) Received: from mail-pf0-x244.google.com (mail-pf0-x244.google.com [IPv6:2607:f8b0:400e:c00::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 86A772243694C for ; Fri, 23 Feb 2018 00:47:47 -0800 (PST) Received: by mail-pf0-x244.google.com with SMTP id y186so2580771pfb.2 for ; Fri, 23 Feb 2018 00:53:49 -0800 (PST) Received: from localhost.localdomain ([45.56.152.187]) by smtp.gmail.com with ESMTPSA id j25sm3422694pgn.92.2018.02.23.00.53.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 23 Feb 2018 00:53:47 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c00::244; helo=mail-pf0-x244.google.com; envelope-from=heyi.guo@linaro.org; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=EgMXjdbPi0RyUHr9/f3hsdNcmB6zDIDaFA9iWRJI2D8=; b=RdzF8LQzlb7ifyl572tJHMtxk8B6unjHaQU/bTW/eMFkZT8f5a9qIKsCcPj/20vVlR MPaJ+sUwE3ZkGBY77jFF+8fiaZNXdKj8llNhEAvV5ufEBxiKZntqy1dE5jhpT9UmWj99 sbK4tym9JF7Q6SAr4LRwtvB6vuyAoeWHyrnNk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=EgMXjdbPi0RyUHr9/f3hsdNcmB6zDIDaFA9iWRJI2D8=; b=Ul9bXFqo9UODhpzzUzmCPDZjPUDKn89bfR1P/C5eZADSXP0lfGl3XmzwNNRwSjljHC KNQtv7q/f9gJkNDQItLYPi5XqOChYL1EHmgEa0dgh71q1iBWD/6kvt8/FrNfz9Z6p4ej i9T3kb1snuGc7OydU6jDMx7GhfTsOWRDqe6XqqL2ck7F6acXNLiaIT7iycWwEXOcCI9Z 5AUG9B7Q3nCBZqUxntdG/QXh4UC63aY7IuReS2pFMpjbbfREUSXkwlCMPovzjHjGF35b ARV0ta+CFQds/1LzudpEHt4w1p9W0adFU3ukzTd/Fx6epCgbK0RbZDxM8NaBXb+8D2im pjIA== X-Gm-Message-State: APf1xPDdlVxzQtthWMHH0CST2nNQq/6EUTe+N9i0UCvxD7b4bylEFj0m ukaISF/+a7CDrfOfvGHG50YCHPpCbfU= X-Google-Smtp-Source: AH8x225gX1z7updJWYUw4h39/2yvvGriXyuXB5xWgePi3JpV0Mqrw7qkLj1DDpTmrnEU/NcPRqKTtA== X-Received: by 10.98.155.194 with SMTP id e63mr1016288pfk.95.1519376028538; Fri, 23 Feb 2018 00:53:48 -0800 (PST) From: Heyi Guo To: edk2-devel@lists.01.org Date: Fri, 23 Feb 2018 16:53:26 +0800 Message-Id: <1519376008-110662-2-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1519376008-110662-1-git-send-email-heyi.guo@linaro.org> References: <1519376008-110662-1-git-send-email-heyi.guo@linaro.org> Subject: [edk2] [RFC v3 1/3] MdeModulePkg/PciHostBridgeDxe: Add support for address translation X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ruiyu Ni , Eric Dong , Ard Biesheuvel , Heyi Guo , Michael D Kinney , Laszlo Ersek , Star Zeng MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" PCI address translation is necessary for some non-x86 platforms. On such platforms, address value (denoted as "device address" or "address in PCI view") set to PCI BAR registers in configuration space might be different from the address which is used by CPU to access the registers in memory BAR or IO BAR spaces (denoted as "host address" or "address in CPU view"). The difference between the two addresses is called "Address Translation Offset" or simply "translation", and can be represented by "Address Translation Offset" in ACPI QWORD Address Space Descriptor (Offset 0x1E). However UEFI and ACPI differs on the definitions of QWORD Address Space Descriptor, and we will follow UEFI definition on UEFI protocols, such as PCI root bridge IO protocol and PCI IO protocol. In UEFI 2.7, "Address Translation Offset" is "Offset to apply to the Starting address to convert it to a PCI address". This means: 1. Translation =3D device address - host address. 2. PciRootBridgeIo->Configuration should return CPU view address, as well as PciIo->GetBarAttributes. Summary of addresses used: 1. Base and Limit in PCI_ROOT_BRIDGE_APERTURE are device address, for it is easy to check whether the address is below 4G or above 4G. 2. Address returned by EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL::GetProposedResources is device address, or else PCI bus driver cannot set correct address into PCI BAR registers. 3. Address returned by PciRootBridgeIo->Configuration is host address per UEFI 2.7 definition. 4. Addresses used in GCD manipulation are host address. 5. Addresses in ResAllocNode of PCI_ROOT_BRIDGE_INSTANCE are host address, for they are allocated from GCD. 6. Address passed to PciHostBridgeResourceConflict is host address, for it comes from ResAllocNode. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Heyi Guo Cc: Ruiyu Ni Cc: Ard Biesheuvel Cc: Star Zeng Cc: Eric Dong Cc: Laszlo Ersek Cc: Michael D Kinney --- .../Bus/Pci/PciHostBridgeDxe/PciHostBridge.c | 74 +++++++++++--- .../Bus/Pci/PciHostBridgeDxe/PciHostResource.h | 2 + .../Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c | 112 +++++++++++++++++= +--- MdeModulePkg/Include/Library/PciHostBridgeLib.h | 8 ++ 4 files changed, 167 insertions(+), 29 deletions(-) diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c b/MdeMod= ulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c index 1494848..e8979eb 100644 --- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c +++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c @@ -32,6 +32,29 @@ EDKII_IOMMU_PROTOCOL *mIoMmuProtocol; EFI_EVENT mIoMmuEvent; VOID *mIoMmuRegistration; =20 +STATIC +UINT64 +GetTranslationByResourceType ( + IN PCI_ROOT_BRIDGE_INSTANCE *RootBridge, + IN PCI_RESOURCE_TYPE ResourceType + ) +{ + switch (ResourceType) { + case TypeIo: + return RootBridge->Io.Translation; + case TypeMem32: + return RootBridge->Mem.Translation; + case TypePMem32: + return RootBridge->PMem.Translation; + case TypeMem64: + return RootBridge->MemAbove4G.Translation; + case TypePMem64: + return RootBridge->PMemAbove4G.Translation; + default: + return 0; + } +} + /** Ensure the compatibility of an IO space descriptor with the IO aperture. =20 @@ -411,8 +434,12 @@ InitializePciHostBridge ( } =20 if (RootBridges[Index].Io.Base <=3D RootBridges[Index].Io.Limit) { + // Base and Limit in PCI_ROOT_BRIDGE_APERTURE are device address. + // According to UEFI 2.7, device address =3D host address + Translat= ion. + // For GCD resource manipulation, we should use host address, so + // Translation is subtracted from device address here. Status =3D AddIoSpace ( - RootBridges[Index].Io.Base, + RootBridges[Index].Io.Base - RootBridges[Index].Io.Transl= ation, RootBridges[Index].Io.Limit - RootBridges[Index].Io.Base = + 1 ); ASSERT_EFI_ERROR (Status); @@ -422,7 +449,7 @@ InitializePciHostBridge ( EfiGcdIoTypeIo, 0, RootBridges[Index].Io.Limit - RootBridges[Index].I= o.Base + 1, - &RootBridges[Index].Io.Base, + &RootBridges[Index].Io.Base - RootBridges[Index].I= o.Translation, gImageHandle, NULL ); @@ -443,14 +470,18 @@ InitializePciHostBridge ( =20 for (MemApertureIndex =3D 0; MemApertureIndex < ARRAY_SIZE (MemApertur= es); MemApertureIndex++) { if (MemApertures[MemApertureIndex]->Base <=3D MemApertures[MemApertu= reIndex]->Limit) { + // Base and Limit in PCI_ROOT_BRIDGE_APERTURE are device address. + // According to UEFI 2.7, device address =3D host address + Transl= ation. + // For GCD resource manipulation, we should use host address, so + // Translation is subtracted from device address here. Status =3D AddMemoryMappedIoSpace ( - MemApertures[MemApertureIndex]->Base, + MemApertures[MemApertureIndex]->Base - MemApertures[Mem= ApertureIndex]->Translation, MemApertures[MemApertureIndex]->Limit - MemApertures[Me= mApertureIndex]->Base + 1, EFI_MEMORY_UC ); ASSERT_EFI_ERROR (Status); Status =3D gDS->SetMemorySpaceAttributes ( - MemApertures[MemApertureIndex]->Base, + MemApertures[MemApertureIndex]->Base - MemAperture= s[MemApertureIndex]->Translation, MemApertures[MemApertureIndex]->Limit - MemApertur= es[MemApertureIndex]->Base + 1, EFI_MEMORY_UC ); @@ -463,7 +494,7 @@ InitializePciHostBridge ( EfiGcdMemoryTypeMemoryMappedIo, 0, MemApertures[MemApertureIndex]->Limit - MemApert= ures[MemApertureIndex]->Base + 1, - &MemApertures[MemApertureIndex]->Base, + &MemApertures[MemApertureIndex]->Base - MemApert= ures[MemApertureIndex]->Translation, gImageHandle, NULL ); @@ -824,12 +855,17 @@ NotifyPhase ( =20 switch (Index) { case TypeIo: + // Base and Limit in PCI_ROOT_BRIDGE_APERTURE are device addre= ss. + // According to UEFI 2.7, device address =3D host address + Tr= anslation. + // For AllocateResource is manipulating GCD resource, we shoul= d use + // host address here, so Translation is subtracted from Base a= nd + // Limit. BaseAddress =3D AllocateResource ( FALSE, RootBridge->ResAllocNode[Index].Length, MIN (15, BitsOfAlignment), - ALIGN_VALUE (RootBridge->Io.Base, Alignment + = 1), - RootBridge->Io.Limit + ALIGN_VALUE (RootBridge->Io.Base, Alignment + = 1) - RootBridge->Io.Translation, + RootBridge->Io.Limit - RootBridge->Io.Translat= ion ); break; =20 @@ -838,8 +874,8 @@ NotifyPhase ( TRUE, RootBridge->ResAllocNode[Index].Length, MIN (63, BitsOfAlignment), - ALIGN_VALUE (RootBridge->MemAbove4G.Base, Alig= nment + 1), - RootBridge->MemAbove4G.Limit + ALIGN_VALUE (RootBridge->MemAbove4G.Base, Alig= nment + 1) - RootBridge->MemAbove4G.Translation, + RootBridge->MemAbove4G.Limit - RootBridge->Mem= Above4G.Translation ); if (BaseAddress !=3D MAX_UINT64) { break; @@ -853,8 +889,8 @@ NotifyPhase ( TRUE, RootBridge->ResAllocNode[Index].Length, MIN (31, BitsOfAlignment), - ALIGN_VALUE (RootBridge->Mem.Base, Alignment += 1), - RootBridge->Mem.Limit + ALIGN_VALUE (RootBridge->Mem.Base, Alignment += 1) - RootBridge->Mem.Translation, + RootBridge->Mem.Limit - RootBridge->Mem.Transl= ation ); break; =20 @@ -863,8 +899,8 @@ NotifyPhase ( TRUE, RootBridge->ResAllocNode[Index].Length, MIN (63, BitsOfAlignment), - ALIGN_VALUE (RootBridge->PMemAbove4G.Base, Ali= gnment + 1), - RootBridge->PMemAbove4G.Limit + ALIGN_VALUE (RootBridge->PMemAbove4G.Base, Ali= gnment + 1) - RootBridge->PMemAbove4G.Translation, + RootBridge->PMemAbove4G.Limit - RootBridge->PM= emAbove4G.Translation ); if (BaseAddress !=3D MAX_UINT64) { break; @@ -877,8 +913,8 @@ NotifyPhase ( TRUE, RootBridge->ResAllocNode[Index].Length, MIN (31, BitsOfAlignment), - ALIGN_VALUE (RootBridge->PMem.Base, Alignment = + 1), - RootBridge->PMem.Limit + ALIGN_VALUE (RootBridge->PMem.Base, Alignment = + 1) - RootBridge->PMem.Translation, + RootBridge->PMem.Limit - RootBridge->PMem.Tran= slation ); break; =20 @@ -1152,6 +1188,7 @@ StartBusEnumeration ( Descriptor->AddrSpaceGranularity =3D 0; Descriptor->AddrRangeMin =3D RootBridge->Bus.Base; Descriptor->AddrRangeMax =3D 0; + // Ignore translation offset for bus Descriptor->AddrTranslationOffset =3D 0; Descriptor->AddrLen =3D RootBridge->Bus.Limit - RootBr= idge->Bus.Base + 1; =20 @@ -1421,7 +1458,12 @@ GetProposedResources ( Descriptor->Desc =3D ACPI_ADDRESS_SPACE_DESCRIP= TOR; Descriptor->Len =3D sizeof (EFI_ACPI_ADDRESS_S= PACE_DESCRIPTOR) - 3;; Descriptor->GenFlag =3D 0; - Descriptor->AddrRangeMin =3D RootBridge->ResAllocNode[I= ndex].Base; + // AddrRangeMin in Resource Descriptor here should be device add= ress + // instead of host address, or else PCI bus driver cannot set co= rrect + // address into PCI BAR registers. + // Base in ResAllocNode is a host address, so Translation is add= ed. + Descriptor->AddrRangeMin =3D RootBridge->ResAllocNode[I= ndex].Base + + GetTranslationByResourceType (RootBridge, Index); Descriptor->AddrRangeMax =3D 0; Descriptor->AddrTranslationOffset =3D (ResStatus =3D=3D ResAlloc= ated) ? EFI_RESOURCE_SATISFIED : PCI_RESOURCE_LESS; Descriptor->AddrLen =3D RootBridge->ResAllocNode[I= ndex].Length; diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostResource.h b/MdeM= odulePkg/Bus/Pci/PciHostBridgeDxe/PciHostResource.h index 8612c0c..662c2dd 100644 --- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostResource.h +++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostResource.h @@ -38,6 +38,8 @@ typedef enum { =20 typedef struct { PCI_RESOURCE_TYPE Type; + // Base is a host address instead of a device address when address trans= lation + // exists and host address !=3D device address UINT64 Base; UINT64 Length; UINT64 Alignment; diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c b/MdeM= odulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c index dc06c16..04ed411 100644 --- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c +++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c @@ -86,12 +86,23 @@ CreateRootBridge ( (Bridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_COMBINE_MEM_= PMEM) !=3D 0 ? L"CombineMemPMem " : L"", (Bridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_MEM64_DECODE= ) !=3D 0 ? L"Mem64Decode" : L"" )); + // We don't see any scenario for bus translation, so translation for bus= is just ignored. DEBUG ((EFI_D_INFO, " Bus: %lx - %lx\n", Bridge->Bus.Base, Bri= dge->Bus.Limit)); - DEBUG ((EFI_D_INFO, " Io: %lx - %lx\n", Bridge->Io.Base, Brid= ge->Io.Limit)); - DEBUG ((EFI_D_INFO, " Mem: %lx - %lx\n", Bridge->Mem.Base, Bri= dge->Mem.Limit)); - DEBUG ((EFI_D_INFO, " MemAbove4G: %lx - %lx\n", Bridge->MemAbove4G.Ba= se, Bridge->MemAbove4G.Limit)); - DEBUG ((EFI_D_INFO, " PMem: %lx - %lx\n", Bridge->PMem.Base, Br= idge->PMem.Limit)); - DEBUG ((EFI_D_INFO, " PMemAbove4G: %lx - %lx\n", Bridge->PMemAbove4G.B= ase, Bridge->PMemAbove4G.Limit)); + DEBUG ((DEBUG_INFO, " Io: %lx - %lx translation=3D%lx\n", + Bridge->Io.Base, Bridge->Io.Limit, Bridge->Io.Translation + )); + DEBUG ((DEBUG_INFO, " Mem: %lx - %lx translation=3D%lx\n", + Bridge->Mem.Base, Bridge->Mem.Limit, Bridge->Mem.Translation + )); + DEBUG ((DEBUG_INFO, " MemAbove4G: %lx - %lx translation=3D%lx\n", + Bridge->MemAbove4G.Base, Bridge->MemAbove4G.Limit, Bridge->MemAb= ove4G.Translation + )); + DEBUG ((DEBUG_INFO, " PMem: %lx - %lx translation=3D%lx\n", + Bridge->PMem.Base, Bridge->PMem.Limit, Bridge->PMem.Translation + )); + DEBUG ((DEBUG_INFO, " PMemAbove4G: %lx - %lx translation=3D%lx\n", + Bridge->PMemAbove4G.Base, Bridge->PMemAbove4G.Limit, Bridge->PMe= mAbove4G.Translation + )); =20 // // Make sure Mem and MemAbove4G apertures are valid @@ -206,7 +217,10 @@ CreateRootBridge ( } RootBridge->ResAllocNode[Index].Type =3D Index; if (Bridge->ResourceAssigned && (Aperture->Limit >=3D Aperture->Base))= { - RootBridge->ResAllocNode[Index].Base =3D Aperture->Base; + // Base in ResAllocNode is a host address, while Base in Aperture is= a + // device address, so translation needs to be subtracted. + RootBridge->ResAllocNode[Index].Base =3D Aperture->Base - + Aperture->Translation; RootBridge->ResAllocNode[Index].Length =3D Aperture->Limit - Apertur= e->Base + 1; RootBridge->ResAllocNode[Index].Status =3D ResAllocated; } else { @@ -403,6 +417,28 @@ RootBridgeIoCheckParameter ( return EFI_SUCCESS; } =20 +EFI_STATUS +RootBridgeIoGetMemTranslationByAddress ( + IN PCI_ROOT_BRIDGE_INSTANCE *RootBridge, + IN UINT64 Address, + IN OUT UINT64 *Translation + ) +{ + if (Address >=3D RootBridge->Mem.Base && Address <=3D RootBridge->Mem.Li= mit) { + *Translation =3D RootBridge->Mem.Translation; + } else if (Address >=3D RootBridge->PMem.Base && Address <=3D RootBridge= ->PMem.Limit) { + *Translation =3D RootBridge->PMem.Translation; + } else if (Address >=3D RootBridge->MemAbove4G.Base && Address <=3D Root= Bridge->MemAbove4G.Limit) { + *Translation =3D RootBridge->MemAbove4G.Translation; + } else if (Address >=3D RootBridge->PMemAbove4G.Base && Address <=3D Roo= tBridge->PMemAbove4G.Limit) { + *Translation =3D RootBridge->PMemAbove4G.Translation; + } else { + return EFI_INVALID_PARAMETER; + } + + return EFI_SUCCESS; +} + /** Polls an address in memory mapped I/O space until an exit condition is m= et, or a timeout occurs. @@ -658,13 +694,24 @@ RootBridgeIoMemRead ( ) { EFI_STATUS Status; + PCI_ROOT_BRIDGE_INSTANCE *RootBridge; + UINT64 Translation; =20 Status =3D RootBridgeIoCheckParameter (This, MemOperation, Width, Addres= s, Count, Buffer); if (EFI_ERROR (Status)) { return Status; } - return mCpuIo->Mem.Read (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width, Addr= ess, Count, Buffer); + + RootBridge =3D ROOT_BRIDGE_FROM_THIS (This); + Status =3D RootBridgeIoGetMemTranslationByAddress (RootBridge, Address, = &Translation); + if (EFI_ERROR (Status)) { + return Status; + } + + // Address passed to CpuIo->Mem.Read should be a host address instead of + // device address, so Translation should be subtracted. + return mCpuIo->Mem.Read (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width, Addr= ess - Translation, Count, Buffer); } =20 /** @@ -705,13 +752,24 @@ RootBridgeIoMemWrite ( ) { EFI_STATUS Status; + PCI_ROOT_BRIDGE_INSTANCE *RootBridge; + UINT64 Translation; =20 Status =3D RootBridgeIoCheckParameter (This, MemOperation, Width, Addres= s, Count, Buffer); if (EFI_ERROR (Status)) { return Status; } - return mCpuIo->Mem.Write (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width, Add= ress, Count, Buffer); + + RootBridge =3D ROOT_BRIDGE_FROM_THIS (This); + Status =3D RootBridgeIoGetMemTranslationByAddress (RootBridge, Address, = &Translation); + if (EFI_ERROR (Status)) { + return Status; + } + + // Address passed to CpuIo->Mem.Write should be a host address instead of + // device address, so Translation should be subtracted. + return mCpuIo->Mem.Write (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width, Add= ress - Translation, Count, Buffer); } =20 /** @@ -746,6 +804,8 @@ RootBridgeIoIoRead ( ) { EFI_STATUS Status; + PCI_ROOT_BRIDGE_INSTANCE *RootBridge; + Status =3D RootBridgeIoCheckParameter ( This, IoOperation, Width, Address, Count, Buffer @@ -753,7 +813,12 @@ RootBridgeIoIoRead ( if (EFI_ERROR (Status)) { return Status; } - return mCpuIo->Io.Read (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width, Addre= ss, Count, Buffer); + + RootBridge =3D ROOT_BRIDGE_FROM_THIS (This); + + // Address passed to CpuIo->Io.Read should be a host address instead of + // device address, so Translation should be subtracted. + return mCpuIo->Io.Read (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width, Addre= ss - RootBridge->Io.Translation, Count, Buffer); } =20 /** @@ -788,6 +853,8 @@ RootBridgeIoIoWrite ( ) { EFI_STATUS Status; + PCI_ROOT_BRIDGE_INSTANCE *RootBridge; + Status =3D RootBridgeIoCheckParameter ( This, IoOperation, Width, Address, Count, Buffer @@ -795,7 +862,12 @@ RootBridgeIoIoWrite ( if (EFI_ERROR (Status)) { return Status; } - return mCpuIo->Io.Write (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width, Addr= ess, Count, Buffer); + + RootBridge =3D ROOT_BRIDGE_FROM_THIS (This); + + // Address passed to CpuIo->Io.Write should be a host address instead of + // device address, so Translation should be subtracted. + return mCpuIo->Io.Write (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width, Addr= ess - RootBridge->Io.Translation, Count, Buffer); } =20 /** @@ -1615,25 +1687,39 @@ RootBridgeIoConfiguration ( =20 Descriptor->Desc =3D ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor->Len =3D sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3; + // According to UEFI 2.7, RootBridgeIo->Configuration should return ad= dress + // range in CPU view (host address), and ResAllocNode->Base is already= a CPU + // view address (host address). Descriptor->AddrRangeMin =3D ResAllocNode->Base; Descriptor->AddrRangeMax =3D ResAllocNode->Base + ResAllocNode->Lengt= h - 1; Descriptor->AddrLen =3D ResAllocNode->Length; switch (ResAllocNode->Type) { =20 case TypeIo: - Descriptor->ResType =3D ACPI_ADDRESS_SPACE_TYPE_IO; + Descriptor->ResType =3D ACPI_ADDRESS_SPACE_TYPE_IO; + Descriptor->AddrTranslationOffset =3D RootBridge->Io.Translation; break; =20 case TypePMem32: - Descriptor->SpecificFlag =3D EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_= CACHEABLE_PREFETCHABLE; + Descriptor->SpecificFlag =3D EFI_ACPI_MEMORY_RESOURCE_SPECI= FIC_FLAG_CACHEABLE_PREFETCHABLE; + Descriptor->AddrTranslationOffset =3D RootBridge->PMem.Translation; + Descriptor->ResType =3D ACPI_ADDRESS_SPACE_TYPE_MEM; + Descriptor->AddrSpaceGranularity =3D 32; + break; + case TypeMem32: + Descriptor->AddrTranslationOffset =3D RootBridge->Mem.Translation; Descriptor->ResType =3D ACPI_ADDRESS_SPACE_TYPE_MEM; Descriptor->AddrSpaceGranularity =3D 32; break; =20 case TypePMem64: - Descriptor->SpecificFlag =3D EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_= CACHEABLE_PREFETCHABLE; + Descriptor->SpecificFlag =3D EFI_ACPI_MEMORY_RESOURCE_SPECI= FIC_FLAG_CACHEABLE_PREFETCHABLE; + Descriptor->AddrTranslationOffset =3D RootBridge->PMemAbove4G.Transl= ation; + Descriptor->ResType =3D ACPI_ADDRESS_SPACE_TYPE_MEM; + Descriptor->AddrSpaceGranularity =3D 64; case TypeMem64: + Descriptor->AddrTranslationOffset =3D RootBridge->MemAbove4G.Transla= tion; Descriptor->ResType =3D ACPI_ADDRESS_SPACE_TYPE_MEM; Descriptor->AddrSpaceGranularity =3D 64; break; diff --git a/MdeModulePkg/Include/Library/PciHostBridgeLib.h b/MdeModulePkg= /Include/Library/PciHostBridgeLib.h index d42e9ec..21ee8cd 100644 --- a/MdeModulePkg/Include/Library/PciHostBridgeLib.h +++ b/MdeModulePkg/Include/Library/PciHostBridgeLib.h @@ -20,8 +20,16 @@ // (Base > Limit) indicates an aperture is not available. // typedef struct { + // Base and Limit are the device address instead of host address when + // Translation is not zero UINT64 Base; UINT64 Limit; + // According to UEFI 2.7, Device Address =3D Host Address + Translation, + // so Translation =3D Device Address - Host Address. + // On platforms where Translation is not zero, Translation is probably + // negative for we may translate an above-4G host address into a below-4G + // device address for legacy PCIe device compatibility. + UINT64 Translation; } PCI_ROOT_BRIDGE_APERTURE; =20 typedef struct { --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon Apr 29 11:01:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1519376035367623.7223077913368; Fri, 23 Feb 2018 00:53:55 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 8801422436955; Fri, 23 Feb 2018 00:47:52 -0800 (PST) Received: from mail-pl0-x242.google.com (mail-pl0-x242.google.com [IPv6:2607:f8b0:400e:c01::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 173BC2243694C for ; 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charset="utf-8" According to UEFI spec 2.7, PciRootBridgeIo->Configuration() should return host address (CPU view ddress) rather than device address (PCI view address), so in function GetMmioAddressTranslationOffset we need to convert the range to device address before comparing. And device address =3D host address + translation offset. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Heyi Guo Cc: Ruiyu Ni Cc: Ard Biesheuvel Cc: Star Zeng Cc: Eric Dong Cc: Laszlo Ersek Cc: Michael D Kinney --- MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c b/MdeModulePkg/Bus/Pci/= PciBusDxe/PciIo.c index 190f4b0..fef3ece 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c @@ -1812,10 +1812,14 @@ GetMmioAddressTranslationOffset ( return (UINT64) -1; } =20 + // According to UEFI 2.7, EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL::Configuration= () + // returns host address instead of device address, while AddrTranslation= Offset + // is not zero, and device address =3D host address + AddrTranslationOff= set, so + // we convert host address to device address for range compare. while (Configuration->Desc =3D=3D ACPI_ADDRESS_SPACE_DESCRIPTOR) { if ((Configuration->ResType =3D=3D ACPI_ADDRESS_SPACE_TYPE_MEM) && - (Configuration->AddrRangeMin <=3D AddrRangeMin) && - (Configuration->AddrRangeMin + Configuration->AddrLen >=3D AddrRan= geMin + AddrLen) + (Configuration->AddrRangeMin + Configuration->AddrTranslationOffse= t <=3D AddrRangeMin) && + (Configuration->AddrRangeMin + Configuration->AddrLen + Configurat= ion->AddrTranslationOffset >=3D AddrRangeMin + AddrLen) ) { return Configuration->AddrTranslationOffset; } --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon Apr 29 11:01:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1519376040815933.0588048330588; Fri, 23 Feb 2018 00:54:00 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id F034922436958; Fri, 23 Feb 2018 00:47:57 -0800 (PST) Received: from mail-pl0-x244.google.com (mail-pl0-x244.google.com [IPv6:2607:f8b0:400e:c01::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 410102243694C for ; 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charset="utf-8" According to UEFI spec 2.7, PciIo->GetBarAttributes should return host address (CPU view ddress) rather than device address (PCI view address), and device address =3D host address + address translation offset, so we subtract translation from device address before returning. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Heyi Guo Cc: Ruiyu Ni Cc: Ard Biesheuvel Cc: Star Zeng Cc: Eric Dong Cc: Laszlo Ersek Cc: Michael D Kinney --- MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c b/MdeModulePkg/Bus/Pci/= PciBusDxe/PciIo.c index fef3ece..62179eb 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c @@ -1972,6 +1972,10 @@ PciIoGetBarAttributes ( return EFI_UNSUPPORTED; } } + + // According to UEFI spec 2.7, we need return host address for + // PciIo->GetBarAttributes, and host address =3D device address - tran= slation. + Descriptor->AddrRangeMin -=3D Descriptor->AddrTranslationOffset; } =20 return EFI_SUCCESS; --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel