From nobody Fri May 3 06:15:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1519282507420861.3090797944947; Wed, 21 Feb 2018 22:55:07 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id C80FE21FD73EE; Wed, 21 Feb 2018 22:49:05 -0800 (PST) Received: from mail-pg0-x241.google.com (mail-pg0-x241.google.com [IPv6:2607:f8b0:400e:c05::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id F02B62034D8C2 for ; Wed, 21 Feb 2018 22:49:03 -0800 (PST) Received: by mail-pg0-x241.google.com with SMTP id y8so1676723pgr.9 for ; Wed, 21 Feb 2018 22:55:04 -0800 (PST) Received: from localhost.localdomain ([45.56.152.187]) by smtp.gmail.com with ESMTPSA id v88sm35677342pfd.68.2018.02.21.22.55.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 21 Feb 2018 22:55:03 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c05::241; helo=mail-pg0-x241.google.com; envelope-from=heyi.guo@linaro.org; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=BNeoMGEoAK5Q1oyazxXgvHMNYXFDnVdcKATLiIfVa/A=; b=kt338KCkRYSpOgelR7ia+IO2+SH2G1e7zHy0AVi9qeDctdSoI8GKGCYET2EvNgyghw rbPS42dPt+0QvPc9bTxt8C6PySzIFkTUnkB4B3TAxb+BZk+HFc6vL8UVSKVMbn0ugLhV WJ36j1IRybcy2JHFJ/NY5iztiBPe9ZwG2veNI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=BNeoMGEoAK5Q1oyazxXgvHMNYXFDnVdcKATLiIfVa/A=; b=hkmskcDLPAD2ik9ehx8EBaXI5AN4OY4149Wez/9ir5USmK4bFRj/pX+AAvpfeWiq7p UC+F1o4FdtUu/LaNW6EnIwvCTnn2wd8aey2e4dmKO0O4yrCfdYkJwYion/No/7MK1U5P Cx8bZfHbvx6QIESZKK00qstoYUKKkzPuyVt1QsHuF21GLTrMsAx3h0/i31Ktmm9CS7aj wqwCL3ydBFRnwokNgpXPVFpqDfT6neI/TRBcq6sImfXM6vlW8hcJS4942cziNcr2BLkQ I15ONdGYbEOvVEfoWhzTQutqevXJqpYFulqR/Ei8kSXnrhVxy1CM2Kb+LNUSzlqp5pfq 0TuQ== X-Gm-Message-State: APf1xPDR7CVbEIKcqzrNnn3jClfdGSjZFRb1bdzG5hOf4OU7SHpo2+fr DmsNFvkkrw2anDuENcEg4B55E0kJ0Hc= X-Google-Smtp-Source: AH8x227Y7DGkm46Y6xWXIoi4d6NOkjJFyUGBCJ/iOUhQYS7uGdzYtGAYRsrxkfjYJluVbxjQRWkxmg== X-Received: by 10.101.66.129 with SMTP id j1mr4738064pgp.56.1519282503777; Wed, 21 Feb 2018 22:55:03 -0800 (PST) From: Heyi Guo To: edk2-devel@lists.01.org Date: Thu, 22 Feb 2018 14:54:33 +0800 Message-Id: <1519282474-94811-2-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1519282474-94811-1-git-send-email-heyi.guo@linaro.org> References: <1519282474-94811-1-git-send-email-heyi.guo@linaro.org> Subject: [edk2] [RFC v2 1/2] MdeModulePkg/PciHostBridgeDxe: Add support for address translation X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ruiyu Ni , Eric Dong , Ard Biesheuvel , Heyi Guo , Michael D Kinney , Laszlo Ersek , Star Zeng MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This is the draft patch for the discussion posted in edk2-devel mailing list: https://lists.01.org/pipermail/edk2-devel/2017-December/019289.html As discussed in the mailing list, we'd like to add support for PCI address translation which is necessary for some non-x86 platforms. I also want to minimize the changes to the generic host bridge driver and platform PciHostBridgeLib implemetations, so additional two interfaces are added to expose translation information of the platform. To be generic, I add translation for each type of IO or memory resources. The patch is still a RFC, so I only passed the build for qemu64 and the function has not been tested yet. Please let me know your comments about it. Thanks. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Heyi Guo Cc: Ruiyu Ni Cc: Ard Biesheuvel Cc: Star Zeng Cc: Eric Dong Cc: Laszlo Ersek Cc: Michael D Kinney --- .../Bus/Pci/PciHostBridgeDxe/PciHostBridge.c | 57 ++++++++---- .../Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c | 101 +++++++++++++++++= +--- MdeModulePkg/Include/Library/PciHostBridgeLib.h | 1 + 3 files changed, 131 insertions(+), 28 deletions(-) diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c b/MdeMod= ulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c index 1494848..fa22d8d 100644 --- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c +++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c @@ -32,6 +32,29 @@ EDKII_IOMMU_PROTOCOL *mIoMmuProtocol; EFI_EVENT mIoMmuEvent; VOID *mIoMmuRegistration; =20 +STATIC +UINT64 +GetTranslationByResourceType ( + IN PCI_ROOT_BRIDGE_INSTANCE *RootBridge, + IN PCI_RESOURCE_TYPE ResourceType + ) +{ + switch (ResourceType) { + case TypeIo: + return RootBridge->Io.Translation; + case TypeMem32: + return RootBridge->Mem.Translation; + case TypePMem32: + return RootBridge->PMem.Translation; + case TypeMem64: + return RootBridge->MemAbove4G.Translation; + case TypePMem64: + return RootBridge->PMemAbove4G.Translation; + default: + return 0; + } +} + /** Ensure the compatibility of an IO space descriptor with the IO aperture. =20 @@ -412,7 +435,7 @@ InitializePciHostBridge ( =20 if (RootBridges[Index].Io.Base <=3D RootBridges[Index].Io.Limit) { Status =3D AddIoSpace ( - RootBridges[Index].Io.Base, + RootBridges[Index].Io.Base + RootBridges[Index].Io.Transl= ation, RootBridges[Index].Io.Limit - RootBridges[Index].Io.Base = + 1 ); ASSERT_EFI_ERROR (Status); @@ -422,7 +445,7 @@ InitializePciHostBridge ( EfiGcdIoTypeIo, 0, RootBridges[Index].Io.Limit - RootBridges[Index].I= o.Base + 1, - &RootBridges[Index].Io.Base, + &RootBridges[Index].Io.Base + RootBridges[Index].I= o.Translation, gImageHandle, NULL ); @@ -444,13 +467,13 @@ InitializePciHostBridge ( for (MemApertureIndex =3D 0; MemApertureIndex < ARRAY_SIZE (MemApertur= es); MemApertureIndex++) { if (MemApertures[MemApertureIndex]->Base <=3D MemApertures[MemApertu= reIndex]->Limit) { Status =3D AddMemoryMappedIoSpace ( - MemApertures[MemApertureIndex]->Base, + MemApertures[MemApertureIndex]->Base + MemApertures[Mem= ApertureIndex]->Translation, MemApertures[MemApertureIndex]->Limit - MemApertures[Me= mApertureIndex]->Base + 1, EFI_MEMORY_UC ); ASSERT_EFI_ERROR (Status); Status =3D gDS->SetMemorySpaceAttributes ( - MemApertures[MemApertureIndex]->Base, + MemApertures[MemApertureIndex]->Base + MemAperture= s[MemApertureIndex]->Translation, MemApertures[MemApertureIndex]->Limit - MemApertur= es[MemApertureIndex]->Base + 1, EFI_MEMORY_UC ); @@ -463,7 +486,7 @@ InitializePciHostBridge ( EfiGcdMemoryTypeMemoryMappedIo, 0, MemApertures[MemApertureIndex]->Limit - MemApert= ures[MemApertureIndex]->Base + 1, - &MemApertures[MemApertureIndex]->Base, + &MemApertures[MemApertureIndex]->Base + MemApert= ures[MemApertureIndex]->Translation, gImageHandle, NULL ); @@ -828,8 +851,8 @@ NotifyPhase ( FALSE, RootBridge->ResAllocNode[Index].Length, MIN (15, BitsOfAlignment), - ALIGN_VALUE (RootBridge->Io.Base, Alignment + = 1), - RootBridge->Io.Limit + ALIGN_VALUE (RootBridge->Io.Base, Alignment + = 1) + RootBridge->Io.Translation, + RootBridge->Io.Limit + RootBridge->Io.Translat= ion ); break; =20 @@ -838,8 +861,8 @@ NotifyPhase ( TRUE, RootBridge->ResAllocNode[Index].Length, MIN (63, BitsOfAlignment), - ALIGN_VALUE (RootBridge->MemAbove4G.Base, Alig= nment + 1), - RootBridge->MemAbove4G.Limit + ALIGN_VALUE (RootBridge->MemAbove4G.Base, Alig= nment + 1) + RootBridge->MemAbove4G.Translation, + RootBridge->MemAbove4G.Limit + RootBridge->Mem= Above4G.Translation ); if (BaseAddress !=3D MAX_UINT64) { break; @@ -853,8 +876,8 @@ NotifyPhase ( TRUE, RootBridge->ResAllocNode[Index].Length, MIN (31, BitsOfAlignment), - ALIGN_VALUE (RootBridge->Mem.Base, Alignment += 1), - RootBridge->Mem.Limit + ALIGN_VALUE (RootBridge->Mem.Base, Alignment += 1) + RootBridge->Mem.Translation, + RootBridge->Mem.Limit + RootBridge->Mem.Transl= ation ); break; =20 @@ -863,8 +886,8 @@ NotifyPhase ( TRUE, RootBridge->ResAllocNode[Index].Length, MIN (63, BitsOfAlignment), - ALIGN_VALUE (RootBridge->PMemAbove4G.Base, Ali= gnment + 1), - RootBridge->PMemAbove4G.Limit + ALIGN_VALUE (RootBridge->PMemAbove4G.Base, Ali= gnment + 1) + RootBridge->PMemAbove4G.Translation, + RootBridge->PMemAbove4G.Limit + RootBridge->PM= emAbove4G.Translation ); if (BaseAddress !=3D MAX_UINT64) { break; @@ -877,8 +900,8 @@ NotifyPhase ( TRUE, RootBridge->ResAllocNode[Index].Length, MIN (31, BitsOfAlignment), - ALIGN_VALUE (RootBridge->PMem.Base, Alignment = + 1), - RootBridge->PMem.Limit + ALIGN_VALUE (RootBridge->PMem.Base, Alignment = + 1) + RootBridge->PMem.Translation, + RootBridge->PMem.Limit + RootBridge->PMem.Tran= slation ); break; =20 @@ -1152,6 +1175,7 @@ StartBusEnumeration ( Descriptor->AddrSpaceGranularity =3D 0; Descriptor->AddrRangeMin =3D RootBridge->Bus.Base; Descriptor->AddrRangeMax =3D 0; + // Ignore translation offset for bus Descriptor->AddrTranslationOffset =3D 0; Descriptor->AddrLen =3D RootBridge->Bus.Limit - RootBr= idge->Bus.Base + 1; =20 @@ -1421,7 +1445,8 @@ GetProposedResources ( Descriptor->Desc =3D ACPI_ADDRESS_SPACE_DESCRIP= TOR; Descriptor->Len =3D sizeof (EFI_ACPI_ADDRESS_S= PACE_DESCRIPTOR) - 3;; Descriptor->GenFlag =3D 0; - Descriptor->AddrRangeMin =3D RootBridge->ResAllocNode[I= ndex].Base; + Descriptor->AddrRangeMin =3D RootBridge->ResAllocNode[I= ndex].Base - + GetTranslationByResourceType (RootBridge, Index); Descriptor->AddrRangeMax =3D 0; Descriptor->AddrTranslationOffset =3D (ResStatus =3D=3D ResAlloc= ated) ? EFI_RESOURCE_SATISFIED : PCI_RESOURCE_LESS; Descriptor->AddrLen =3D RootBridge->ResAllocNode[I= ndex].Length; diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c b/MdeM= odulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c index dc06c16..bd3394a 100644 --- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c +++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c @@ -86,12 +86,23 @@ CreateRootBridge ( (Bridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_COMBINE_MEM_= PMEM) !=3D 0 ? L"CombineMemPMem " : L"", (Bridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_MEM64_DECODE= ) !=3D 0 ? L"Mem64Decode" : L"" )); + // We don't see any scenario for bus translation, so translation for bus= is just ignored. DEBUG ((EFI_D_INFO, " Bus: %lx - %lx\n", Bridge->Bus.Base, Bri= dge->Bus.Limit)); - DEBUG ((EFI_D_INFO, " Io: %lx - %lx\n", Bridge->Io.Base, Brid= ge->Io.Limit)); - DEBUG ((EFI_D_INFO, " Mem: %lx - %lx\n", Bridge->Mem.Base, Bri= dge->Mem.Limit)); - DEBUG ((EFI_D_INFO, " MemAbove4G: %lx - %lx\n", Bridge->MemAbove4G.Ba= se, Bridge->MemAbove4G.Limit)); - DEBUG ((EFI_D_INFO, " PMem: %lx - %lx\n", Bridge->PMem.Base, Br= idge->PMem.Limit)); - DEBUG ((EFI_D_INFO, " PMemAbove4G: %lx - %lx\n", Bridge->PMemAbove4G.B= ase, Bridge->PMemAbove4G.Limit)); + DEBUG ((DEBUG_INFO, " Io: %lx - %lx translation=3D%lx\n", + Bridge->Io.Base, Bridge->Io.Limit, Bridge->Io.Translation + )); + DEBUG ((DEBUG_INFO, " Mem: %lx - %lx translation=3D%lx\n", + Bridge->Mem.Base, Bridge->Mem.Limit, Bridge->Mem.Translation + )); + DEBUG ((DEBUG_INFO, " MemAbove4G: %lx - %lx translation=3D%lx\n", + Bridge->MemAbove4G.Base, Bridge->MemAbove4G.Limit, Bridge->MemAb= ove4G.Translation + )); + DEBUG ((DEBUG_INFO, " PMem: %lx - %lx translation=3D%lx\n", + Bridge->PMem.Base, Bridge->PMem.Limit, Bridge->PMem.Translation + )); + DEBUG ((DEBUG_INFO, " PMemAbove4G: %lx - %lx translation=3D%lx\n", + Bridge->PMemAbove4G.Base, Bridge->PMemAbove4G.Limit, Bridge->PMe= mAbove4G.Translation + )); =20 // // Make sure Mem and MemAbove4G apertures are valid @@ -403,6 +414,28 @@ RootBridgeIoCheckParameter ( return EFI_SUCCESS; } =20 +EFI_STATUS +RootBridgeIoGetMemTranslationByAddress ( + IN PCI_ROOT_BRIDGE_INSTANCE *RootBridge, + IN UINT64 Address, + IN OUT UINT64 *Translation + ) +{ + if (Address >=3D RootBridge->Mem.Base && Address <=3D RootBridge->Mem.Li= mit) { + *Translation =3D RootBridge->Mem.Translation; + } else if (Address >=3D RootBridge->PMem.Base && Address <=3D RootBridge= ->PMem.Limit) { + *Translation =3D RootBridge->PMem.Translation; + } else if (Address >=3D RootBridge->MemAbove4G.Base && Address <=3D Root= Bridge->MemAbove4G.Limit) { + *Translation =3D RootBridge->MemAbove4G.Translation; + } else if (Address >=3D RootBridge->PMemAbove4G.Base && Address <=3D Roo= tBridge->PMemAbove4G.Limit) { + *Translation =3D RootBridge->PMemAbove4G.Translation; + } else { + return EFI_INVALID_PARAMETER; + } + + return EFI_SUCCESS; +} + /** Polls an address in memory mapped I/O space until an exit condition is m= et, or a timeout occurs. @@ -658,13 +691,22 @@ RootBridgeIoMemRead ( ) { EFI_STATUS Status; + PCI_ROOT_BRIDGE_INSTANCE *RootBridge; + UINT64 Translation; =20 Status =3D RootBridgeIoCheckParameter (This, MemOperation, Width, Addres= s, Count, Buffer); if (EFI_ERROR (Status)) { return Status; } - return mCpuIo->Mem.Read (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width, Addr= ess, Count, Buffer); + + RootBridge =3D ROOT_BRIDGE_FROM_THIS (This); + Status =3D RootBridgeIoGetMemTranslationByAddress (RootBridge, Address, = &Translation); + if (EFI_ERROR (Status)) { + return Status; + } + + return mCpuIo->Mem.Read (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width, Addr= ess + Translation, Count, Buffer); } =20 /** @@ -705,13 +747,22 @@ RootBridgeIoMemWrite ( ) { EFI_STATUS Status; + PCI_ROOT_BRIDGE_INSTANCE *RootBridge; + UINT64 Translation; =20 Status =3D RootBridgeIoCheckParameter (This, MemOperation, Width, Addres= s, Count, Buffer); if (EFI_ERROR (Status)) { return Status; } - return mCpuIo->Mem.Write (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width, Add= ress, Count, Buffer); + + RootBridge =3D ROOT_BRIDGE_FROM_THIS (This); + Status =3D RootBridgeIoGetMemTranslationByAddress (RootBridge, Address, = &Translation); + if (EFI_ERROR (Status)) { + return Status; + } + + return mCpuIo->Mem.Write (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width, Add= ress + Translation, Count, Buffer); } =20 /** @@ -746,6 +797,8 @@ RootBridgeIoIoRead ( ) { EFI_STATUS Status; + PCI_ROOT_BRIDGE_INSTANCE *RootBridge; + Status =3D RootBridgeIoCheckParameter ( This, IoOperation, Width, Address, Count, Buffer @@ -753,7 +806,10 @@ RootBridgeIoIoRead ( if (EFI_ERROR (Status)) { return Status; } - return mCpuIo->Io.Read (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width, Addre= ss, Count, Buffer); + + RootBridge =3D ROOT_BRIDGE_FROM_THIS (This); + + return mCpuIo->Io.Read (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width, Addre= ss + RootBridge->Io.Translation, Count, Buffer); } =20 /** @@ -788,6 +844,8 @@ RootBridgeIoIoWrite ( ) { EFI_STATUS Status; + PCI_ROOT_BRIDGE_INSTANCE *RootBridge; + Status =3D RootBridgeIoCheckParameter ( This, IoOperation, Width, Address, Count, Buffer @@ -795,7 +853,10 @@ RootBridgeIoIoWrite ( if (EFI_ERROR (Status)) { return Status; } - return mCpuIo->Io.Write (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width, Addr= ess, Count, Buffer); + + RootBridge =3D ROOT_BRIDGE_FROM_THIS (This); + + return mCpuIo->Io.Write (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width, Addr= ess + RootBridge->Io.Translation, Count, Buffer); } =20 /** @@ -1615,25 +1676,41 @@ RootBridgeIoConfiguration ( =20 Descriptor->Desc =3D ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor->Len =3D sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3; + // According to UEFI 2.7, RootBridgeIo::Configuration should return ad= dress + // range in CPU view, and TranslationOffset =3D PCI view - CPU view. Descriptor->AddrRangeMin =3D ResAllocNode->Base; Descriptor->AddrRangeMax =3D ResAllocNode->Base + ResAllocNode->Lengt= h - 1; Descriptor->AddrLen =3D ResAllocNode->Length; switch (ResAllocNode->Type) { =20 case TypeIo: - Descriptor->ResType =3D ACPI_ADDRESS_SPACE_TYPE_IO; + Descriptor->ResType =3D ACPI_ADDRESS_SPACE_TYPE_IO; + // According to UEFI 2.7, translation =3D PCI address - CPU address, + // so we change the sign here to make it consistent with UEFI spec. + // The other translations will be treated as the same. + Descriptor->AddrTranslationOffset =3D -RootBridge->Io.Translation; break; =20 case TypePMem32: - Descriptor->SpecificFlag =3D EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_= CACHEABLE_PREFETCHABLE; + Descriptor->SpecificFlag =3D EFI_ACPI_MEMORY_RESOURCE_SPECI= FIC_FLAG_CACHEABLE_PREFETCHABLE; + Descriptor->AddrTranslationOffset =3D -RootBridge->PMem.Translation; + Descriptor->ResType =3D ACPI_ADDRESS_SPACE_TYPE_MEM; + Descriptor->AddrSpaceGranularity =3D 32; + break; + case TypeMem32: + Descriptor->AddrTranslationOffset =3D -RootBridge->Mem.Translation; Descriptor->ResType =3D ACPI_ADDRESS_SPACE_TYPE_MEM; Descriptor->AddrSpaceGranularity =3D 32; break; =20 case TypePMem64: - Descriptor->SpecificFlag =3D EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_= CACHEABLE_PREFETCHABLE; + Descriptor->SpecificFlag =3D EFI_ACPI_MEMORY_RESOURCE_SPECI= FIC_FLAG_CACHEABLE_PREFETCHABLE; + Descriptor->AddrTranslationOffset =3D -RootBridge->PMemAbove4G.Trans= lation; + Descriptor->ResType =3D ACPI_ADDRESS_SPACE_TYPE_MEM; + Descriptor->AddrSpaceGranularity =3D 64; case TypeMem64: + Descriptor->AddrTranslationOffset =3D -RootBridge->MemAbove4G.Transl= ation; Descriptor->ResType =3D ACPI_ADDRESS_SPACE_TYPE_MEM; Descriptor->AddrSpaceGranularity =3D 64; break; diff --git a/MdeModulePkg/Include/Library/PciHostBridgeLib.h b/MdeModulePkg= /Include/Library/PciHostBridgeLib.h index d42e9ec..b9e8c0f 100644 --- a/MdeModulePkg/Include/Library/PciHostBridgeLib.h +++ b/MdeModulePkg/Include/Library/PciHostBridgeLib.h @@ -22,6 +22,7 @@ typedef struct { UINT64 Base; UINT64 Limit; + UINT64 Translation; } PCI_ROOT_BRIDGE_APERTURE; =20 typedef struct { --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Fri May 3 06:15:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1519282511970150.5262006026345; Wed, 21 Feb 2018 22:55:11 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 3A339223230EA; Wed, 21 Feb 2018 22:49:10 -0800 (PST) Received: from mail-pg0-x241.google.com (mail-pg0-x241.google.com [IPv6:2607:f8b0:400e:c05::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id C1AA62034D8DA for ; Wed, 21 Feb 2018 22:49:08 -0800 (PST) Received: by mail-pg0-x241.google.com with SMTP id w17so1678590pgv.6 for ; Wed, 21 Feb 2018 22:55:09 -0800 (PST) Received: from localhost.localdomain ([45.56.152.187]) by smtp.gmail.com with ESMTPSA id v88sm35677342pfd.68.2018.02.21.22.55.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 21 Feb 2018 22:55:08 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c05::241; helo=mail-pg0-x241.google.com; envelope-from=heyi.guo@linaro.org; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=+GJo2QQXZEN++sPMqRowakOjtGx+V6d9h5IFqO803no=; b=YymQMF+F4UsUboJDukORe9WZgW8u/DvODOKGKBZuOfV6iqGcLhuEvzlH7Z5afUSP10 C0nXNiMOHTHfKCH7sYy45rTFe4XZWEOXl3eSJdYnCeXPtFtqxjcqYe4TmoIi9l+n4T2F PYSbfcO4RQdbbi8A3Un8noRXskAnt6ZkBPZec= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=+GJo2QQXZEN++sPMqRowakOjtGx+V6d9h5IFqO803no=; b=Xj6wV9yHm0sqfzN8Dse9aaOzY2qT/wSW8lYexUz7+8ETJtdaiCFOzkp6SVYd9dR8jA RdBkt/jsbVXtSTFxlsqhNJHS1w1rkwcBF1qqChZWWElM+Wz6XMBg2AWfe13Rv19BWdKn uto+5Ydl9fNlFXulIjL+Nd96/WF2cCHqnoNufe7MSVrkH7v7vM5ZvHdLdJaWEeRLi2R2 AE+mHmO55jXySsWy60NWJ8jvEAzLIQRXzWhlX9AGXjkLcbBRPntgHDzSUcE2wddbU6wM 6tTEm8Typlz+C0GSFMA7z981hwAEY6HLrdq0d+ioz/nBwobKo7J3HChfR2gl2bAXqoge 8V3A== X-Gm-Message-State: APf1xPD36cXiHY8lQ2oCsQELjeanVJuj/HpwR7MswyyX6pkul/UrmE/G 1p6CC5+oWP1E6Q8hpt/e7ZOSITkDmB4= X-Google-Smtp-Source: AH8x227mMfyCYLwqWcc/HOGZljV7aq0gFJjG1Fi/HdwTbFaXdrpZNSsT81bgZC/3oZ1aV4qCGJr6Ig== X-Received: by 10.99.125.16 with SMTP id y16mr4780627pgc.3.1519282508615; Wed, 21 Feb 2018 22:55:08 -0800 (PST) From: Heyi Guo To: edk2-devel@lists.01.org Date: Thu, 22 Feb 2018 14:54:34 +0800 Message-Id: <1519282474-94811-3-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1519282474-94811-1-git-send-email-heyi.guo@linaro.org> References: <1519282474-94811-1-git-send-email-heyi.guo@linaro.org> Subject: [edk2] [RFC v2 2/2] MdeModulePkg/PciBus: return CPU address for GetBarAttributes X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ruiyu Ni , Eric Dong , Ard Biesheuvel , Heyi Guo , Michael D Kinney , Laszlo Ersek , Star Zeng MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" PciIo::GetBarAttributes should return CPU view address according to UEFI spec 2.7, so we change the implementation to follow the spec. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Heyi Guo Cc: Ruiyu Ni Cc: Ard Biesheuvel Cc: Star Zeng Cc: Eric Dong Cc: Laszlo Ersek Cc: Michael D Kinney --- MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c b/MdeModulePkg/Bus/Pci/= PciBusDxe/PciIo.c index 190f4b0..0aafcba 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c @@ -1814,8 +1814,8 @@ GetMmioAddressTranslationOffset ( =20 while (Configuration->Desc =3D=3D ACPI_ADDRESS_SPACE_DESCRIPTOR) { if ((Configuration->ResType =3D=3D ACPI_ADDRESS_SPACE_TYPE_MEM) && - (Configuration->AddrRangeMin <=3D AddrRangeMin) && - (Configuration->AddrRangeMin + Configuration->AddrLen >=3D AddrRan= geMin + AddrLen) + (Configuration->AddrRangeMin + Configuration->AddrTranslationOffse= t <=3D AddrRangeMin) && + (Configuration->AddrRangeMin + Configuration->AddrLen + Configurat= ion->AddrTranslationOffset >=3D AddrRangeMin + AddrLen) ) { return Configuration->AddrTranslationOffset; } @@ -1968,6 +1968,11 @@ PciIoGetBarAttributes ( return EFI_UNSUPPORTED; } } + + // According to UEFI spec 2.7, we need return CPU view address for Pci= Io::GetBarAttributes, + // and PCI view =3D CPU view + translation + Descriptor->AddrRangeMin -=3D Descriptor->AddrTranslationOffset; + Descriptor->AddrRangeMax -=3D Descriptor->AddrTranslationOffset; } =20 return EFI_SUCCESS; --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel