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charset="utf-8" From: Meenakshi Aggarwal This library add supports for BE read/write and other MMIO helper function. In this data swapped after reading from MMIO and before write using MMIO. It can be used by any module with BE address space. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Meenakshi Aggarwal --- Silicon/NXP/Include/Library/BeIoLib.h | 332 ++++++++++++++++++++++++++ Silicon/NXP/Library/BeIoLib/BeIoLib.c | 400 ++++++++++++++++++++++++++++= ++++ Silicon/NXP/Library/BeIoLib/BeIoLib.inf | 31 +++ 3 files changed, 763 insertions(+) create mode 100644 Silicon/NXP/Include/Library/BeIoLib.h create mode 100644 Silicon/NXP/Library/BeIoLib/BeIoLib.c create mode 100644 Silicon/NXP/Library/BeIoLib/BeIoLib.inf diff --git a/Silicon/NXP/Include/Library/BeIoLib.h b/Silicon/NXP/Include/Li= brary/BeIoLib.h new file mode 100644 index 0000000..a58883a --- /dev/null +++ b/Silicon/NXP/Include/Library/BeIoLib.h @@ -0,0 +1,332 @@ +/** BeIoLib.h + * + * Copyright 2017 NXP + * + * This program and the accompanying materials + * are licensed and made available under the terms and conditions of the = BSD License + * which accompanies this distribution. The full text of the license may= be found at + * http://opensource.org/licenses/bsd-license.php + * + * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR I= MPLIED. + * + **/ + +#ifndef __BE_IOLIB_H__ +#define __BE_IOLIB_H__ + +#include + +/** + MmioRead8 for Big-Endian modules. + + @param Address The MMIO register to read. + + @return The value read. + +**/ +UINT8 +EFIAPI +BeMmioRead8 ( + IN UINTN Address + ); + +/** + MmioRead16 for Big-Endian modules. + + @param Address The MMIO register to read. + + @return The value read. + +**/ +UINT16 +EFIAPI +BeMmioRead16 ( + IN UINTN Address + ); + +/** + MmioRead32 for Big-Endian modules. + + @param Address The MMIO register to read. + + @return The value read. + +**/ +UINT32 +EFIAPI +BeMmioRead32 ( + IN UINTN Address + ); + +/** + MmioRead64 for Big-Endian modules. + + @param Address The MMIO register to read. + + @return The value read. + +**/ +UINT64 +EFIAPI +BeMmioRead64 ( + IN UINTN Address + ); + +/** + MmioWrite8 for Big-Endian modules. + + @param Address The MMIO register to write. + @param Value The value to write to the MMIO register. + +**/ +UINT8 +EFIAPI +BeMmioWrite8 ( + IN UINTN Address, + IN UINT8 Value + ); + +/** + MmioWrite16 for Big-Endian modules. + + @param Address The MMIO register to write. + @param Value The value to write to the MMIO register. + +**/ +UINT16 +EFIAPI +BeMmioWrite16 ( + IN UINTN Address, + IN UINT16 Value + ); + +/** + MmioWrite32 for Big-Endian modules. + + @param Address The MMIO register to write. + @param Value The value to write to the MMIO register. + +**/ +UINT32 +EFIAPI +BeMmioWrite32 ( + IN UINTN Address, + IN UINT32 Value + ); + +/** + MmioWrite64 for Big-Endian modules. + + @param Address The MMIO register to write. + @param Value The value to write to the MMIO register. + +**/ +UINT64 +EFIAPI +BeMmioWrite64 ( + IN UINTN Address, + IN UINT64 Value + ); + +/** + MmioAndThenOr8 for Big-Endian modules. + + @param Address The MMIO register to write. + @param AndData The value to AND with the read value from the MMIO regis= ter. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the MMIO register. + +**/ +UINT8 +EFIAPI +BeMmioAndThenOr8 ( + IN UINTN Address, + IN UINT8 AndData, + IN UINT8 OrData + ); + +/** + MmioAndThenOr16 for Big-Endian modules. + + @param Address The MMIO register to write. + @param AndData The value to AND with the read value from the MMIO regis= ter. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the MMIO register. + +**/ +UINT16 +EFIAPI +BeMmioAndThenOr16 ( + IN UINTN Address, + IN UINT16 AndData, + IN UINT16 OrData + ); + +/** + MmioAndThenOr32 for Big-Endian modules. + + @param Address The MMIO register to write. + @param AndData The value to AND with the read value from the MMIO regis= ter. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the MMIO register. + +**/ +UINT32 +EFIAPI +BeMmioAndThenOr32 ( + IN UINTN Address, + IN UINT32 AndData, + IN UINT32 OrData + ); + +/** + MmioAndThenOr64 for Big-Endian modules. + + @param Address The MMIO register to write. + @param AndData The value to AND with the read value from the MMIO regis= ter. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the MMIO register. + +**/ +UINT64 +EFIAPI +BeMmioAndThenOr64 ( + IN UINTN Address, + IN UINT64 AndData, + IN UINT64 OrData + ); + +/** + MmioOr8 for Big-Endian modules. + + @param Address The MMIO register to write. + @param OrData The value to OR with the read value from the MMIO regist= er. + + @return The value written back to the MMIO register. + +**/ +UINT8 +EFIAPI +BeMmioOr8 ( + IN UINTN Address, + IN UINT8 OrData + ); + +/** + MmioOr16 for Big-Endian modules. + + @param Address The MMIO register to write. + @param OrData The value to OR with the read value from the MMIO regist= er. + + @return The value written back to the MMIO register. + +**/ +UINT16 +EFIAPI +BeMmioOr16 ( + IN UINTN Address, + IN UINT16 OrData + ); + +/** + MmioOr32 for Big-Endian modules. + + @param Address The MMIO register to write. + @param OrData The value to OR with the read value from the MMIO regist= er. + + @return The value written back to the MMIO register. + +**/ +UINT32 +EFIAPI +BeMmioOr32 ( + IN UINTN Address, + IN UINT32 OrData + ); + +/** + MmioOr64 for Big-Endian modules. + + @param Address The MMIO register to write. + @param OrData The value to OR with the read value from the MMIO regist= er. + + @return The value written back to the MMIO register. + +**/ +UINT64 +EFIAPI +BeMmioOr64 ( + IN UINTN Address, + IN UINT64 OrData + ); + +/** + MmioAnd8 for Big-Endian modules. + + @param Address The MMIO register to write. + @param AndData The value to AND with the read value from the MMIO regis= ter. + + @return The value written back to the MMIO register. + +**/ +UINT8 +EFIAPI +BeMmioAnd8 ( + IN UINTN Address, + IN UINT8 AndData + ); + +/** + MmioAnd16 for Big-Endian modules. + + @param Address The MMIO register to write. + @param AndData The value to AND with the read value from the MMIO regis= ter. + + @return The value written back to the MMIO register. + +**/ +UINT16 +EFIAPI +BeMmioAnd16 ( + IN UINTN Address, + IN UINT16 AndData + ); + +/** + MmioAnd32 for Big-Endian modules. + + @param Address The MMIO register to write. + @param AndData The value to AND with the read value from the MMIO regis= ter. + + @return The value written back to the MMIO register. + +**/ +UINT32 +EFIAPI +BeMmioAnd32 ( + IN UINTN Address, + IN UINT32 AndData + ); + +/** + MmioAnd64 for Big-Endian modules. + + @param Address The MMIO register to write. + @param AndData The value to AND with the read value from the MMIO regis= ter. + + @return The value written back to the MMIO register. + +**/ +UINT64 +EFIAPI +BeMmioAnd64 ( + IN UINTN Address, + IN UINT64 AndData + ); + +#endif /* _BE_IOLIB_H */ diff --git a/Silicon/NXP/Library/BeIoLib/BeIoLib.c b/Silicon/NXP/Library/Be= IoLib/BeIoLib.c new file mode 100644 index 0000000..b4b12ac --- /dev/null +++ b/Silicon/NXP/Library/BeIoLib/BeIoLib.c @@ -0,0 +1,400 @@ +/** BeIoLib.c + + Provide MMIO APIs for BE modules. + + Copyright 2017 NXP + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include +#include +#include + +/** + MmioRead8 for Big-Endian modules. + + @param Address The MMIO register to read. + + @return The value read. + +**/ +UINT8 +EFIAPI +BeMmioRead8 ( + IN UINTN Address + ) +{ + return MmioRead8 (Address); +} + +/** + MmioRead16 for Big-Endian modules. + + @param Address The MMIO register to read. + + @return The value read. + +**/ +UINT16 +EFIAPI +BeMmioRead16 ( + IN UINTN Address + ) +{ + return SwapBytes16 (MmioRead16 (Address)); +} + +/** + MmioRead32 for Big-Endian modules. + + @param Address The MMIO register to read. + + @return The value read. + +**/ +UINT32 +EFIAPI +BeMmioRead32 ( + IN UINTN Address + ) +{ + return SwapBytes32 (MmioRead32 (Address)); +} + +/** + MmioRead64 for Big-Endian modules. + + @param Address The MMIO register to read. + + @return The value read. + +**/ +UINT64 +EFIAPI +BeMmioRead64 ( + IN UINTN Address + ) +{ + return SwapBytes64 (MmioRead64 (Address)); +} + +/** + MmioWrite8 for Big-Endian modules. + + @param Address The MMIO register to write. + @param Value The value to write to the MMIO register. + +**/ +UINT8 +EFIAPI +BeMmioWrite8 ( + IN UINTN Address, + IN UINT8 Value + ) +{ + return MmioWrite8 (Address, Value); +} + +/** + MmioWrite16 for Big-Endian modules. + + @param Address The MMIO register to write. + @param Value The value to write to the MMIO register. + +**/ +UINT16 +EFIAPI +BeMmioWrite16 ( + IN UINTN Address, + IN UINT16 Value + ) +{ + return MmioWrite16 (Address, SwapBytes16 (Value)); +} + +/** + MmioWrite32 for Big-Endian modules. + + @param Address The MMIO register to write. + @param Value The value to write to the MMIO register. + +**/ +UINT32 +EFIAPI +BeMmioWrite32 ( + IN UINTN Address, + IN UINT32 Value + ) +{ + return MmioWrite32 (Address, SwapBytes32 (Value)); +} + +/** + MmioWrite64 for Big-Endian modules. + + @param Address The MMIO register to write. + @param Value The value to write to the MMIO register. + +**/ +UINT64 +EFIAPI +BeMmioWrite64 ( + IN UINTN Address, + IN UINT64 Value + ) +{ + return MmioWrite64 (Address, SwapBytes64 (Value)); +} + +/** + MmioAndThenOr8 for Big-Endian modules. + + @param Address The MMIO register to write. + @param AndData The value to AND with the read value from the MMIO regis= ter. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the MMIO register. + +**/ +UINT8 +EFIAPI +BeMmioAndThenOr8 ( + IN UINTN Address, + IN UINT8 AndData, + IN UINT8 OrData + ) +{ + return MmioAndThenOr8 (Address, AndData, OrData); +} + +/** + MmioAndThenOr16 for Big-Endian modules. + + @param Address The MMIO register to write. + @param AndData The value to AND with the read value from the MMIO regis= ter. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the MMIO register. + +**/ +UINT16 +EFIAPI +BeMmioAndThenOr16 ( + IN UINTN Address, + IN UINT16 AndData, + IN UINT16 OrData + ) +{ + AndData =3D SwapBytes16 (AndData); + OrData =3D SwapBytes16 (OrData); + + return MmioAndThenOr16 (Address, AndData, OrData); +} + +/** + MmioAndThenOr32 for Big-Endian modules. + + @param Address The MMIO register to write. + @param AndData The value to AND with the read value from the MMIO regis= ter. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the MMIO register. + +**/ +UINT32 +EFIAPI +BeMmioAndThenOr32 ( + IN UINTN Address, + IN UINT32 AndData, + IN UINT32 OrData + ) +{ + AndData =3D SwapBytes32 (AndData); + OrData =3D SwapBytes32 (OrData); + + return MmioAndThenOr32 (Address, AndData, OrData); +} + +/** + MmioAndThenOr64 for Big-Endian modules. + + @param Address The MMIO register to write. + @param AndData The value to AND with the read value from the MMIO regis= ter. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the MMIO register. + +**/ +UINT64 +EFIAPI +BeMmioAndThenOr64 ( + IN UINTN Address, + IN UINT64 AndData, + IN UINT64 OrData + ) +{ + AndData =3D SwapBytes64 (AndData); + OrData =3D SwapBytes64 (OrData); + + return MmioAndThenOr64 (Address, AndData, OrData); +} + +/** + MmioOr8 for Big-Endian modules. + + @param Address The MMIO register to write. + @param OrData The value to OR with the read value from the MMIO regist= er. + + @return The value written back to the MMIO register. + +**/ +UINT8 +EFIAPI +BeMmioOr8 ( + IN UINTN Address, + IN UINT8 OrData + ) +{ + return MmioOr8 (Address, OrData); +} + +/** + MmioOr16 for Big-Endian modules. + + @param Address The MMIO register to write. + @param OrData The value to OR with the read value from the MMIO regist= er. + + @return The value written back to the MMIO register. + +**/ +UINT16 +EFIAPI +BeMmioOr16 ( + IN UINTN Address, + IN UINT16 OrData + ) +{ + return MmioOr16 (Address, SwapBytes16 (OrData)); +} + +/** + MmioOr32 for Big-Endian modules. + + @param Address The MMIO register to write. + @param OrData The value to OR with the read value from the MMIO regist= er. + + @return The value written back to the MMIO register. + +**/ +UINT32 +EFIAPI +BeMmioOr32 ( + IN UINTN Address, + IN UINT32 OrData + ) +{ + return MmioOr32 (Address, SwapBytes32 (OrData)); +} + +/** + MmioOr64 for Big-Endian modules. + + @param Address The MMIO register to write. + @param OrData The value to OR with the read value from the MMIO regist= er. + + @return The value written back to the MMIO register. + +**/ +UINT64 +EFIAPI +BeMmioOr64 ( + IN UINTN Address, + IN UINT64 OrData + ) +{ + return MmioOr64 (Address, SwapBytes64 (OrData)); +} + +/** + MmioAnd8 for Big-Endian modules. + + @param Address The MMIO register to write. + @param AndData The value to AND with the read value from the MMIO regis= ter. + + @return The value written back to the MMIO register. + +**/ +UINT8 +EFIAPI +BeMmioAnd8 ( + IN UINTN Address, + IN UINT8 AndData + ) +{ + return MmioAnd8 (Address, AndData); +} + +/** + MmioAnd16 for Big-Endian modules. + + @param Address The MMIO register to write. + @param AndData The value to AND with the read value from the MMIO regis= ter. + + @return The value written back to the MMIO register. + +**/ +UINT16 +EFIAPI +BeMmioAnd16 ( + IN UINTN Address, + IN UINT16 AndData + ) +{ + return MmioAnd16 (Address, SwapBytes16 (AndData)); +} + +/** + MmioAnd32 for Big-Endian modules. + + @param Address The MMIO register to write. + @param AndData The value to AND with the read value from the MMIO regis= ter. + + @return The value written back to the MMIO register. + +**/ +UINT32 +EFIAPI +BeMmioAnd32 ( + IN UINTN Address, + IN UINT32 AndData + ) +{ + return MmioAnd32 (Address, SwapBytes32 (AndData)); +} + +/** + MmioAnd64 for Big-Endian modules. + + @param Address The MMIO register to write. + @param AndData The value to AND with the read value from the MMIO regis= ter. + + @return The value written back to the MMIO register. + +**/ +UINT64 +EFIAPI +BeMmioAnd64 ( + IN UINTN Address, + IN UINT64 AndData + ) +{ + return MmioAnd64 (Address, SwapBytes64 (AndData)); +} diff --git a/Silicon/NXP/Library/BeIoLib/BeIoLib.inf b/Silicon/NXP/Library/= BeIoLib/BeIoLib.inf new file mode 100644 index 0000000..a1c19d0 --- /dev/null +++ b/Silicon/NXP/Library/BeIoLib/BeIoLib.inf @@ -0,0 +1,31 @@ +## @BeIoLib.inf + +# Copyright 2017 NXP +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +## + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D BeIoLib + FILE_GUID =3D 28d77333-77eb-4faf-8735-130e5eb3e343 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D BeIoLib + +[Sources.common] + BeIoLib.c + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses] + IoLib --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun May 5 06:05:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; 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charset="utf-8" From: Meenakshi Aggarwal Installs watchdog timer arch protocol Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Meenakshi Aggarwal --- Silicon/NXP/Drivers/WatchDog/WatchDog.c | 459 +++++++++++++++++++++++= ++++ Silicon/NXP/Drivers/WatchDog/WatchDog.h | 39 +++ Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf | 47 +++ 3 files changed, 545 insertions(+) create mode 100644 Silicon/NXP/Drivers/WatchDog/WatchDog.c create mode 100644 Silicon/NXP/Drivers/WatchDog/WatchDog.h create mode 100644 Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf diff --git a/Silicon/NXP/Drivers/WatchDog/WatchDog.c b/Silicon/NXP/Drivers/= WatchDog/WatchDog.c new file mode 100644 index 0000000..ca1377b --- /dev/null +++ b/Silicon/NXP/Drivers/WatchDog/WatchDog.c @@ -0,0 +1,459 @@ +/** WatchDog.c +* +* Based on Watchdog driver implemenation available in +* ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805Watchdog.c +* +* Copyright 2017 NXP +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the B= SD License +* which accompanies this distribution. The full text of the license may = be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "WatchDog.h" + +STATIC EFI_EVENT EfiExitBootServicesEvent; +STATIC EFI_EVENT WdogFeedEvent; + +STATIC +UINT16 +EFIAPI +WdogRead ( + IN UINTN Address + ) +{ + if (FixedPcdGetBool (PcdWdogBigEndian)) { + return BeMmioRead16 (Address); + } else { + return MmioRead16(Address); + } +} + +STATIC +UINT16 +EFIAPI +WdogWrite ( + IN UINTN Address, + IN UINT16 Value + ) +{ + if (FixedPcdGetBool (PcdWdogBigEndian)) { + return BeMmioWrite16 (Address, Value); + } else { + return MmioWrite16 (Address, Value); + } +} + +STATIC +UINT16 +EFIAPI +WdogAndThenOr ( + IN UINTN Address, + IN UINT16 And, + IN UINT16 Or + ) +{ + if (FixedPcdGetBool (PcdWdogBigEndian)) { + return BeMmioAndThenOr16 (Address, And, Or); + } else { + return MmioAndThenOr16 (Address, And, Or); + } +} + +STATIC +UINT16 +EFIAPI +WdogOr ( + IN UINTN Address, + IN UINT16 Or + ) +{ + if (FixedPcdGetBool (PcdWdogBigEndian)) { + return BeMmioOr16 (Address, Or); + } else { + return MmioOr16 (Address, Or); + } +} + +STATIC +VOID +WdogPing ( + VOID + ) +{ + // + // To reload a timeout value to the counter the proper service sequence = begins by + // writing 0x_5555 followed by 0x_AAAA to the Watchdog Service Register = (WDOG_WSR). + // This service sequence will reload the counter with the timeout value = WT[7:0] of + // Watchdog Control Register (WDOG_WCR). + // + + WdogWrite (PcdGet64 (PcdWdog1BaseAddr) + WDOG_WSR_OFFSET, + WDOG_SERVICE_SEQ1); + WdogWrite (PcdGet64 (PcdWdog1BaseAddr) + WDOG_WSR_OFFSET, + WDOG_SERVICE_SEQ2); +} + +/** + Stop the Wdog watchdog timer from counting down. +**/ +STATIC +VOID +WdogStop ( + VOID + ) +{ + // Watchdog cannot be disabled by software once started. + // At best, we can keep reload counter with maximum value + + WdogAndThenOr (PcdGet64 (PcdWdog1BaseAddr) + WDOG_WCR_OFFSET, + (UINT16)(~WDOG_WCR_WT), + (WD_COUNT (WT_MAX_TIME) & WD_COUNT_MASK)); + WdogPing (); +} + +/** + Starts the Wdog counting down by feeding Service register with + desired pattern. + The count down will start from the value stored in the Load register, + not from the value where it was previously stopped. +**/ +STATIC +VOID +WdogStart ( + VOID + ) +{ + //Reload the timeout value + WdogPing (); +} + +/** + On exiting boot services we must make sure the Wdog Watchdog Timer + is stopped. +**/ +STATIC +VOID +EFIAPI +ExitBootServicesEvent ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + WdogStop (); +} + +/** + This function registers the handler NotifyFunction so it is called every= time + the watchdog timer expires. It also passes the amount of time since the= last + handler call to the NotifyFunction. + If NotifyFunction is not NULL and a handler is not already registered, + then the new handler is registered and EFI_SUCCESS is returned. + If NotifyFunction is NULL, and a handler is already registered, + then that handler is unregistered. + If an attempt is made to register a handler when a handler is already re= gistered, + then EFI_ALREADY_STARTED is returned. + If an attempt is made to unregister a handler when a handler is not regi= stered, + then EFI_INVALID_PARAMETER is returned. + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + @param NotifyFunction The function to call when a timer interrupt fir= es. This + function executes at TPL_HIGH_LEVEL. The DXE Co= re will + register a handler for the timer interrupt, so = it can know + how much time has passed. This information is u= sed to + signal timer based events. NULL will unregister= the handler. + + @retval EFI_SUCCESS The watchdog timer handler was registered. + @retval EFI_ALREADY_STARTED NotifyFunction is not NULL, and a handler = is already + registered. + @retval EFI_INVALID_PARAMETER NotifyFunction is NULL, and a handler was = not + previously registered. + +**/ +STATIC +EFI_STATUS +EFIAPI +WdogRegisterHandler ( + IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This, + IN EFI_WATCHDOG_TIMER_NOTIFY NotifyFunction + ) +{ + // ERROR: This function is not supported. + // The hardware watchdog will reset the board + return EFI_INVALID_PARAMETER; +} + +/** + + This function adjusts the period of timer interrupts to the value specif= ied + by TimerPeriod. If the timer period is updated, then the selected timer + period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned. = If + the timer hardware is not programmable, then EFI_UNSUPPORTED is returned. + If an error occurs while attempting to update the timer period, then the + timer hardware will be put back in its state prior to this call, and + EFI_DEVICE_ERROR is returned. If TimerPeriod is 0, then the timer inter= rupt + is disabled. This is not the same as disabling the CPU's interrupts. + Instead, it must either turn off the timer hardware, or it must adjust t= he + interrupt controller so that a CPU interrupt is not generated when the t= imer + interrupt fires. + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + @param TimerPeriod The rate to program the timer interrupt in 100 = nS units. If + the timer hardware is not programmable, then EF= I_UNSUPPORTED is + returned. If the timer is programmable, then th= e timer period + will be rounded up to the nearest timer period = that is supported + by the timer hardware. If TimerPeriod is set to= 0, then the + timer interrupts will be disabled. + + + @retval EFI_SUCCESS The timer period was changed. + @retval EFI_UNSUPPORTED The platform cannot change the period of t= he timer interrupt. + @retval EFI_DEVICE_ERROR The timer period could not be changed due = to a device error. + +**/ +STATIC +EFI_STATUS +EFIAPI +WdogSetTimerPeriod ( + IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This, + IN UINT64 TimerPeriod // In 100ns units + ) +{ + EFI_STATUS Status; + UINT64 TimerPeriodInSec; + UINT16 Val; + + Status =3D EFI_SUCCESS; + + if (TimerPeriod =3D=3D 0) { + // This is a watchdog stop request + WdogStop (); + return Status; + } else { + // Convert the TimerPeriod (in 100 ns unit) to an equivalent second va= lue + + TimerPeriodInSec =3D DivU64x32 (TimerPeriod, NANO_SECOND_BASE); + + // The registers in the Wdog are only 32 bits + if (TimerPeriodInSec > WT_MAX_TIME) { + // We could load the watchdog with the maximum supported value but + // if a smaller value was requested, this could have the watchdog + // triggering before it was intended. + // Better generate an error to let the caller know. + Status =3D EFI_DEVICE_ERROR; + return Status; + } + + // set the new timeout value in the WCR + // Convert the timeout value from Seconds to timer count + Val =3D ((WD_COUNT(TimerPeriodInSec) & WD_COUNT_MASK) << 8); + + WdogAndThenOr (PcdGet64 (PcdWdog1BaseAddr) + WDOG_WCR_OFFSET, + (UINT16)(~WDOG_WCR_WT), + Val); + // Start the watchdog + WdogStart (); + } + + return Status; +} + +/** + This function retrieves the period of timer interrupts in 100 ns units, + returns that value in TimerPeriod, and returns EFI_SUCCESS. If TimerPer= iod + is NULL, then EFI_INVALID_PARAMETER is returned. If a TimerPeriod of 0 = is + returned, then the timer is currently disabled. + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + @param TimerPeriod A pointer to the timer period to retrieve in 10= 0 ns units. If + 0 is returned, then the timer is currently disa= bled. + + + @retval EFI_SUCCESS The timer period was returned in TimerPeri= od. + @retval EFI_INVALID_PARAMETER TimerPeriod is NULL. + +**/ +STATIC +EFI_STATUS +EFIAPI +WdogGetTimerPeriod ( + IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This, + OUT UINT64 *TimerPeriod + ) +{ + EFI_STATUS Status; + UINT64 ReturnValue; + UINT16 Val; + + Status =3D EFI_SUCCESS; + + if (TimerPeriod =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + // Check if the watchdog is stopped + if ((WdogRead (PcdGet64 (PcdWdog1BaseAddr) + WDOG_WCR_OFFSET) + & WDOG_WCR_WDE) =3D=3D 0 ) { + // It is stopped, so return zero. + ReturnValue =3D 0; + } else { + // Convert the Watchdog ticks into equivalent TimerPeriod second value. + Val =3D (WdogRead (PcdGet64 (PcdWdog1BaseAddr) + WDOG_WCR_OFFSET) + & WDOG_WCR_WT ) >> 8; + ReturnValue =3D WD_SEC(Val); + } + + *TimerPeriod =3D ReturnValue; + return Status; +} + +/** + Interface structure for the Watchdog Architectural Protocol. + + @par Protocol Description: + This protocol provides a service to set the amount of time to wait + before firing the watchdog timer, and it also provides a service to + register a handler that is invoked when the watchdog timer fires. + + @par When the watchdog timer fires, control will be passed to a handler + if one has been registered. If no handler has been registered, + or the registered handler returns, then the system will be + reset by calling the Runtime Service ResetSystem(). + + @param RegisterHandler + Registers a handler that will be called each time the + watchdogtimer interrupt fires. TimerPeriod defines the minimum + time between timer interrupts, so TimerPeriod will also + be the minimum time between calls to the registered + handler. + NOTE: If the watchdog resets the system in hardware, then + this function will not have any chance of executing. + + @param SetTimerPeriod + Sets the period of the timer interrupt in 100 nS units. + This function is optional, and may return EFI_UNSUPPORTED. + If this function is supported, then the timer period will + be rounded up to the nearest supported timer period. + + @param GetTimerPeriod + Retrieves the period of the timer interrupt in 100 nS units. + +**/ +STATIC +EFI_WATCHDOG_TIMER_ARCH_PROTOCOL gWatchdogTimer =3D { + WdogRegisterHandler, + WdogSetTimerPeriod, + WdogGetTimerPeriod +}; + +/** + Call back function when the timer event is signaled. + This function will feed the watchdog with maximum value + so that system wont reset in idle case e.g. stopped on UEFI shell. + + @param[in] Event The Event this notify function registered to. + @param[in] Context Pointer to the context data registered to the + Event. + +**/ +VOID +EFIAPI +WdogFeed ( + IN EFI_EVENT Event, + IN VOID* Context + ) +{ + WdogPing(); +} +/** + Initialize state information for the Watchdog Timer Architectural Protoc= ol. + + @param ImageHandle of the loaded driver + @param SystemTable Pointer to the System Table + + @retval EFI_SUCCESS Protocol registered + @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure + @retval EFI_DEVICE_ERROR Hardware problems + +**/ +EFI_STATUS +EFIAPI +WdogInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_HANDLE Handle; + + WdogAndThenOr (PcdGet64 (PcdWdog1BaseAddr) + WDOG_WCR_OFFSET, + (UINT16)(~WDOG_WCR_WT), + (WD_COUNT (WT_MAX_TIME) & WD_COUNT_MASK)); + + WdogOr (PcdGet64 (PcdWdog1BaseAddr) + WDOG_WCR_OFFSET, WDOG_WCR_WDE); + + // + // Make sure the Watchdog Timer Architectural Protocol + // has not been installed in the system yet. + // This will avoid conflicts with the universal watchdog + // + ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiWatchdogTimerArchProtocolG= uid); + + // Register for an ExitBootServicesEvent + Status =3D gBS->CreateEvent (EVT_SIGNAL_EXIT_BOOT_SERVICES, TPL_NOTIFY, + ExitBootServicesEvent, NULL, &EfiExitBootServicesEvent); + if (EFI_ERROR (Status)) { + Status =3D EFI_OUT_OF_RESOURCES; + return Status; + } + + // + // Start the timer to feed Watchdog with maximum timeout value. + // + Status =3D gBS->CreateEvent ( + EVT_TIMER | EVT_NOTIFY_SIGNAL, + TPL_NOTIFY, + WdogFeed, + NULL, + &WdogFeedEvent + ); + if (EFI_ERROR (Status)) { + return Status; + } + + Status =3D gBS->SetTimer (WdogFeedEvent, TimerPeriodic, WT_FEED_INTERVAL= ); + if (EFI_ERROR (Status)) { + return Status; + } + + // Install the Timer Architectural Protocol onto a new handle + Handle =3D NULL; + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &Handle, + &gEfiWatchdogTimerArchProtocolGuid, &gWatchdogTimer, + NULL + ); + if (EFI_ERROR (Status)) { + gBS->CloseEvent (EfiExitBootServicesEvent); + Status =3D EFI_OUT_OF_RESOURCES; + return Status; + } + + WdogPing (); + + return Status; +} diff --git a/Silicon/NXP/Drivers/WatchDog/WatchDog.h b/Silicon/NXP/Drivers/= WatchDog/WatchDog.h new file mode 100644 index 0000000..9542608 --- /dev/null +++ b/Silicon/NXP/Drivers/WatchDog/WatchDog.h @@ -0,0 +1,39 @@ +/** WatchDog.h +* +* Copyright 2017 NXP +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the B= SD License +* which accompanies this distribution. The full text of the license may = be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#ifndef __WATCHDOG_H__ +#define __WATCHDOG_H__ + +#define WDOG_SIZE 0x1000 +#define WDOG_WCR_OFFSET 0 +#define WDOG_WSR_OFFSET 2 +#define WDOG_WRSR_OFFSET 4 +#define WDOG_WICR_OFFSET 6 +#define WDOG_WCR_WT (0xFF << 8) +#define WDOG_WCR_WDE (1 << 2) +#define WDOG_SERVICE_SEQ1 0x5555 +#define WDOG_SERVICE_SEQ2 0xAAAA +#define WDOG_WCR_WDZST 0x1 +#define WDOG_WCR_WRE (1 << 3) /* -> WDOG Reset Enable */ + +#define WT_MAX_TIME 128 +#define WD_COUNT(Sec) (((Sec) * 2 - 1) << 8) +#define WD_COUNT_MASK 0xff00 +#define WD_SEC(Cnt) (((Cnt) + 1) / 2) + +#define NANO_SECOND_BASE 10000000 + +#define WT_FEED_INTERVAL (WT_MAX_TIME * NANO_SECOND_BASE) + +#endif //__WATCHDOG_H__ diff --git a/Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf b/Silicon/NXP/Dri= vers/WatchDog/WatchDogDxe.inf new file mode 100644 index 0000000..e6c06ef --- /dev/null +++ b/Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf @@ -0,0 +1,47 @@ +# WatchDog.inf +# +# Component description file for WatchDog module +# +# Copyright 2017 NXP +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +# + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D WatchDogDxe + FILE_GUID =3D 0358b544-ec65-4339-89cd-cad60a3dd787 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D WdogInitialize + +[Sources.common] + WatchDog.c + +[Packages] + MdePkg/MdePkg.dec + Silicon/NXP/NxpQoriqLs.dec + +[LibraryClasses] + BaseLib + BeIoLib + PcdLib + UefiBootServicesTableLib + UefiDriverEntryPoint + +[Pcd] + gNxpQoriqLsTokenSpaceGuid.PcdWdog1BaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdWdogBigEndian + +[Protocols] + gEfiWatchdogTimerArchProtocolGuid + +[Depex] + TRUE --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun May 5 06:05:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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VI1PR04MB1008; 6:f7ljjNZi0Ld8s4gJszIn7ZrmnkYvKrQtwfGldgmBNXaH7sop+dTA/f4M/KShSnLLOmFS9balIbv0e8HIWLo5jjwrIBOjH46dUX3Xw4jcOI6vX/88wL17gM9yDCeZ5gRKPpVImWTuISz52+0t829G8hqs3j3oVtrOSVVFnGI2YXaMli54/4uqLrDaAUcrhBPSlGSm3mtodW34WiIvaPf9G7Y8yDMu5kykn/uuH2S7scIGySLJWvPg/gJ+2x6NfJzTOsf/2IOA678RsrFv6HsF8Y96j28hXI1lPAes9DJL1YRqYv+eqnqF8U1RJsKGdujpPa8eS/Mss6oGBPbhJJGM8Khp4XlAqd14gyK71TkLREg=; 5:1Lw94g85kWGpkO3AgdCJr40mE0mMAIfopAoaxXuwBKkDic1fSjTC1d22kM6pNtX0NIRsHnJXocKmQbyid7yWE/JbES6NDMytDJAnGYfCXD3vstkVM88Pzh5o2rIFFXo+foWdqxZHUWClc47dznJuV7qW9q8dNIK/87tuuU2gYmo=; 24:03y3Ew4IUgb8RIx1VbAsC0C5IlgwV7DZmcxb+39bE393iMf4wb9ZHHacGPUc2q06yHsi8p9/W3dqDflQdsHDopEwiXutIVRPO6R/1a6Ia+8=; 7:jdtD1rZivgjsH7C7pU72mMnwEmylfuzmzGY91Z6ztyKTWWcSnp+9W6XoDu4C9lqjnqmDXEJh5wApDcMpH/z+mCAt68rXSWnl/Xxnj9c+Pwxy0woSKPbAPl2hkbb2gW4cUBla+2Yob13Jt5z6A3vN15gPVh/3qB9ONAgDeCL2viMOsSq8C0B5z9eVbYoR5UrpgqxZNUTaOpDhSCjKCJ28ZizKU9QzPycyUpcWNEUHmr/hDXfqMJihO9ZNFX/ElY3A SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Feb 2018 08:52:35.1704 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 37f6a76a-8737-4947-d2a3-08d5751aa17c X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB1008 Subject: [edk2] [PATCH edk2-platforms 03/39] SocLib : Add support for initialization of peripherals X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Meenakshi Aggarwal Add SocInit function that initializes peripherals and print board and soc information. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Meenakshi Aggarwal --- Silicon/NXP/Chassis/Chassis.c | 388 ++++++++++++++++++++++++++= ++++ Silicon/NXP/Chassis/Chassis.h | 144 +++++++++++ Silicon/NXP/Chassis/Chassis2/Chassis2.dec | 19 ++ Silicon/NXP/Chassis/Chassis2/SerDes.h | 68 ++++++ Silicon/NXP/Chassis/Chassis2/Soc.c | 172 +++++++++++++ Silicon/NXP/Chassis/Chassis2/Soc.h | 367 ++++++++++++++++++++++++++= ++ Silicon/NXP/Chassis/LS1043aSocLib.inf | 47 ++++ Silicon/NXP/Chassis/SerDes.c | 271 +++++++++++++++++++++ Silicon/NXP/Include/Bitops.h | 179 ++++++++++++++ Silicon/NXP/LS1043A/Include/SocSerDes.h | 55 +++++ 10 files changed, 1710 insertions(+) create mode 100644 Silicon/NXP/Chassis/Chassis.c create mode 100644 Silicon/NXP/Chassis/Chassis.h create mode 100644 Silicon/NXP/Chassis/Chassis2/Chassis2.dec create mode 100644 Silicon/NXP/Chassis/Chassis2/SerDes.h create mode 100644 Silicon/NXP/Chassis/Chassis2/Soc.c create mode 100644 Silicon/NXP/Chassis/Chassis2/Soc.h create mode 100644 Silicon/NXP/Chassis/LS1043aSocLib.inf create mode 100644 Silicon/NXP/Chassis/SerDes.c create mode 100644 Silicon/NXP/Include/Bitops.h create mode 100644 Silicon/NXP/LS1043A/Include/SocSerDes.h diff --git a/Silicon/NXP/Chassis/Chassis.c b/Silicon/NXP/Chassis/Chassis.c new file mode 100644 index 0000000..9f2928b --- /dev/null +++ b/Silicon/NXP/Chassis/Chassis.c @@ -0,0 +1,388 @@ +/** @file + SoC specific Library containg functions to initialize various SoC compon= ents + + Copyright 2017 NXP + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may be= found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "Chassis.h" + +UINT32 +EFIAPI +GurRead ( + IN UINTN Address + ) +{ + if (FixedPcdGetBool (PcdGurBigEndian)) { + return BeMmioRead32 (Address); + } else { + return MmioRead32 (Address); + } +} + +/* + * Structure to list available SOCs. + */ +STATIC CPU_TYPE CpuTypeList[] =3D { + CPU_TYPE_ENTRY (LS1043A, LS1043A, 4), +}; + +/* + * Return the number of bits set + */ +STATIC +inline +UINTN +CountSetBits ( + IN UINTN Num + ) +{ + UINTN Count; + + Count =3D 0; + + while (Num) { + Count +=3D Num & 1; + Num >>=3D 1; + } + + return Count; +} + +/* + * Return the type of initiator (core or hardware accelerator) + */ +UINT32 +InitiatorType ( + IN UINT32 Cluster, + IN UINTN InitId + ) +{ + CCSR_GUR *GurBase; + UINT32 Idx; + UINT32 Type; + + GurBase =3D (VOID *)PcdGet64 (PcdGutsBaseAddr); + Idx =3D (Cluster >> (InitId * 8)) & TP_CLUSTER_INIT_MASK; + Type =3D GurRead ((UINTN)&GurBase->TpItyp[Idx]); + + if (Type & TP_ITYP_AV_MASK) { + return Type; + } + + return 0; +} + +/* + * Return the mask for number of cores on this SOC. + */ +UINT32 +CpuMask ( + VOID + ) +{ + CCSR_GUR *GurBase; + UINTN ClusterIndex; + UINTN Count; + UINT32 Cluster; + UINT32 Type; + UINT32 Mask; + UINTN InitiatorIndex; + + GurBase =3D (VOID *)PcdGet64 (PcdGutsBaseAddr); + ClusterIndex =3D 0; + Count =3D 0; + Mask =3D 0; + + do { + Cluster =3D GurRead ((UINTN)&GurBase->TpCluster[ClusterIndex].Lower); + for (InitiatorIndex =3D 0; InitiatorIndex < TP_INIT_PER_CLUSTER; Initi= atorIndex++) { + Type =3D InitiatorType (Cluster, InitiatorIndex); + if (Type) { + if (TP_ITYP_TYPE_MASK (Type) =3D=3D TP_ITYP_TYPE_ARM) + Mask |=3D 1 << Count; + Count++; + } + } + ClusterIndex++; + } while (CHECK_CLUSTER (Cluster)); + + return Mask; +} + +/* + * Return the number of cores on this SOC. + */ +UINTN +CpuNumCores ( + VOID + ) +{ + return CountSetBits (CpuMask ()); +} + +/* + * Return the type of core i.e. A53, A57 etc of inputted + * core number. + */ +UINT32 +QoriqCoreToType ( + IN UINTN Core + ) +{ + CCSR_GUR *GurBase; + UINTN ClusterIndex; + UINTN Count; + UINT32 Cluster; + UINT32 Type; + UINTN InitiatorIndex; + + GurBase =3D (VOID *)PcdGet64 (PcdGutsBaseAddr); + ClusterIndex =3D 0; + Count =3D 0; + + do { + Cluster =3D GurRead ((UINTN)&GurBase->TpCluster[ClusterIndex].Lower); + for (InitiatorIndex =3D 0; InitiatorIndex < TP_INIT_PER_CLUSTER; Initi= atorIndex++) { + Type =3D InitiatorType (Cluster, InitiatorIndex); + if (Type) { + if (Count =3D=3D Core) + return Type; + Count++; + } + } + ClusterIndex++; + } while (CHECK_CLUSTER (Cluster)); + + return -1; /* cannot identify the cluster */ +} + +/* + * Print CPU information + */ +VOID +PrintCpuInfo ( + VOID + ) +{ + SYS_INFO SysInfo; + UINTN CoreIndex; + UINTN Core; + UINT32 Type; + CHAR8 Buffer[100]; + UINTN CharCount; + + GetSysInfo (&SysInfo); + CharCount =3D AsciiSPrint (Buffer, sizeof (Buffer), "Clock Configuration= :"); + SerialPortWrite ((UINT8 *) Buffer, CharCount); + + ForEachCpu (CoreIndex, Core, CpuNumCores (), CpuMask ()) { + if (!(CoreIndex % 3)) { + CharCount =3D AsciiSPrint (Buffer, sizeof (Buffer), "\n "); + SerialPortWrite ((UINT8 *) Buffer, CharCount); + } + + Type =3D TP_ITYP_VERSION (QoriqCoreToType (Core)); + CharCount =3D AsciiSPrint (Buffer, sizeof (Buffer), "CPU%d(%a):%-4d MH= z ", Core, + Type =3D=3D TY_ITYP_VERSION_A7 ? "A7 " : + (Type =3D=3D TY_ITYP_VERSION_A53 ? "A53" : + (Type =3D=3D TY_ITYP_VERSION_A57 ? "A57" : + (Type =3D=3D TY_ITYP_VERSION_A72 ? "A72" : " Unknown Core "))), + SysInfo.FreqProcessor[Core] / MEGA_HZ); + SerialPortWrite ((UINT8 *) Buffer, CharCount); + } + + CharCount =3D AsciiSPrint (Buffer, sizeof (Buffer), "\n Bus: %= -4d MHz ", + SysInfo.FreqSystemBus / MEGA_HZ); + SerialPortWrite ((UINT8 *) Buffer, CharCount); + CharCount =3D AsciiSPrint (Buffer, sizeof (Buffer), "DDR: %-4d MT/s= ", + SysInfo.FreqDdrBus / MEGA_HZ); + SerialPortWrite ((UINT8 *) Buffer, CharCount); + + if (SysInfo.FreqFman[0] !=3D 0) { + CharCount =3D AsciiSPrint (Buffer, sizeof (Buffer), "\n FMAN: = %-4d MHz ", + SysInfo.FreqFman[0] / MEGA_HZ); + SerialPortWrite ((UINT8 *) Buffer, CharCount); + } + + CharCount =3D AsciiSPrint (Buffer, sizeof (Buffer), "\n"); + SerialPortWrite ((UINT8 *) Buffer, CharCount); +} + +/* + * Return system bus frequency + */ +UINT64 +GetBusFrequency ( + VOID + ) +{ + SYS_INFO SocSysInfo; + + GetSysInfo (&SocSysInfo); + + return SocSysInfo.FreqSystemBus; +} + +/* + * Return SDXC bus frequency + */ +UINT64 +GetSdxcFrequency ( + VOID + ) +{ + SYS_INFO SocSysInfo; + + GetSysInfo (&SocSysInfo); + + return SocSysInfo.FreqSdhc; +} + +/* + * Print Soc information + */ +VOID +PrintSoc ( + VOID + ) +{ + CHAR8 Buf[16]; + CCSR_GUR *GurBase; + UINTN Count; + UINTN Svr; + UINTN Ver; + + GurBase =3D (VOID *)PcdGet64 (PcdGutsBaseAddr); + + Buf[0] =3D L'\0'; + Svr =3D GurRead ((UINTN)&GurBase->Svr); + Ver =3D SVR_SOC_VER (Svr); + + for (Count =3D 0; Count < ARRAY_SIZE (CpuTypeList); Count++) + if ((CpuTypeList[Count].SocVer & SVR_WO_E) =3D=3D Ver) { + AsciiStrCpy (Buf, (CONST CHAR8 *)CpuTypeList[Count].Name); + + if (IS_E_PROCESSOR (Svr)) { + AsciiStrCat (Buf, (CONST CHAR8 *)"E"); + } + break; + } + + if (Count =3D=3D ARRAY_SIZE (CpuTypeList)) { + AsciiStrCpy (Buf, (CONST CHAR8 *)"unknown"); + } + + DEBUG ((DEBUG_INFO, "SoC: %a (0x%x); Rev %d.%d\n", + Buf, Svr, SVR_MAJOR (Svr), SVR_MINOR (Svr))); + + return; +} + +/* + * Dump RCW (Reset Control Word) on console + */ +VOID +PrintRCW ( + VOID + ) +{ + CCSR_GUR *Base; + UINTN Count; + CHAR8 Buffer[100]; + UINTN CharCount; + + Base =3D (VOID *)PcdGet64 (PcdGutsBaseAddr); + + /* + * Display the RCW, so that no one gets confused as to what RCW + * we're actually using for this boot. + */ + + CharCount =3D AsciiSPrint (Buffer, sizeof (Buffer), + "Reset Configuration Word (RCW):"); + SerialPortWrite ((UINT8 *) Buffer, CharCount); + for (Count =3D 0; Count < ARRAY_SIZE(Base->RcwSr); Count++) { + UINT32 Rcw =3D BeMmioRead32((UINTN)&Base->RcwSr[Count]); + + if ((Count % 4) =3D=3D 0) { + CharCount =3D AsciiSPrint (Buffer, sizeof (Buffer), + "\n %08x:", Count * 4); + SerialPortWrite ((UINT8 *) Buffer, CharCount); + } + + CharCount =3D AsciiSPrint (Buffer, sizeof (Buffer), " %08x", Rcw); + SerialPortWrite ((UINT8 *) Buffer, CharCount); + } + + CharCount =3D AsciiSPrint (Buffer, sizeof (Buffer), "\n"); + SerialPortWrite ((UINT8 *) Buffer, CharCount); +} + +/* + * Setup SMMU in bypass mode + * and also set its pagesize + */ +VOID +SmmuInit ( + VOID + ) +{ + UINT32 Value; + + /* set pagesize as 64K and ssmu-500 in bypass mode */ + Value =3D (MmioRead32 ((UINTN)SMMU_REG_SACR) | SACR_PAGESIZE_MASK); + MmioWrite32 ((UINTN)SMMU_REG_SACR, Value); + + Value =3D (MmioRead32 ((UINTN)SMMU_REG_SCR0) | SCR0_CLIENTPD_MASK) & ~SC= R0_USFCFG_MASK; + MmioWrite32 ((UINTN)SMMU_REG_SCR0, Value); + + Value =3D (MmioRead32 ((UINTN)SMMU_REG_NSCR0) | SCR0_CLIENTPD_MASK) & ~S= CR0_USFCFG_MASK; + MmioWrite32 ((UINTN)SMMU_REG_NSCR0, Value); +} + +/* + * Return current Soc Name form CpuTypeList + */ +CHAR8 * +GetSocName ( + VOID + ) +{ + UINT8 Count; + UINTN Svr; + UINTN Ver; + CCSR_GUR *GurBase; + + GurBase =3D (VOID *)PcdGet64 (PcdGutsBaseAddr); + + Svr =3D GurRead ((UINTN)&GurBase->Svr); + Ver =3D SVR_SOC_VER (Svr); + + for (Count =3D 0; Count < ARRAY_SIZE (CpuTypeList); Count++) { + if ((CpuTypeList[Count].SocVer & SVR_WO_E) =3D=3D Ver) { + return (CHAR8 *)CpuTypeList[Count].Name; + } + } + + return NULL; +} diff --git a/Silicon/NXP/Chassis/Chassis.h b/Silicon/NXP/Chassis/Chassis.h new file mode 100644 index 0000000..4bdb4d0 --- /dev/null +++ b/Silicon/NXP/Chassis/Chassis.h @@ -0,0 +1,144 @@ +/** @file +* Header defining the Base addresses, sizes, flags etc for chassis 1 +* +* Copyright 2017 NXP +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the B= SD License +* which accompanies this distribution. The full text of the license may = be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#ifndef __CHASSIS_H__ +#define __CHASSIS_H__ + +#define TP_ITYP_AV_MASK 0x00000001 /* Initiator available */ +#define TP_ITYP_TYPE_MASK(x) (((x) & 0x6) >> 1) /* Initiator Type */ +#define TP_ITYP_TYPE_ARM 0x0 +#define TP_ITYP_TYPE_PPC 0x1 +#define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */ +#define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */ +#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */ +#define TP_ITYP_VERSION(x) (((x) & 0xe0) >> 5) /* Initiator Versi= on */ +#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */ +#define TP_INIT_PER_CLUSTER 4 + +#define TY_ITYP_VERSION_A7 0x1 +#define TY_ITYP_VERSION_A53 0x2 +#define TY_ITYP_VERSION_A57 0x3 +#define TY_ITYP_VERSION_A72 0x4 + +STATIC +inline +UINTN +CpuMaskNext ( + IN UINTN Cpu, + IN UINTN Mask + ) +{ + for (Cpu++; !((1 << Cpu) & Mask); Cpu++) + ; + + return Cpu; +} + +#define ForEachCpu(Iter, Cpu, NumCpus, Mask) \ + for (Iter =3D 0, Cpu =3D CpuMaskNext(-1, Mask); \ + Iter < NumCpus; \ + Iter++, Cpu =3D CpuMaskNext(Cpu, Mask)) \ + +#define CPU_TYPE_ENTRY(N, V, NC) \ + { .Name =3D #N, .SocVer =3D SVR_##V, .NumCores =3D (NC)} + +#define SVR_WO_E 0xFFFFFE +#define SVR_LS1043A 0x879200 + +#define SVR_MAJOR(svr) (((svr) >> 4) & 0xf) +#define SVR_MINOR(svr) (((svr) >> 0) & 0xf) +#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E) +#define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1)) + +#define MEGA_HZ 1000000 + +typedef struct { + CHAR8 Name[16]; + UINT32 SocVer; + UINT32 NumCores; +} CPU_TYPE; + +typedef struct { + UINTN CpuClk; /* CPU clock in Hz! */ + UINTN BusClk; + UINTN MemClk; + UINTN PciClk; + UINTN SdhcClk; +} SOC_CLOCK_INFO; + +/* + * Print Soc information + */ +VOID +PrintSoc ( + VOID + ); + +/* + * Initialize Clock structure + */ +VOID +ClockInit ( + VOID + ); + +/* + * Setup SMMU in bypass mode + * and also set its pagesize + */ +VOID +SmmuInit ( + VOID + ); + +/* + * Print CPU information + */ +VOID +PrintCpuInfo ( + VOID + ); + +/* + * Dump RCW (Reset Control Word) on console + */ +VOID +PrintRCW ( + VOID + ); + +UINT32 +InitiatorType ( + IN UINT32 Cluster, + IN UINTN InitId + ); + +/* + * Return the mask for number of cores on this SOC. + */ +UINT32 +CpuMask ( + VOID + ); + +/* + * Return the number of cores on this SOC. + */ +UINTN +CpuNumCores ( + VOID + ); + +#endif /* __CHASSIS_H__ */ diff --git a/Silicon/NXP/Chassis/Chassis2/Chassis2.dec b/Silicon/NXP/Chassi= s/Chassis2/Chassis2.dec new file mode 100644 index 0000000..cf41b3c --- /dev/null +++ b/Silicon/NXP/Chassis/Chassis2/Chassis2.dec @@ -0,0 +1,19 @@ +# @file +# +# Copyright 2017 NXP +# +# This program and the accompanying materials are licensed and made availa= ble under +# the terms and conditions of the BSD License which accompanies this distr= ibution. +# The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. +# +# + +[Defines] + DEC_SPECIFICATION =3D 0x00010005 + +[Includes] + . diff --git a/Silicon/NXP/Chassis/Chassis2/SerDes.h b/Silicon/NXP/Chassis/Ch= assis2/SerDes.h new file mode 100644 index 0000000..4c874aa --- /dev/null +++ b/Silicon/NXP/Chassis/Chassis2/SerDes.h @@ -0,0 +1,68 @@ +/** SerDes.h + The Header file of SerDes Module for Chassis 2 + + Copyright 2017 NXP + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD= License + which accompanies this distribution. The full text of the license may be = found + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPL= IED. + +**/ + +#ifndef __SERDES_H__ +#define __SERDES_H__ + +#include + +#define SRDS_MAX_LANES 4 + +typedef enum { + NONE =3D 0, + PCIE1, + PCIE2, + PCIE3, + SATA, + SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC5, + SGMII_FM1_DTSEC6, + SGMII_FM1_DTSEC9, + SGMII_FM1_DTSEC10, + QSGMII_FM1_A, + XFI_FM1_MAC9, + XFI_FM1_MAC10, + SGMII_2500_FM1_DTSEC2, + SGMII_2500_FM1_DTSEC5, + SGMII_2500_FM1_DTSEC9, + SGMII_2500_FM1_DTSEC10, + SERDES_PRTCL_COUNT +} SERDES_PROTOCOL; + +typedef enum { + SRDS_1 =3D 0, + SRDS_2, + SRDS_MAX_NUM +} SERDES_NUMBER; + +typedef struct { + UINT16 Protocol; + UINT8 SrdsLane[SRDS_MAX_LANES]; +} SERDES_CONFIG; + +typedef VOID +(*SERDES_PROBE_LANES_CALLBACK) ( + IN SERDES_PROTOCOL LaneProtocol, + IN VOID *Arg + ); + +VOID +SerDesProbeLanes( + IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback, + IN VOID *Arg + ); + +#endif /* __SERDES_H */ diff --git a/Silicon/NXP/Chassis/Chassis2/Soc.c b/Silicon/NXP/Chassis/Chass= is2/Soc.c new file mode 100644 index 0000000..7f9f963 --- /dev/null +++ b/Silicon/NXP/Chassis/Chassis2/Soc.c @@ -0,0 +1,172 @@ +/** @Soc.c + SoC specific Library containg functions to initialize various SoC compon= ents + + Copyright 2017 NXP + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may be= found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "Soc.h" + +/** + Calculate the frequency of various controllers and + populate the passed structure with frequuencies. + + @param PtrSysInfo Input structure to populate with + frequencies. +**/ +VOID +GetSysInfo ( + OUT SYS_INFO *PtrSysInfo + ) +{ + CCSR_GUR *GurBase; + CCSR_CLOCK *ClkBase; + UINTN CpuIndex; + UINT32 TempRcw; + UINT32 CPllSel; + UINT32 CplxPll; + CONST UINT8 CoreCplxPll[8] =3D { + [0] =3D 0, /* CC1 PPL / 1 */ + [1] =3D 0, /* CC1 PPL / 2 */ + [4] =3D 1, /* CC2 PPL / 1 */ + [5] =3D 1, /* CC2 PPL / 2 */ + }; + + CONST UINT8 CoreCplxPllDivisor[8] =3D { + [0] =3D 1, /* CC1 PPL / 1 */ + [1] =3D 2, /* CC1 PPL / 2 */ + [4] =3D 1, /* CC2 PPL / 1 */ + [5] =3D 2, /* CC2 PPL / 2 */ + }; + + UINTN PllCount; + UINTN FreqCPll[NUM_CC_PLLS]; + UINTN PllRatio[NUM_CC_PLLS]; + UINTN SysClk; + + GurBase =3D (VOID *)PcdGet64 (PcdGutsBaseAddr); + ClkBase =3D (VOID *)PcdGet64 (PcdClkBaseAddr); + SysClk =3D CLK_FREQ; + + SetMem (PtrSysInfo, sizeof (SYS_INFO), 0); + + PtrSysInfo->FreqSystemBus =3D SysClk; + PtrSysInfo->FreqDdrBus =3D SysClk; + + // + // selects the platform clock:SYSCLK ratio and calculate + // system frequency + // + PtrSysInfo->FreqSystemBus *=3D (GurRead ((UINTN)&GurBase->RcwSr[0]) >> + CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) & + CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK; + // + // selects the DDR PLL:SYSCLK Ratio and calculate DDR frequency + // + PtrSysInfo->FreqDdrBus *=3D (GurRead ((UINTN)&GurBase->RcwSr[0]) >> + CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) & + CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK; + + for (PllCount =3D 0; PllCount < NUM_CC_PLLS; PllCount++) { + PllRatio[PllCount] =3D (GurRead ((UINTN)&ClkBase->PllCgSr[PllCount].Pl= lCnGSr) >> 1) & 0xff; + if (PllRatio[PllCount] > 4) { + FreqCPll[PllCount] =3D SysClk * PllRatio[PllCount]; + } else { + FreqCPll[PllCount] =3D PtrSysInfo->FreqSystemBus * PllRatio[PllCount= ]; + } + } + + // + // Calculate Core frequency + // + for (CpuIndex =3D 0; CpuIndex < MAX_CPUS; CpuIndex++) { + CPllSel =3D (GurRead ((UINTN)&ClkBase->ClkcSr[CpuIndex].ClkCnCSr) >> 2= 7) & 0xf; + CplxPll =3D CoreCplxPll[CPllSel]; + + PtrSysInfo->FreqProcessor[CpuIndex] =3D FreqCPll[CplxPll] / CoreCplxPl= lDivisor[CPllSel]; + } + + // + // Calculate FMAN frequency + // + TempRcw =3D GurRead ((UINTN)&GurBase->RcwSr[7]); + switch ((TempRcw & HWA_CGA_M1_CLK_SEL) >> HWA_CGA_M1_CLK_SHIFT) { + case 2: + PtrSysInfo->FreqFman[0] =3D FreqCPll[0] / 2; + break; + case 3: + PtrSysInfo->FreqFman[0] =3D FreqCPll[0] / 3; + break; + case 4: + PtrSysInfo->FreqFman[0] =3D FreqCPll[0] / 4; + break; + case 5: + PtrSysInfo->FreqFman[0] =3D PtrSysInfo->FreqSystemBus; + break; + case 6: + PtrSysInfo->FreqFman[0] =3D FreqCPll[1] / 2; + break; + case 7: + PtrSysInfo->FreqFman[0] =3D FreqCPll[1] / 3; + break; + default: + DEBUG ((DEBUG_WARN, "Error: Unknown FMan1 clock select!\n")); + break; + } + PtrSysInfo->FreqSdhc =3D PtrSysInfo->FreqSystemBus/PcdGet32 (PcdPlatform= FreqDiv); + PtrSysInfo->FreqQman =3D PtrSysInfo->FreqSystemBus/PcdGet32 (PcdPlatform= FreqDiv); +} + +/** + Function to initialize SoC specific constructs + CPU Info + SoC Personality + Board Personality + RCW prints + **/ +VOID +SocInit ( + VOID + ) +{ + CHAR8 Buffer[100]; + UINTN CharCount; + + SmmuInit (); + + // + // Early init serial Port to get board information. + // + SerialPortInitialize (); + CharCount =3D AsciiSPrint (Buffer, sizeof (Buffer), "\nUEFI firmware (ve= rsion %s built at %a on %a)\n\r", + (CHAR16*)PcdGetPtr (PcdFirmwareVersionString), __TIME__, __DATE__); + SerialPortWrite ((UINT8 *) Buffer, CharCount); + + PrintCpuInfo (); + + // + // Print Reset control Word + // + PrintRCW (); + PrintSoc (); + + return; +} diff --git a/Silicon/NXP/Chassis/Chassis2/Soc.h b/Silicon/NXP/Chassis/Chass= is2/Soc.h new file mode 100644 index 0000000..10e99ab --- /dev/null +++ b/Silicon/NXP/Chassis/Chassis2/Soc.h @@ -0,0 +1,367 @@ +/** Soc.h +* Header defining the Base addresses, sizes, flags etc for chassis 1 +* +* Copyright 2017 NXP +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the B= SD License +* which accompanies this distribution. The full text of the license may = be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#ifndef __SOC_H__ +#define __SOC_H__ + +#define HWA_CGA_M1_CLK_SEL 0xe0000000 +#define HWA_CGA_M1_CLK_SHIFT 29 + +#define TP_CLUSTER_EOC_MASK 0xc0000000 /* end of clusters mask */ +#define NUM_CC_PLLS 2 +#define CLK_FREQ 100000000 +#define MAX_CPUS 4 +#define NUM_FMAN 1 +#define CHECK_CLUSTER(Cluster) ((Cluster & TP_CLUSTER_EOC_MASK) =3D=3D = 0x0) + +/* RCW SERDES MACRO */ +#define RCWSR_INDEX 4 +#define RCWSR_SRDS1_PRTCL_MASK 0xffff0000 +#define RCWSR_SRDS1_PRTCL_SHIFT 16 +#define RCWSR_SRDS2_PRTCL_MASK 0x0000ffff +#define RCWSR_SRDS2_PRTCL_SHIFT 0 + +/* SMMU Defintions */ +#define SMMU_BASE_ADDR 0x09000000 +#define SMMU_REG_SCR0 (SMMU_BASE_ADDR + 0x0) +#define SMMU_REG_SACR (SMMU_BASE_ADDR + 0x10) +#define SMMU_REG_IDR1 (SMMU_BASE_ADDR + 0x24) +#define SMMU_REG_NSCR0 (SMMU_BASE_ADDR + 0x400) +#define SMMU_REG_NSACR (SMMU_BASE_ADDR + 0x410) + +#define SCR0_USFCFG_MASK 0x00000400 +#define SCR0_CLIENTPD_MASK 0x00000001 +#define SACR_PAGESIZE_MASK 0x00010000 +#define IDR1_PAGESIZE_MASK 0x80000000 + +typedef struct { + UINTN FreqProcessor[MAX_CPUS]; + UINTN FreqSystemBus; + UINTN FreqDdrBus; + UINTN FreqLocalBus; + UINTN FreqSdhc; + UINTN FreqFman[NUM_FMAN]; + UINTN FreqQman; +} SYS_INFO; + +/* Device Configuration and Pin Control */ +typedef struct { + UINT32 PorSr1; /* POR status 1 */ +#define CHASSIS2_CCSR_PORSR1_RCW_MASK 0xFF800000 + UINT32 PorSr2; /* POR status 2 */ + UINT8 Res008[0x20-0x8]; + UINT32 GppOrCr1; /* General-purpose POR configuration */ + UINT32 GppOrCr2; + UINT32 DcfgFuseSr; /* Fuse status register */ + UINT8 Res02c[0x70-0x2c]; + UINT32 DevDisr; /* Device disable control */ + UINT32 DevDisr2; /* Device disable control 2 */ + UINT32 DevDisr3; /* Device disable control 3 */ + UINT32 DevDisr4; /* Device disable control 4 */ + UINT32 DevDisr5; /* Device disable control 5 */ + UINT32 DevDisr6; /* Device disable control 6 */ + UINT32 DevDisr7; /* Device disable control 7 */ + UINT8 Res08c[0x94-0x8c]; + UINT32 CoreDisrU; /* uppper portion for support of 64 cores */ + UINT32 CoreDisrL; /* lower portion for support of 64 cores */ + UINT8 Res09c[0xa0-0x9c]; + UINT32 Pvr; /* Processor version */ + UINT32 Svr; /* System version */ + UINT32 Mvr; /* Manufacturing version */ + UINT8 Res0ac[0xb0-0xac]; + UINT32 RstCr; /* Reset control */ + UINT32 RstRqPblSr; /* Reset request preboot loader status */ + UINT8 Res0b8[0xc0-0xb8]; + UINT32 RstRqMr1; /* Reset request mask */ + UINT8 Res0c4[0xc8-0xc4]; + UINT32 RstRqSr1; /* Reset request status */ + UINT8 Res0cc[0xd4-0xcc]; + UINT32 RstRqWdTmrL; /* Reset request WDT mask */ + UINT8 Res0d8[0xdc-0xd8]; + UINT32 RstRqWdtSrL; /* Reset request WDT status */ + UINT8 Res0e0[0xe4-0xe0]; + UINT32 BrrL; /* Boot release */ + UINT8 Res0e8[0x100-0xe8]; + UINT32 RcwSr[16]; /* Reset control word status */ +#define CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT 25 +#define CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK 0x1f +#define CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT 16 +#define CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK 0x3f + UINT8 Res140[0x200-0x140]; + UINT32 ScratchRw[4]; /* Scratch Read/Write */ + UINT8 Res210[0x300-0x210]; + UINT32 ScratcHw1R[4]; /* Scratch Read (Write once) */ + UINT8 Res310[0x400-0x310]; + UINT32 CrstSr[12]; + UINT8 Res430[0x500-0x430]; + /* PCI Express n Logical I/O Device Number register */ + UINT32 DcfgCcsrPex1LiodNr; + UINT32 DcfgCcsrPex2LiodNr; + UINT32 DcfgCcsrPex3LiodNr; + UINT32 DcfgCcsrPex4LiodNr; + /* RIO n Logical I/O Device Number register */ + UINT32 DcfgCcsrRio1LiodNr; + UINT32 DcfgCcsrRio2LiodNr; + UINT32 DcfgCcsrRio3LiodNr; + UINT32 DcfgCcsrRio4LiodNr; + /* USB Logical I/O Device Number register */ + UINT32 DcfgCcsrUsb1LiodNr; + UINT32 DcfgCcsrUsb2LiodNr; + UINT32 DcfgCcsrUsb3LiodNr; + UINT32 DcfgCcsrUsb4LiodNr; + /* SD/MMC Logical I/O Device Number register */ + UINT32 DcfgCcsrSdMmc1LiodNr; + UINT32 DcfgCcsrSdMmc2LiodNr; + UINT32 DcfgCcsrSdMmc3LiodNr; + UINT32 DcfgCcsrSdMmc4LiodNr; + /* RIO Message Unit Logical I/O Device Number register */ + UINT32 DcfgCcsrRiomaintLiodNr; + UINT8 Res544[0x550-0x544]; + UINT32 SataLiodNr[4]; + UINT8 Res560[0x570-0x560]; + UINT32 DcfgCcsrMisc1LiodNr; + UINT32 DcfgCcsrMisc2LiodNr; + UINT32 DcfgCcsrMisc3LiodNr; + UINT32 DcfgCcsrMisc4LiodNr; + UINT32 DcfgCcsrDma1LiodNr; + UINT32 DcfgCcsrDma2LiodNr; + UINT32 DcfgCcsrDma3LiodNr; + UINT32 DcfgCcsrDma4LiodNr; + UINT32 DcfgCcsrSpare1LiodNr; + UINT32 DcfgCcsrSpare2LiodNr; + UINT32 DcfgCcsrSpare3LiodNr; + UINT32 DcfgCcsrSpare4LiodNr; + UINT8 Res5a0[0x600-0x5a0]; + UINT32 DcfgCcsrPblSr; + UINT32 PamuBypENr; + UINT32 DmaCr1; + UINT8 Res60c[0x610-0x60c]; + UINT32 DcfgCcsrGenSr1; + UINT32 DcfgCcsrGenSr2; + UINT32 DcfgCcsrGenSr3; + UINT32 DcfgCcsrGenSr4; + UINT32 DcfgCcsrGenCr1; + UINT32 DcfgCcsrGenCr2; + UINT32 DcfgCcsrGenCr3; + UINT32 DcfgCcsrGenCr4; + UINT32 DcfgCcsrGenCr5; + UINT32 DcfgCcsrGenCr6; + UINT32 DcfgCcsrGenCr7; + UINT8 Res63c[0x658-0x63c]; + UINT32 DcfgCcsrcGenSr1; + UINT32 DcfgCcsrcGenSr0; + UINT8 Res660[0x678-0x660]; + UINT32 DcfgCcsrcGenCr1; + UINT32 DcfgCcsrcGenCr0; + UINT8 Res680[0x700-0x680]; + UINT32 DcfgCcsrSrIoPstecr; + UINT32 DcfgCcsrDcsrCr; + UINT8 Res708[0x740-0x708]; /* add more registers when needed */ + UINT32 TpItyp[64]; /* Topology Initiator Type Register */ + struct { + UINT32 Upper; + UINT32 Lower; + } TpCluster[16]; + UINT8 Res8c0[0xa00-0x8c0]; /* add more registers when needed */ + UINT32 DcfgCcsrQmBmWarmRst; + UINT8 Resa04[0xa20-0xa04]; /* add more registers when needed */ + UINT32 DcfgCcsrReserved0; + UINT32 DcfgCcsrReserved1; +} CCSR_GUR; + +/* Supplemental Configuration Unit */ +typedef struct { + UINT8 Res000[0x070-0x000]; + UINT32 Usb1Prm1Cr; + UINT32 Usb1Prm2Cr; + UINT32 Usb1Prm3Cr; + UINT32 Usb2Prm1Cr; + UINT32 Usb2Prm2Cr; + UINT32 Usb2Prm3Cr; + UINT32 Usb3Prm1Cr; + UINT32 Usb3Prm2Cr; + UINT32 Usb3Prm3Cr; + UINT8 Res094[0x100-0x094]; + UINT32 Usb2Icid; + UINT32 Usb3Icid; + UINT8 Res108[0x114-0x108]; + UINT32 DmaIcid; + UINT32 SataIcid; + UINT32 Usb1Icid; + UINT32 QeIcid; + UINT32 SdhcIcid; + UINT32 EdmaIcid; + UINT32 EtrIcid; + UINT32 Core0SftRst; + UINT32 Core1SftRst; + UINT32 Core2SftRst; + UINT32 Core3SftRst; + UINT8 Res140[0x158-0x140]; + UINT32 AltCBar; + UINT32 QspiCfg; + UINT8 Res160[0x180-0x160]; + UINT32 DmaMcr; + UINT8 Res184[0x188-0x184]; + UINT32 GicAlign; + UINT32 DebugIcid; + UINT8 Res190[0x1a4-0x190]; + UINT32 SnpCnfGcr; +#define CCSR_SCFG_SNPCNFGCR_SECRDSNP BIT31 +#define CCSR_SCFG_SNPCNFGCR_SECWRSNP BIT30 +#define CCSR_SCFG_SNPCNFGCR_SATARDSNP BIT23 +#define CCSR_SCFG_SNPCNFGCR_SATAWRSNP BIT22 +#define CCSR_SCFG_SNPCNFGCR_USB1RDSNP BIT21 +#define CCSR_SCFG_SNPCNFGCR_USB1WRSNP BIT20 +#define CCSR_SCFG_SNPCNFGCR_USB2RDSNP BIT15 +#define CCSR_SCFG_SNPCNFGCR_USB2WRSNP BIT16 +#define CCSR_SCFG_SNPCNFGCR_USB3RDSNP BIT13 +#define CCSR_SCFG_SNPCNFGCR_USB3WRSNP BIT14 + UINT8 Res1a8[0x1ac-0x1a8]; + UINT32 IntpCr; + UINT8 Res1b0[0x204-0x1b0]; + UINT32 CoreSrEnCr; + UINT8 Res208[0x220-0x208]; + UINT32 RvBar00; + UINT32 RvBar01; + UINT32 RvBar10; + UINT32 RvBar11; + UINT32 RvBar20; + UINT32 RvBar21; + UINT32 RvBar30; + UINT32 RvBar31; + UINT32 LpmCsr; + UINT8 Res244[0x400-0x244]; + UINT32 QspIdQScr; + UINT32 EcgTxcMcr; + UINT32 SdhcIoVSelCr; + UINT32 RcwPMuxCr0; + /**Setting RCW PinMux Register bits 17-19 to select USB2_DRVVBUS + *Setting RCW PinMux Register bits 21-23 to select USB2_PWRFAULT + *Setting RCW PinMux Register bits 25-27 to select USB3_DRVVBUS + Setting RCW PinMux Register bits 29-31 to select USB3_DRVVBUS*/ +#define CCSR_SCFG_RCWPMUXCRO_SELCR_USB 0x3333 + /**Setting RCW PinMux Register bits 17-19 to select USB2_DRVVBUS + *Setting RCW PinMux Register bits 21-23 to select USB2_PWRFAULT + *Setting RCW PinMux Register bits 25-27 to select IIC4_SCL + Setting RCW PinMux Register bits 29-31 to select IIC4_SDA*/ +#define CCSR_SCFG_RCWPMUXCRO_NOT_SELCR_USB 0x3300 + UINT32 UsbDrvVBusSelCr; +#define CCSR_SCFG_USBDRVVBUS_SELCR_USB1 0x00000000 +#define CCSR_SCFG_USBDRVVBUS_SELCR_USB2 0x00000001 +#define CCSR_SCFG_USBDRVVBUS_SELCR_USB3 0x00000003 + UINT32 UsbPwrFaultSelCr; +#define CCSR_SCFG_USBPWRFAULT_INACTIVE 0x00000000 +#define CCSR_SCFG_USBPWRFAULT_SHARED 0x00000001 +#define CCSR_SCFG_USBPWRFAULT_DEDICATED 0x00000002 +#define CCSR_SCFG_USBPWRFAULT_USB3_SHIFT 4 +#define CCSR_SCFG_USBPWRFAULT_USB2_SHIFT 2 +#define CCSR_SCFG_USBPWRFAULT_USB1_SHIFT 0 + UINT32 UsbRefclkSelcr1; + UINT32 UsbRefclkSelcr2; + UINT32 UsbRefclkSelcr3; + UINT8 Res424[0x600-0x424]; + UINT32 ScratchRw[4]; + UINT8 Res610[0x680-0x610]; + UINT32 CoreBCr; + UINT8 Res684[0x1000-0x684]; + UINT32 Pex1MsiIr; + UINT32 Pex1MsiR; + UINT8 Res1008[0x2000-0x1008]; + UINT32 Pex2; + UINT32 Pex2MsiR; + UINT8 Res2008[0x3000-0x2008]; + UINT32 Pex3MsiIr; + UINT32 Pex3MsiR; +} CCSR_SCFG; + +#define USB_TXVREFTUNE 0x9 +#define USB_SQRXTUNE 0xFC7FFFFF +#define USB_PCSTXSWINGFULL 0x47 +#define USB_PHY_RX_EQ_VAL_1 0x0000 +#define USB_PHY_RX_EQ_VAL_2 0x8000 +#define USB_PHY_RX_EQ_VAL_3 0x8003 +#define USB_PHY_RX_EQ_VAL_4 0x800b + +/*USB_PHY_SS memory map*/ +typedef struct { + UINT16 IpIdcodeLo; + UINT16 SupIdcodeHi; + UINT8 Res4[0x0006-0x0004]; + UINT16 RtuneDebug; + UINT16 RtuneStat; + UINT16 SupSsPhase; + UINT16 SsFreq; + UINT8 ResE[0x0020-0x000e]; + UINT16 Ateovrd; + UINT16 MpllOvrdInLo; + UINT8 Res24[0x0026-0x0024]; + UINT16 SscOvrdIn; + UINT8 Res28[0x002A-0x0028]; + UINT16 LevelOvrdIn; + UINT8 Res2C[0x0044-0x002C]; + UINT16 ScopeCount; + UINT8 Res46[0x0060-0x0046]; + UINT16 MpllLoopCtl; + UINT8 Res62[0x006C-0x0062]; + UINT16 SscClkCntrl; + UINT8 Res6E[0x2002-0x006E]; + UINT16 Lane0TxOvrdInHi; + UINT16 Lane0TxOvrdDrvLo; + UINT8 Res2006[0x200C-0x2006]; + UINT16 Lane0RxOvrdInHi; + UINT8 Res200E[0x2022-0x200E]; + UINT16 Lane0TxCmWaitTimeOvrd; + UINT8 Res2024[0x202A-0x2024]; + UINT16 Lane0TxLbertCtl; + UINT16 Lane0RxLbertCtl; + UINT16 Lane0RxLbertErr; + UINT8 Res2030[0x205A-0x2030]; + UINT16 Lane0TxAltBlock; +} CCSR_USB_PHY; + +/* Clocking */ +typedef struct { + struct { + UINT32 ClkCnCSr; /* core cluster n clock control status */ + UINT8 Res004[0x0c]; + UINT32 ClkcGHwAcSr; /* Clock generator n hardware accelerator */ + UINT8 Res014[0x0c]; + } ClkcSr[4]; + UINT8 Res040[0x780]; /* 0x100 */ + struct { + UINT32 PllCnGSr; + UINT8 Res804[0x1c]; + } PllCgSr[NUM_CC_PLLS]; + UINT8 Res840[0x1c0]; + UINT32 ClkPCSr; /* 0xa00 Platform clock domain control/status */ + UINT8 Resa04[0x1fc]; + UINT32 PllPGSr; /* 0xc00 Platform PLL General Status */ + UINT8 Resc04[0x1c]; + UINT32 PllDGSr; /* 0xc20 DDR PLL General Status */ + UINT8 Resc24[0x3dc]; +} CCSR_CLOCK; + +VOID +GetSysInfo ( + OUT SYS_INFO * + ); + +UINT32 +EFIAPI +GurRead ( + IN UINTN Address + ); + +#endif /* __SOC_H__ */ diff --git a/Silicon/NXP/Chassis/LS1043aSocLib.inf b/Silicon/NXP/Chassis/LS= 1043aSocLib.inf new file mode 100644 index 0000000..1b2f9c4 --- /dev/null +++ b/Silicon/NXP/Chassis/LS1043aSocLib.inf @@ -0,0 +1,47 @@ +# @file +# +# Copyright 2017 NXP +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +# + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D SocLib + FILE_GUID =3D e868c5ca-9729-43ae-bff4-438c67de8c68 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SocLib + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/NXP/NxpQoriqLs.dec + Silicon/NXP/Chassis/Chassis2/Chassis2.dec + Silicon/NXP/LS1043A/LS1043A.dec + +[LibraryClasses] + BaseLib + BeIoLib + DebugLib + SerialPortLib + +[Sources.common] + Chassis.c + Chassis2/Soc.c + SerDes.c + +[FixedPcd] + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString + gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv + gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled + gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian + gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr diff --git a/Silicon/NXP/Chassis/SerDes.c b/Silicon/NXP/Chassis/SerDes.c new file mode 100644 index 0000000..e4578c3 --- /dev/null +++ b/Silicon/NXP/Chassis/SerDes.c @@ -0,0 +1,271 @@ +/** SerDes.c + Provides the basic interfaces for SerDes Module + + Copyright 2017 NXP + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may be= found + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include +#include +#include +#include +#include +#include + +/** + Function to get serdes Lane protocol corresponding to + serdes protocol. + + @param SerDes Serdes number. + @param Cfg Serdes Protocol. + @param Lane Serdes Lane number. + + @return Serdes Lane protocol. + +**/ +STATIC +SERDES_PROTOCOL +GetSerDesPrtcl ( + IN INTN SerDes, + IN INTN Cfg, + IN INTN Lane + ) +{ + SERDES_CONFIG *Config; + + if (SerDes >=3D ARRAY_SIZE (SerDesConfigTbl)) { + return 0; + } + + Config =3D SerDesConfigTbl[SerDes]; + while (Config->Protocol) { + if (Config->Protocol =3D=3D Cfg) { + return Config->SrdsLane[Lane]; + } + Config++; + } + + return EFI_SUCCESS; +} + +/** + Function to check if inputted protocol is a valid serdes protocol. + + @param SerDes Serdes number. + @param Prtcl Serdes Protocol to be verified. + + @return EFI_INVALID_PARAMETER Input parameter in invalid. + @return EFI_NOT_FOUND Serdes Protocol not a valid protocol. + @return EFI_SUCCESS Serdes Protocol is a valid protocol. + +**/ +STATIC +EFI_STATUS +CheckSerDesPrtclValid ( + IN INTN SerDes, + IN UINT32 Prtcl + ) +{ + SERDES_CONFIG *Config; + INTN Cnt; + + if (SerDes >=3D ARRAY_SIZE (SerDesConfigTbl)) { + return EFI_INVALID_PARAMETER; + } + + Config =3D SerDesConfigTbl[SerDes]; + while (Config->Protocol) { + if (Config->Protocol =3D=3D Prtcl) { + DEBUG ((DEBUG_INFO, "Protocol: %x Matched with the one in Table\n", = Prtcl)); + break; + } + Config++; + } + + if (!Config->Protocol) { + return EFI_NOT_FOUND; + } + + for (Cnt =3D 0; Cnt < SRDS_MAX_LANES; Cnt++) { + if (Config->SrdsLane[Cnt] !=3D NONE) { + return EFI_SUCCESS; + } + } + + return EFI_NOT_FOUND; +} + +/** + Function to fill serdes map information. + + @param Srds Serdes number. + @param SerdesProtocolMask Serdes Protocol Mask. + @param SerdesProtocolShift Serdes Protocol shift value. + @param SerDesPrtclMap Pointer to Serdes Protocol map. + +**/ +STATIC +VOID +LSSerDesMap ( + IN UINT32 Srds, + IN UINT32 SerdesProtocolMask, + IN UINT32 SerdesProtocolShift, + OUT UINT64 *SerDesPrtclMap + ) +{ + CCSR_GUR *Gur; + UINT32 SrdsProt; + INTN Lane; + UINT32 Flag; + + Gur =3D (VOID *)PcdGet64 (PcdGutsBaseAddr); + *SerDesPrtclMap =3D 0x0; + Flag =3D 0; + + SrdsProt =3D GurRead ((UINTN)&Gur->RcwSr[RCWSR_INDEX]) & SerdesProtocolM= ask; + SrdsProt >>=3D SerdesProtocolShift; + + DEBUG ((DEBUG_INFO, "Using SERDES%d Protocol: %d (0x%x)\n", + Srds + 1, SrdsProt, SrdsProt)); + + if (EFI_SUCCESS !=3D CheckSerDesPrtclValid (Srds, SrdsProt)) { + DEBUG ((DEBUG_ERROR, "SERDES%d[PRTCL] =3D 0x%x is not valid\n", + Srds + 1, SrdsProt)); + Flag++; + } + + for (Lane =3D 0; Lane < SRDS_MAX_LANES; Lane++) { + SERDES_PROTOCOL LanePrtcl =3D GetSerDesPrtcl (Srds, SrdsProt, Lane); + if (LanePrtcl >=3D SERDES_PRTCL_COUNT) { + DEBUG ((DEBUG_ERROR, "Unknown SerDes lane protocol %d\n", LanePrtcl)= ); + Flag++; + } else { + *SerDesPrtclMap |=3D BIT (LanePrtcl); + } + } + + if (Flag) { + DEBUG ((DEBUG_ERROR, "Could not configure SerDes module!!\n")); + } else { + DEBUG ((DEBUG_INFO, "Successfully configured SerDes module!!\n")); + } +} + +/** + Get lane protocol on provided serdes lane and execute callback function. + + @param Srds Serdes number. + @param SerdesProtocolMask Mask to get Serdes Protocol for Srds + @param SerdesProtocolShift Shift value to get Serdes Protocol for S= rds. + @param SerDesLaneProbeCallback Pointer Callback function to be called f= or Lane protocol + @param Arg Pointer to Arguments to be passed to cal= lback function. + +**/ +STATIC +VOID +SerDesInstanceProbeLanes ( + IN UINT32 Srds, + IN UINT32 SerdesProtocolMask, + IN UINT32 SerdesProtocolShift, + IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback, + IN VOID *Arg + ) +{ + + CCSR_GUR *Gur; + UINT32 SrdsProt; + INTN Lane; + + Gur =3D (VOID *)PcdGet64 (PcdGutsBaseAddr);; + + SrdsProt =3D GurRead ((UINTN)&Gur->RcwSr[RCWSR_INDEX]) & SerdesProtocolM= ask; + SrdsProt >>=3D SerdesProtocolShift; + + /* + * Invoke callback for all lanes in the SerDes instance: + */ + for (Lane =3D 0; Lane < SRDS_MAX_LANES; Lane++) { + SERDES_PROTOCOL LanePrtcl =3D GetSerDesPrtcl (Srds, SrdsProt, Lane); + if (LanePrtcl >=3D SERDES_PRTCL_COUNT || LanePrtcl < NONE) { + DEBUG ((DEBUG_ERROR, "Unknown SerDes lane protocol %d\n", LanePrtcl)= ); + } + else if (LanePrtcl !=3D NONE) { + SerDesLaneProbeCallback (LanePrtcl, Arg); + } + } +} + +/** + Probe all serdes lanes for lane protocol and execute provided callback f= unction. + + @param SerDesLaneProbeCallback Pointer Callback function to be called f= or Lane protocol + @param Arg Pointer to Arguments to be passed to cal= lback function. + +**/ +VOID +SerDesProbeLanes ( + IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback, + IN VOID *Arg + ) +{ + SerDesInstanceProbeLanes (SRDS_1, + RCWSR_SRDS1_PRTCL_MASK, + RCWSR_SRDS1_PRTCL_SHIFT, + SerDesLaneProbeCallback, + Arg); + + if (PcdGetBool (PcdSerdes2Enabled)) { + SerDesInstanceProbeLanes (SRDS_2, + RCWSR_SRDS2_PRTCL_MASK, + RCWSR_SRDS2_PRTCL_SHIFT, + SerDesLaneProbeCallback, + Arg); + } +} + +/** + Function to return Serdes protocol map for all serdes available on board. + + @param SerDesPrtclMap Pointer to Serdes protocl map. + +**/ +VOID +GetSerdesProtocolMaps ( + OUT UINT64 *SerDesPrtclMap + ) +{ + LSSerDesMap (SRDS_1, + RCWSR_SRDS1_PRTCL_MASK, + RCWSR_SRDS1_PRTCL_SHIFT, + SerDesPrtclMap); + + if (PcdGetBool (PcdSerdes2Enabled)) { + LSSerDesMap (SRDS_2, + RCWSR_SRDS2_PRTCL_MASK, + RCWSR_SRDS2_PRTCL_SHIFT, + SerDesPrtclMap); + } + +} + +BOOLEAN +IsSerDesLaneProtocolConfigured ( + IN UINT64 SerDesPrtclMap, + IN SERDES_PROTOCOL Device + ) +{ + if (Device >=3D SERDES_PRTCL_COUNT || Device < NONE) { + ASSERT (Device > NONE && Device < SERDES_PRTCL_COUNT); + DEBUG ((DEBUG_ERROR, "Unknown SerDes lane protocol Device %d\n", Devic= e)); + } + + return (SerDesPrtclMap & BIT (Device)) !=3D 0 ; +} diff --git a/Silicon/NXP/Include/Bitops.h b/Silicon/NXP/Include/Bitops.h new file mode 100644 index 0000000..beddb4e --- /dev/null +++ b/Silicon/NXP/Include/Bitops.h @@ -0,0 +1,179 @@ +/** Bitops.h + Header defining the general bitwise operations + + Copyright 2017 NXP + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#ifndef __BITOPS_H__ +#define __BITOPS_H__ + +#include + +#define MASK_LOWER_16 0xFFFF0000 +#define MASK_UPPER_16 0x0000FFFF +#define MASK_LOWER_8 0xFF000000 +#define MASK_UPPER_8 0x000000FF + +/* + * Returns the bit mask for a bit index from 0 to 31 + */ +#define BIT(_BitIndex) (0x1u << (_BitIndex)) + +/** + * Upper32Bits - return bits 32-63 of a number + * @N: the number we're accessing + * + * A basic shift-right of a 64- or 32-bit quantity. Use this to suppress + * the "right shift count >=3D width of type" warning when that quantity is + * 32-bits. + */ +#define Upper32Bits(N) ((UINT32)(((N) >> 16) >> 16)) + +/** + * Lower32Bits - return bits 0-31 of a number + * @N: the number we're accessing + */ +#define Lower32Bits(N) ((UINT32)(N)) + + +/* + * Stores a value for a given bit field in 32-bit '_Container' + */ + +#define SET_BIT_FIELD32(_Container, _BitShift, _BitWidth, _Value) \ + __SET_BIT_FIELD32(_Container, \ + __GEN_BIT_FIELD_MASK32(_BitShift, _BitWidth), \ + _BitShift, \ + _Value) + +#define __SET_BIT_FIELD32(_Container, _BitMask, _BitShift, _Value) \ + do { \ + (_Container) &=3D ~(_BitMask); \ + if ((_Value) !=3D 0) { \ + ASSERT(((UINT32)(_Value) << (_BitShift)) <=3D (_BitMask)); \ + (_Container) |=3D \ + ((UINT32)(_Value) << (_BitShift)) & (_BitMask); \ + } \ + } while (0) + +/* + * Extracts the value for a given bit field in 32-bit _Container + */ + +#define GET_BIT_FIELD32(_Container, _BitShift, _BitWidth) \ + __GET_BIT_FIELD32(_Container, \ + __GEN_BIT_FIELD_MASK32(_BitShift, _BitWidth), \ + _BitShift) + +#define __GET_BIT_FIELD32(_Container, _BitMask, _BitShift) \ + (((UINT32)(_Container) & (_BitMask)) >> (_BitShift)) + +#define __GEN_BIT_FIELD_MASK32(_BitShift, _BitWidth) \ + ((_BitWidth) < 32 ? \ + (((UINT32)1 << (_BitWidth)) - 1) << (_BitShift) : \ + ~(UINT32)0) + +/* + *Stores a value for a given bit field in 64-bit '_Container' + */ +#define SET_BIT_FIELD64(_Container, _BitShift, _BitWidth, _Value) \ + __SET_BIT_FIELD64(_Container, \ + __GEN_BIT_FIELD_MASK64(_BitShift, _BitWidth), \ + _BitShift, \ + _Value) + +#define __SET_BIT_FIELD64(_Container, _BitMask, _BitShift, _Value) \ + do { \ + (_Container) &=3D ~(_BitMask); \ + if ((_Value) !=3D 0) { \ + ASSERT(((UINT64)(_Value) << (_BitShift)) <=3D (_BitMask)); \ + (_Container) |=3D \ + ((UINT64)(_Value) << (_BitShift)) & (_BitMask); \ + } \ + } while (0) + +/* + * Extracts the value for a given bit field in 64-bit _Container + */ +#define GET_BIT_FIELD64(_Container, _BitShift, _BitWidth) \ + __GET_BIT_FIELD64(_Container, \ + __GEN_BIT_FIELD_MASK64(_BitShift, _BitWidth), \ + _BitShift) + +#define __GET_BIT_FIELD64(_Container, _BitMask, _BitShift) \ + (((UINT64)(_Container) & (_BitMask)) >> (_BitShift)) + +#define __GEN_BIT_FIELD_MASK64(_BitShift, _BitWidth) \ + ((_BitWidth) < 64 ? \ + (((UINT64)1 << (_BitWidth)) - 1) << (_BitShift) : \ + ~(UINT64)0) + +/** + + Test If the Destination buffer sets (0->1) or clears (1->0) any bit in So= urce buffer ? + + @param[in] Source Source Buffer Pointer + @param[in] Destination Destination Buffer Pointer + @param[in] NumBytes Bytes to Compare + @param[in] Set True : Test Weather Destination buffer sets any = bit in Source buffer ? + False : Test Weather Destination buffer clears a= ny bit in Source buffer ? + + @retval TRUE Destination buffer sets/clear a bit in source bu= ffer. + @retval FALSE Destination buffer doesn't sets/clear bit in sou= rce buffer. + +**/ +STATIC +inline +BOOLEAN +TestBitSetClear ( + IN VOID *Source, + IN VOID *Destination, + IN UINTN NumBytes, + IN BOOLEAN Set + ) +{ + UINTN Index =3D 0; + VOID* Buffer; + + if (Set) { + Buffer =3D Destination; + } else { + Buffer =3D Source; + } + + while (Index < NumBytes) { + if ((NumBytes - Index) >=3D 8) { + if ((*((UINT64*)(Source+Index)) ^ *((UINT64*)(Destination+Index))) &= *((UINT64*)(Buffer+Index))) { + return TRUE; + } + Index +=3D 8; + } else if ((NumBytes - Index) >=3D 4) { + if ((*((UINT32*)(Source+Index)) ^ *((UINT32*)(Destination+Index))) &= *((UINT32*)(Buffer+Index))) { + return TRUE; + } + Index +=3D 4; + } else if ((NumBytes - Index) >=3D 2) { + if ((*((UINT16*)(Source+Index)) ^ *((UINT16*)(Destination+Index))) &= *((UINT16*)(Buffer+Index))) { + return TRUE; + } + Index +=3D 2; + } else if ((NumBytes - Index) >=3D 1) { + if ((*((UINT8*)(Source+Index)) ^ *((UINT8*)(Destination+Index))) & *= ((UINT8*)(Buffer+Index))) { + return TRUE; + } + Index +=3D 1; + } + } + return FALSE; +} + +#endif diff --git a/Silicon/NXP/LS1043A/Include/SocSerDes.h b/Silicon/NXP/LS1043A/= Include/SocSerDes.h new file mode 100644 index 0000000..90e165f --- /dev/null +++ b/Silicon/NXP/LS1043A/Include/SocSerDes.h @@ -0,0 +1,55 @@ +/** @file + The Header file of SerDes Module for LS1043A + + Copyright 2017 NXP + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD= License + which accompanies this distribution. The full text of the license may be = found + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPL= IED. + +**/ + +#ifndef __SOC_SERDES_H__ +#define __SOC_SERDES_H__ + +#include + +SERDES_CONFIG SerDes1ConfigTbl[] =3D { + /* SerDes 1 */ + {0x1555, {XFI_FM1_MAC9, PCIE1, PCIE2, PCIE3 } }, + {0x2555, {SGMII_2500_FM1_DTSEC9, PCIE1, PCIE2, PCIE3 } }, + {0x4555, {QSGMII_FM1_A, PCIE1, PCIE2, PCIE3 } }, + {0x4558, {QSGMII_FM1_A, PCIE1, PCIE2, SATA } }, + {0x1355, {XFI_FM1_MAC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3 } }, + {0x2355, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3 } }, + {0x3335, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5, PCIE3 } = }, + {0x3355, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3 } }, + {0x3358, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, SATA } }, + {0x3555, {SGMII_FM1_DTSEC9, PCIE1, PCIE2, PCIE3 } }, + {0x3558, {SGMII_FM1_DTSEC9, PCIE1, PCIE2, SATA } }, + {0x7000, {PCIE1, PCIE1, PCIE1, PCIE1 } }, + {0x9998, {PCIE1, PCIE2, PCIE3, SATA } }, + {0x6058, {PCIE1, PCIE1, PCIE2, SATA } }, + {0x1455, {XFI_FM1_MAC9, QSGMII_FM1_A, PCIE2, PCIE3 } }, + {0x2455, {SGMII_2500_FM1_DTSEC9, QSGMII_FM1_A, PCIE2, PCIE3 } }, + {0x2255, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC2, PCIE2, PCIE3 } }, + {0x3333, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5, SGMII_FM= 1_DTSEC6 } }, + {0x1460, {XFI_FM1_MAC9, QSGMII_FM1_A, PCIE3, PCIE3 } }, + {0x2460, {SGMII_2500_FM1_DTSEC9, QSGMII_FM1_A, PCIE3, PCIE3 } }, + {0x3460, {SGMII_FM1_DTSEC9, QSGMII_FM1_A, PCIE3, PCIE3 } }, + {0x3455, {SGMII_FM1_DTSEC9, QSGMII_FM1_A, PCIE2, PCIE3 } }, + {0x9960, {PCIE1, PCIE2, PCIE3, PCIE3 } }, + {0x2233, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5, SGM= II_FM1_DTSEC6 } }, + {0x2533, {SGMII_2500_FM1_DTSEC9, PCIE1, SGMII_FM1_DTSEC5, SGMII_FM1_DTSE= C6 } }, + {} +}; + +SERDES_CONFIG *SerDesConfigTbl[] =3D { + SerDes1ConfigTbl +}; + +#endif /* __SOC_SERDES_H */ --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun May 5 06:05:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=nxp.com Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1518771171427805.3012434331408; Fri, 16 Feb 2018 00:52:51 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 7019321E0B9FA; Fri, 16 Feb 2018 00:46:56 -0800 (PST) Received: from EUR02-AM5-obe.outbound.protection.outlook.com (mail-eopbgr00087.outbound.protection.outlook.com [40.107.0.87]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id A5A8D21CF1D18 for ; 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charset="utf-8" From: Meenakshi Aggarwal Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Meenakshi Aggarwal Reviewed-by: Leif Lindholm --- Silicon/NXP/Library/DUartPortLib/DUart.h | 128 ++++++++ Silicon/NXP/Library/DUartPortLib/DUartPortLib.c | 370 ++++++++++++++++++= ++++ Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf | 41 +++ 3 files changed, 539 insertions(+) create mode 100644 Silicon/NXP/Library/DUartPortLib/DUart.h create mode 100644 Silicon/NXP/Library/DUartPortLib/DUartPortLib.c create mode 100644 Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf diff --git a/Silicon/NXP/Library/DUartPortLib/DUart.h b/Silicon/NXP/Library= /DUartPortLib/DUart.h new file mode 100644 index 0000000..3fa0a68 --- /dev/null +++ b/Silicon/NXP/Library/DUartPortLib/DUart.h @@ -0,0 +1,128 @@ +/** DUart.h +* Header defining the DUART constants (Base addresses, sizes, flags) +* +* Based on Serial I/O Port library headers available in PL011Uart.h +* +* Copyright (c) 2011-2012, ARM Limited. All rights reserved. +* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved. +* Copyright 2017 NXP +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the B= SD License +* which accompanies this distribution. The full text of the license may = be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#ifndef __DUART_H__ +#define __DUART_H__ + +// FIFO Control Register +#define DUART_FCR_FIFO_EN 0x01 /* Fifo enable */ +#define DUART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ +#define DUART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ +#define DUART_FCR_DMA_SELECT 0x08 /* For DMA applications */ +#define DUART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range= */ +#define DUART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */ +#define DUART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */ +#define DUART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */ +#define DUART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */ +#define DUART_FCR_RXSR 0x02 /* Receiver soft reset */ +#define DUART_FCR_TXSR 0x04 /* Transmitter soft reset */ + +// Modem Control Register +#define DUART_MCR_DTR 0x01 /* Reserved */ +#define DUART_MCR_RTS 0x02 /* RTS */ +#define DUART_MCR_OUT1 0x04 /* Reserved */ +#define DUART_MCR_OUT2 0x08 /* Reserved */ +#define DUART_MCR_LOOP 0x10 /* Enable loopback test mode */ +#define DUART_MCR_AFE 0x20 /* AFE (Auto Flow Control) */ +#define DUART_MCR_DMA_EN 0x04 +#define DUART_MCR_TX_DFR 0x08 + +// Line Control Register +/* +* Note: if the word length is 5 bits (DUART_LCR_WLEN5), then setting +* DUART_LCR_STOP will select 1.5 stop bits, not 2 stop bits. +*/ +#define DUART_LCR_WLS_MSK 0x03 /* character length select mask */ +#define DUART_LCR_WLS_5 0x00 /* 5 bit character length */ +#define DUART_LCR_WLS_6 0x01 /* 6 bit character length */ +#define DUART_LCR_WLS_7 0x02 /* 7 bit character length */ +#define DUART_LCR_WLS_8 0x03 /* 8 bit character length */ +#define DUART_LCR_STB 0x04 /* # stop Bits, off=3D1, on=3D1.5 = or 2) */ +#define DUART_LCR_PEN 0x08 /* Parity eneble */ +#define DUART_LCR_EPS 0x10 /* Even Parity Select */ +#define DUART_LCR_STKP 0x20 /* Stick Parity */ +#define DUART_LCR_SBRK 0x40 /* Set Break */ +#define DUART_LCR_BKSE 0x80 /* Bank select enable */ +#define DUART_LCR_DLAB 0x80 /* Divisor latch access bit */ + +// Line Status Register +#define DUART_LSR_DR 0x01 /* Data ready */ +#define DUART_LSR_OE 0x02 /* Overrun */ +#define DUART_LSR_PE 0x04 /* Parity error */ +#define DUART_LSR_FE 0x08 /* Framing error */ +#define DUART_LSR_BI 0x10 /* Break */ +#define DUART_LSR_THRE 0x20 /* Xmit holding register empty */ +#define DUART_LSR_TEMT 0x40 /* Xmitter empty */ +#define DUART_LSR_ERR 0x80 /* Error */ + +// Modem Status Register +#define DUART_MSR_DCTS 0x01 /* Delta CTS */ +#define DUART_MSR_DDSR 0x02 /* Reserved */ +#define DUART_MSR_TERI 0x04 /* Reserved */ +#define DUART_MSR_DDCD 0x08 /* Reserved */ +#define DUART_MSR_CTS 0x10 /* Clear to Send */ +#define DUART_MSR_DSR 0x20 /* Reserved */ +#define DUART_MSR_RI 0x40 /* Reserved */ +#define DUART_MSR_DCD 0x80 /* Reserved */ + +// Interrupt Identification Register +#define DUART_IIR_NO_INT 0x01 /* No interrupts pending */ +#define DUART_IIR_ID 0x06 /* Mask for the interrupt ID */ +#define DUART_IIR_MSI 0x00 /* Modem status interrupt */ +#define DUART_IIR_THRI 0x02 /* Transmitter holding register em= pty */ +#define DUART_IIR_RDI 0x04 /* Receiver data interrupt */ +#define DUART_IIR_RLSI 0x06 /* Receiver line status interrupt = */ + +// Interrupt Enable Register +#define DUART_IER_MSI 0x08 /* Enable Modem status interrupt */ +#define DUART_IER_RLSI 0x04 /* Enable receiver line status int= errupt */ +#define DUART_IER_THRI 0x02 /* Enable Transmitter holding regi= ster int. */ +#define DUART_IER_RDI 0x01 /* Enable receiver data interrupt = */ + +// LCR defaults +#define DUART_LCR_8N1 0x03 +#define DUART_LCRVAL DUART_LCR_8N1 /* 8 data, 1 sto= p, no parity */ +#define DUART_MCRVAL (DUART_MCR_DTR | \ + DUART_MCR_RTS) /* RTS/DTR */ +#define DUART_FCRVAL (DUART_FCR_FIFO_EN | \ + DUART_FCR_RXSR | \ + DUART_FCR_TXSR) /* Clear & enabl= e FIFOs */ + +#define URBR 0x0 +#define UTHR 0x0 +#define UDLB 0x0 +#define UDMB 0x1 +#define UIER 0x1 +#define UIIR 0x2 +#define UFCR 0x2 +#define UAFR 0x2 +#define ULCR 0x3 +#define UMCR 0x4 +#define ULSR 0x5 +#define UMSR 0x6 +#define USCR 0x7 +#define UDSR 0x10 + +extern +UINT64 +GetBusFrequency ( + VOID + ); + +#endif /* __DUART_H__ */ diff --git a/Silicon/NXP/Library/DUartPortLib/DUartPortLib.c b/Silicon/NXP/= Library/DUartPortLib/DUartPortLib.c new file mode 100644 index 0000000..5fcfa9a --- /dev/null +++ b/Silicon/NXP/Library/DUartPortLib/DUartPortLib.c @@ -0,0 +1,370 @@ +/** DuartPortLib.c + DUART (NS16550) library functions + + Based on Serial I/O Port library functions available in PL011SerialPortL= ib.c + + Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.
+ Copyright (c) 2012 - 2013, ARM Ltd. All rights reserved.
+ Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved. + Copyright 2017 NXP + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include +#include +#include +#include + +#include "DUart.h" + +STATIC CONST UINT32 mInvalidControlBits =3D (EFI_SERIAL_SOFTWARE_LOOPBACK_= ENABLE | \ + EFI_SERIAL_DATA_TERMINAL_READY); + +/** + Assert or deassert the control signals on a serial port. + The following control signals are set according their bit settings : + . Request to Send + . Data Terminal Ready + + @param[in] Control The following bits are taken into account : + . EFI_SERIAL_REQUEST_TO_SEND : assert/deassert t= he + "Request To Send" control signal if this bit is + equal to one/zero. + . EFI_SERIAL_DATA_TERMINAL_READY : assert/deasse= rt + the "Data Terminal Ready" control signal if th= is + bit is equal to one/zero. + . EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : enable/d= isable + the hardware loopback if this bit is equal to + one/zero. + . EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : not supp= orted. + . EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : enab= le/ + disable the hardware flow control based on CTS= (Clear + To Send) and RTS (Ready To Send) control signa= ls. + + @retval EFI_SUCCESS The new control bits were set on the device. + @retval EFI_UNSUPPORTED The device does not support this operation. + +**/ +EFI_STATUS +EFIAPI +SerialPortSetControl ( + IN UINT32 Control + ) +{ + UINT32 McrBits; + UINTN UartBase; + + UartBase =3D (UINTN)PcdGet64 (PcdSerialRegisterBase); + + if (Control & (mInvalidControlBits)) { + return EFI_UNSUPPORTED; + } + + McrBits =3D MmioRead8 (UartBase + UMCR); + + if (Control & EFI_SERIAL_REQUEST_TO_SEND) { + McrBits |=3D DUART_MCR_RTS; + } else { + McrBits &=3D ~DUART_MCR_RTS; + } + + if (Control & EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE) { + McrBits |=3D DUART_MCR_LOOP; + } else { + McrBits &=3D ~DUART_MCR_LOOP; + } + + if (Control & EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE) { + McrBits |=3D DUART_MCR_AFE; + } else { + McrBits &=3D ~DUART_MCR_AFE; + } + + MmioWrite32 (UartBase + UMCR, McrBits); + + return EFI_SUCCESS; +} + +/** + Retrieve the status of the control bits on a serial device. + + @param[out] Control Status of the control bits on a serial device : + + . EFI_SERIAL_DATA_CLEAR_TO_SEND, + EFI_SERIAL_DATA_SET_READY, + EFI_SERIAL_RING_INDICATE, + EFI_SERIAL_CARRIER_DETECT, + EFI_SERIAL_REQUEST_TO_SEND, + EFI_SERIAL_DATA_TERMINAL_READY + are all related to the DTE (Data Terminal Equip= ment) + and DCE (Data Communication Equipment) modes of + operation of the serial device. + . EFI_SERIAL_INPUT_BUFFER_EMPTY : equal to one if= the + receive buffer is empty, 0 otherwise. + . EFI_SERIAL_OUTPUT_BUFFER_EMPTY : equal to one i= f the + transmit buffer is empty, 0 otherwise. + . EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : equal to = one if + the hardware loopback is enabled (the ouput fee= ds the + receive buffer), 0 otherwise. + . EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : equal to = one if + a loopback is accomplished by software, 0 other= wise. + . EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : equal= to + one if the hardware flow control based on CTS (= Clear + To Send) and RTS (Ready To Send) control signal= s is + enabled, 0 otherwise. + + @retval EFI_SUCCESS The control bits were read from the serial devi= ce. + +**/ +EFI_STATUS +EFIAPI +SerialPortGetControl ( + OUT UINT32 *Control + ) +{ + UINT32 MsrRegister; + UINT32 McrRegister; + UINT32 LsrRegister; + UINTN UartBase; + + UartBase =3D (UINTN)PcdGet64 (PcdSerialRegisterBase); + + MsrRegister =3D MmioRead8 (UartBase + UMSR); + McrRegister =3D MmioRead8 (UartBase + UMCR); + LsrRegister =3D MmioRead8 (UartBase + ULSR); + + *Control =3D 0; + + if ((MsrRegister & DUART_MSR_CTS) =3D=3D DUART_MSR_CTS) { + *Control |=3D EFI_SERIAL_CLEAR_TO_SEND; + } + + if ((McrRegister & DUART_MCR_RTS) =3D=3D DUART_MCR_RTS) { + *Control |=3D EFI_SERIAL_REQUEST_TO_SEND; + } + + if ((LsrRegister & DUART_LSR_TEMT) =3D=3D DUART_LSR_TEMT) { + *Control |=3D EFI_SERIAL_OUTPUT_BUFFER_EMPTY; + } + + if ((McrRegister & DUART_MCR_AFE) =3D=3D DUART_MCR_AFE) { + *Control |=3D EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE; + } + + if ((McrRegister & DUART_MCR_LOOP) =3D=3D DUART_MCR_LOOP) { + *Control |=3D EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE; + } + + return EFI_SUCCESS; +} + +/* + * Return Baud divisor on basis of Baudrate + */ +UINT32 +CalculateBaudDivisor ( + IN UINT64 BaudRate + ) +{ + UINTN DUartClk; + UINTN FreqSystemBus; + + FreqSystemBus =3D GetBusFrequency (); + DUartClk =3D FreqSystemBus/PcdGet32(PcdPlatformFreqDiv); + + return ((DUartClk)/(BaudRate * 16)); +} + +/* + Initialise the serial port to the specified settings. + All unspecified settings will be set to the default values. + + @return Always return EFI_SUCCESS or EFI_INVALID_PARAMETER. + + **/ +VOID +EFIAPI +DuartInitializePort ( + IN UINT64 BaudRate + ) +{ + UINTN UartBase; + UINT32 BaudDivisor; + + UartBase =3D (UINTN)PcdGet64 (PcdSerialRegisterBase); + BaudDivisor =3D CalculateBaudDivisor (BaudRate); + + + while (!(MmioRead8 (UartBase + ULSR) & DUART_LSR_TEMT)); + + // + // Enable and assert interrupt when new data is available on + // external device, + // setup data format, setup baud divisor + // + MmioWrite8 (UartBase + UIER, 0x1); + MmioWrite8 (UartBase + ULCR, DUART_LCR_BKSE | DUART_LCRVAL); + MmioWrite8 (UartBase + UDLB, 0); + MmioWrite8 (UartBase + UDMB, 0); + MmioWrite8 (UartBase + ULCR, DUART_LCRVAL); + MmioWrite8 (UartBase + UMCR, DUART_MCRVAL); + MmioWrite8 (UartBase + UFCR, DUART_FCRVAL); + MmioWrite8 (UartBase + ULCR, DUART_LCR_BKSE | DUART_LCRVAL); + MmioWrite8 (UartBase + UDLB, BaudDivisor & 0xff); + MmioWrite8 (UartBase + UDMB, (BaudDivisor >> 8) & 0xff); + MmioWrite8 (UartBase + ULCR, DUART_LCRVAL); + + return; +} + +/** + Programmed hardware of Serial port. + + @return Always return EFI_SUCCESS. + +**/ +EFI_STATUS +EFIAPI +SerialPortInitialize ( + VOID + ) +{ + UINT64 BaudRate; + BaudRate =3D (UINTN)PcdGet64 (PcdUartDefaultBaudRate); + + + DuartInitializePort (BaudRate); + + return EFI_SUCCESS; +} + +/** + Write data to serial device. + + @param Buffer Point of data buffer which need to be written. + @param NumberOfBytes Number of output bytes which are cached in Buff= er. + + @retval 0 Write data failed. + @retval !0 Actual number of bytes written to serial device. + +**/ +UINTN +EFIAPI +SerialPortWrite ( + IN UINT8 *Buffer, + IN UINTN NumberOfBytes + ) +{ + UINT8 *Final; + UINTN UartBase; + + Final =3D &Buffer[NumberOfBytes]; + UartBase =3D (UINTN)PcdGet64 (PcdSerialRegisterBase); + + while (Buffer < Final) { + while ((MmioRead8 (UartBase + ULSR) & DUART_LSR_THRE) =3D=3D 0); + MmioWrite8 (UartBase + UTHR, *Buffer++); + } + + return NumberOfBytes; +} + +/** + Read data from serial device and save the data in buffer. + + @param Buffer Point of data buffer which need to be written. + @param NumberOfBytes Number of output bytes which are cached in Buff= er. + + @retval 0 Read data failed. + @retval !0 Actual number of bytes read from serial device. + +**/ +UINTN +EFIAPI +SerialPortRead ( + OUT UINT8 *Buffer, + IN UINTN NumberOfBytes + ) +{ + UINTN Count; + UINTN UartBase; + + UartBase =3D (UINTN)PcdGet64 (PcdSerialRegisterBase); + + for (Count =3D 0; Count < NumberOfBytes; Count++, Buffer++) { + // Loop while waiting for a new char(s) to arrive in the + // RxFIFO + while ((MmioRead8 (UartBase + ULSR) & DUART_LSR_DR) =3D=3D 0); + + *Buffer =3D MmioRead8 (UartBase + URBR); + } + + return NumberOfBytes; +} + +/** + Check to see if any data is available to be read from the debug device. + + @retval EFI_SUCCESS At least one byte of data is available to be r= ead + @retval EFI_NOT_READY No data is available to be read + @retval EFI_DEVICE_ERROR The serial device is not functioning properly + +**/ +BOOLEAN +EFIAPI +SerialPortPoll ( + VOID + ) +{ + UINTN UartBase; + + UartBase =3D (UINTN)PcdGet64 (PcdSerialRegisterBase); + + return ((MmioRead8 (UartBase + ULSR) & DUART_LSR_DR) !=3D 0); +} + +/** + Set new attributes to LS1043a. + + @param BaudRate The baud rate of the serial device. If t= he baud rate is not supported, + the speed will be reduced down to the ne= arest supported one and the + variable's value will be updated accordi= ngly. + @param ReceiveFifoDepth The number of characters the device will= buffer on input. If the specified + value is not supported, the variable's v= alue will be reduced down to the + nearest supported one. + @param Timeout If applicable, the number of microsecond= s the device will wait + before timing out a Read or a Write oper= ation. + @param Parity If applicable, this is the EFI_PARITY_TY= PE that is computed or checked + as each character is transmitted or rece= ived. If the device does not + support parity, the value is the default= parity value. + @param DataBits The number of data bits in each character + @param StopBits If applicable, the EFI_STOP_BITS_TYPE nu= mber of stop bits per character. + If the device does not support stop bits= , the value is the default stop + bit value. + + @retval EFI_SUCCESS All attributes were set correctly on the= serial device. + +**/ +EFI_STATUS +EFIAPI +SerialPortSetAttributes ( + IN OUT UINT64 *BaudRate, + IN OUT UINT32 *ReceiveFifoDepth, + IN OUT UINT32 *Timeout, + IN OUT EFI_PARITY_TYPE *Parity, + IN OUT UINT8 *DataBits, + IN OUT EFI_STOP_BITS_TYPE *StopBits + ) +{ + DuartInitializePort (*BaudRate); + + return EFI_SUCCESS; +} diff --git a/Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf b/Silicon/NX= P/Library/DUartPortLib/DUartPortLib.inf new file mode 100644 index 0000000..6940de9 --- /dev/null +++ b/Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf @@ -0,0 +1,41 @@ +# DUartPortLib.inf +# +# Component description file for DUartPortLib module +# +# Copyright (c) 2013, Freescale Ltd. All rights reserved. +# Copyright 2017 NXP +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +# + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D DUartPortLib + FILE_GUID =3D c42dfe79-8de5-429e-a055-2d0a58591498 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SerialPortLib + +[Sources.common] + DUartPortLib.c + +[LibraryClasses] + PcdLib + SocLib + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/NXP/NxpQoriqLs.dec + +[Pcd] + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate + gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun May 5 06:05:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" From: Meenakshi Aggarwal I2C driver produces gEfiI2cMasterProtocolGuid which can be used by other modules. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Meenakshi Aggarwal --- Silicon/NXP/Drivers/I2cDxe/I2cDxe.c | 726 ++++++++++++++++++++++++++++++= ++++ Silicon/NXP/Drivers/I2cDxe/I2cDxe.h | 65 +++ Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf | 55 +++ 3 files changed, 846 insertions(+) create mode 100644 Silicon/NXP/Drivers/I2cDxe/I2cDxe.c create mode 100644 Silicon/NXP/Drivers/I2cDxe/I2cDxe.h create mode 100644 Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c b/Silicon/NXP/Drivers/I2cD= xe/I2cDxe.c new file mode 100644 index 0000000..80a8826 --- /dev/null +++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c @@ -0,0 +1,726 @@ +/** I2cDxe.c + I2c driver APIs for read, write, initialize, set speed and reset + + Copyright 2017 NXP + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may be= found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include +#include +#include +#include +#include + +#include + +#include "I2cDxe.h" + +STATIC CONST UINT16 ClkDiv[60][2] =3D { + { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 }, + { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 }, + { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D }, + { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 }, + { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 }, + { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 }, + { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 }, + { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 }, + { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 }, + { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B }, + { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 }, + { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 },{ 1280, 0x35 }, + { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B }, + { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A }, + { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E }, +}; + +/** + Calculate and return proper clock divider + + @param Rate clock rate + + @retval ClkDiv Value used to get frequency divider value + +**/ +STATIC +UINT8 +GetClkDiv ( + IN UINT32 Rate + ) +{ + UINTN ClkRate; + UINT32 Div; + UINT8 ClkDivx; + + ClkRate =3D GetBusFrequency (); + + Div =3D (ClkRate + Rate - 1) / Rate; + + if (Div < ClkDiv[0][0]) { + ClkDivx =3D 0; + } else if (Div > ClkDiv[ARRAY_SIZE (ClkDiv) - 1][0]){ + ClkDivx =3D ARRAY_SIZE (ClkDiv) - 1; + } else { + for (ClkDivx =3D 0; ClkDiv[ClkDivx][0] < Div; ClkDivx++); + } + + return ClkDivx; +} + +/** + Function used to check if i2c is in mentioned state or not + + @param I2cRegs Pointer to I2C registers + @param State i2c state need to be checked + + @retval EFI_NOT_READY Arbitration was lost + @retval EFI_TIMEOUT Timeout occured + @retval CurrState Value of state register + +**/ +STATIC +EFI_STATUS +WaitForI2cState ( + IN I2C_REGS *I2cRegs, + IN UINT32 State + ) +{ + UINT8 CurrState; + UINT64 Cnt; + + for (Cnt =3D 0; Cnt < 50000; Cnt++) { + MemoryFence (); + CurrState =3D MmioRead8 ((UINTN)&I2cRegs->I2cSr); + if (CurrState & I2C_SR_IAL) { + MmioWrite8 ((UINTN)&I2cRegs->I2cSr, CurrState | I2C_SR_IAL); + return EFI_NOT_READY; + } + + if ((CurrState & (State >> 8)) =3D=3D (UINT8)State) { + return CurrState; + } + } + + return EFI_TIMEOUT; +} + +/** + Function to transfer byte on i2c + + @param I2cRegs Pointer to i2c registers + @param Byte Byte to be transferred on i2c bus + + @retval EFI_NOT_READY Arbitration was lost + @retval EFI_TIMEOUT Timeout occured + @retval EFI_NOT_FOUND ACK was not recieved + @retval EFI_SUCCESS Data transfer was succesful + +**/ +STATIC +EFI_STATUS +TransferByte ( + IN I2C_REGS *I2cRegs, + IN UINT8 Byte + ) +{ + EFI_STATUS Ret; + + MmioWrite8 ((UINTN)&I2cRegs->I2cSr, I2C_SR_IIF_CLEAR); + MmioWrite8 ((UINTN)&I2cRegs->I2cDr, Byte); + + Ret =3D WaitForI2cState (I2cRegs, IIF); + if ((Ret =3D=3D EFI_TIMEOUT) || (Ret =3D=3D EFI_NOT_READY)) { + return Ret; + } + + if (Ret & I2C_SR_RX_NO_AK) { + return EFI_NOT_FOUND; + } + + return EFI_SUCCESS; +} + +/** + Function to stop transaction on i2c bus + + @param I2cRegs Pointer to i2c registers + + @retval EFI_NOT_READY Arbitration was lost + @retval EFI_TIMEOUT Timeout occured + @retval EFI_SUCCESS Stop operation was successful + +**/ +STATIC +EFI_STATUS +I2cStop ( + IN I2C_REGS *I2cRegs + ) +{ + INT32 Ret; + UINT32 Temp; + + Temp =3D MmioRead8 ((UINTN)&I2cRegs->I2cCr); + + Temp &=3D ~(I2C_CR_MSTA | I2C_CR_MTX); + MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp); + + Ret =3D WaitForI2cState (I2cRegs, BUS_IDLE); + + if (Ret < 0) { + return Ret; + } else { + return EFI_SUCCESS; + } +} + +/** + Function to send start signal, Chip Address and + memory offset + + @param I2cRegs Pointer to i2c base registers + @param Chip Chip Address + @param Offset Slave memory's offset + @param Alen length of chip address + + @retval EFI_NOT_READY Arbitration lost + @retval EFI_TIMEOUT Failed to initialize data transfer in predefine= d time + @retval EFI_NOT_FOUND ACK was not recieved + @retval EFI_SUCCESS Read was successful + +**/ +STATIC +EFI_STATUS +InitTransfer ( + IN I2C_REGS *I2cRegs, + IN UINT8 Chip, + IN UINT32 Offset, + IN INT32 Alen + ) +{ + UINT32 Temp; + EFI_STATUS Ret; + + // Enable I2C controller + if (MmioRead8 ((UINTN)&I2cRegs->I2cCr) & I2C_CR_IDIS) { + MmioWrite8 ((UINTN)&I2cRegs->I2cCr, I2C_CR_IEN); + } + + if (MmioRead8 ((UINTN)&I2cRegs->I2cAdr) =3D=3D (Chip << 1)) { + MmioWrite8 ((UINTN)&I2cRegs->I2cAdr, (Chip << 1) ^ 2); + } + + MmioWrite8 ((UINTN)&I2cRegs->I2cSr, I2C_SR_IIF_CLEAR); + Ret =3D WaitForI2cState (I2cRegs, BUS_IDLE); + if ((Ret =3D=3D EFI_TIMEOUT) || (Ret =3D=3D EFI_NOT_READY)) { + return Ret; + } + + // Start I2C transaction + Temp =3D MmioRead8 ((UINTN)&I2cRegs->I2cCr); + // set to master mode + Temp |=3D I2C_CR_MSTA; + MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp); + + Ret =3D WaitForI2cState (I2cRegs, BUS_BUSY); + if ((Ret =3D=3D EFI_TIMEOUT) || (Ret =3D=3D EFI_NOT_READY)) { + return Ret; + } + + Temp |=3D I2C_CR_MTX | I2C_CR_TX_NO_AK; + MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp); + + // write slave Address + Ret =3D TransferByte (I2cRegs, Chip << 1); + if (Ret !=3D EFI_SUCCESS) { + return Ret; + } + + if (Alen >=3D 0) { + while (Alen--) { + Ret =3D TransferByte (I2cRegs, (Offset >> (Alen * 8)) & 0xff); + if (Ret !=3D EFI_SUCCESS) + return Ret; + } + } + return EFI_SUCCESS; +} + +/** + Function to check if i2c bus is idle + + @param Base Pointer to base address of I2c controller + + @retval EFI_SUCCESS + +**/ +STATIC +INT32 +I2cBusIdle ( + IN VOID *Base + ) +{ + return EFI_SUCCESS; +} + +/** + Function to initiate data transfer on i2c bus + + @param I2cRegs Pointer to i2c base registers + @param Chip Chip Address + @param Offset Slave memory's offset + @param Alen length of chip address + + @retval EFI_NOT_READY Arbitration lost + @retval EFI_TIMEOUT Failed to initialize data transfer in predefine= d time + @retval EFI_NOT_FOUND ACK was not recieved + @retval EFI_SUCCESS Read was successful + +**/ +STATIC +EFI_STATUS +InitDataTransfer ( + IN I2C_REGS *I2cRegs, + IN UINT8 Chip, + IN UINT32 Offset, + IN INT32 Alen + ) +{ + EFI_STATUS Status; + INT32 Retry; + + for (Retry =3D 0; Retry < 3; Retry++) { + Status =3D InitTransfer (I2cRegs, Chip, Offset, Alen); + if (Status =3D=3D EFI_SUCCESS) { + return EFI_SUCCESS; + } + + I2cStop (I2cRegs); + + if (EFI_NOT_FOUND =3D=3D Status) { + return Status; + } + + // Disable controller + if (Status !=3D EFI_NOT_READY) { + MmioWrite8 ((UINTN)&I2cRegs->I2cCr, I2C_CR_IDIS); + } + + if (I2cBusIdle (I2cRegs) < 0) { + break; + } + } + return Status; +} + +/** + Function to read data using i2c bus + + @param I2cBus I2c Controller number + @param Chip Address of slave device from where data to be r= ead + @param Offset Offset of slave memory + @param Alen Address length of slave + @param Buffer A pointer to the destination buffer for the data + @param Len Length of data to be read + + @retval EFI_NOT_READY Arbitration lost + @retval EFI_TIMEOUT Failed to initialize data transfer in predefine= d time + @retval EFI_NOT_FOUND ACK was not recieved + @retval EFI_SUCCESS Read was successful + +**/ +STATIC +EFI_STATUS +I2cDataRead ( + IN UINT32 I2cBus, + IN UINT8 Chip, + IN UINT32 Offset, + IN UINT32 Alen, + IN UINT8 *Buffer, + IN UINT32 Len + ) +{ + EFI_STATUS Status; + UINT32 Temp; + INT32 I; + I2C_REGS *I2cRegs; + + I2cRegs =3D (I2C_REGS *)(FixedPcdGet64 (PcdI2c0BaseAddr + + (I2cBus * FixedPcdGet32 (PcdI2cSize)))); + + Status =3D InitDataTransfer (I2cRegs, Chip, Offset, Alen); + if (Status !=3D EFI_SUCCESS) { + return Status; + } + + Temp =3D MmioRead8 ((UINTN)&I2cRegs->I2cCr); + Temp |=3D I2C_CR_RSTA; + MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp); + + Status =3D TransferByte (I2cRegs, (Chip << 1) | 1); + if (Status !=3D EFI_SUCCESS) { + I2cStop (I2cRegs); + return Status; + } + + // setup bus to read data + Temp =3D MmioRead8 ((UINTN)&I2cRegs->I2cCr); + Temp &=3D ~(I2C_CR_MTX | I2C_CR_TX_NO_AK); + if (Len =3D=3D 1) { + Temp |=3D I2C_CR_TX_NO_AK; + } + + MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp); + MmioWrite8 ((UINTN)&I2cRegs->I2cSr, I2C_SR_IIF_CLEAR); + + // Dummy Read to initiate recieve operation + MmioRead8 ((UINTN)&I2cRegs->I2cDr); + + for (I =3D 0; I < Len; I++) { + Status =3D WaitForI2cState (I2cRegs, IIF); + if ((Status =3D=3D EFI_TIMEOUT) || (Status =3D=3D EFI_NOT_READY)) { + I2cStop (I2cRegs); + return Status; + } + // + // It must generate STOP before read I2DR to prevent + // controller from generating another clock cycle + // + if (I =3D=3D (Len - 1)) { + I2cStop (I2cRegs); + } else if (I =3D=3D (Len - 2)) { + Temp =3D MmioRead8 ((UINTN)&I2cRegs->I2cCr); + Temp |=3D I2C_CR_TX_NO_AK; + MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp); + } + MmioWrite8 ((UINTN)&I2cRegs->I2cSr, I2C_SR_IIF_CLEAR); + Buffer[I] =3D MmioRead8 ((UINTN)&I2cRegs->I2cDr); + } + + I2cStop (I2cRegs); + + return EFI_SUCCESS; +} + +/** + Function to write data using i2c bus + + @param I2cBus I2c Controller number + @param Chip Address of slave device where data to be written + @param Offset Offset of slave memory + @param Alen Address length of slave + @param Buffer A pointer to the source buffer for the data + @param Len Length of data to be write + + @retval EFI_NOT_READY Arbitration lost + @retval EFI_TIMEOUT Failed to initialize data transfer in predefine= d time + @retval EFI_NOT_FOUND ACK was not recieved + @retval EFI_SUCCESS Read was successful + +**/ +STATIC +EFI_STATUS +I2cDataWrite ( + IN UINT32 I2cBus, + IN UINT8 Chip, + IN UINT32 Offset, + IN INT32 Alen, + OUT UINT8 *Buffer, + IN INT32 Len + ) +{ + EFI_STATUS Status; + I2C_REGS *I2cRegs; + INT32 I; + + I2cRegs =3D (I2C_REGS *)(FixedPcdGet64 (PcdI2c0BaseAddr + + (I2cBus * FixedPcdGet32 (PcdI2cSize)))); + + Status =3D InitDataTransfer (I2cRegs, Chip, Offset, Alen); + if (Status !=3D EFI_SUCCESS) { + return Status; + } + + // Write operation + for (I =3D 0; I < Len; I++) { + Status =3D TransferByte (I2cRegs, Buffer[I]); + if (Status !=3D EFI_SUCCESS) { + break; + } + } + + I2cStop (I2cRegs); + return Status; +} + +/** + Function to set i2c bus frequency + + @param This Pointer to I2c master protocol + @param BusClockHertz value to be set + + @retval EFI_SUCCESS Operation successfull +**/ + +EFI_STATUS +EFIAPI +SetBusFrequency ( + IN CONST EFI_I2C_MASTER_PROTOCOL *This, + IN OUT UINTN *BusClockHertz + ) +{ + I2C_REGS *I2cRegs; + UINT8 ClkId; + UINT8 SpeedId; + + I2cRegs =3D (I2C_REGS *)(FixedPcdGet64 (PcdI2c0BaseAddr + + (PcdGet32 (PcdI2cBus) * FixedPcdGet32 (PcdI2cSize= )))); + + ClkId =3D GetClkDiv (*BusClockHertz); + SpeedId =3D ClkDiv[ClkId][1]; + + // Store divider value + MmioWrite8 ((UINTN)&I2cRegs->I2cFdr, SpeedId); + + MemoryFence (); + + return EFI_SUCCESS; +} + +/** + Function to reset I2c Controller + + @param This Pointer to I2c master protocol + + @return EFI_SUCCESS Operation successfull +**/ +EFI_STATUS +EFIAPI +Reset ( + IN CONST EFI_I2C_MASTER_PROTOCOL *This + ) +{ + I2C_REGS *I2cRegs; + + I2cRegs =3D (I2C_REGS *)(FixedPcdGet64 (PcdI2c0BaseAddr + + (PcdGet32 (PcdI2cBus) * FixedPcdGet32 (PcdI2cSize= )))); + + // Reset module + MmioWrite8 ((UINTN)&I2cRegs->I2cCr, I2C_CR_IDIS); + MmioWrite8 ((UINTN)&I2cRegs->I2cSr, 0); + + MemoryFence (); + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +StartRequest ( + IN CONST EFI_I2C_MASTER_PROTOCOL *This, + IN UINTN SlaveAddress, + IN EFI_I2C_REQUEST_PACKET *RequestPacket, + IN EFI_EVENT Event OPTIONAL, + OUT EFI_STATUS *I2cStatus OPTIONAL + ) +{ + UINT32 Count; + INT32 Ret; + UINT32 Length; + UINT8 *Buffer; + UINT32 Flag; + UINT32 RegAddress; + UINT32 OffsetLength; + + RegAddress =3D 0; + + if (RequestPacket->OperationCount <=3D 0) { + DEBUG ((DEBUG_ERROR,"%a: Operation count is not valid %d\n", + __FUNCTION__, RequestPacket->OperationCount)); + return EFI_INVALID_PARAMETER; + } + + OffsetLength =3D RequestPacket->Operation[0].LengthInBytes; + RegAddress =3D *RequestPacket->Operation[0].Buffer; + + for (Count =3D 1; Count < RequestPacket->OperationCount; Count++) { + Flag =3D RequestPacket->Operation[Count].Flags; + Length =3D RequestPacket->Operation[Count].LengthInBytes; + Buffer =3D RequestPacket->Operation[Count].Buffer; + + if (Length <=3D 0) { + DEBUG ((DEBUG_ERROR,"%a: Invalid length of buffer %d\n", + __FUNCTION__, Length)); + return EFI_INVALID_PARAMETER; + } + + if (Flag =3D=3D I2C_FLAG_READ) { + Ret =3D I2cDataRead (PcdGet32 (PcdI2cBus), SlaveAddress, + RegAddress, OffsetLength, Buffer, Length); + if (Ret !=3D EFI_SUCCESS) { + DEBUG ((DEBUG_ERROR,"%a: I2c read operation failed (error %d)\n", + __FUNCTION__, Ret)); + return Ret; + } + } else if (Flag =3D=3D I2C_FLAG_WRITE) { + Ret =3D I2cDataWrite (PcdGet32 (PcdI2cBus), SlaveAddress, + RegAddress, OffsetLength, Buffer, Length); + if (Ret !=3D EFI_SUCCESS) { + DEBUG ((DEBUG_ERROR,"%a: I2c write operation failed (error %d)\n", + __FUNCTION__, Ret)); + return Ret; + } + } else { + DEBUG ((DEBUG_ERROR,"%a: Invalid Flag %d\n", + __FUNCTION__, Flag)); + return EFI_INVALID_PARAMETER; + } + } + + return EFI_SUCCESS; +} + +CONST EFI_I2C_CONTROLLER_CAPABILITIES I2cControllerCapabilities =3D { + 0, + 0, + 0, + 0 +}; + +STATIC EFI_I2C_MASTER_PROTOCOL gI2c =3D { + /// + /// Set the clock frequency for the I2C bus. + /// + SetBusFrequency, + /// + /// Reset the I2C host controller. + /// + Reset, + /// + /// Start an I2C transaction in master mode on the host controller. + /// + StartRequest, + /// + /// Pointer to an EFI_I2C_CONTROLLER_CAPABILITIES data structure contain= ing + /// the capabilities of the I2C host controller. + /// + &I2cControllerCapabilities +}; + +STATIC I2C_DEVICE_PATH gDevicePath =3D { + { + { + HARDWARE_DEVICE_PATH, HW_VENDOR_DP, + { + sizeof (VENDOR_DEVICE_PATH), 0 + } + }, + EFI_CALLER_ID_GUID + }, + { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { + sizeof (EFI_DEVICE_PATH_PROTOCOL), 0 + } + } +}; + +/** + The Entry Point for I2C driver. + + @param[in] ImageHandle The firmware allocated handle for the EFI imag= e. + @param[in] SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS The entry point is executed successfully. + @retval other Some error occurs when executing this entry po= int. + +**/ +EFI_STATUS +EFIAPI +I2cDxeEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + // + // Install I2c Master protocol on this controller + // + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &ImageHandle, + &gEfiI2cMasterProtocolGuid, + (VOID**)&gI2c, + &gEfiDevicePathProtocolGuid, + &gDevicePath, + NULL + ); + + ASSERT_EFI_ERROR (Status); + + return Status; +} + +/** + Unload function for the I2c Driver. + + @param ImageHandle[in] The allocated handle for the EFI image + + @retval EFI_SUCCESS The driver was unloaded successfully + @retval EFI_INVALID_PARAMETER ImageHandle is not a valid image handle. + +**/ +EFI_STATUS +EFIAPI +I2cDxeUnload ( + IN EFI_HANDLE ImageHandle + ) +{ + EFI_STATUS Status; + EFI_HANDLE *HandleBuffer; + UINTN HandleCount; + UINTN Index; + + // + // Retrieve all I2c handles in the handle database + // + Status =3D gBS->LocateHandleBuffer (ByProtocol, + &gEfiI2cMasterProtocolGuid, + NULL, + &HandleCount, + &HandleBuffer); + if (EFI_ERROR (Status)) { + return Status; + } + + // + // Disconnect the driver from the handles in the handle database + // + for (Index =3D 0; Index < HandleCount; Index++) { + Status =3D gBS->DisconnectController (HandleBuffer[Index], + gImageHandle, + NULL); + } + + // + // Free the handle array + // + gBS->FreePool (HandleBuffer); + + // + // Uninstall protocols installed by the driver in its entrypoint + // + Status =3D gBS->UninstallMultipleProtocolInterfaces (ImageHandle, + &gEfiI2cMasterProtocolGuid, &gI2c, + &gEfiDevicePathProtocolGuid, &gDevicePath, + NULL); + + return Status; +} diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h b/Silicon/NXP/Drivers/I2cD= xe/I2cDxe.h new file mode 100644 index 0000000..4a562d3 --- /dev/null +++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h @@ -0,0 +1,65 @@ +/** I2cDxe.h + Header defining the constant, base address amd function for I2C controll= er + + Copyright 2017 NXP + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#ifndef __I2C_DXE_H___ +#define __I2C_DXE_H__ + +#include + +#define I2C_CR_IIEN (1 << 6) +#define I2C_CR_MSTA (1 << 5) +#define I2C_CR_MTX (1 << 4) +#define I2C_CR_TX_NO_AK (1 << 3) +#define I2C_CR_RSTA (1 << 2) + +#define I2C_SR_ICF (1 << 7) +#define I2C_SR_IBB (1 << 5) +#define I2C_SR_IAL (1 << 4) +#define I2C_SR_IIF (1 << 1) +#define I2C_SR_RX_NO_AK (1 << 0) + +#define I2C_CR_IEN (0 << 7) +#define I2C_CR_IDIS (1 << 7) +#define I2C_SR_IIF_CLEAR (1 << 1) + +#define BUS_IDLE (0 | (I2C_SR_IBB << 8)) +#define BUS_BUSY (I2C_SR_IBB | (I2C_SR_IBB << 8)) +#define IIF (I2C_SR_IIF | (I2C_SR_IIF << 8)) + +#define I2C_FLAG_WRITE 0x0 + +typedef struct { + VENDOR_DEVICE_PATH Guid; + EFI_DEVICE_PATH_PROTOCOL End; +} I2C_DEVICE_PATH; + +/** + Record defining i2c registers +**/ +typedef struct { + UINT8 I2cAdr; + UINT8 I2cFdr; + UINT8 I2cCr; + UINT8 I2cSr; + UINT8 I2cDr; +} I2C_REGS ; + +extern +UINT64 +GetBusFrequency ( + VOID + ); + +#endif diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf b/Silicon/NXP/Drivers/I2= cDxe/I2cDxe.inf new file mode 100644 index 0000000..ceb1b11 --- /dev/null +++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf @@ -0,0 +1,55 @@ +# @file +# +# Component description file for I2c driver +# +# Copyright (c) 2015, Freescale Semiconductor, Inc. All rights reserved. +# Copyright 2017 NXP +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may b= e found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +# + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D I2cDxe + FILE_GUID =3D 5f2927ba-1b04-4d5f-8bef-2b50c635d1e7 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D I2cDxeEntryPoint + UNLOAD =3D I2cDxeUnload + +[Sources.common] + I2cDxe.c + +[LibraryClasses] + ArmLib + IoLib + MemoryAllocationLib + PcdLib + SocLib + TimerLib + UefiDriverEntryPoint + UefiLib + +[Packages] + MdePkg/MdePkg.dec + Silicon/NXP/NxpQoriqLs.dec + +[Protocols] + gEfiI2cMasterProtocolGuid + +[Pcd] + gNxpQoriqLsTokenSpaceGuid.PcdI2cBus + gNxpQoriqLsTokenSpaceGuid.PcdI2cSpeed + gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdI2cSize + gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController + +[Depex] + TRUE --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun May 5 06:05:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" From: Meenakshi Aggarwal Real time clock Apis on top of I2C Apis Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Meenakshi Aggarwal Reviewed-by: Leif Lindholm --- Silicon/Maxim/Library/Ds1307RtcLib/Ds1307Rtc.h | 59 ++++ Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c | 329 +++++++++++++++++= ++++ .../Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec | 26 ++ .../Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf | 45 +++ 4 files changed, 459 insertions(+) create mode 100644 Silicon/Maxim/Library/Ds1307RtcLib/Ds1307Rtc.h create mode 100644 Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c create mode 100644 Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec create mode 100644 Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf diff --git a/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307Rtc.h b/Silicon/Maxim= /Library/Ds1307RtcLib/Ds1307Rtc.h new file mode 100644 index 0000000..96271f8 --- /dev/null +++ b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307Rtc.h @@ -0,0 +1,59 @@ +/** Ds1307Rtc.h +* +* Copyright 2017 NXP +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the B= SD License +* which accompanies this distribution. The full text of the license may = be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#ifndef __DS1307RTC_H__ +#define __DS1307RTC_H__ + +/* + * RTC time register + */ +#define DS1307_SEC_REG_ADDR 0x00 +#define DS1307_MIN_REG_ADDR 0x01 +#define DS1307_HR_REG_ADDR 0x02 +#define DS1307_DAY_REG_ADDR 0x03 +#define DS1307_DATE_REG_ADDR 0x04 +#define DS1307_MON_REG_ADDR 0x05 +#define DS1307_YR_REG_ADDR 0x06 + +#define DS1307_SEC_BIT_CH 0x80 /* Clock Halt (in Register 0) */ + +/* + * RTC control register + */ +#define DS1307_CTL_REG_ADDR 0x07 + +#define START_YEAR 1970 +#define END_YEAR 2070 + +/* + * TIME MASKS + */ +#define MASK_SEC 0x7F +#define MASK_MIN 0x7F +#define MASK_HOUR 0x3F +#define MASK_DAY 0x3F +#define MASK_MONTH 0x1F + +/* + * I2C FLAGS + */ +#define I2C_REG_ADDRESS 0x2 + +typedef struct { + UINTN OperationCount; + EFI_I2C_OPERATION SetAddressOp; + EFI_I2C_OPERATION GetSetDateTimeOp; +} RTC_I2C_REQUEST; + +#endif // __DS1307RTC_H__ diff --git a/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c b/Silicon/Ma= xim/Library/Ds1307RtcLib/Ds1307RtcLib.c new file mode 100644 index 0000000..cf45d49 --- /dev/null +++ b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c @@ -0,0 +1,329 @@ +/** Ds1307RtcLib.c + Implement EFI RealTimeClock via RTC Lib for DS1307 RTC. + + Based on RTC implementation available in + EmbeddedPkg/Library/TemplateRealTimeClockLib/RealTimeClockLib.c + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+ Copyright 2017 NXP + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "Ds1307Rtc.h" + +STATIC VOID *mDriverEventRegistration; +STATIC EFI_I2C_MASTER_PROTOCOL *mI2cMaster; + +/** + Read RTC register. + + @param RtcRegAddr Register offset of RTC to be read. + + @retval Register Value read + +**/ + +STATIC +UINT8 +RtcRead ( + IN UINT8 RtcRegAddr + ) +{ + RTC_I2C_REQUEST Req; + EFI_STATUS Status; + UINT8 Val; + + Val =3D 0; + + Req.OperationCount =3D 2; + + Req.SetAddressOp.Flags =3D 0; + Req.SetAddressOp.LengthInBytes =3D sizeof (RtcRegAddr); + Req.SetAddressOp.Buffer =3D &RtcRegAddr; + + Req.GetSetDateTimeOp.Flags =3D I2C_FLAG_READ; + Req.GetSetDateTimeOp.LengthInBytes =3D sizeof (Val); + Req.GetSetDateTimeOp.Buffer =3D &Val; + + Status =3D mI2cMaster->StartRequest (mI2cMaster, FixedPcdGet8 (PcdI2cSla= veAddress), + (VOID *)&Req, + NULL, NULL); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "RTC read error at Addr:0x%x\n", RtcRegAddr)); + } + + return Val; +} + +/** + Write RTC register. + + @param RtcRegAddr Register offset of RTC to write. + @param Val Value to be written + +**/ + +STATIC +VOID +RtcWrite ( + IN UINT8 RtcRegAddr, + IN UINT8 Val + ) +{ + RTC_I2C_REQUEST Req; + EFI_STATUS Status; + + Req.OperationCount =3D 2; + + Req.SetAddressOp.Flags =3D 0; + Req.SetAddressOp.LengthInBytes =3D sizeof (RtcRegAddr); + Req.SetAddressOp.Buffer =3D &RtcRegAddr; + + Req.GetSetDateTimeOp.Flags =3D 0; + Req.GetSetDateTimeOp.LengthInBytes =3D sizeof (Val); + Req.GetSetDateTimeOp.Buffer =3D &Val; + + Status =3D mI2cMaster->StartRequest (mI2cMaster, FixedPcdGet8 (PcdI2cSla= veAddress), + (VOID *)&Req, + NULL, NULL); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "RTC write error at Addr:0x%x\n", RtcRegAddr)); + } +} + +/** + Returns the current time and date information, and the time-keeping capa= bilities + of the hardware platform. + + @param Time A pointer to storage to receive a snapshot= of the current time. + @param Capabilities An optional pointer to a buffer to receive= the real time clock + device's capabilities. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_INVALID_PARAMETER Time is NULL. + @retval EFI_DEVICE_ERROR The time could not be retrieved due to har= dware error. + +**/ + +EFI_STATUS +EFIAPI +LibGetTime ( + OUT EFI_TIME *Time, + OUT EFI_TIME_CAPABILITIES *Capabilities + ) +{ + EFI_STATUS Status; + UINT8 Second; + UINT8 Minute; + UINT8 Hour; + UINT8 Day; + UINT8 Month; + UINT8 Year; + + if (mI2cMaster =3D=3D NULL) { + return EFI_DEVICE_ERROR; + } + + Status =3D EFI_SUCCESS; + + Second =3D RtcRead (DS1307_SEC_REG_ADDR); + Minute =3D RtcRead (DS1307_MIN_REG_ADDR); + Hour =3D RtcRead (DS1307_HR_REG_ADDR); + Day =3D RtcRead (DS1307_DATE_REG_ADDR); + Month =3D RtcRead (DS1307_MON_REG_ADDR); + Year =3D RtcRead (DS1307_YR_REG_ADDR); + + if (Second & DS1307_SEC_BIT_CH) { + DEBUG ((DEBUG_ERROR, "### Warning: RTC oscillator has stopped\n")); + /* clear the CH flag */ + RtcWrite (DS1307_SEC_REG_ADDR, + RtcRead (DS1307_SEC_REG_ADDR) & ~DS1307_SEC_BIT_CH); + Status =3D EFI_DEVICE_ERROR; + } + + Time->Second =3D BcdToDecimal8 (Second & MASK_SEC); + Time->Minute =3D BcdToDecimal8 (Minute & MASK_MIN); + Time->Hour =3D BcdToDecimal8 (Hour & MASK_HOUR); + Time->Day =3D BcdToDecimal8 (Day & MASK_DAY); + Time->Month =3D BcdToDecimal8 (Month & MASK_MONTH); + + // + // RTC can save year 1970 to 2069 + // On writing Year, save year % 100 + // On Reading reversing the operation e.g. 2012 + // write =3D 12 (2012 % 100) + // read =3D 2012 (12 + 2000) + // + Time->Year =3D BcdToDecimal8 (Year) + + (BcdToDecimal8 (Year) >=3D 70 ? START_YEAR - 70 : END_YEAR = -70); + + return Status; +} + +/** + Sets the current local time and date information. + + @param Time A pointer to the current time. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_INVALID_PARAMETER A time field is out of range. + +**/ +EFI_STATUS +EFIAPI +LibSetTime ( + IN EFI_TIME *Time + ) +{ + if (mI2cMaster =3D=3D NULL) { + return EFI_DEVICE_ERROR; + } + + if (Time->Year < START_YEAR || Time->Year >=3D END_YEAR){ + DEBUG ((DEBUG_ERROR, "WARNING: Year should be between 1970 and 2069!\n= ")); + return EFI_INVALID_PARAMETER; + } + + RtcWrite (DS1307_YR_REG_ADDR, DecimalToBcd8 (Time->Year % 100)); + RtcWrite (DS1307_MON_REG_ADDR, DecimalToBcd8 (Time->Month)); + RtcWrite (DS1307_DATE_REG_ADDR, DecimalToBcd8 (Time->Day)); + RtcWrite (DS1307_HR_REG_ADDR, DecimalToBcd8 (Time->Hour)); + RtcWrite (DS1307_MIN_REG_ADDR, DecimalToBcd8 (Time->Minute)); + RtcWrite (DS1307_SEC_REG_ADDR, DecimalToBcd8 (Time->Second)); + + return EFI_SUCCESS; +} + +/** + Returns the current wakeup alarm clock setting. + + @param Enabled Indicates if the alarm is currently enable= d or disabled. + @param Pending Indicates if the alarm signal is pending a= nd requires acknowledgement. + @param Time The current alarm setting. + + @retval EFI_SUCCESS The alarm settings were returned. + @retval EFI_INVALID_PARAMETER Any parameter is NULL. + @retval EFI_DEVICE_ERROR The wakeup time could not be retrieved due= to a hardware error. + @retval EFI_UNSUPPORTED A wakeup timer is not supported on this + platform. + +**/ +EFI_STATUS +EFIAPI +LibGetWakeupTime ( + OUT BOOLEAN *Enabled, + OUT BOOLEAN *Pending, + OUT EFI_TIME *Time + ) +{ + // The DS1307 does not support setting the alarm + return EFI_UNSUPPORTED; +} + +/** + Sets the system wakeup alarm clock time. + + @param Enabled Enable or disable the wakeup alarm. + @param Time If Enable is TRUE, the time to set the wak= eup alarm for. + + @retval EFI_SUCCESS If Enable is TRUE, then the wakeup alarm w= as enabled. If + Enable is FALSE, then the wakeup alarm was= disabled. + @retval EFI_INVALID_PARAMETER A time field is out of range. + @retval EFI_DEVICE_ERROR The wakeup time could not be set due to a = hardware error. + @retval EFI_UNSUPPORTED A wakeup timer is not supported on this pl= atform. + +**/ +EFI_STATUS +EFIAPI +LibSetWakeupTime ( + IN BOOLEAN Enabled, + OUT EFI_TIME *Time + ) +{ + // The DS1307 does not support setting the alarm + return EFI_UNSUPPORTED; +} + +STATIC +VOID +I2cDriverRegistrationEvent ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + EFI_STATUS Status; + EFI_I2C_MASTER_PROTOCOL *I2cMaster; + UINTN BusFrequency; + + Status =3D gBS->LocateProtocol (&gEfiI2cMasterProtocolGuid, NULL, (VOID = **)&I2cMaster); + + gBS->CloseEvent (Event); + + ASSERT_EFI_ERROR (Status); + + Status =3D I2cMaster->Reset (I2cMaster); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: I2CMaster->Reset () failed - %r\n", + __FUNCTION__, Status)); + return; + } + + BusFrequency =3D FixedPcdGet16 (PcdI2cBusFrequency); + Status =3D I2cMaster->SetBusFrequency (I2cMaster, &BusFrequency); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: I2CMaster->SetBusFrequency () failed - %r\n", + __FUNCTION__, Status)); + return; + } + + mI2cMaster =3D I2cMaster; +} + +/** + This is the declaration of an EFI image entry point. This can be the ent= ry point to an application + written to this specification, an EFI boot service driver. + + @param ImageHandle Handle that identifies the loaded image. + @param SystemTable System Table for this image. + + @retval EFI_SUCCESS The operation completed successfully. + +**/ +EFI_STATUS +EFIAPI +LibRtcInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + // + // Register a protocol registration notification callback on the driver + // binding protocol so we can attempt to connect our I2C master to it + // as soon as it appears. + // + EfiCreateProtocolNotifyEvent ( + &gEfiI2cMasterProtocolGuid, + TPL_CALLBACK, + I2cDriverRegistrationEvent, + NULL, + &mDriverEventRegistration); + + return EFI_SUCCESS; +} diff --git a/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec b/Silicon/= Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec new file mode 100644 index 0000000..1aaf897 --- /dev/null +++ b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec @@ -0,0 +1,26 @@ +#/** @file +# +# Copyright 2017 NXP +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BS= D License +# which accompanies this distribution. The full text of the license may b= e found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. +# +#**/ + +[Defines] + DEC_SPECIFICATION =3D 0x0001001A + PACKAGE_NAME =3D Ds1307RtcLib + PACKAGE_GUID =3D 0c095cf6-834d-4fa2-a5a0-31ac35591ad2 + PACKAGE_VERSION =3D 0.1 + +[Guids] + gDs1307RtcLibTokenSpaceGuid =3D { 0xd939eb84, 0xa95a, 0x46a0, { 0xa8, 0x= 2b, 0xb9, 0x64, 0x30, 0xcf, 0xf5, 0x99 }} + +[PcdsFixedAtBuild] + gDs1307RtcLibTokenSpaceGuid.PcdI2cSlaveAddress|0|UINT8|0x00000001 + gDs1307RtcLibTokenSpaceGuid.PcdI2cBusFrequency|0|UINT32|0x00000002 diff --git a/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf b/Silicon/= Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf new file mode 100644 index 0000000..268873b --- /dev/null +++ b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf @@ -0,0 +1,45 @@ +# @Ds1307RtcLib.inf +# +# Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved. +# Copyright 2017 NXP +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may b= e found at +# http://opensource.org/licenses/bsd-license.php +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +# + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D Ds1307RtcLib + FILE_GUID =3D 7112fb46-8dda-4a41-ac40-bf212fedfc08 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D RealTimeClockLib + +[Sources.common] + Ds1307RtcLib.c + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec + +[LibraryClasses] + DebugLib + UefiBootServicesTableLib + UefiLib + +[Protocols] + gEfiDriverBindingProtocolGuid ## CONSUMES + gEfiI2cMasterProtocolGuid ## CONSUMES + +[FixedPcd] + gDs1307RtcLibTokenSpaceGuid.PcdI2cSlaveAddress + gDs1307RtcLibTokenSpaceGuid.PcdI2cBusFrequency + +[Depex] + gEfiI2cMasterProtocolGuid --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun May 5 06:05:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" From: Meenakshi Aggarwal Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Meenakshi Aggarwal Reviewed-by: Leif Lindholm --- .../Library/PlatformLib/ArmPlatformLib.c | 105 ++++++++++++++ .../Library/PlatformLib/ArmPlatformLib.inf | 67 +++++++++ .../Library/PlatformLib/NxpQoriqLsHelper.S | 38 ++++++ .../Library/PlatformLib/NxpQoriqLsMem.c | 152 +++++++++++++++++= ++++ 4 files changed, 362 insertions(+) create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatf= ormLib.c create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatf= ormLib.inf create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriq= LsHelper.S create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriq= LsMem.c diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.= c b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.c new file mode 100644 index 0000000..ab4815d --- /dev/null +++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.c @@ -0,0 +1,105 @@ +/** ArmPlatformLib.c +* +* Contains board initialization functions. +* +* Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoard.c +* +* Copyright (c) 2011-2012, ARM Limited. All rights reserved. +* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved. +* Copyright 2017 NXP +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the B= SD License +* which accompanies this distribution. The full text of the license may = be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#include +#include + +extern VOID SocInit (VOID); + +/** + Return the current Boot Mode + + This function returns the boot reason on the platform + +**/ +EFI_BOOT_MODE +ArmPlatformGetBootMode ( + VOID + ) +{ + return BOOT_WITH_FULL_CONFIGURATION; +} + +/** + Placeholder for Platform Initialization +**/ +EFI_STATUS +ArmPlatformInitialize ( + IN UINTN MpId + ) +{ + SocInit (); + + return EFI_SUCCESS; +} + +ARM_CORE_INFO LS1043aMpCoreInfoCTA53x4[] =3D { + { + // Cluster 0, Core 0 + 0x0, 0x0, + + // MP Core MailBox Set/Get/Clear Addresses and Clear Value + (EFI_PHYSICAL_ADDRESS)0, + (EFI_PHYSICAL_ADDRESS)0, + (EFI_PHYSICAL_ADDRESS)0, + (UINT64)0xFFFFFFFF + }, +}; + +EFI_STATUS +PrePeiCoreGetMpCoreInfo ( + OUT UINTN *CoreCount, + OUT ARM_CORE_INFO **ArmCoreTable + ) +{ + *CoreCount =3D sizeof (LS1043aMpCoreInfoCTA53x4) / sizeof (ARM_CORE_I= NFO); + *ArmCoreTable =3D LS1043aMpCoreInfoCTA53x4; + + return EFI_SUCCESS; +} + +ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi =3D { PrePeiCoreGetMpCoreInfo }; + +EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] =3D { + { + EFI_PEI_PPI_DESCRIPTOR_PPI, + &gArmMpCoreInfoPpiGuid, + &mMpCoreInfoPpi + } +}; + +VOID +ArmPlatformGetPlatformPpiList ( + OUT UINTN *PpiListSize, + OUT EFI_PEI_PPI_DESCRIPTOR **PpiList + ) +{ + *PpiListSize =3D sizeof (gPlatformPpiTable); + *PpiList =3D gPlatformPpiTable; +} + + +UINTN +ArmPlatformGetCorePosition ( + IN UINTN MpId + ) +{ + return 1; +} diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.= inf b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf new file mode 100644 index 0000000..7feac56 --- /dev/null +++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf @@ -0,0 +1,67 @@ +# @file +# +# Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved. +# Copyright 2017 NXP +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D PlatformLib + FILE_GUID =3D 736343a0-1d96-11e0-aaaa-0002a5d5c51b + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D ArmPlatformLib + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + Silicon/NXP/NxpQoriqLs.dec + +[LibraryClasses] + ArmLib + SocLib + +[Sources.common] + NxpQoriqLsHelper.S | GCC + NxpQoriqLsMem.c + ArmPlatformLib.c + +[Ppis] + gArmMpCoreInfoPpiGuid + +[FixedPcd] + gArmTokenSpaceGuid.PcdArmPrimaryCore + gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size + gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize + gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize + gNxpQoriqLsTokenSpaceGuid.PcdDram1BaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdDram1Size + gNxpQoriqLsTokenSpaceGuid.PcdDram2BaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdDram2Size + gNxpQoriqLsTokenSpaceGuid.PcdDram3BaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdDram3Size + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelpe= r.S b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S new file mode 100644 index 0000000..205c0d8 --- /dev/null +++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S @@ -0,0 +1,38 @@ +# @file +# +# Copyright (c) 2012-2013, ARM Limited. All rights reserved. +# Copyright 2017 NXP +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +# + +#include +#include + +.text +.align 2 + +GCC_ASM_IMPORT(ArmReadMpidr) + +ASM_FUNC(ArmPlatformIsPrimaryCore) + tst x0, #3 + cset x0, eq + ret + +ASM_FUNC(ArmPlatformPeiBootAction) +EL1_OR_EL2(x0) +1: +2: + ret + +ASM_FUNC(ArmPlatformGetPrimaryCoreMpId) + MOV32 (x0, FixedPcdGet32(PcdArmPrimaryCore)) + ldrh w0, [x0] + ret diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c= b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c new file mode 100644 index 0000000..64c5612 --- /dev/null +++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c @@ -0,0 +1,152 @@ +/** NxpQoriqLsMem.c +* +* Board memory specific Library. +* +* Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoardMem.c +* +* Copyright (c) 2011, ARM Limited. All rights reserved. +* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved. +* Copyright 2017 NXP +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the B= SD License +* which accompanies this distribution. The full text of the license may b= e found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#include +#include +#include +#include + +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 25 + +/** + Return the Virtual Memory Map of your platform + + This Virtual Memory Map is used by MemoryInitPei Module to initialize th= e MMU on your platform. + + @param VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR descr= ibing a Physical-to- + Virtual Memory mapping. This array must be = ended by a zero-filled + entry + +**/ + +VOID +ArmPlatformGetVirtualMemoryMap ( + IN ARM_MEMORY_REGION_DESCRIPTOR **VirtualMemoryMap + ) +{ + UINTN Index; + ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; + + Index =3D 0; + + ASSERT (VirtualMemoryMap !=3D NULL); + + VirtualMemoryTable =3D (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages ( + EFI_SIZE_TO_PAGES (sizeof (ARM_MEMORY_REGION_DESCRIPTOR) * MAX_V= IRTUAL_MEMORY_MAP_DESCRIPTORS)); + + if (VirtualMemoryTable =3D=3D NULL) { + return; + } + + // DRAM1 (Must be 1st entry) + VirtualMemoryTable[Index].PhysicalBase =3D FixedPcdGet64 (PcdDram1BaseAd= dr); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdDram1BaseAd= dr); + VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdDram1Size); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_W= RITE_BACK; + + // CCSR Space + VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdCcsrBaseA= ddr); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdCcsrBaseAdd= r); + VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdCcsrSize); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + // IFC region 1 + // + // A-009241 : Unaligned write transactions to IFC may result in corrup= tion of data + // Affects : IFC + // Description: 16 byte unaligned write from system bus to IFC may resul= t in extra unintended + // writes on external IFC interface that can corrupt data o= n external flash. + // Impact : Data corruption on external flash may happen in case of = unaligned writes to + // IFC memory space. + // Workaround: Following are the workarounds: + // For write transactions from core, IFC interface memories = (including IFC SRAM) + // should be configured as device type memory in MMU. + // For write transactions from non-core masters (like system= DMA), the address + // should be 16 byte aligned and the data size should be = multiple of 16 bytes. + // + VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdIfcRegion= 1BaseAddr); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdIfcRegion1B= aseAddr); + VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdIfcRegion1S= ize); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + // QMAN SWP + VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdQmanSwpBa= seAddr); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdQmanSwpBase= Addr); + VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdQmanSwpSize= ); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_U= NCACHED_UNBUFFERED; + + // BMAN SWP + VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdBmanSwpBa= seAddr); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdBmanSwpBase= Addr); + VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdBmanSwpSize= ); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_U= NCACHED_UNBUFFERED; + + // IFC region 2 + VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdIfcRegion= 2BaseAddr); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdIfcRegion2B= aseAddr); + VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdIfcRegion2S= ize); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + // DRAM2 + VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdDram2Base= Addr); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdDram2BaseAd= dr); + VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdDram2Size); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_W= RITE_BACK; + + // PCIe1 + VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdPciExp1Ba= seAddr); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdPciExp1Base= Addr); + VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdPciExp1Base= Size); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + // PCIe2 + VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdPciExp2Ba= seAddr); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdPciExp2Base= Addr); + VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdPciExp2Base= Size); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + // PCIe3 + VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdPciExp3Ba= seAddr); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdPciExp3Base= Addr); + VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdPciExp3Base= Size); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + // DRAM3 + VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdDram3Base= Addr); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdDram3BaseAd= dr); + VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdDram3Size); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_W= RITE_BACK; + + // QSPI region + VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdQspiRegio= nBaseAddr); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdQspiRegionB= aseAddr); + VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdQspiRegionS= ize); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_U= NCACHED_UNBUFFERED; + + // End of Table + VirtualMemoryTable[++Index].PhysicalBase =3D 0; + VirtualMemoryTable[Index].VirtualBase =3D 0; + VirtualMemoryTable[Index].Length =3D 0; + VirtualMemoryTable[Index].Attributes =3D (ARM_MEMORY_REGION_ATTRIBUTES= )0; + + ASSERT ((Index + 1) <=3D MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS); + + *VirtualMemoryMap =3D VirtualMemoryTable; +} --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun May 5 06:05:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; 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VI1PR04MB1008; 6:fOJZCmqcoxgwmRkf7Ef0RBM0y64xiNCkO+mnGEn6DKZ/DS0adH9wWvz2D1LRXu5HPV/mDtrAir00hAV2HLqRq1NS+IKwfsiZRHKPPS4ySUBK8Hi4vMug9DxGgDnWZ1vjlnE7HsDQA4SkGerWNSmMKfsn/sPQVNk/tMDPDIIgAH9UTsxZ4oOktHPuc/t4xG4AWaWo3YRWapx2CBhXCoTTsrzFrUrsV4TFiYe9Y+YbLrxorjewtBLlMymeG2eoueOI+iV6VEQJZ9PiXTc5rC80B7v/7LP230U8Gk/BFT1c4Kx04wX0PpKl51LcSE3Rhe9XeRbQcKD1Vhly1epDTaQu4kZrNvo1RaSFfdU7YDEsuDs=; 5:kiW3u9HTR7DWqMotbOAwZB2/oUhOH7nauJaW6a/Kq1R1fezzUAd4mjJ4rdZSZpnCHo7Khu2EimfTyNFtgaTRMCuOW7m9iqPRt0gIT8kasCn3nMxb5qldFE1cZ4dpiLxnNKU87YjG+N+G50Wk8YngZPJNYS+0WyAs0rlDr1Zadl0=; 24:9aF/JQlwWvumqiaZih64vuFT1BbtifLssvUvSFDm0I8TTKq8Q5eox9I74+bTiXDZBvYaKsribDTzEt/7LSi9QCZXXquqd+BU81z9FZvy3/A=; 7:p5bmQaGYdJVwgjsT5DOz9+ttOsEm/JNkWFAmyuAdxN4SHpTcFw7j9HX1+02OEvTBVgqWNuoJO2svY4oJjWU4i+JhqyfTtLtIKQPAhP15WIZfz2nJHgC5ai3mFPnUt3YqilimK0Ffqs91hUDesvafqbgCg+4RAlKCALuG7UT6fErhcRMl7LwREogctQiTfxdVZuP/L0FXCl5D513lynL8cba8Zn4FDHmrP+VAayc4I/3OT25XY2cAf1eRkuD9g636 SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Feb 2018 08:52:57.3579 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f4bddc32-abaa-44cc-bfbf-08d5751aaeb8 X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB1008 Subject: [edk2] [PATCH edk2-platforms 08/39] Compilation : Add the fdf, dsc and dec files. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Meenakshi Aggarwal The firmware device, description and declaration files. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Meenakshi Aggarwal --- Platform/NXP/FVRules.fdf.inc | 99 +++++++ Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec | 29 ++ Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 84 ++++++ Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 197 +++++++++++++ Platform/NXP/NxpQoriqLs.dsc | 412 +++++++++++++++++++++++= ++++ Silicon/NXP/LS1043A/LS1043A.dec | 22 ++ Silicon/NXP/LS1043A/LS1043A.dsc | 73 +++++ Silicon/NXP/NxpQoriqLs.dec | 117 ++++++++ 8 files changed, 1033 insertions(+) create mode 100644 Platform/NXP/FVRules.fdf.inc create mode 100644 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec create mode 100644 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc create mode 100644 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf create mode 100644 Platform/NXP/NxpQoriqLs.dsc create mode 100644 Silicon/NXP/LS1043A/LS1043A.dec create mode 100644 Silicon/NXP/LS1043A/LS1043A.dsc create mode 100644 Silicon/NXP/NxpQoriqLs.dec diff --git a/Platform/NXP/FVRules.fdf.inc b/Platform/NXP/FVRules.fdf.inc new file mode 100644 index 0000000..d0e17cb --- /dev/null +++ b/Platform/NXP/FVRules.fdf.inc @@ -0,0 +1,99 @@ +# FvRules.fdf.inc +# +# Rules for creating FD. +# +# Copyright 2017 NXP +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may b= e found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# + +##########################################################################= ###### +# +# Rules are use with the [FV] section's module INF type to define +# how an FFS file is created for a given INF file. The following Rule are = the default +# rules for the different module type. User can add the customized rules t= o define the +# content of the FFS file. +# +##########################################################################= ###### + +[Rule.Common.SEC] + FILE SEC =3D $(NAMED_GUID) RELOCS_STRIPPED { + TE TE Align =3D 32 $(INF_OUTPUT)/$(MODULE_NAME).efi + } + +[Rule.Common.PEI_CORE] + FILE PEI_CORE =3D $(NAMED_GUID) { + TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING =3D"$(MODULE_NAME)" Optional + } + +[Rule.Common.PEIM] + FILE PEIM =3D $(NAMED_GUID) { + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + } + +[Rule.Common.PEIM.TIANOCOMPRESSED] + FILE PEIM =3D $(NAMED_GUID) DEBUG_MYTOOLS_IA32 { + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED =3D TR= UE { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + } + } + +[Rule.Common.DXE_CORE] + FILE DXE_CORE =3D $(NAMED_GUID) { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + } + + +[Rule.Common.UEFI_DRIVER] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NA= ME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + } + +[Rule.Common.DXE_DRIVER] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NA= ME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + } + +[Rule.Common.DXE_RUNTIME_DRIVER] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NA= ME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + } + +[Rule.Common.UEFI_APPLICATION] + FILE APPLICATION =3D $(NAMED_GUID) { + UI STRING =3D"$(MODULE_NAME)" Optional + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + } + +[Rule.Common.UEFI_DRIVER.BINARY] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional |.depex + PE32 PE32 |.efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R) + } + +[Rule.Common.UEFI_APPLICATION.BINARY] + FILE APPLICATION =3D $(NAMED_GUID) { + PE32 PE32 |.efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R) + } diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec b/Platform/NXP/LS= 1043aRdbPkg/LS1043aRdbPkg.dec new file mode 100644 index 0000000..1b639e2 --- /dev/null +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec @@ -0,0 +1,29 @@ +# LS1043aRdbPkg.dec +# LS1043a board package. +# +# Copyright 2017 NXP +# +# This program and the accompanying materials are licensed and made avail= able under +# the terms and conditions of the BSD License which accompanies this dist= ribution. +# The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# + +[Defines] + PACKAGE_NAME =3D LS1043aRdbPkg + PACKAGE_GUID =3D 6eba6648-d853-4eb3-9761-528b82d5ab04 + +##########################################################################= ###### +# +# Include Section - list of Include Paths that are provided by this packag= e. +# Comments are used for Keywords and Module Types. +# +# Supported Module Types: +# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_D= RIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION +# +##########################################################################= ###### +[Includes.common] + Include # Root include for the package diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS= 1043aRdbPkg/LS1043aRdbPkg.dsc new file mode 100644 index 0000000..6e9e7e0 --- /dev/null +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc @@ -0,0 +1,84 @@ +# LS1043aRdbPkg.dsc +# +# LS1043ARDB Board package. +# +# Copyright 2017 NXP +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may b= e found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# + +##########################################################################= ###### +# +# Defines Section - statements that will be processed to create a Makefile. +# +##########################################################################= ###### +[Defines] + # + # Defines for default states. These can be changed on the command line. + # -D FLAG=3DVALUE + # + PLATFORM_NAME =3D LS1043aRdbPkg + PLATFORM_GUID =3D 60169ec4-d2b4-44f8-825e-f8684fd42e4f + OUTPUT_DIRECTORY =3D Build/LS1043aRdbPkg + FLASH_DEFINITION =3D Platform/NXP/LS1043aRdbPkg/LS1043aRdb= Pkg.fdf + +!include ../NxpQoriqLs.dsc +!include ../../../Silicon/NXP/LS1043A/LS1043A.dsc + +[LibraryClasses.common] + ArmPlatformLib|Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatfor= mLib.inf + ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSy= stemLib.inf + SerialPortLib|Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf + BeIoLib|Silicon/NXP/Library/BeIoLib/BeIoLib.inf + SocLib|Silicon/NXP/Chassis/LS1043aSocLib.inf + RealTimeClockLib|Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf + +[PcdsFixedAtBuild.common] + + # + # LS1043a board Specific PCDs + # XX (DRAM - Region 1 2GB) + # (NOR - IFC Region 1 512MB) + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000 + gArmTokenSpaceGuid.PcdSystemMemorySize|0x80000000 + gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x02000000 + + # + # Board Specific Pcds + # + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500 + gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE + gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x1 + + # + # I2C controller Pcds + # + gNxpQoriqLsTokenSpaceGuid.PcdI2cBus|0 + + # + # RTC Pcds + # + gDs1307RtcLibTokenSpaceGuid.PcdI2cSlaveAddress|0x68 + gDs1307RtcLibTokenSpaceGuid.PcdI2cBusFrequency|100000 + +##########################################################################= ###### +# +# Components Section - list of all EDK II Modules needed by this Platform +# +##########################################################################= ###### +[Components.common] + # + # Architectural Protocols + # + MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf + + Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf + Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf + + ## diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf b/Platform/NXP/LS= 1043aRdbPkg/LS1043aRdbPkg.fdf new file mode 100644 index 0000000..fa6510c --- /dev/null +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf @@ -0,0 +1,197 @@ +# LS1043aRdbPkg.fdf +# +# FLASH layout file for LS1043a board. +# +# Copyright (c) 2016, Freescale Ltd. All rights reserved. +# Copyright 2017 NXP +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may b= e found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# + +##########################################################################= ###### +# +# FD Section +# The [FD] Section is made up of the definition statements and a +# description of what goes into the Flash Device Image. Each FD section +# defines one flash "device" image. A flash device image may be one of +# the following: Removable media bootable image (like a boot floppy +# image,) an Option ROM image (that would be "flashed" into an add-in +# card,) a System "Flash" image (that would be burned into a system's +# flash) or an Update ("Capsule") image that will be used to update and +# existing system flash. +# +##########################################################################= ###### + +[FD.LS1043ARDB_EFI] +BaseAddress =3D 0x82000000|gArmTokenSpaceGuid.PcdFdBaseAddress #The bas= e address of the FLASH Device. +Size =3D 0x000EC890|gArmTokenSpaceGuid.PcdFdSize #The siz= e in bytes of the FLASH Device +ErasePolarity =3D 1 +BlockSize =3D 0x1 +NumBlocks =3D 0xEC890 + +##########################################################################= ###### +# +# Following are lists of FD Region layout which correspond to the location= s of different +# images within the flash device. +# +# Regions must be defined in ascending order and may not overlap. +# +# A Layout Region start with a eight digit hex offset (leading "0x" requir= ed) followed by +# the pipe "|" character, followed by the size of the region, also in hex = with the leading +# "0x" characters. Like: +# Offset|Size +# PcdOffsetCName|PcdSizeCName +# RegionType +# +##########################################################################= ###### +0x00000000|0x000EC890 +gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize +FV =3D FVMAIN_COMPACT + +!include ../FVRules.fdf.inc +##########################################################################= ###### +# +# FV Section +# +# [FV] section is used to define what components or modules are placed wit= hin a flash +# device file. This section also defines order the components and modules= are positioned +# within the image. The [FV] section consists of define statements, set s= tatements and +# module statements. +# +##########################################################################= ###### + +[FV.FvMain] +FvNameGuid =3D 1037c42b-8452-4c41-aac7-41e6c31468da +BlockSize =3D 0x1 +NumBlocks =3D 0 # This FV gets compressed so make it just= big enough +FvAlignment =3D 8 # FV alignment and FV attributes setting. +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE + + INF MdeModulePkg/Core/Dxe/DxeMain.inf + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + + # + # PI DXE Drivers producing Architectural Protocols (EFI Services) + # + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf + + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf + INF Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf + INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.= inf + INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.i= nf + + INF Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf + + INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + + # + # Multiple Console IO support + # + INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe= .inf + INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + + INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf + + # + # Network modules + # + INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf + INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf + INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf + INF MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf + INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf + INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf + INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf + INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf + INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf + INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf + INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf +!if $(NETWORK_IP6_ENABLE) =3D=3D TRUE + INF NetworkPkg/Ip6Dxe/Ip6Dxe.inf + INF NetworkPkg/TcpDxe/TcpDxe.inf + INF NetworkPkg/Udp6Dxe/Udp6Dxe.inf + INF NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf + INF NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf + INF NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf +!else + INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf +!endif + + # + # FAT filesystem + GPT/MBR partitioning + # + INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.i= nf + INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + INF FatPkg/FatPei/FatPei.inf + INF FatPkg/EnhancedFatDxe/Fat.inf + + # + # UEFI application (Shell Embedded Boot Loader) + # + INF ShellPkg/Application/Shell/Shell.inf + + # + # Bds + # + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + INF MdeModulePkg/Application/UiApp/UiApp.inf + +[FV.FVMAIN_COMPACT] +FvAlignment =3D 8 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE + + INF ArmPlatformPkg/PrePi/PeiUniCore.inf + + FILE FV_IMAGE =3D 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRE= D =3D TRUE { + SECTION FV_IMAGE =3D FVMAIN + } + } diff --git a/Platform/NXP/NxpQoriqLs.dsc b/Platform/NXP/NxpQoriqLs.dsc new file mode 100644 index 0000000..5987cd6 --- /dev/null +++ b/Platform/NXP/NxpQoriqLs.dsc @@ -0,0 +1,412 @@ +# @file +# +# Copyright 2017 NXP. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may b= e found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +# + +##########################################################################= ###### +# +# Defines Section - statements that will be processed to create a Makefile. +# +##########################################################################= ###### +[Defines] + # + # Defines for default states. These can be changed on the command line. + # -D FLAG=3DVALUE + # + PLATFORM_VERSION =3D 0.1 + DSC_SPECIFICATION =3D 0x00010005 + SUPPORTED_ARCHITECTURES =3D AARCH64 + BUILD_TARGETS =3D DEBUG|RELEASE + SKUID_IDENTIFIER =3D DEFAULT + +[LibraryClasses.common] + ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf + ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf + ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf + ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/Ar= mGenericTimerPhyCounterLib.inf + TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf + ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatfo= rmStackLib.inf + HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf + UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServic= esLib.inf + FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf + BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf + PlatformBootManagerLib|ArmPkg/Library/PlatformBootManagerLib/PlatformBoo= tManagerLib.inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManag= erLib.inf + CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/Customize= dDisplayLib.inf + + # Networking Requirements + NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf + DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf + UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf + IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf + + # ARM GIC400 General Interrupt Driver + ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf + ArmGicArchLib|ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf + DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseD= ebugPrintErrorLevelLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf + BaseLib|MdePkg/Library/BaseLib/BaseLib.inf + SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchroniza= tionLib.inf + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibN= ull.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeC= offGetEntryPointLib.inf + PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCof= fExtraActionLib.inf + CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMainte= nanceLib.inf + DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/Def= aultExceptionHandlerLib.inf + CpuExceptionHandlerLib|ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf + PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf + SemihostLib|ArmPkg/Library/SemihostLib/SemihostLib.inf + IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf + UefiLib|MdePkg/Library/UefiLib/UefiLib.inf + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/U= efiRuntimeServicesTableLib.inf + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBoo= tServicesTableLib.inf + DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableL= ib.inf + UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntry= Point.inf + UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiA= pplicationEntryPoint.inf + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf + CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf + ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.= inf + DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.i= nf + DmaLib|EmbeddedPkg/Library/NonCoherentDmaLib/NonCoherentDmaLib.inf + FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf + ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib= .inf + FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf + ShellCEntryLib|ShellPkg/Library/UefiShellCEntryLib/UefiShellCEntryLib.inf + SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf + NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf + HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsing= Lib.inf + BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCom= mandLib.inf + TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurem= entLibNull.inf + AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLib= Null.inf + VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf + NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf + +[LibraryClasses.common.SEC] + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + ReportStatusCodeLib|IntelFrameworkModulePkg/Library/PeiDxeDebugLibReport= StatusCode/PeiDxeDebugLibReportStatusCode.inf + UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompres= sLib.inf + ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib= /PrePiExtractGuidedSectionLib.inf + LzmaDecompressLib|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLi= b/LzmaCustomDecompressLib.inf + PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf + HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf + PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/Pre= PiHobListPointerLib.inf + MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMe= moryAllocationLib.inf + PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.= inf + PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf + MemoryInitPeiLib|ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.inf + + # 1/123 faster than Stm or Vstm version + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + + # Uncomment to turn on GDB stub in SEC. + #DebugAgentLib|EmbeddedPkg/Library/GdbDebugAgent/GdbDebugAgent.inf + +[LibraryClasses.common.PEIM] + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf + PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf + PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLib/Pei= ServicesTablePointerLib.inf + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAlloc= ationLib.inf + +[LibraryClasses.common.DXE_CORE] + HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf + MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeC= oreMemoryAllocationLib.inf + DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf + ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeL= ibFramework/DxeReportStatusCodeLib.inf + ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExt= ractGuidedSectionLib.inf + UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompres= sLib.inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerform= anceLib.inf + +[LibraryClasses.common.DXE_DRIVER] + ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeL= ibFramework/DxeReportStatusCodeLib.inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeS= ecurityManagementLib.inf + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.= inf + MemoryInitPeiLib|ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.inf + +[LibraryClasses.common.UEFI_APPLICATION] + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeL= ibFramework/DxeReportStatusCodeLib.inf + UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDec= ompressLib/BaseUefiTianoCustomDecompressLib.inf + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.= inf + +[LibraryClasses.common.UEFI_DRIVER] + ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeL= ibFramework/DxeReportStatusCodeLib.inf + UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDec= ompressLib/BaseUefiTianoCustomDecompressLib.inf + ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExt= ractGuidedSectionLib.inf + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.= inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + +[LibraryClasses.common.DXE_RUNTIME_DRIVER] + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf + ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeL= ibFramework/DxeReportStatusCodeLib.inf + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf + +[LibraryClasses.AARCH64] + # + # It is not possible to prevent the ARM compiler for generic intrinsic f= unctions. + # This library provides the instrinsic functions generate by a given com= piler. + # [LibraryClasses.ARM] and NULL mean link this library into all ARM imag= es. + # + NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf + +[BuildOptions] + XCODE:*_*_ARM_PLATFORM_FLAGS =3D=3D -arch armv7 + GCC:*_*_ARM_PLATFORM_FLAGS =3D=3D -march=3Darmv7-a + RVCT:*_*_ARM_PLATFORM_FLAGS =3D=3D --cpu cortex-a9 + +[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER] + GCC:*_*_ARM_DLINK_FLAGS =3D -z common-page-size=3D0x1000 + GCC:*_*_AARCH64_DLINK_FLAGS =3D -z common-page-size=3D0x10000 + +##########################################################################= ###### +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +##########################################################################= ###### + +[PcdsFeatureFlag.common] + ## If TRUE, Graphics Output Protocol will be installed on virtual handle= created by ConsplitterDxe. + # It could be set FALSE to save size. + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE + gEfiMdePkgTokenSpaceGuid.PcdComponentNameDisable|TRUE + gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnosticsDisable|TRUE + gEfiMdePkgTokenSpaceGuid.PcdComponentName2Disable|TRUE + gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnostics2Disable|TRUE + + # Use the Vector Table location in CpuDxe. We will not copy the Vector T= able at PcdCpuVectorBaseAddress + gArmTokenSpaceGuid.PcdRelocateVectorTable|FALSE + gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob|TRUE + gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE + +[PcdsDynamicDefault.common] + # + # Set video resolution for boot options and for text setup. + # PlatformDxe can set the former at runtime. + # + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|800 + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|600 + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|640 + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|480 + +[PcdsDynamicHii.common.DEFAULT] + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVar= iableGuid|0x0|10 + +[PcdsFixedAtBuild.common] + gEmbeddedTokenSpaceGuid.PcdMetronomeTickPeriod|1000 + gEmbeddedTokenSpaceGuid.PcdTimerPeriod|10000 # expressed in 100ns units,= 100,000 x 100 ns =3D 10,000,000 ns =3D 10 ms + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxAuthVariableSize|0x2800 + gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FAL= SE + gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c= , 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0= x31 } + gArmPlatformTokenSpaceGuid.PcdCoreCount|1 # Only one core + gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000 + gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|2000000 + gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000 + gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000 + gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF + gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|1 + gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0 + gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320 + +!if $(TARGET) =3D=3D RELEASE + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x27 + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x81000000 +!else + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x81000044 +!endif + + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 + + # + # Optional feature to help prevent EFI memory map fragments + # Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob + # Values are in EFI Pages (4K). DXE Core will make sure that + # at least this much of each type of memory can be allocated + # from a single memory range. This way you only end up with + # maximum of two fragements for each type in the memory map + # (the memory used, and the free memory that was prereserved + # but not used). + # + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|80 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|40 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|400 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|3000 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|10 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0 + + # Serial Terminal + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200 + gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4 + + # Size of the region reserved for fixed address allocations (Reserved 32= MB) + gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset|0x08000000 + gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment|0x0 + gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0x94A00000 + gArmTokenSpaceGuid.PcdCpuResetAddress|0x94A00000 + + # Timer + gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0 + + # We want to use the Shell Libraries but don't want it to initialise + # automatically. We initialise the libraries when the command is called = by the + # Shell. + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + + # Use the serial console for both ConIn & ConOut + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|16000 +!ifdef $(NO_SHELL_PROFILES) + gEfiShellPkgTokenSpaceGuid.PcdShellProfileMask|0x00 +!endif #$(NO_SHELL_PROFILES) + +##########################################################################= ###### +# +# Components Section - list of all EDK II Modules needed by this Platform +# +##########################################################################= ###### +[Components.common] + # + # SEC + # + ArmPlatformPkg/PrePi/PeiUniCore.inf + MdeModulePkg/Universal/PCD/Pei/Pcd.inf { + + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + } + + # + # DXE + # + MdeModulePkg/Core/Dxe/DxeMain.inf { + + NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32Gu= idedSectionExtractLib.inf + } + MdeModulePkg/Universal/PCD/Dxe/Pcd.inf { + + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + } + + # + # Architectural Protocols + # + ArmPkg/Drivers/CpuDxe/CpuDxe.inf + MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf + EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf + + # FDT installation + MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf + MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf + EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + ArmPkg/Drivers/TimerDxe/TimerDxe.inf + ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf + + # + # Networking stack + # + MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf + MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf + MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf + MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf + MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf + MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf + MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf + MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf + MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf + MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf + MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf +!if $(NETWORK_IP6_ENABLE) =3D=3D TRUE + NetworkPkg/Ip6Dxe/Ip6Dxe.inf + NetworkPkg/TcpDxe/TcpDxe.inf + NetworkPkg/Udp6Dxe/Udp6Dxe.inf + NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf + NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf + NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf +!else + MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf +!endif + + # + # FAT filesystem + GPT/MBR partitioning + # + MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + FatPkg/FatPei/FatPei.inf + FatPkg/EnhancedFatDxe/Fat.inf + + # + # Bds + # + MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + MdeModulePkg/Application/UiApp/UiApp.inf { + + NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf + NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf + NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanc= eManagerUiLib.inf + } + MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + + # + # Example Application + # + MdeModulePkg/Application/HelloWorld/HelloWorld.inf + ShellPkg/Library/UefiShellLib/UefiShellLib.inf + ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf + ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.i= nf + ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf + ShellPkg/Application/Shell/Shell.inf { + + NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2Comm= andsLib.inf + NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1Comm= andsLib.inf + NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3Comm= andsLib.inf +!ifndef $(NO_SHELL_PROFILES) + NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1Co= mmandsLib.inf + NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1= CommandsLib.inf + NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1Comm= andsLib.inf + NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1= CommandsLib.inf +!endif #$(NO_SHELL_PROFILES) + } + + ## diff --git a/Silicon/NXP/LS1043A/LS1043A.dec b/Silicon/NXP/LS1043A/LS1043A.= dec new file mode 100644 index 0000000..f14edb2 --- /dev/null +++ b/Silicon/NXP/LS1043A/LS1043A.dec @@ -0,0 +1,22 @@ +# LS1043A.dec +# +# Copyright 2017 NXP +# +# This program and the accompanying materials are licensed and made availa= ble under +# the terms and conditions of the BSD License which accompanies this distr= ibution. +# The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. +# +# + +[Defines] + DEC_SPECIFICATION =3D 0x00010005 + +[Guids.common] + gNxpLs1043ATokenSpaceGuid =3D {0x6834fe45, 0x4aee, 0x4fc6, {0xbc, 0= xb5, 0xff, 0x45, 0xb7, 0xa8, 0x71, 0xf2}} + +[Includes] + Include diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc b/Silicon/NXP/LS1043A/LS1043A.= dsc new file mode 100644 index 0000000..8395dfd --- /dev/null +++ b/Silicon/NXP/LS1043A/LS1043A.dsc @@ -0,0 +1,73 @@ +# LS1043A.dsc +# LS1043A Soc package. +# +# Copyright 2017 NXP +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may b= e found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +# + +##########################################################################= ###### +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +##########################################################################= ###### +[PcdsDynamicDefault.common] + + # + # ARM General Interrupt Controller + gArmTokenSpaceGuid.PcdGicDistributorBase|0x01401000 + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x01402000 + +[PcdsFixedAtBuild.common] + + # + # CCSR Address Space and other attached Memories + # + gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x01000000 + gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0F000000 + gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr|0x01EE1000 + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr|0x60000000 + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size|0x20000000 + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr|0x0620000000 + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size|0x00E0000000 + gNxpQoriqLsTokenSpaceGuid.PcdIfcNandReservedSize|0x2EA + gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr|0x0500000000 + gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize|0x0080000000 + gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr|0x0508000000 + gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize|0x0080000000 + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr|0x4000000000 + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize|0x800000000 + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr|0x4800000000 + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize|0x800000000 + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr|0x5000000000 + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize|0x800000000 + gNxpQoriqLsTokenSpaceGuid.PcdDram1BaseAddr|0x0080000000 + gNxpQoriqLsTokenSpaceGuid.PcdDram1Size|0x0080000000 + gNxpQoriqLsTokenSpaceGuid.PcdDram2BaseAddr|0x0880000000 + gNxpQoriqLsTokenSpaceGuid.PcdDram2Size|0x0780000000 + gNxpQoriqLsTokenSpaceGuid.PcdDram3BaseAddr|0x8800000000 + gNxpQoriqLsTokenSpaceGuid.PcdDram3Size|0x7800000000 + gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr|0x1570000 + gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr|0x01EE0000 + gNxpQoriqLsTokenSpaceGuid.PcdWdog1BaseAddr|0x02AD0000 + gNxpQoriqLsTokenSpaceGuid.PcdSdxcBaseAddr|0x01560000 + gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr|0x02180000 + gNxpQoriqLsTokenSpaceGuid.PcdI2cSize|0x10000 + gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|4 + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x40000000 + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x20000000 + + # + # Big Endian IPs + # + gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|TRUE + gNxpQoriqLsTokenSpaceGuid.PcdWdogBigEndian|TRUE + +## diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec new file mode 100644 index 0000000..a73e9d5 --- /dev/null +++ b/Silicon/NXP/NxpQoriqLs.dec @@ -0,0 +1,117 @@ +# @file. +# +# Copyright 2017 NXP +# +# This program and the accompanying materials are licensed and made avail= able under +# the terms and conditions of the BSD License which accompanies this dist= ribution. +# The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +# + +[Defines] + DEC_SPECIFICATION =3D 0x00010005 + PACKAGE_VERSION =3D 0.1 + +[Includes] + . + Include + +[Guids.common] + gNxpQoriqLsTokenSpaceGuid =3D {0x98657342, 0x4aee, 0x4fc6, {0xbc, 0= xb5, 0xff, 0x45, 0xb7, 0xa8, 0x71, 0xf2}} + +[PcdsFixedAtBuild.common] + # + # Pcds for I2C Controller + # + gNxpQoriqLsTokenSpaceGuid.PcdI2cBus|0|UINT32|0x00000001 + gNxpQoriqLsTokenSpaceGuid.PcdI2cSpeed|0|UINT32|0x00000002 + gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|0|UINT32|0x00000003 + + # + # Pcds for base address and size + # + gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr|0x0|UINT64|0x00000100 + gNxpQoriqLsTokenSpaceGuid.PcdPiFdSize|0x0|UINT32|0x00000101 + gNxpQoriqLsTokenSpaceGuid.PcdPiFdBaseAddress|0x0|UINT64|0x00000102 + gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr|0x0|UINT64|0x00000103 + gNxpQoriqLsTokenSpaceGuid.PcdWdog1BaseAddr|0x0|UINT64|0x00000104 + gNxpQoriqLsTokenSpaceGuid.PcdDdrBaseAddr|0x0|UINT64|0x00000105 + gNxpQoriqLsTokenSpaceGuid.PcdSdxcBaseAddr|0x0|UINT64|0x00000106 + gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr|0x0|UINT64|0x00000107 + gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr|0x0|UINT64|0x00000108 + gNxpQoriqLsTokenSpaceGuid.PcdI2cSize|0x0|UINT32|0x00000109 + gNxpQoriqLsTokenSpaceGuid.PcdDcsrBaseAddr|0x0|UINT64|0x0000010A + gNxpQoriqLsTokenSpaceGuid.PcdDcsrSize|0x0|UINT64|0x0000010B + gNxpQoriqLsTokenSpaceGuid.PcdSataBaseAddr|0x0|UINT32|0x0000010C + gNxpQoriqLsTokenSpaceGuid.PcdSataSize|0x0|UINT32|0x0000010D + gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr|0x0|UINT64|0x0000010E + gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize|0x0|UINT64|0x0000010F + gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr|0x0|UINT64|0x00000110 + gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize|0x0|UINT64|0x00000111 + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr|0x0|UINT64|0x00000112 + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize|0x0|UINT64|0x00000113 + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr|0x0|UINT64|0x00000114 + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize|0x0|UINT64|0x00000115 + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr|0x0|UINT64|0x00000116 + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize|0x0|UINT64|0x00000117 + gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseAddr|0x0|UINT64|0x0000118 + gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseSize|0x0|UINT64|0x0000119 + gNxpQoriqLsTokenSpaceGuid.PcdDram1BaseAddr|0x0|UINT64|0x0000011A + gNxpQoriqLsTokenSpaceGuid.PcdDram1Size|0x0|UINT64|0x0000011B + gNxpQoriqLsTokenSpaceGuid.PcdDram2BaseAddr|0x0|UINT64|0x0000011C + gNxpQoriqLsTokenSpaceGuid.PcdDram2Size|0x0|UINT64|0x0000011D + gNxpQoriqLsTokenSpaceGuid.PcdDram3BaseAddr|0x0|UINT64|0x0000011E + gNxpQoriqLsTokenSpaceGuid.PcdDram3Size|0x0|UINT64|0x0000011F + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x0|UINT64|0x00000120 + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x0|UINT64|0x00000121 + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2BaseAddr|0x0|UINT64|0x00000122 + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2Size|0x0|UINT64|0x00000123 + gNxpQoriqLsTokenSpaceGuid.PcdSystemMemoryExBase|0x0|UINT64|0x00000124 + gNxpQoriqLsTokenSpaceGuid.PcdSystemMemoryExSize|0x0|UINT64|0x00000125 + gNxpQoriqLsTokenSpaceGuid.PcdUsbBaseAddr|0x0|UINT32|0x00000126 + gNxpQoriqLsTokenSpaceGuid.PcdUsbSize|0x0|UINT32|0x00000127 + gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x0|UINT64|0x00000128 + gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0|UINT64|0x00000129 + gNxpQoriqLsTokenSpaceGuid.PcdDramMemSize|0x0|UINT64|0x0000012A + + # + # IFC PCDs + # + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr|0x0|UINT64|0x00000190 + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size|0x0|UINT64|0x00000191 + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr|0x0|UINT64|0x00000192 + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size|0x0|UINT64|0x00000193 + gNxpQoriqLsTokenSpaceGuid.PcdIfcNandReservedSize|0x0|UINT32|0x00000194 + gNxpQoriqLsTokenSpaceGuid.PcdFlashDeviceBase64|0x0|UINT64|0x00000195 + gNxpQoriqLsTokenSpaceGuid.PcdFlashReservedRegionBase64|0x0|UINT64|0x0000= 0196 + + # + # NV Pcd + # + gNxpQoriqLsTokenSpaceGuid.PcdNvFdBase|0x0|UINT64|0x00000210 + gNxpQoriqLsTokenSpaceGuid.PcdNvFdSize|0x0|UINT64|0x00000211 + + # + # Platform PCDs + # + gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x0|UINT32|0x00000250 + gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE|BOOLEAN|0x00000251 + + # + # Clock PCDs + # + gNxpQoriqLsTokenSpaceGuid.PcdSysClk|0x0|UINT64|0x000002A0 + gNxpQoriqLsTokenSpaceGuid.PcdDdrClk|0x0|UINT64|0x000002A1 + + # + # Pcds to support Big Endian IPs + # + gNxpQoriqLsTokenSpaceGuid.PcdMmcBigEndian|FALSE|BOOLEAN|0x0000310 + gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|FALSE|BOOLEAN|0x0000311 + gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian|FALSE|BOOLEAN|0x00000312 + gNxpQoriqLsTokenSpaceGuid.PcdWdogBigEndian|FALSE|BOOLEAN|0x00000313 + gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian|FALSE|BOOLEAN|0x00000314 --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun May 5 06:05:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=nxp.com Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by 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edk2-platforms 09/39] Build : Add build script and environment script X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Meenakshi Aggarwal Build script and Environment setup script. Readme to explain how to run build script Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Meenakshi Aggarwal Signed-off-by: Wasim Khan --- Platform/NXP/Env.cshrc | 78 +++++++++++++++++++++++++++++++++ Platform/NXP/Readme.md | 17 +++++++ Platform/NXP/build.sh | 117 +++++++++++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 212 insertions(+) create mode 100755 Platform/NXP/Env.cshrc create mode 100644 Platform/NXP/Readme.md create mode 100755 Platform/NXP/build.sh diff --git a/Platform/NXP/Env.cshrc b/Platform/NXP/Env.cshrc new file mode 100755 index 0000000..eb51018 --- /dev/null +++ b/Platform/NXP/Env.cshrc @@ -0,0 +1,78 @@ +# @file. +# +# Copyright 2017 NXP +# +# This program and the accompanying materials are licensed and made avail= able under +# the terms and conditions of the BSD License which accompanies this dist= ribution. +# The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +# + +unset GCC_UTILITY GCC_VERSION MajorVersion MinorVersion + +if [ X"$CROSS_COMPILE_64" !=3D X"" ]; then + ARM64_PREFIX=3D"$CROSS_COMPILE_64" +elif [ X"$CROSS_COMPILE" !=3D X"" ]; then + ARM64_PREFIX=3D"$CROSS_COMPILE" +else + ARM64_PREFIX=3D"aarch64-linux-gnu-" +fi + +GCC_UTILITY=3D"${ARM64_PREFIX}gcc" +CheckGcc=3D`which $GCC_UTILITY >/dev/null 2>&1` +if [ "$?" -eq 0 ];then + GCC_VERSION=3D`$GCC_UTILITY -v 2>&1 | tail -n 1 | awk '{print $3}'` + MajorVersion=3D`echo $GCC_VERSION | cut -d . -f 1` + MinorVersion=3D`echo $GCC_VERSION | cut -d . -f 2` + GCC_ARCH_PREFIX=3D + NOTSUPPORTED=3D0 + + case $MajorVersion in + 4) + case $MinorVersion in + 9) + GCC_ARCH_PREFIX=3D"GCC49_AARCH64_PREFIX" + ;; + *) + NOTSUPPORTED=3D1 + ;; + esac + ;; + 5) + case $MinorVersion in + 4) + GCC_ARCH_PREFIX=3D"GCC5_AARCH64_PREFIX" + ;; + *) + GCC_ARCH_PREFIX=3D"GCC5_AARCH64_PREFIX" + echo "Warning: ${GCC_UTILITY} version ($MajorVersion.$MinorVersion= ) has not been tested, please use at own risk." + ;; + esac + ;; + *) + NOTSUPPORTED=3D1 + ;; + esac + + [ "$NOTSUPPORTED" -eq 1 ] && { + echo "Error: ${GCC_UTILITY} version ($MajorVersion.$MinorVersion) no= t supported ." + unset GCC_UTILITY GCC_VERSION MajorVersion MinorVersion + } + + [ -n "$GCC_ARCH_PREFIX" ] && { + export GCC_ARCH_PREFIX=3D"$GCC_ARCH_PREFIX" + export "$GCC_ARCH_PREFIX=3D$ARM64_PREFIX" + } + + unset ARCH +else + echo "Error: ${GCC_UTILITY} not found. Please check PATH variable." + unset GCC_UTILITY GCC_VERSION MajorVersion MinorVersion +fi + +# Export the edk2-platforms path +export PACKAGES_PATH=3D`dirname \`dirname "$PWD"\`` diff --git a/Platform/NXP/Readme.md b/Platform/NXP/Readme.md new file mode 100644 index 0000000..94174a7 --- /dev/null +++ b/Platform/NXP/Readme.md @@ -0,0 +1,17 @@ +Support for all NXP boards is available in this directory. + +# How to build + +build script source environment file Env.cshrc + +user need to run only build command. + +1. source Env.cshrc + +2. Build desired board + ./build.sh (optional) + + Soc-name : LS1043 / LS1046 / LS2088 + board-type : RDB / QDS + build-candidate : DEBUG / RELEASE + diff --git a/Platform/NXP/build.sh b/Platform/NXP/build.sh new file mode 100755 index 0000000..eea83ee --- /dev/null +++ b/Platform/NXP/build.sh @@ -0,0 +1,117 @@ +#!/bin/bash + +# UEFI build script for NXP LS SoCs +# +# Copyright 2017 NXP +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BS= D License +# which accompanies this distribution. The full text of the license may b= e found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. +# + +# source environment file +source Env.cshrc + +# Global Defaults +ARCH=3DAARCH64 +TARGET_TOOLS=3D`echo $GCC_ARCH_PREFIX | cut -d _ -f 1` +BASE_DIR=3D../../.. + +[ -z "$TARGET_TOOLS" ] && { + echo "TARGET_TOOLS not found. Please run \"source Env.cshrc\" ." + exit 1 +} + +print_usage_banner() +{ + echo "" + echo "This shell script expects:" + echo " Arg 1 (mandatory): SoC Type (can be LS1043 / LS1046 / LS2088= )." + echo " Arg 2 (mandatory): Board Type (can be RDB / QDS)." + echo " Arg 3 (mandatory): Build candidate (can be RELEASE or DEBUG)= . By + default we build the RELEASE candidate." + echo " Arg 4 (optional): clean - To do a 'make clean' operation." +} + +# Check for total num of input arguments +if [[ "$#" -gt 4 ]]; then + echo "Illegal number of parameters" + print_usage_banner + exit +fi + +# Check for third parameter to be clean only +if [[ "$4" && $4 !=3D "clean" ]]; then + echo "Error ! Either clean or emplty" + print_usage_banner + exit +fi + +# Check for input arguments +if [[ $1 =3D=3D "" || $2 =3D=3D "" || $3 =3D=3D "" ]]; then + echo "Error !" + print_usage_banner + exit +fi + +# Check for input arguments +if [[ $1 !=3D "LS1043" && $1 !=3D "LS1046" && $1 !=3D "LS2088" ]]; then + echo "Error ! Incorrect Soc Type specified." + print_usage_banner + exit +fi + +# Check for input arguments +if [[ $2 !=3D "RDB" && $2 !=3D "QDS" ]]; then + echo "Error ! Incorrect Board Type specified." + print_usage_banner + exit +fi + +# Check for input arguments +if [[ $3 !=3D "RELEASE" ]]; then + if [[ $3 !=3D "DEBUG" ]]; then + echo "Error ! Incorrect build target specified." + print_usage_banner + exit + fi +fi + +# Set Package drirectory +if [[ $2 =3D=3D "RDB" ]]; then + PKG=3D"aRdbPkg" + if [[ $2 =3D=3D "QDS" ]]; then + PKG=3D"aQdsPkg" + fi +fi + +echo ".........................................." +echo "Welcome to $1$PKG UEFI Build environment" +echo ".........................................." + +if [[ $4 =3D=3D "clean" ]]; then + echo "Cleaning up the build directory '$BASE_DIR/Build/$1$PKG/'.." + rm -rf $BASE_DIR/Build/$1$PKG/* + exit +fi + +# Clean-up +set -e +shopt -s nocasematch + +# +# Setup workspace now +# +echo Initializing workspace +cd $BASE_DIR + +# Use the BaseTools in edk2 +export EDK_TOOLS_PATH=3D`pwd`/BaseTools +source edksetup.sh BaseTools + + +build -p "$PACKAGES_PATH/Platform/NXP/$1$PKG/$1$PKG.dsc" -a $ARCH -t $TARG= ET_TOOLS -b $3 --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun May 5 06:05:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" From: Meenakshi Aggarwal This header file contain IFC controller timing structure, chip select enum and other IFC macros. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Meenakshi Aggarwal --- Silicon/NXP/Include/Ifc.h | 420 ++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 420 insertions(+) create mode 100644 Silicon/NXP/Include/Ifc.h diff --git a/Silicon/NXP/Include/Ifc.h b/Silicon/NXP/Include/Ifc.h new file mode 100644 index 0000000..0bb7230 --- /dev/null +++ b/Silicon/NXP/Include/Ifc.h @@ -0,0 +1,420 @@ +/** @Ifc.h + + Copyright 2017 NXP + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#ifndef __IFC_H__ +#define __IFC_H__ + +#include +#include + +#define IFC_BANK_COUNT 4 + +#define IFC_CSPR_REG_LEN 148 +#define IFC_AMASK_REG_LEN 144 +#define IFC_CSOR_REG_LEN 144 +#define IFC_FTIM_REG_LEN 576 + +#define IFC_CSPR_USED_LEN sizeof (IFC_CSPR) * \ + IFC_BANK_COUNT + +#define IFC_AMASK_USED_LEN sizeof (IFC_AMASK) * \ + IFC_BANK_COUNT + +#define IFC_CSOR_USED_LEN sizeof (IFC_CSOR) * \ + IFC_BANK_COUNT + +#define IFC_FTIM_USED_LEN sizeof (IFC_FTIM) * \ + IFC_BANK_COUNT + +/* List of commands */ +#define IFC_NAND_CMD_RESET 0xFF +#define IFC_NAND_CMD_READID 0x90 +#define IFC_NAND_CMD_STATUS 0x70 +#define IFC_NAND_CMD_READ0 0x00 +#define IFC_NAND_CMD_READSTART 0x30 +#define IFC_NAND_CMD_ERASE1 0x60 +#define IFC_NAND_CMD_ERASE2 0xD0 +#define IFC_NAND_CMD_SEQIN 0x80 +#define IFC_NAND_CMD_PAGEPROG 0x10 +#define MAX_RETRY_COUNT 150000 + + +#define IFC_NAND_SEQ_STRT_FIR_STRT 0x80000000 + +/* + * NAND Event and Error Status Register (NAND_EVTER_STAT) + */ + +/* Operation Complete */ +#define IFC_NAND_EVTER_STAT_OPC 0x80000000 + +/* Flash Timeout Error */ +#define IFC_NAND_EVTER_STAT_FTOER 0x08000000 + +/* Write Protect Error */ +#define IFC_NAND_EVTER_STAT_WPER 0x04000000 + +/* ECC Error */ +#define IFC_NAND_EVTER_STAT_ECCER 0x02000000 + +/* + * NAND Flash Instruction Registers (NAND_FIR0/NAND_FIR1/NAND_FIR2) + */ + +/* NAND Machine specific opcodes OP0-OP14*/ +#define IFC_NAND_FIR0_OP0 0xFC000000 +#define IFC_NAND_FIR0_OP0_SHIFT 26 +#define IFC_NAND_FIR0_OP1 0x03F00000 +#define IFC_NAND_FIR0_OP1_SHIFT 20 +#define IFC_NAND_FIR0_OP2 0x000FC000 +#define IFC_NAND_FIR0_OP2_SHIFT 14 +#define IFC_NAND_FIR0_OP3 0x00003F00 +#define IFC_NAND_FIR0_OP3_SHIFT 8 +#define IFC_NAND_FIR0_OP4 0x000000FC +#define IFC_NAND_FIR0_OP4_SHIFT 2 +#define IFC_NAND_FIR1_OP5 0xFC000000 +#define IFC_NAND_FIR1_OP5_SHIFT 26 +#define IFC_NAND_FIR1_OP6 0x03F00000 +#define IFC_NAND_FIR1_OP6_SHIFT 20 +#define IFC_NAND_FIR1_OP7 0x000FC000 +#define IFC_NAND_FIR1_OP7_SHIFT 14 +#define IFC_NAND_FIR1_OP8 0x00003F00 +#define IFC_NAND_FIR1_OP8_SHIFT 8 +#define IFC_NAND_FIR1_OP9 0x000000FC +#define IFC_NAND_FIR1_OP9_SHIFT 2 +#define IFC_NAND_FIR2_OP10 0xFC000000 +#define IFC_NAND_FIR2_OP10_SHIFT 26 +#define IFC_NAND_FIR2_OP11 0x03F00000 +#define IFC_NAND_FIR2_OP11_SHIFT 20 +#define IFC_NAND_FIR2_OP12 0x000FC000 +#define IFC_NAND_FIR2_OP12_SHIFT 14 +#define IFC_NAND_FIR2_OP13 0x00003F00 +#define IFC_NAND_FIR2_OP13_SHIFT 8 +#define IFC_NAND_FIR2_OP14 0x000000FC +#define IFC_NAND_FIR2_OP14_SHIFT 2 + +/* + * NAND Flash Command Registers (NAND_FCR0/NAND_FCR1) + */ + +/* General purpose FCM flash command bytes CMD0-CMD7 */ +#define IFC_NAND_FCR0_CMD0 0xFF000000 +#define IFC_NAND_FCR0_CMD0_SHIFT 24 +#define IFC_NAND_FCR0_CMD1 0x00FF0000 +#define IFC_NAND_FCR0_CMD1_SHIFT 16 +#define IFC_NAND_FCR0_CMD2 0x0000FF00 +#define IFC_NAND_FCR0_CMD2_SHIFT 8 +#define IFC_NAND_FCR0_CMD3 0x000000FF +#define IFC_NAND_FCR0_CMD3_SHIFT 0 +#define IFC_NAND_FCR1_CMD4 0xFF000000 +#define IFC_NAND_FCR1_CMD4_SHIFT 24 +#define IFC_NAND_FCR1_CMD5 0x00FF0000 +#define IFC_NAND_FCR1_CMD5_SHIFT 16 +#define IFC_NAND_FCR1_CMD6 0x0000FF00 +#define IFC_NAND_FCR1_CMD6_SHIFT 8 +#define IFC_NAND_FCR1_CMD7 0x000000FF +#define IFC_NAND_FCR1_CMD7_SHIFT 0 + +/* Timing registers for NAND Flash */ + +#define IFC_FTIM0_NAND_TCCST_SHIFT 25 +#define IFC_FTIM0_NAND_TCCST(n) ((n) << IFC_FTIM0_NAND_TCCST_SHIFT) +#define IFC_FTIM0_NAND_TWP_SHIFT 16 +#define IFC_FTIM0_NAND_TWP(n) ((n) << IFC_FTIM0_NAND_TWP_SHIFT) +#define IFC_FTIM0_NAND_TWCHT_SHIFT 8 +#define IFC_FTIM0_NAND_TWCHT(n) ((n) << IFC_FTIM0_NAND_TWCHT_SHIFT) +#define IFC_FTIM0_NAND_TWH_SHIFT 0 +#define IFC_FTIM0_NAND_TWH(n) ((n) << IFC_FTIM0_NAND_TWH_SHIFT) +#define IFC_FTIM1_NAND_TADLE_SHIFT 24 +#define IFC_FTIM1_NAND_TADLE(n) ((n) << IFC_FTIM1_NAND_TADLE_SHIFT) +#define IFC_FTIM1_NAND_TWBE_SHIFT 16 +#define IFC_FTIM1_NAND_TWBE(n) ((n) << IFC_FTIM1_NAND_TWBE_SHIFT) +#define IFC_FTIM1_NAND_TRR_SHIFT 8 +#define IFC_FTIM1_NAND_TRR(n) ((n) << IFC_FTIM1_NAND_TRR_SHIFT) +#define IFC_FTIM1_NAND_TRP_SHIFT 0 +#define IFC_FTIM1_NAND_TRP(n) ((n) << IFC_FTIM1_NAND_TRP_SHIFT) +#define IFC_FTIM2_NAND_TRAD_SHIFT 21 +#define IFC_FTIM2_NAND_TRAD(n) ((n) << IFC_FTIM2_NAND_TRAD_SHIFT) +#define IFC_FTIM2_NAND_TREH_SHIFT 11 +#define IFC_FTIM2_NAND_TREH(n) ((n) << IFC_FTIM2_NAND_TREH_SHIFT) +#define IFC_FTIM2_NAND_TWHRE_SHIFT 0 +#define IFC_FTIM2_NAND_TWHRE(n) ((n) << IFC_FTIM2_NAND_TWHRE_SHIFT) +#define IFC_FTIM3_NAND_TWW_SHIFT 24 +#define IFC_FTIM3_NAND_TWW(n) ((n) << IFC_FTIM3_NAND_TWW_SHIFT) + +/* + * Flash ROW and COL Address Register (ROWn, COLn) + */ + +/* Main/spare region locator */ +#define IFC_NAND_COL_MS 0x80000000 + +/* Column Address */ +#define IFC_NAND_COL_CA_MASK 0x00000FFF + +#define NAND_STATUS_WP 0x80 + +/* + * NAND Event and Error Enable Register (NAND_EVTER_EN) + */ + +/* Operation complete event enable */ +#define IFC_NAND_EVTER_EN_OPC_EN 0x80000000 + +/* Page read complete event enable */ +#define IFC_NAND_EVTER_EN_PGRDCMPL_EN 0x20000000 + +/* Flash Timeout error enable */ +#define IFC_NAND_EVTER_EN_FTOER_EN 0x08000000 + +/* Write Protect error enable */ +#define IFC_NAND_EVTER_EN_WPER_EN 0x04000000 + +/* ECC error logging enable */ +#define IFC_NAND_EVTER_EN_ECCER_EN 0x02000000 + +/* + * CSPR - Chip Select Property Register + */ + +#define IFC_CSPR_BA 0xFFFF0000 +#define IFC_CSPR_BA_SHIFT 16 +#define IFC_CSPR_PORT_SIZE 0x00000180 +#define IFC_CSPR_PORT_SIZE_SHIFT 7 + +// Port Size 8 bit +#define IFC_CSPR_PORT_SIZE_8 0x00000080 + +// Port Size 16 bit +#define IFC_CSPR_PORT_SIZE_16 0x00000100 + +// Port Size 32 bit +#define IFC_CSPR_PORT_SIZE_32 0x00000180 + +// Write Protect +#define IFC_CSPR_WP 0x00000040 +#define IFC_CSPR_WP_SHIFT 6 + +// Machine Select +#define IFC_CSPR_MSEL 0x00000006 +#define IFC_CSPR_MSEL_SHIFT 1 + +// NOR +#define IFC_CSPR_MSEL_NOR 0x00000000 + +/* NAND */ +#define IFC_CSPR_MSEL_NAND 0x00000002 + +/* GPCM */ +#define IFC_CSPR_MSEL_GPCM 0x00000004 + +// Bank Valid +#define IFC_CSPR_V 0x00000001 +#define IFC_CSPR_V_SHIFT 0 + +/* + * Chip Select Option Register - NOR Flash Mode + */ + +// Enable Address shift Mode +#define IFC_CSOR_NOR_ADM_SHFT_MODE_EN 0x80000000 + +// Page Read Enable from NOR device +#define IFC_CSOR_NOR_PGRD_EN 0x10000000 + +// AVD Toggle Enable during Burst Program +#define IFC_CSOR_NOR_AVD_TGL_PGM_EN 0x01000000 + +// Address Data Multiplexing Shift +#define IFC_CSOR_NOR_ADM_MASK 0x0003E000 +#define IFC_CSOR_NOR_ADM_SHIFT_SHIFT 13 +#define IFC_CSOR_NOR_ADM_SHIFT(n) ((n) << IFC_CSOR_NOR_ADM_SHIFT_SHIFT) + +// Type of the NOR device hooked +#define IFC_CSOR_NOR_NOR_MODE_AYSNC_NOR 0x00000000 +#define IFC_CSOR_NOR_NOR_MODE_AVD_NOR 0x00000020 + +// Time for Read Enable High to Output High Impedance +#define IFC_CSOR_NOR_TRHZ_MASK 0x0000001C +#define IFC_CSOR_NOR_TRHZ_SHIFT 2 +#define IFC_CSOR_NOR_TRHZ_20 0x00000000 +#define IFC_CSOR_NOR_TRHZ_40 0x00000004 +#define IFC_CSOR_NOR_TRHZ_60 0x00000008 +#define IFC_CSOR_NOR_TRHZ_80 0x0000000C +#define IFC_CSOR_NOR_TRHZ_100 0x00000010 + +// Buffer control disable +#define IFC_CSOR_NOR_BCTLD 0x00000001 + +/* + * Chip Select Option Register IFC_NAND Machine + */ + +/* Enable ECC Encoder */ +#define IFC_CSOR_NAND_ECC_ENC_EN 0x80000000 +#define IFC_CSOR_NAND_ECC_MODE_MASK 0x30000000 + +/* 4 bit correction per 520 Byte sector */ +#define IFC_CSOR_NAND_ECC_MODE_4 0x00000000 + +/* 8 bit correction per 528 Byte sector */ +#define IFC_CSOR_NAND_ECC_MODE_8 0x10000000 + +/* Enable ECC Decoder */ +#define IFC_CSOR_NAND_ECC_DEC_EN 0x04000000 + +/* Row Address Length */ +#define IFC_CSOR_NAND_RAL_MASK 0x01800000 +#define IFC_CSOR_NAND_RAL_SHIFT 20 +#define IFC_CSOR_NAND_RAL_1 0x00000000 +#define IFC_CSOR_NAND_RAL_2 0x00800000 +#define IFC_CSOR_NAND_RAL_3 0x01000000 +#define IFC_CSOR_NAND_RAL_4 0x01800000 + +/* Page Size 512b, 2k, 4k */ +#define IFC_CSOR_NAND_PGS_MASK 0x00180000 +#define IFC_CSOR_NAND_PGS_SHIFT 16 +#define IFC_CSOR_NAND_PGS_512 0x00000000 +#define IFC_CSOR_NAND_PGS_2K 0x00080000 +#define IFC_CSOR_NAND_PGS_4K 0x00100000 +#define IFC_CSOR_NAND_PGS_8K 0x00180000 + +/* Spare region Size */ +#define IFC_CSOR_NAND_SPRZ_MASK 0x0000E000 +#define IFC_CSOR_NAND_SPRZ_SHIFT 13 +#define IFC_CSOR_NAND_SPRZ_16 0x00000000 +#define IFC_CSOR_NAND_SPRZ_64 0x00002000 +#define IFC_CSOR_NAND_SPRZ_128 0x00004000 +#define IFC_CSOR_NAND_SPRZ_210 0x00006000 +#define IFC_CSOR_NAND_SPRZ_218 0x00008000 +#define IFC_CSOR_NAND_SPRZ_224 0x0000A000 +#define IFC_CSOR_NAND_SPRZ_CSOR_EXT 0x0000C000 + +/* Pages Per Block */ +#define IFC_CSOR_NAND_PB_MASK 0x00000700 +#define IFC_CSOR_NAND_PB_SHIFT 8 +#define IFC_CSOR_NAND_PB(n) (n-5) << IFC_CSOR_NAND_PB_SHIFT + +/* Time for Read Enable High to Output High Impedance */ +#define IFC_CSOR_NAND_TRHZ_MASK 0x0000001C +#define IFC_CSOR_NAND_TRHZ_SHIFT 2 +#define IFC_CSOR_NAND_TRHZ_20 0x00000000 +#define IFC_CSOR_NAND_TRHZ_40 0x00000004 +#define IFC_CSOR_NAND_TRHZ_60 0x00000008 +#define IFC_CSOR_NAND_TRHZ_80 0x0000000C +#define IFC_CSOR_NAND_TRHZ_100 0x00000010 + +/* + * FTIM0 - NOR Flash Mode + */ +#define IFC_FTIM0_NOR 0xF03F3F3F +#define IFC_FTIM0_NOR_TACSE_SHIFT 28 +#define IFC_FTIM0_NOR_TACSE(n) ((n) << IFC_FTIM0_NOR_TACSE_SHIFT) +#define IFC_FTIM0_NOR_TEADC_SHIFT 16 +#define IFC_FTIM0_NOR_TEADC(n) ((n) << IFC_FTIM0_NOR_TEADC_SHIFT) +#define IFC_FTIM0_NOR_TAVDS_SHIFT 8 +#define IFC_FTIM0_NOR_TAVDS(n) ((n) << IFC_FTIM0_NOR_TAVDS_SHIFT) +#define IFC_FTIM0_NOR_TEAHC_SHIFT 0 +#define IFC_FTIM0_NOR_TEAHC(n) ((n) << IFC_FTIM0_NOR_TEAHC_SHIFT) + +/* + * FTIM1 - NOR Flash Mode + */ +#define IFC_FTIM1_NOR 0xFF003F3F +#define IFC_FTIM1_NOR_TACO_SHIFT 24 +#define IFC_FTIM1_NOR_TACO(n) ((n) << IFC_FTIM1_NOR_TACO_SHIFT) +#define IFC_FTIM1_NOR_TRAD_NOR_SHIFT 8 +#define IFC_FTIM1_NOR_TRAD_NOR(n) ((n) << IFC_FTIM1_NOR_TRAD_NOR_SHI= FT) +#define IFC_FTIM1_NOR_TSEQRAD_NOR_SHIFT 0 +#define IFC_FTIM1_NOR_TSEQRAD_NOR(n) ((n) << IFC_FTIM1_NOR_TSEQRAD_NOR_= SHIFT) + +/* + * FTIM2 - NOR Flash Mode + */ +#define IFC_FTIM2_NOR 0x0F3CFCFF +#define IFC_FTIM2_NOR_TCS_SHIFT 24 +#define IFC_FTIM2_NOR_TCS(n) ((n) << IFC_FTIM2_NOR_TCS_SHIFT) +#define IFC_FTIM2_NOR_TCH_SHIFT 18 +#define IFC_FTIM2_NOR_TCH(n) ((n) << IFC_FTIM2_NOR_TCH_SHIFT) +#define IFC_FTIM2_NOR_TWPH_SHIFT 10 +#define IFC_FTIM2_NOR_TWPH(n) ((n) << IFC_FTIM2_NOR_TWPH_SHIFT) +#define IFC_FTIM2_NOR_TWP_SHIFT 0 +#define IFC_FTIM2_NOR_TWP(n) ((n) << IFC_FTIM2_NOR_TWP_SHIFT) + +/* + * FTIM0 - Normal GPCM Mode + */ +#define IFC_FTIM0_GPCM 0xF03F3F3F +#define IFC_FTIM0_GPCM_TACSE_SHIFT 28 +#define IFC_FTIM0_GPCM_TACSE(n) ((n) << IFC_FTIM0_GPCM_TACSE_SHIFT) +#define IFC_FTIM0_GPCM_TEADC_SHIFT 16 +#define IFC_FTIM0_GPCM_TEADC(n) ((n) << IFC_FTIM0_GPCM_TEADC_SHIFT) +#define IFC_FTIM0_GPCM_TAVDS_SHIFT 8 +#define IFC_FTIM0_GPCM_TAVDS(n) ((n) << IFC_FTIM0_GPCM_TAVDS_SHIFT) +#define IFC_FTIM0_GPCM_TEAHC_SHIFT 0 +#define IFC_FTIM0_GPCM_TEAHC(n) ((n) << IFC_FTIM0_GPCM_TEAHC_SHIFT) + +/* + * FTIM1 - Normal GPCM Mode + */ +#define IFC_FTIM1_GPCM 0xFF003F00 +#define IFC_FTIM1_GPCM_TACO_SHIFT 24 +#define IFC_FTIM1_GPCM_TACO(n) ((n) << IFC_FTIM1_GPCM_TACO_SHIFT) +#define IFC_FTIM1_GPCM_TRAD_SHIFT 8 +#define IFC_FTIM1_GPCM_TRAD(n) ((n) << IFC_FTIM1_GPCM_TRAD_SHIFT) + +/* + * FTIM2 - Normal GPCM Mode + */ +#define IFC_FTIM2_GPCM 0x0F3C00FF +#define IFC_FTIM2_GPCM_TCS_SHIFT 24 +#define IFC_FTIM2_GPCM_TCS(n) ((n) << IFC_FTIM2_GPCM_TCS_SHIFT) +#define IFC_FTIM2_GPCM_TCH_SHIFT 18 +#define IFC_FTIM2_GPCM_TCH(n) ((n) << IFC_FTIM2_GPCM_TCH_SHIFT) +#define IFC_FTIM2_GPCM_TWP_SHIFT 0 +#define IFC_FTIM2_GPCM_TWP(n) ((n) << IFC_FTIM2_GPCM_TWP_SHIFT) + +/* Convert an address into the right format for the CSPR Registers */ +#define IFC_CSPR_PHYS_ADDR(x) (((UINTN)x) & 0xffff0000) + +/* + * Address Mask Register + */ +#define IFC_AMASK_MASK 0xFFFF0000 +#define IFC_AMASK_SHIFT 16 +#define IFC_AMASK(n) (IFC_AMASK_MASK << \ + (HighBitSet32(n) - IFC_AMASK_SHIFT)) + +typedef enum { + IFC_CS0 =3D 0, + IFC_CS1, + IFC_CS2, + IFC_CS3, + IFC_CS4, + IFC_CS5, + IFC_CS6, + IFC_CS7, + IFC_CS_MAX, +} IFC_CHIP_SEL; + +typedef struct { + UINT32 Ftim[IFC_BANK_COUNT]; + UINT32 CsprExt; + UINT32 Cspr; + UINT32 Csor; + UINT32 Amask; + UINT8 CS; +} IFC_TIMINGS; + +#endif //__IFC_H__ --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun May 5 06:05:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=nxp.com Return-Path: Received: from ml01.01.org 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X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Feb 2018 08:53:10.9829 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fcd7f34f-2b45-4da6-881c-08d5751ab6bd X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB1008 Subject: [edk2] [PATCH edk2-platforms 11/39] LS1043/BoardLib : Add support for LS1043 BoardLib. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Meenakshi Aggarwal BoardLib will contain functions specific for LS1043aRdb board. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Meenakshi Aggarwal --- .../NXP/LS1043aRdbPkg/Include/IfcBoardSpecific.h | 109 +++++++++++++++++= ++++ .../NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.c | 69 +++++++++++++ .../LS1043aRdbPkg/Library/BoardLib/BoardLib.inf | 31 ++++++ 3 files changed, 209 insertions(+) create mode 100644 Platform/NXP/LS1043aRdbPkg/Include/IfcBoardSpecific.h create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.c create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.inf diff --git a/Platform/NXP/LS1043aRdbPkg/Include/IfcBoardSpecific.h b/Platfo= rm/NXP/LS1043aRdbPkg/Include/IfcBoardSpecific.h new file mode 100644 index 0000000..261867a --- /dev/null +++ b/Platform/NXP/LS1043aRdbPkg/Include/IfcBoardSpecific.h @@ -0,0 +1,109 @@ +/** IfcBoardSpecificLib.h + + IFC Flash Board Specific Macros and structure + + Copyright 2017 NXP + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may be= found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ +#ifndef __IFC__BOARD_SPECIFIC_H__ +#define __IFC__BOARD_SPECIFIC_H__ + +#include + +// On board flash support +#define IFC_NAND_BUF_BASE 0x7E800000 + +// On board Inegrated flash Controller chip select configuration +#define IFC_NOR_CS IFC_CS0 +#define IFC_NAND_CS IFC_CS1 +#define IFC_FPGA_CS IFC_CS2 + +// board-specific NAND timing +#define NAND_FTIM0 (IFC_FTIM0_NAND_TCCST(0x7) | \ + IFC_FTIM0_NAND_TWP(0x18) | \ + IFC_FTIM0_NAND_TWCHT(0x7) | \ + IFC_FTIM0_NAND_TWH(0xa)) + +#define NAND_FTIM1 (IFC_FTIM1_NAND_TADLE(0x32) | \ + IFC_FTIM1_NAND_TWBE(0x39) | \ + IFC_FTIM1_NAND_TRR(0xe) | \ + IFC_FTIM1_NAND_TRP(0x18)) + +#define NAND_FTIM2 (IFC_FTIM2_NAND_TRAD(0xf) | \ + IFC_FTIM2_NAND_TREH(0xa) | \ + IFC_FTIM2_NAND_TWHRE(0x1e)) + +#define NAND_FTIM3 0x0 + +#define NAND_CSPR (IFC_CSPR_PHYS_ADDR(IFC_NAND_BUF_BASE) \ + | IFC_CSPR_PORT_SIZE_8 \ + | IFC_CSPR_MSEL_NAND \ + | IFC_CSPR_V) + +#define NAND_CSPR_EXT 0x0 +#define NAND_AMASK 0xFFFF0000 + +#define NAND_CSOR (IFC_CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | IFC_CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | IFC_CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ + | IFC_CSOR_NAND_RAL_3 /* RAL =3D 3 Bytes */ \ + | IFC_CSOR_NAND_PGS_2K /* Page Size =3D 2K */ \ + | IFC_CSOR_NAND_SPRZ_64 /* Spare size =3D 64 */ \ + | IFC_CSOR_NAND_PB(6)) /* 2^6 Pages Per Block */ + +// board-specific NOR timing +#define NOR_FTIM0 (IFC_FTIM0_NOR_TACSE(0x1) | \ + IFC_FTIM0_NOR_TEADC(0x1) | \ + IFC_FTIM0_NOR_TAVDS(0x0) | \ + IFC_FTIM0_NOR_TEAHC(0xc)) +#define NOR_FTIM1 (IFC_FTIM1_NOR_TACO(0x1c) | \ + IFC_FTIM1_NOR_TRAD_NOR(0xb) |\ + IFC_FTIM1_NOR_TSEQRAD_NOR(0x9)) +#define NOR_FTIM2 (IFC_FTIM2_NOR_TCS(0x1) | \ + IFC_FTIM2_NOR_TCH(0x4) | \ + IFC_FTIM2_NOR_TWPH(0x8) | \ + IFC_FTIM2_NOR_TWP(0x10)) +#define NOR_FTIM3 0x0 + +#define NOR_CSPR (IFC_CSPR_PHYS_ADDR(FixedPcdGet64 (PcdIfcRegion1Base= Addr)) \ + | IFC_CSPR_PORT_SIZE_16 \ + | IFC_CSPR_MSEL_NOR \ + | IFC_CSPR_V) + +#define NOR_CSPR_EXT 0x0 +#define NOR_AMASK IFC_AMASK(128*1024*1024) +#define NOR_CSOR (IFC_CSOR_NOR_ADM_SHIFT(4) | \ + IFC_CSOR_NOR_TRHZ_80) + +// board-specific fpga timing +#define FPGA_BASE_PHYS 0x7fb00000 +#define FPGA_CSPR_EXT 0x0 +#define FPGA_CSPR (IFC_CSPR_PHYS_ADDR(FPGA_BASE_PHYS) | \ + IFC_CSPR_PORT_SIZE_8 | \ + IFC_CSPR_MSEL_GPCM | \ + IFC_CSPR_V) + +#define FPGA_AMASK IFC_AMASK(64 * 1024) +#define FPGA_CSOR (IFC_CSOR_NOR_ADM_SHIFT(4) | \ + IFC_CSOR_NOR_NOR_MODE_AVD_NOR | \ + IFC_CSOR_NOR_TRHZ_80) + +#define FPGA_FTIM0 (IFC_FTIM0_GPCM_TACSE(0xf) | \ + IFC_FTIM0_GPCM_TEADC(0xf) | \ + IFC_FTIM0_GPCM_TEAHC(0xf)) +#define FPGA_FTIM1 (IFC_FTIM1_GPCM_TACO(0xff) | \ + IFC_FTIM1_GPCM_TRAD(0x3f)) +#define FPGA_FTIM2 (IFC_FTIM2_GPCM_TCS(0xf) | \ + IFC_FTIM2_GPCM_TCH(0xf) | \ + IFC_FTIM2_GPCM_TWP(0xff)) +#define FPGA_FTIM3 0x0 + +#endif //__IFC__BOARD_SPECIFIC_H__ diff --git a/Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.c b/Platf= orm/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.c new file mode 100644 index 0000000..a101a8d --- /dev/null +++ b/Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.c @@ -0,0 +1,69 @@ +/** @file + + Copyright 2018 NXP + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include + +VOID +GetIfcNorFlashTimings ( + IN IFC_TIMINGS * NorIfcTimings + ) +{ + NorIfcTimings->Ftim[0] =3D NOR_FTIM0; + NorIfcTimings->Ftim[1] =3D NOR_FTIM1; + NorIfcTimings->Ftim[2] =3D NOR_FTIM2; + NorIfcTimings->Ftim[3] =3D NOR_FTIM3; + NorIfcTimings->Cspr =3D NOR_CSPR; + NorIfcTimings->CsprExt =3D NOR_CSPR_EXT; + NorIfcTimings->Amask =3D NOR_AMASK; + NorIfcTimings->Csor =3D NOR_CSOR; + NorIfcTimings->CS =3D IFC_NOR_CS; + + return ; +} + +VOID +GetIfcFpgaTimings ( + IN IFC_TIMINGS *FpgaIfcTimings + ) +{ + FpgaIfcTimings->Ftim[0] =3D FPGA_FTIM0; + FpgaIfcTimings->Ftim[1] =3D FPGA_FTIM1; + FpgaIfcTimings->Ftim[2] =3D FPGA_FTIM2; + FpgaIfcTimings->Ftim[3] =3D FPGA_FTIM3; + FpgaIfcTimings->Cspr =3D FPGA_CSPR; + FpgaIfcTimings->CsprExt =3D FPGA_CSPR_EXT; + FpgaIfcTimings->Amask =3D FPGA_AMASK; + FpgaIfcTimings->Csor =3D FPGA_CSOR; + FpgaIfcTimings->CS =3D IFC_FPGA_CS; + + return; +} + +VOID +GetIfcNandFlashTimings ( + IN IFC_TIMINGS * NandIfcTimings + ) +{ + NandIfcTimings->Ftim[0] =3D NAND_FTIM0; + NandIfcTimings->Ftim[1] =3D NAND_FTIM1; + NandIfcTimings->Ftim[2] =3D NAND_FTIM2; + NandIfcTimings->Ftim[3] =3D NAND_FTIM3; + NandIfcTimings->Cspr =3D NAND_CSPR; + NandIfcTimings->CsprExt =3D NAND_CSPR_EXT; + NandIfcTimings->Amask =3D NAND_AMASK; + NandIfcTimings->Csor =3D NAND_CSOR; + NandIfcTimings->CS =3D IFC_NAND_CS; + + return; +} diff --git a/Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.inf b/Pla= tform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.inf new file mode 100644 index 0000000..7d2702b --- /dev/null +++ b/Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.inf @@ -0,0 +1,31 @@ +# @file +# +# Copyright 2018 NXP +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D BoardLib + FILE_GUID =3D 8ecefc8f-a2c4-4091-b80f-92da7c4ab37f + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D BoardLib + +[Sources.common] + BoardLib.c + +[Packages] + MdePkg/MdePkg.dec + Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec + Silicon/NXP/NxpQoriqLs.dec + +[FixedPcd] + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun May 5 06:05:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; 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charset="utf-8" From: Meenakshi Aggarwal Add support of IfcLib, it will be used to perform any operation on IFC controller. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Meenakshi Aggarwal --- Silicon/NXP/Include/Library/IfcLib.h | 23 +++++ Silicon/NXP/Library/IfcLib/IfcLib.c | 155 ++++++++++++++++++++++++++++ Silicon/NXP/Library/IfcLib/IfcLib.h | 184 ++++++++++++++++++++++++++++++= ++++ Silicon/NXP/Library/IfcLib/IfcLib.inf | 38 +++++++ Silicon/NXP/NxpQoriqLs.dec | 1 + 5 files changed, 401 insertions(+) create mode 100644 Silicon/NXP/Include/Library/IfcLib.h create mode 100644 Silicon/NXP/Library/IfcLib/IfcLib.c create mode 100644 Silicon/NXP/Library/IfcLib/IfcLib.h create mode 100644 Silicon/NXP/Library/IfcLib/IfcLib.inf diff --git a/Silicon/NXP/Include/Library/IfcLib.h b/Silicon/NXP/Include/Lib= rary/IfcLib.h new file mode 100644 index 0000000..f350d33 --- /dev/null +++ b/Silicon/NXP/Include/Library/IfcLib.h @@ -0,0 +1,23 @@ +/** @IfcLib.h + + Copyright 2018 NXP + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#ifndef __IFC_LIB_H__ +#define __IFC_LIB_H__ + +VOID +IfcInit ( + VOID + ); + +#endif //__IFC_LIB_H__ diff --git a/Silicon/NXP/Library/IfcLib/IfcLib.c b/Silicon/NXP/Library/IfcL= ib/IfcLib.c new file mode 100644 index 0000000..97a6591 --- /dev/null +++ b/Silicon/NXP/Library/IfcLib/IfcLib.c @@ -0,0 +1,155 @@ +/** @IfcLib.c + + Copyright 2018 NXP + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include +#include +#include "IfcLib.h" + +UINT8 mNandCS; +UINT8 mNorCS; +UINT8 mFpgaCS; + +UINT32 +EFIAPI +IfcWrite ( + IN UINTN Address, + IN UINT32 Value + ) +{ + if (FixedPcdGetBool(PcdIfcBigEndian)) { + return BeMmioWrite32 (Address, Value); + } else { + return MmioWrite32 (Address, Value); + } +} + +VOID +SetTimings ( + IN UINT8 CS, + IN IFC_TIMINGS IfcTimings + ) +{ + IFC_REGS* IfcRegs; + + IfcRegs =3D (IFC_REGS*) PcdGet64 (PcdIfcBaseAddr); + + // Configure Extended chip select property registers + IfcWrite ((UINTN)&IfcRegs->CsprCs[CS].CsprExt, IfcTimings.CsprExt); + + // Configure Fpga timing registers + IfcWrite ((UINTN)&IfcRegs->FtimCs[CS].Ftim[IFC_FTIM0], IfcTimings.Ftim[0= ]); + IfcWrite ((UINTN)&IfcRegs->FtimCs[CS].Ftim[IFC_FTIM1], IfcTimings.Ftim[1= ]); + IfcWrite ((UINTN)&IfcRegs->FtimCs[CS].Ftim[IFC_FTIM2], IfcTimings.Ftim[2= ]); + IfcWrite ((UINTN)&IfcRegs->FtimCs[CS].Ftim[IFC_FTIM3], IfcTimings.Ftim[3= ]); + + // Configure chip select option registers + IfcWrite ((UINTN)&IfcRegs->CsprCs[CS].Cspr, IfcTimings.Cspr); + + // Configure address mask registers + IfcWrite ((UINTN)&IfcRegs->AmaskCs[CS].Amask, IfcTimings.Amask); + + // Configure chip select property registers + IfcWrite ((UINTN)&IfcRegs->CsorCs[CS].Csor, IfcTimings.Csor); + + return; +} + +VOID +NandInit( + VOID + ) +{ + IFC_REGS* IfcRegs; + IFC_TIMINGS NandIfcTimings; + + IfcRegs =3D (IFC_REGS*) PcdGet64 (PcdIfcBaseAddr); + + // Get Nand Flash Timings + GetIfcNandFlashTimings (&NandIfcTimings); + + // Validate chip select + if (NandIfcTimings.CS < IFC_CS_MAX) { + mNandCS =3D NandIfcTimings.CS; + + // clear event registers + IfcWrite ((UINTN)&IfcRegs->IfcNand.PgrdcmplEvtStat, ~0U); + + IfcWrite ((UINTN)&IfcRegs->IfcNand.NandEvterStat, ~0U); + + // Enable error and event for any detected errors + IfcWrite ((UINTN)&IfcRegs->IfcNand.NandEvterEn, + IFC_NAND_EVTER_EN_OPC_EN | + IFC_NAND_EVTER_EN_PGRDCMPL_EN | + IFC_NAND_EVTER_EN_FTOER_EN | + IFC_NAND_EVTER_EN_WPER_EN); + IfcWrite ((UINTN)&IfcRegs->IfcNand.Ncfgr, 0x0); + + SetTimings (mNandCS, NandIfcTimings); + } + + return; +} + +VOID +FpgaInit ( + VOID + ) +{ + IFC_TIMINGS FpgaIfcTimings; + + // Get Fpga Flash Timings + GetIfcFpgaTimings (&FpgaIfcTimings); + + // Validate chip select + if (FpgaIfcTimings.CS < IFC_CS_MAX) { + mFpgaCS =3D FpgaIfcTimings.CS; + SetTimings (mFpgaCS, FpgaIfcTimings); + } + + return; +} + +VOID +NorInit ( + VOID + ) +{ + IFC_TIMINGS NorIfcTimings; + + // Get NOR Flash Timings + GetIfcNorFlashTimings (&NorIfcTimings); + + // Validate chip select + if (NorIfcTimings.CS < IFC_CS_MAX) { + mNorCS =3D NorIfcTimings.CS; + SetTimings (mNorCS, NorIfcTimings); + } + + return; +} + +// +// IFC has NOR , NAND and FPGA +// +VOID +IfcInit ( + VOID + ) +{ + NorInit(); + NandInit(); + FpgaInit(); + + return; +} diff --git a/Silicon/NXP/Library/IfcLib/IfcLib.h b/Silicon/NXP/Library/IfcL= ib/IfcLib.h new file mode 100644 index 0000000..9f52576 --- /dev/null +++ b/Silicon/NXP/Library/IfcLib/IfcLib.h @@ -0,0 +1,184 @@ +/** @IfcLib.h + + Copyright 2017 NXP + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#ifndef __IFC_LIB_H__ +#define __IFC_LIB_H__ + +#include +#include + +#define IFC_NAND_RESERVED_SIZE FixedPcdGet32 (PcdIfcNandReservedSize) + +typedef enum { + IFC_FTIM0 =3D 0, + IFC_FTIM1, + IFC_FTIM2, + IFC_FTIM3, +} IFC_FTIMS; + +typedef struct { + UINT32 CsprExt; + UINT32 Cspr; + UINT32 Res; +} IFC_CSPR; + +typedef struct { + UINT32 Amask; + UINT32 Res[0x2]; +} IFC_AMASK; + +typedef struct { + UINT32 Csor; + UINT32 CsorExt; + UINT32 Res; +} IFC_CSOR; + +typedef struct { + UINT32 Ftim[4]; + UINT32 Res[0x8]; +}IFC_FTIM ; + +typedef struct { + UINT32 Ncfgr; + UINT32 Res1[0x4]; + UINT32 NandFcr0; + UINT32 NandFcr1; + UINT32 Res2[0x8]; + UINT32 Row0; + UINT32 Res3; + UINT32 Col0; + UINT32 Res4; + UINT32 Row1; + UINT32 Res5; + UINT32 Col1; + UINT32 Res6; + UINT32 Row2; + UINT32 Res7; + UINT32 Col2; + UINT32 Res8; + UINT32 Row3; + UINT32 Res9; + UINT32 Col3; + UINT32 Res10[0x24]; + UINT32 NandFbcr; + UINT32 Res11; + UINT32 NandFir0; + UINT32 NandFir1; + UINT32 nandFir2; + UINT32 Res12[0x10]; + UINT32 NandCsel; + UINT32 Res13; + UINT32 NandSeqStrt; + UINT32 Res14; + UINT32 NandEvterStat; + UINT32 Res15; + UINT32 PgrdcmplEvtStat; + UINT32 Res16[0x2]; + UINT32 NandEvterEn; + UINT32 Res17[0x2]; + UINT32 NandEvterIntrEn; + UINT32 Res18[0x2]; + UINT32 NandErattr0; + UINT32 NandErattr1; + UINT32 Res19[0x10]; + UINT32 NandFsr; + UINT32 Res20; + UINT32 NandEccstat[4]; + UINT32 Res21[0x20]; + UINT32 NanNdcr; + UINT32 Res22[0x2]; + UINT32 NandAutobootTrgr; + UINT32 Res23; + UINT32 NandMdr; + UINT32 Res24[0x5C]; +} IFC_NAND; + +/* + * IFC controller NOR Machine registers + */ +typedef struct { + UINT32 NorEvterStat; + UINT32 Res1[0x2]; + UINT32 NorEvterEn; + UINT32 Res2[0x2]; + UINT32 NorEvterIntrEn; + UINT32 Res3[0x2]; + UINT32 NorErattr0; + UINT32 NorErattr1; + UINT32 NorErattr2; + UINT32 Res4[0x4]; + UINT32 NorCr; + UINT32 Res5[0xEF]; +} IFC_NOR; + +/* + * IFC controller GPCM Machine registers + */ +typedef struct { + UINT32 GpcmEvterStat; + UINT32 Res1[0x2]; + UINT32 GpcmEvterEn; + UINT32 Res2[0x2]; + UINT32 gpcmEvterIntrEn; + UINT32 Res3[0x2]; + UINT32 GpcmErattr0; + UINT32 GpcmErattr1; + UINT32 GcmErattr2; + UINT32 GpcmStat; +} IFC_GPCM; + +/* + * IFC Controller Registers + */ +typedef struct { + UINT32 IfcRev; + UINT32 Res1[0x2]; + IFC_CSPR CsprCs[IFC_BANK_COUNT]; + UINT8 Res2[IFC_CSPR_REG_LEN - IFC_CSPR_USED_LEN]; + IFC_AMASK AmaskCs[IFC_BANK_COUNT]; + UINT8 Res3[IFC_AMASK_REG_LEN - IFC_AMASK_USED_LEN]; + IFC_CSOR CsorCs[IFC_BANK_COUNT]; + UINT8 Res4[IFC_CSOR_REG_LEN - IFC_CSOR_USED_LEN]; + IFC_FTIM FtimCs[IFC_BANK_COUNT]; + UINT8 Res5[IFC_FTIM_REG_LEN - IFC_FTIM_USED_LEN]; + UINT32 RbStat; + UINT32 RbMap; + UINT32 WpMap; + UINT32 IfcGcr; + UINT32 Res7[0x2]; + UINT32 CmEvter_stat; + UINT32 Res8[0x2]; + UINT32 CmEvterEn; + UINT32 Res9[0x2]; + UINT32 CmEvterIntrEn; + UINT32 Res10[0x2]; + UINT32 CmErattr0; + UINT32 CmErattr1; + UINT32 Res11[0x2]; + UINT32 IfcCcr; + UINT32 IfcCsr; + UINT32 DdrCcrLow; + UINT32 Res12[IFC_NAND_RESERVED_SIZE]; + IFC_NAND IfcNand; + IFC_NOR IfcNor; + IFC_GPCM IfcGpcm; +} IFC_REGS; + +extern VOID GetIfcNorFlashTimings (IFC_TIMINGS * NorIfcTimings); + +extern VOID GetIfcFpgaTimings (IFC_TIMINGS *FpgaIfcTimings); + +extern VOID GetIfcNandFlashTimings (IFC_TIMINGS * NandIfcTimings); + +#endif //__IFC_LIB_H__ diff --git a/Silicon/NXP/Library/IfcLib/IfcLib.inf b/Silicon/NXP/Library/If= cLib/IfcLib.inf new file mode 100644 index 0000000..170ed38 --- /dev/null +++ b/Silicon/NXP/Library/IfcLib/IfcLib.inf @@ -0,0 +1,38 @@ +# IfcLib.inf +# +# Component description file for IFC Library +# +# Copyright 2018 NXP +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D IfcLib + FILE_GUID =3D a465d76c-0785-4ee7-bd72-767983d575a2 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D IfcLib + +[Sources.common] + IfcLib.c + +[Packages] + MdePkg/MdePkg.dec + Silicon/NXP/NxpQoriqLs.dec + +[LibraryClasses] + BoardLib + BeIoLib + +[FixedPcd] + gNxpQoriqLsTokenSpaceGuid.PcdIfcBaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian + gNxpQoriqLsTokenSpaceGuid.PcdIfcNandReservedSize diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec index a73e9d5..43d0a71 100644 --- a/Silicon/NXP/NxpQoriqLs.dec +++ b/Silicon/NXP/NxpQoriqLs.dec @@ -77,6 +77,7 @@ gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x0|UINT64|0x00000128 gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0|UINT64|0x00000129 gNxpQoriqLsTokenSpaceGuid.PcdDramMemSize|0x0|UINT64|0x0000012A + gNxpQoriqLsTokenSpaceGuid.PcdIfcBaseAddr|0x0|UINT64|0x0000012B =20 # # IFC PCDs --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun May 5 06:05:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Meenakshi Aggarwal FpgaLib export FPGA_READ and FPGA_WRITE function and provide a function to print Board personality. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Meenakshi Aggarwal --- .../NXP/LS1043aRdbPkg/Include/Library/FpgaLib.h | 79 ++++++++++++ .../NXP/LS1043aRdbPkg/Library/FpgaLib/FpgaLib.c | 142 +++++++++++++++++= ++++ .../NXP/LS1043aRdbPkg/Library/FpgaLib/FpgaLib.inf | 31 +++++ 3 files changed, 252 insertions(+) create mode 100644 Platform/NXP/LS1043aRdbPkg/Include/Library/FpgaLib.h create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/FpgaLib/FpgaLib.c create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/FpgaLib/FpgaLib.inf diff --git a/Platform/NXP/LS1043aRdbPkg/Include/Library/FpgaLib.h b/Platfor= m/NXP/LS1043aRdbPkg/Include/Library/FpgaLib.h new file mode 100644 index 0000000..3f55a02 --- /dev/null +++ b/Platform/NXP/LS1043aRdbPkg/Include/Library/FpgaLib.h @@ -0,0 +1,79 @@ +/** FpgaLib.h +* Header defining the LS1043a Fpga specific constants (Base addresses, si= zes, flags) +* +* Copyright 2017 NXP +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the B= SD License +* which accompanies this distribution. The full text of the license may = be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#ifndef __LS1043A_FPGA_H__ +#define __LS1043A_FPGA_H__ + +/* + * FPGA register set of LS1043ARDB board-specific. + */ +typedef struct { + UINT8 FpgaVersionMajor; /* 0x0 - FPGA Major Revision Register */ + UINT8 FpgaVersionMinor; /* 0x1 - FPGA Minor Revision Register */ + UINT8 PcbaVersion; /* 0x2 - PCBA Revision Register */ + UINT8 SystemReset; /* 0x3 - system reset register */ + UINT8 SoftMuxOn; /* 0x4 - Switch Control Enable Register */ + UINT8 RcwSource1; /* 0x5 - Reset config word 1 */ + UINT8 RcwSource2; /* 0x6 - Reset config word 1 */ + UINT8 Vbank; /* 0x7 - Flash bank selection Control */ + UINT8 SysclkSelect; /* 0x8 - System clock selection Control */ + UINT8 UartSel; /* 0x9 - Uart selection Control */ + UINT8 Sd1RefClkSel; /* 0xA - Serdes1 reference clock selection Cont= rol */ + UINT8 TdmClkMuxSel; /* 0xB - TDM Clock Mux selection Control */ + UINT8 SdhcSpiCsSel; /* 0xC - SDHC/SPI Chip select selection Control= */ + UINT8 StatusLed; /* 0xD - Status Led */ + UINT8 GlobalReset; /* 0xE - Global reset */ +} FPGA_REG_SET; + +UINT8 +FpgaRead ( + UINTN Reg + ); + +VOID +FpgaWrite ( + UINTN Reg, + UINT8 Value + ); + +VOID +FpgaRevBit ( + UINT8 *Value + ); + +VOID +FpgaInit ( + VOID + ); + +VOID +PrintBoardPersonality ( + VOID + ); + +#define FPGA_BASE_PHYS 0x7fb00000 + +#define SRC_VBANK 0x25 +#define SRC_NAND 0x106 +#define SRC_QSPI 0x44 +#define SRC_SD 0x40 + +#define SERDES_FREQ1 "100.00 MHz" +#define SERDES_FREQ2 "156.25 MHz" + +#define FPGA_READ(Reg) FpgaRead (OFFSET_OF (FPGA_REG_SET, Reg)) +#define FPGA_WRITE(Reg, Value) FpgaWrite (OFFSET_OF (FPGA_REG_SET, Reg), = Value) + +#endif diff --git a/Platform/NXP/LS1043aRdbPkg/Library/FpgaLib/FpgaLib.c b/Platfor= m/NXP/LS1043aRdbPkg/Library/FpgaLib/FpgaLib.c new file mode 100644 index 0000000..99d514d --- /dev/null +++ b/Platform/NXP/LS1043aRdbPkg/Library/FpgaLib/FpgaLib.c @@ -0,0 +1,142 @@ +/** @FpgaLib.c + Fpga Library for LS1043A-RDB board, containing functions to + program and read the Fpga registers. + + FPGA is connected to IFC Controller and so MMIO APIs are used + to read/write FPGA registers + + Copyright 2017 NXP + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may be= found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include +#include +#include +#include +#include + +/** + Function to read FPGA register. + + @param Reg Register offset of FPGA to read. + +**/ +UINT8 +FpgaRead ( + IN UINTN Reg + ) +{ + VOID *Base; + + Base =3D (VOID *)FPGA_BASE_PHYS; + + return MmioRead8 ((UINTN)(Base + Reg)); +} + +/** + Function to write FPGA register. + + @param Reg Register offset of FPGA to write. + @param Value Value to be written. + +**/ +VOID +FpgaWrite ( + IN UINTN Reg, + IN UINT8 Value + ) +{ + VOID *Base; + + Base =3D (VOID *)FPGA_BASE_PHYS; + + MmioWrite8 ((UINTN)(Base + Reg), Value); +} + +/** + Function to reverse the number. + + @param *Value pointer to number to reverse. + + @retval *Value reversed value. + +**/ +VOID +FpgaRevBit ( + OUT UINT8 *Value + ) +{ + UINT8 Rev; + UINT8 Val; + UINTN Index; + + Val =3D *Value; + Rev =3D Val & 1; + for (Index =3D 1; Index <=3D 7; Index++) { + Val >>=3D 1; + Rev <<=3D 1; + Rev |=3D Val & 1; + } + + *Value =3D Rev; +} + +/** + Function to print board personality. + +**/ +VOID +PrintBoardPersonality ( + VOID + ) +{ + UINT8 RcwSrc1; + UINT8 RcwSrc2; + UINT32 RcwSrc; + UINT32 Sd1RefClkSel; + + RcwSrc1 =3D FPGA_READ(RcwSource1); + RcwSrc2 =3D FPGA_READ(RcwSource2); + FpgaRevBit (&RcwSrc1); + RcwSrc =3D RcwSrc1; + RcwSrc =3D (RcwSrc << 1) | RcwSrc2; + + switch (RcwSrc) { + case SRC_VBANK: + DEBUG ((DEBUG_INFO, "vBank: %d\n", FPGA_READ(Vbank))); + break; + case SRC_NAND: + DEBUG ((DEBUG_INFO, "NAND\n")); + break; + case SRC_QSPI: + DEBUG ((DEBUG_INFO, "QSPI vBank %d\n", FPGA_READ(Vbank))); + break; + case SRC_SD: + DEBUG ((DEBUG_INFO, "SD\n")); + break; + default: + DEBUG ((DEBUG_INFO, "Invalid setting of SW5\n")); + break; + } + + DEBUG ((DEBUG_INFO, "FPGA: V%x.%x\nPCBA: V%x.0\n", + FPGA_READ(FpgaVersionMajor), + FPGA_READ(FpgaVersionMinor), + FPGA_READ(PcbaVersion))); + + DEBUG ((DEBUG_INFO, "SERDES Reference Clocks:\n")); + + Sd1RefClkSel =3D FPGA_READ(Sd1RefClkSel); + DEBUG((DEBUG_INFO, "SD1_CLK1 =3D %a, SD1_CLK2 =3D %a\n", + Sd1RefClkSel ? SERDES_FREQ2 : SERDES_FREQ1, SERDES_FREQ1)); + + return; +} diff --git a/Platform/NXP/LS1043aRdbPkg/Library/FpgaLib/FpgaLib.inf b/Platf= orm/NXP/LS1043aRdbPkg/Library/FpgaLib/FpgaLib.inf new file mode 100644 index 0000000..39e9bde --- /dev/null +++ b/Platform/NXP/LS1043aRdbPkg/Library/FpgaLib/FpgaLib.inf @@ -0,0 +1,31 @@ +# @FpgaLib.inf +# +# Copyright 2017 NXP +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# + +[Defines] + INF_VERSION =3D 0x0001000A + BASE_NAME =3D FpgaLib + FILE_GUID =3D 5962d040-8b8a-11df-9a71-0002a5d5c51b + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D FpgaLib + +[Sources.common] + FpgaLib.c + +[Packages] + MdePkg/MdePkg.dec + Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec + Silicon/NXP/NxpQoriqLs.dec + +[LibraryClasses] + BaseLib + IoLib --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun May 5 06:05:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; 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X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Meenakshi Aggarwal Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Meenakshi Aggarwal --- Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 3 +++ Silicon/NXP/Chassis/Chassis2/Soc.c | 5 +++++ Silicon/NXP/Chassis/LS1043aSocLib.inf | 2 ++ Silicon/NXP/LS1043A/LS1043A.dsc | 2 ++ 4 files changed, 12 insertions(+) diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS= 1043aRdbPkg/LS1043aRdbPkg.dsc index 6e9e7e0..df4d917 100644 --- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc @@ -38,6 +38,9 @@ BeIoLib|Silicon/NXP/Library/BeIoLib/BeIoLib.inf SocLib|Silicon/NXP/Chassis/LS1043aSocLib.inf RealTimeClockLib|Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf + IfcLib|Silicon/NXP/Library/IfcLib/IfcLib.inf + BoardLib|Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.inf + FpgaLib|Platform/NXP/LS1043aRdbPkg/Library/FpgaLib/FpgaLib.inf =20 [PcdsFixedAtBuild.common] =20 diff --git a/Silicon/NXP/Chassis/Chassis2/Soc.c b/Silicon/NXP/Chassis/Chass= is2/Soc.c index 7f9f963..17de7e4 100644 --- a/Silicon/NXP/Chassis/Chassis2/Soc.c +++ b/Silicon/NXP/Chassis/Chassis2/Soc.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -25,6 +26,8 @@ =20 #include "Soc.h" =20 +extern VOID PrintBoardPersonality (VOID); + /** Calculate the frequency of various controllers and populate the passed structure with frequuencies. @@ -167,6 +170,8 @@ SocInit ( // PrintRCW (); PrintSoc (); + IfcInit(); + PrintBoardPersonality (); =20 return; } diff --git a/Silicon/NXP/Chassis/LS1043aSocLib.inf b/Silicon/NXP/Chassis/LS= 1043aSocLib.inf index 1b2f9c4..d01b353 100644 --- a/Silicon/NXP/Chassis/LS1043aSocLib.inf +++ b/Silicon/NXP/Chassis/LS1043aSocLib.inf @@ -31,6 +31,8 @@ BaseLib BeIoLib DebugLib + FpgaLib + IfcLib SerialPortLib =20 [Sources.common] diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc b/Silicon/NXP/LS1043A/LS1043A.= dsc index 8395dfd..a4eb117 100644 --- a/Silicon/NXP/LS1043A/LS1043A.dsc +++ b/Silicon/NXP/LS1043A/LS1043A.dsc @@ -63,11 +63,13 @@ gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|4 gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x40000000 gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x20000000 + gNxpQoriqLsTokenSpaceGuid.PcdIfcBaseAddr|0x1530000 =20 # # Big Endian IPs # gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|TRUE gNxpQoriqLsTokenSpaceGuid.PcdWdogBigEndian|TRUE + gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian|TRUE =20 ## --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun May 5 06:05:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" From: Meenakshi Aggarwal NorFlashLib interacts with the underlying IFC NOR controller. This will be used by NOR driver for any information exchange with NOR controller. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Meenakshi Aggarwal --- Silicon/NXP/Include/Library/NorFlashLib.h | 77 +++ Silicon/NXP/Include/NorFlash.h | 48 ++ Silicon/NXP/Library/NorFlashLib/CfiCommand.h | 99 ++++ Silicon/NXP/Library/NorFlashLib/CfiNorFlashLib.c | 233 ++++++++ Silicon/NXP/Library/NorFlashLib/CfiNorFlashLib.h | 68 +++ Silicon/NXP/Library/NorFlashLib/NorFlashLib.c | 660 +++++++++++++++++++= ++++ Silicon/NXP/Library/NorFlashLib/NorFlashLib.inf | 41 ++ 7 files changed, 1226 insertions(+) create mode 100644 Silicon/NXP/Include/Library/NorFlashLib.h create mode 100644 Silicon/NXP/Include/NorFlash.h create mode 100644 Silicon/NXP/Library/NorFlashLib/CfiCommand.h create mode 100644 Silicon/NXP/Library/NorFlashLib/CfiNorFlashLib.c create mode 100644 Silicon/NXP/Library/NorFlashLib/CfiNorFlashLib.h create mode 100644 Silicon/NXP/Library/NorFlashLib/NorFlashLib.c create mode 100644 Silicon/NXP/Library/NorFlashLib/NorFlashLib.inf diff --git a/Silicon/NXP/Include/Library/NorFlashLib.h b/Silicon/NXP/Includ= e/Library/NorFlashLib.h new file mode 100644 index 0000000..defdc61 --- /dev/null +++ b/Silicon/NXP/Include/Library/NorFlashLib.h @@ -0,0 +1,77 @@ +/** @file + + Copyright (c) 2011-2012, ARM Ltd. All rights reserved. + Copyright (c) 2016, Freescale Semiconductor. All rights reserved. + Copyright 2017 NXP + +This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD= License + which accompanies this distribution. The full text of the license may be= found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPL= IED. + + **/ + +#ifndef _NOR_FLASH_LIB_H_ +#define _NOR_FLASH_LIB_H_ + +#include + +#define NOR_FLASH_DEVICE_COUNT 1 + +typedef struct { + UINTN DeviceBaseAddress; // Start address of the Device Base Address = (DBA) + UINTN RegionBaseAddress; // Start address of one single region + UINTN Size; + UINTN BlockSize; + UINTN MultiByteWordCount; // Maximum Word count that can be written to= Nor Flash in multi byte write + UINTN WordWriteTimeOut; // single byte/word timeout usec + UINTN BufferWriteTimeOut; // buffer write timeout usec + UINTN BlockEraseTimeOut; // block erase timeout usec + UINTN ChipEraseTimeOut; // chip erase timeout usec +} NorFlashDescription; + +EFI_STATUS +NorFlashPlatformGetDevices ( + OUT NorFlashDescription **NorFlashDevices, + OUT UINT32 *Count + ); + +EFI_STATUS +NorFlashPlatformFlashGetAttributes ( + OUT NorFlashDescription *NorFlashDevices, + IN UINT32 Count + ); + +EFI_STATUS +NorFlashPlatformWriteBuffer ( + IN NOR_FLASH_INSTANCE *Instance, + IN EFI_LBA Lba, + IN UINTN Offset, + IN OUT UINTN *NumBytes, + IN UINT8 *Buffer + ); + +EFI_STATUS +NorFlashPlatformEraseSector ( + IN NOR_FLASH_INSTANCE *Instance, + IN UINTN SectorAddress + ); + +EFI_STATUS +NorFlashPlatformRead ( + IN NOR_FLASH_INSTANCE *Instance, + IN EFI_LBA Lba, + IN UINTN Offset, + IN UINTN BufferSizeInBytes, + OUT UINT8 *Buffer + ); + +EFI_STATUS +NorFlashPlatformReset ( + IN UINTN Instance + ); + +#endif /* _NOR_FLASH_LIB_H_ */ diff --git a/Silicon/NXP/Include/NorFlash.h b/Silicon/NXP/Include/NorFlash.h new file mode 100644 index 0000000..888f5c1 --- /dev/null +++ b/Silicon/NXP/Include/NorFlash.h @@ -0,0 +1,48 @@ +/** @NorFlash.h + + Contains data structure shared by both NOR Library and Driver. + Copyright 2017 NXP + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#ifndef __NOR_FLASH_H__ +#define __NOR_FLASH_H__ + +#include +#include + +typedef struct _NOR_FLASH_INSTANCE NOR_FLASH_INSTANCE; +typedef EFI_STATUS (*NOR_FLASH_INITIALIZE) (NOR_FLASH_INSTANCE* Ins= tance); + +typedef struct { + VENDOR_DEVICE_PATH Vendor; + EFI_DEVICE_PATH_PROTOCOL End; +} NOR_FLASH_DEVICE_PATH; + +struct _NOR_FLASH_INSTANCE { + UINT32 Signature; + EFI_HANDLE Handle; + BOOLEAN Initialized; + NOR_FLASH_INITIALIZE Initialize; + UINTN DeviceBaseAddress; + UINTN RegionBaseAddress; + UINTN Size; + EFI_LBA StartLba; + EFI_BLOCK_IO_PROTOCOL BlockIoProtocol; + EFI_BLOCK_IO_MEDIA Media; + BOOLEAN SupportFvb; + EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL FvbProtocol; + VOID* ShadowBuffer; + NOR_FLASH_DEVICE_PATH DevicePath; +}; + + +#endif /* __NOR_FLASH_H__ */ diff --git a/Silicon/NXP/Library/NorFlashLib/CfiCommand.h b/Silicon/NXP/Lib= rary/NorFlashLib/CfiCommand.h new file mode 100644 index 0000000..8543227 --- /dev/null +++ b/Silicon/NXP/Library/NorFlashLib/CfiCommand.h @@ -0,0 +1,99 @@ +/** @CfiCommand.h + + Copyright 2017 NXP + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#ifndef __CFI_COMMAND_H__ +#define __CFI_COMMAND_H__ + +// CFI Data "QRY" +#define CFI_QRY_Q 0x51 +#define CFI_QRY_R 0x52 +#define CFI_QRY_Y 0x59 +#define CFI_QRY 0x515259 + +#define ENTER_CFI_QUERY_MODE_ADDR 0x0055 +#define ENTER_CFI_QUERY_MODE_CMD 0x0098 + +#define CFI_QUERY_UNIQUE_QRY_STRING 0x10 + +// Offsets for CFI queries +#define CFI_QUERY_TYP_TIMEOUT_WORD_WRITE 0x1F +#define CFI_QUERY_TYP_TIMEOUT_MAX_BUFFER_WRITE 0x20 +#define CFI_QUERY_TYP_TIMEOUT_BLOCK_ERASE 0x21 +#define CFI_QUERY_TYP_TIMEOUT_CHIP_ERASE 0x22 +#define CFI_QUERY_MAX_TIMEOUT_WORD_WRITE 0x23 +#define CFI_QUERY_MAX_TIMEOUT_MAX_BUFFER_WRITE 0x24 +#define CFI_QUERY_MAX_TIMEOUT_BLOCK_ERASE 0x25 +#define CFI_QUERY_MAX_TIMEOUT_CHIP_ERASE 0x26 +#define CFI_QUERY_DEVICE_SIZE 0x27 +#define CFI_QUERY_MAX_NUM_BYTES_WRITE 0x2A +#define CFI_QUERY_BLOCK_SIZE 0x2F + +// Unlock Address +#define CMD_UNLOCK_1_ADDR 0x555 +#define CMD_UNLOCK_2_ADDR 0x2AA + +// RESET Command +#define CMD_RESET_FIRST 0xAA +#define CMD_RESET_SECOND 0x55 +#define CMD_RESET 0xF0 + +// READ Command + +// Manufacturer ID +#define CMD_READ_M_ID_FIRST 0xAA +#define CMD_READ_M_ID_SECOND 0x55 +#define CMD_READ_M_ID_THIRD 0x90 +#define CMD_READ_M_ID_FOURTH 0x01 + +// Device ID +#define CMD_READ_D_ID_FIRST 0xAA +#define CMD_READ_D_ID_SECOND 0x55 +#define CMD_READ_D_ID_THIRD 0x90 +#define CMD_READ_D_ID_FOURTH 0x7E +#define CMD_READ_D_ID_FIFTH 0x13 +#define CMD_READ_D_ID_SIXTH 0x00 + +// WRITE Command + +// PROGRAM Command +#define CMD_PROGRAM_FIRST 0xAA +#define CMD_PROGRAM_SECOND 0x55 +#define CMD_PROGRAM_THIRD 0xA0 + +// Write Buffer Command +#define CMD_WRITE_TO_BUFFER_FIRST 0xAA +#define CMD_WRITE_TO_BUFFER_SECOND 0x55 +#define CMD_WRITE_TO_BUFFER_THIRD 0x25 +#define CMD_WRITE_TO_BUFFER_CONFIRM 0x29 + +// ERASE Command + +// UNLOCK COMMANDS FOR ERASE +#define CMD_ERASE_FIRST 0xAA +#define CMD_ERASE_SECOND 0x55 +#define CMD_ERASE_THIRD 0x80 +#define CMD_ERASE_FOURTH 0xAA +#define CMD_ERASE_FIFTH 0x55 + +// Chip Erase Command +#define CMD_CHIP_ERASE_SIXTH 0x10 + +// Sector Erase Command +#define CMD_SECTOR_ERASE_SIXTH 0x30 + +// SUSPEND Command +#define CMD_PROGRAM_OR_ERASE_SUSPEND 0xB0 +#define CMD_PROGRAM_OR_ERASE_RESUME 0x30 + +#endif // __CFI_COMMAND_H__ diff --git a/Silicon/NXP/Library/NorFlashLib/CfiNorFlashLib.c b/Silicon/NXP= /Library/NorFlashLib/CfiNorFlashLib.c new file mode 100644 index 0000000..632e943 --- /dev/null +++ b/Silicon/NXP/Library/NorFlashLib/CfiNorFlashLib.c @@ -0,0 +1,233 @@ +/** @CfiNorFlashLib.c + + Copyright (c) 2015, Freescale Semiconductor, Inc. All rights reserved. + Copyright 2017 NXP + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD= License + which accompanies this distribution. The full text of the license may be= found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPL= IED. + + **/ + +#include +#include +#include + +#include "CfiCommand.h" +#include "CfiNorFlashLib.h" + +FLASH_DATA +IfcNorFlashData ( + IN OUT FLASH_DATA Value + ) +{ + if (FixedPcdGetBool (PcdIfcBigEndian)) { + return SwapBytes16 (Value); + } else { + return Value; + } +} + +/** + Write Val at given address. + + @param Val Data to be written. + @param Addr Address where data is to be written. + +**/ +VOID +FlashWriteData ( + IN FLASH_DATA Val, + IN UINTN Addr + ) +{ + *(volatile FLASH_DATA *)(Addr) =3D (Val); +} + +/** + Check endianness of IFC Controller and depending on swap + the data and write on given address. + + @param Val Data to be written. + @param Addr Address where data is to be written. + +**/ +VOID +FlashWrite ( + IN FLASH_DATA Val, + IN UINTN Addr + ) +{ + FLASH_DATA ShiftVal; + + ShiftVal =3D IfcNorFlashData (Val); + + *(volatile FLASH_DATA *)(Addr) =3D (ShiftVal); +} + +/** + Read data from given address. + + @param Addr Address from where data is to be read. + + @return Read Data +**/ +FLASH_DATA +FlashReadData ( + IN UINTN Addr + ) +{ + FLASH_DATA Val; + + Val =3D *(volatile FLASH_DATA *)(Addr); + + return (Val); +} + +/** + Read data from given address and depending on endianness of IFC Controll= er + swap the read data. + + @param Addr Address from where data is to be read. + + @return Read Data +**/ +FLASH_DATA +FlashRead ( + IN UINTN Addr + ) +{ + FLASH_DATA Val; + FLASH_DATA ShiftVal; + + Val =3D *(volatile FLASH_DATA *)(Addr); + ShiftVal =3D IfcNorFlashData (Val); + + return (ShiftVal); +} + +STATIC +VOID +NorFlashReadCfiData ( + IN UINTN DeviceBaseAddress, + IN UINTN CfiOffset, + IN UINT32 NumberOfShorts, + OUT VOID *Data + ) +{ + UINT32 Count; + FLASH_DATA *TmpData =3D (FLASH_DATA *)Data; + + for (Count =3D 0; Count < NumberOfShorts; Count++, TmpData++) { + *TmpData =3D FLASH_READ ((UINTN)((FLASH_DATA*)DeviceBaseAddress + CfiO= ffset)); + CfiOffset++; + } +} + +/* + Currently we support only CFI flash devices; Bail-out otherwise +*/ +EFI_STATUS +CfiNorFlashFlashGetAttributes ( + OUT NorFlashDescription *NorFlashDevices, + IN UINT32 Index + ) +{ + UINT32 Count; + FLASH_DATA QryData[3]; + FLASH_DATA BlockSize[2]; + UINTN DeviceBaseAddress; + FLASH_DATA MaxNumBytes[2]; + FLASH_DATA Size; + FLASH_DATA HighByteMask; // Masks High byte in a UIN16 wo= rd + FLASH_DATA HighByteShift; // Bitshifts needed to make a by= te High Byte in a UIN16 word + FLASH_DATA Temp1; + FLASH_DATA Temp2; + + HighByteMask =3D 0xFF; + HighByteShift =3D 8; + + for (Count =3D 0; Count < Index; Count++) { + + NorFlashDevices[Count].DeviceBaseAddress =3D DeviceBaseAddress =3D Pcd= Get64 (PcdFlashDeviceBase64); + + // Reset flash first + NorFlashPlatformReset (DeviceBaseAddress); + + // Enter the CFI Query Mode + SEND_NOR_COMMAND (DeviceBaseAddress, ENTER_CFI_QUERY_MODE_ADDR, + ENTER_CFI_QUERY_MODE_CMD); + + ArmDataSynchronizationBarrier (); + + // Query the unique QRY + NorFlashReadCfiData (DeviceBaseAddress, + CFI_QUERY_UNIQUE_QRY_STRING, + 3, + &QryData); + if (QryData[0] !=3D (FLASH_DATA)CFI_QRY_Q || QryData[1] !=3D + (FLASH_DATA)CFI_QRY_R || QryData[2] !=3D (FLASH_DATA)CFI_QRY_Y= ) { + DEBUG ((DEBUG_ERROR, "Not a CFI flash (QRY not recvd): " + "Got =3D 0x%04x, 0x%04x, 0x%04x\n", + QryData[0], QryData[1], QryData[2])); + return EFI_DEVICE_ERROR; + } + + NorFlashReadCfiData (DeviceBaseAddress, CFI_QUERY_DEVICE_SIZE, + 1, &Size); + // Refer CFI Specification + NorFlashDevices[Count].Size =3D 1 << Size; + + NorFlashReadCfiData (DeviceBaseAddress, CFI_QUERY_BLOCK_SIZE, + 2, &BlockSize); + // Refer CFI Specification + NorFlashDevices[Count].BlockSize =3D 256 * ((FLASH_DATA) ((BlockSize[1= ] << + HighByteShift) | (BlockSize[0] & HighByteMask))); + + NorFlashReadCfiData (DeviceBaseAddress, + CFI_QUERY_MAX_NUM_BYTES_WRITE, 2, &MaxNumBytes); + // Refer CFI Specification + /* from CFI query we get the Max. number of BYTE in multi-byte write = =3D 2^N. + But our Flash Library is able to read/write in WORD size (2 bytes) = which + is why we need to CONVERT MAX BYTES TO MAX WORDS by diving it by + width of word size */ + NorFlashDevices[Count].MultiByteWordCount =3D\ + (1 << ((FLASH_DATA)((MaxNumBytes[1] << HighByteShift) | + (MaxNumBytes[0] & HighByteMask))))/sizeof(FLASH_DA= TA); + + NorFlashReadCfiData (DeviceBaseAddress, + CFI_QUERY_TYP_TIMEOUT_WORD_WRITE, 1, &Temp1); + NorFlashReadCfiData (DeviceBaseAddress, + CFI_QUERY_MAX_TIMEOUT_WORD_WRITE, 1, &Temp2); + NorFlashDevices[Count].WordWriteTimeOut =3D (1U << Temp1) * (1U << Tem= p2); + + NorFlashReadCfiData (DeviceBaseAddress, + CFI_QUERY_TYP_TIMEOUT_MAX_BUFFER_WRITE, 1, &Temp1); + NorFlashReadCfiData (DeviceBaseAddress, + CFI_QUERY_MAX_TIMEOUT_MAX_BUFFER_WRITE, 1, &Temp2); + NorFlashDevices[Count].BufferWriteTimeOut =3D (1U << Temp1) * (1U << T= emp2); + + NorFlashReadCfiData (DeviceBaseAddress, + CFI_QUERY_TYP_TIMEOUT_BLOCK_ERASE, 1, &Temp1); + NorFlashReadCfiData (DeviceBaseAddress, + CFI_QUERY_MAX_TIMEOUT_BLOCK_ERASE, 1, &Temp2); + NorFlashDevices[Count].BlockEraseTimeOut =3D + (1U << Temp1) * (1U << Temp2) * 1000; + + NorFlashReadCfiData (DeviceBaseAddress, + CFI_QUERY_TYP_TIMEOUT_CHIP_ERASE, 1, &Temp1); + NorFlashReadCfiData (DeviceBaseAddress, + CFI_QUERY_MAX_TIMEOUT_CHIP_ERASE, 1, &Temp2); + NorFlashDevices[Count].ChipEraseTimeOut =3D + (1U << Temp1) * (1U << Temp2) * 1000; + + // Put device back into Read Array mode (via Reset) + NorFlashPlatformReset (DeviceBaseAddress); + } + + return EFI_SUCCESS; +} diff --git a/Silicon/NXP/Library/NorFlashLib/CfiNorFlashLib.h b/Silicon/NXP= /Library/NorFlashLib/CfiNorFlashLib.h new file mode 100644 index 0000000..91d50f0 --- /dev/null +++ b/Silicon/NXP/Library/NorFlashLib/CfiNorFlashLib.h @@ -0,0 +1,68 @@ +/** @CfiNorFlashLib.h + + Copyright (c) 2015, Freescale Semiconductor, Inc. All rights reserved. + Copyright 2017 NXP + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#ifndef __CFI_NOR_FLASH_LIB_H__ +#define __CFI_NOR_FLASH_LIB_H__ + +#include +#include + +/* + * Values for the width of the port + */ +#define FLASH_CFI_8BIT 0x01 +#define FLASH_CFI_16BIT 0x02 +#define FLASH_CFI_32BIT 0x04 +#define FLASH_CFI_64BIT 0x08 + +#define CREATE_BYTE_OFFSET(OffsetAddr) ((sizeof (FLASH_DATA)= ) * (OffsetAddr)) +#define CREATE_NOR_ADDRESS(BaseAddr, OffsetAddr) ((BaseAddr) + (Offset= Addr)) +#define FLASH_READ(Addr) FlashRead ((Addr)) +#define FLASH_WRITE(Addr, Val) FlashWrite ((Val), (A= ddr)) +#define FLASH_READ_DATA(Addr) FlashReadData ((Addr)) +#define FLASH_WRITE_DATA(Addr, Val) FlashWriteData ((Val)= , (Addr)) +#define SEND_NOR_COMMAND(BaseAddr, Offset, Cmd) FLASH_WRITE (CREATE_N= OR_ADDRESS (BaseAddr, CREATE_BYTE_OFFSET (Offset)), (Cmd)) + +typedef UINT16 FLASH_DATA; + +VOID +FlashWrite ( + IN FLASH_DATA Val, + IN UINTN Addr + ); + +FLASH_DATA +FlashRead ( + IN UINTN Addr + ); + +VOID +FlashWriteData ( + IN FLASH_DATA Val, + IN UINTN Addr + ); + +FLASH_DATA +FlashReadData ( + IN UINTN Addr + ); + +EFI_STATUS +CfiNorFlashFlashGetAttributes ( + OUT NorFlashDescription *NorFlashDevices, + IN UINT32 Index + ); + +#endif //__CFI_NOR_FLASH_LIB_H__ diff --git a/Silicon/NXP/Library/NorFlashLib/NorFlashLib.c b/Silicon/NXP/Li= brary/NorFlashLib/NorFlashLib.c new file mode 100644 index 0000000..b74e9eb --- /dev/null +++ b/Silicon/NXP/Library/NorFlashLib/NorFlashLib.c @@ -0,0 +1,660 @@ +/** @NorFlashLib.c + + Based on NorFlash implementation available in NorFlashDxe.c + + Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved. + Copyright (c) 2015, Freescale Semiconductor, Inc. All rights reserved. + Copyright 2017 NXP + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include +#include +#include + +#include "CfiCommand.h" +#include "CfiNorFlashLib.h" + +#define GET_BLOCK_OFFSET(Lba) ((Instance->RegionBaseAddress)-\ + (Instance->DeviceBaseAddress)+((UINTN)((Lba= ) * Instance->Media.BlockSize))) + +NorFlashDescription mNorFlashDevices[NOR_FLASH_DEVICE_COUNT]; + +STATIC VOID +UnlockEraseAddress ( + IN UINTN DeviceBaseAddress + ) +{ // Issue the Unlock cmds + SEND_NOR_COMMAND (DeviceBaseAddress, CMD_UNLOCK_1_ADDR, + CMD_ERASE_FIRST); + + SEND_NOR_COMMAND (DeviceBaseAddress, CMD_UNLOCK_2_ADDR, + CMD_ERASE_SECOND); + + // Issue a setup command + SEND_NOR_COMMAND (DeviceBaseAddress, CMD_UNLOCK_1_ADDR, + CMD_ERASE_THIRD); + + // Issue the Unlock cmds + SEND_NOR_COMMAND (DeviceBaseAddress, CMD_UNLOCK_1_ADDR, + CMD_ERASE_FOURTH); + + SEND_NOR_COMMAND (DeviceBaseAddress, CMD_UNLOCK_2_ADDR, + CMD_ERASE_FIFTH); + + return; +} + +STATIC +UINT64 +ConvertMicroSecondsToTicks ( + IN UINTN MicroSeconds + ) +{ + UINT64 TimerTicks64; + + TimerTicks64 =3D 0; + + // Calculate counter ticks that represent requested delay: + // =3D MicroSeconds x TICKS_PER_MICRO_SEC + // =3D MicroSeconds x Timer Frequency(in Hz) x 10^-6 + // GetPerformanceCounterProperties =3D Get Arm Timer Frequency in Hz + TimerTicks64 =3D DivU64x32 ( + MultU64x64 ( + MicroSeconds, + GetPerformanceCounterProperties (NULL, NULL) + ), + 1000000U + ); + return TimerTicks64; +} + +/** + * The following function erases a NOR flash sector. + **/ +EFI_STATUS +NorFlashPlatformEraseSector ( + IN NOR_FLASH_INSTANCE *Instance, + IN UINTN SectorAddress + ) +{ + FLASH_DATA EraseStatus1; + FLASH_DATA EraseStatus2; + UINT64 Timeout; + UINT64 SystemCounterVal; + + EraseStatus1 =3D 0; + EraseStatus2 =3D 0; + Timeout =3D 0; + + Timeout =3D ConvertMicroSecondsToTicks ( + mNorFlashDevices[Instance->Media.MediaId].BlockEraseTim= eOut); + // Request a sector erase by writing two unlock cycles, followed by a + // setup command and two additional unlock cycles + + UnlockEraseAddress (Instance->DeviceBaseAddress); + + // Now send the address of the sector to be erased + SEND_NOR_COMMAND (SectorAddress, 0, CMD_SECTOR_ERASE_SIXTH); + + // Wait for erase to complete + // Read Sector start address twice to detect bit toggle and to + // determine ERASE DONE (all bits are 1) + // Get the maximum timer ticks needed to complete the operation + // Check if operation is complete or not in continous loop? + // if complete, exit from loop + // if not check the ticks that have been passed from the begining of loop + // if Maximum Ticks allocated for operation has passed exit from loop + + SystemCounterVal =3D GetPerformanceCounter (); + Timeout +=3D SystemCounterVal; + while (SystemCounterVal < Timeout) { + if ((EraseStatus1 =3D FLASH_READ (SectorAddress)) =3D=3D + (EraseStatus2 =3D FLASH_READ (SectorAddress))) { + if (0xFFFF =3D=3D FLASH_READ (SectorAddress)) { + break; + } + } + SystemCounterVal =3D GetPerformanceCounter (); + } + + if (SystemCounterVal >=3D Timeout) { + DEBUG ((DEBUG_ERROR, "%a :Failed to Erase @ SectorAddress 0x%p, Timeou= t\n", + __FUNCTION__, SectorAddress)); + return EFI_DEVICE_ERROR; + } else { + return EFI_SUCCESS; + } +} + +EFI_STATUS +NorFlashPlatformWriteWord ( + IN NOR_FLASH_INSTANCE *Instance, + IN UINTN WordOffset, + IN FLASH_DATA Word + ) +{ + UINT64 Timeout; + UINTN TargetAddress; + UINT64 SystemCounterVal; + FLASH_DATA Read1; + FLASH_DATA Read2; + + Timeout =3D 0; + + Timeout =3D ConvertMicroSecondsToTicks ( + mNorFlashDevices[Instance->Media.MediaId].WordWriteTimeOut); + + TargetAddress =3D CREATE_NOR_ADDRESS (Instance->DeviceBaseAddress, + CREATE_BYTE_OFFSET (WordOffset)); + + // Issue the Unlock cmds + SEND_NOR_COMMAND (Instance->DeviceBaseAddress, CMD_UNLOCK_1_ADDR, + CMD_PROGRAM_FIRST); + + SEND_NOR_COMMAND (Instance->DeviceBaseAddress, CMD_UNLOCK_2_ADDR, + CMD_PROGRAM_SECOND); + + SEND_NOR_COMMAND (Instance->DeviceBaseAddress, CMD_UNLOCK_1_ADDR, + CMD_PROGRAM_THIRD); + + FLASH_WRITE_DATA (TargetAddress, Word); + + // Wait for Write to Complete + // Read the last written address twice to detect bit toggle and + // to determine if date is wriiten successfully or not ? + // Get the maximum timer ticks needed to complete the operation + // Check if operation is complete or not in continous loop? + // if complete, exit from loop + // if not check the ticks that have been passed from the begining of loop + // if Maximum Ticks allocated for operation has passed, then exit from l= oop + + SystemCounterVal =3D GetPerformanceCounter (); + Timeout +=3D SystemCounterVal; + while (SystemCounterVal < Timeout) { + if ((Read1 =3D FLASH_READ_DATA (TargetAddress)) =3D=3D + (Read2 =3D FLASH_READ_DATA (TargetAddress))) { + if (Word =3D=3D FLASH_READ_DATA (TargetAddress)) { + break; + } + } + SystemCounterVal =3D GetPerformanceCounter (); + } + + if (SystemCounterVal >=3D Timeout) { + DEBUG ((DEBUG_ERROR, "%a: Failed to Write @ TargetAddress 0x%p, Timeo= ut\n", + __FUNCTION__, TargetAddress)); + return EFI_DEVICE_ERROR; + } else { + return EFI_SUCCESS; + } +} + +EFI_STATUS +NorFlashPlatformWritePageBuffer ( + IN NOR_FLASH_INSTANCE *Instance, + IN UINTN PageBufferOffset, + IN UINTN NumWords, + IN FLASH_DATA *Buffer + ) +{ + UINT64 Timeout; + UINTN LastWrittenAddress; + FLASH_DATA LastWritenData; + UINTN CurrentOffset; + UINTN EndOffset; + UINTN TargetAddress; + UINT64 SystemCounterVal; + FLASH_DATA Read1; + FLASH_DATA Read2; + + // Initialize variables + Timeout =3D 0; + LastWrittenAddress =3D 0; + LastWritenData =3D 0; + CurrentOffset =3D PageBufferOffset; + EndOffset =3D PageBufferOffset + NumWords - 1; + Timeout =3D ConvertMicroSecondsToTicks ( + mNorFlashDevices[Instance->Media.MediaId].BufferWriteTim= eOut); + TargetAddress =3D CREATE_NOR_ADDRESS (Instance->DeviceBaseAddress, + CREATE_BYTE_OFFSET (CurrentOffset)); + + // don't try with a count of zero + if (!NumWords) { + return EFI_SUCCESS; + } + else if (NumWords =3D=3D 1) { + return NorFlashPlatformWriteWord (Instance, PageBufferOffset, *Buffer); + } + + // Issue the Unlock cmds + SEND_NOR_COMMAND (Instance->DeviceBaseAddress, CMD_UNLOCK_1_ADDR, + CMD_WRITE_TO_BUFFER_FIRST); + + SEND_NOR_COMMAND (Instance->DeviceBaseAddress, CMD_UNLOCK_2_ADDR, + CMD_WRITE_TO_BUFFER_SECOND); + + // Write the buffer load + SEND_NOR_COMMAND (TargetAddress, 0, CMD_WRITE_TO_BUFFER_THIRD); + + // Write # of locations to program + SEND_NOR_COMMAND (TargetAddress, 0, (NumWords - 1)); + + // Load Data into Buffer + while (CurrentOffset <=3D EndOffset) { + LastWrittenAddress =3D CREATE_NOR_ADDRESS (Instance->DeviceBaseAddress, + CREATE_BYTE_OFFSET (CurrentOffset++)); + LastWritenData =3D *Buffer++; + + // Write Data + FLASH_WRITE_DATA (LastWrittenAddress,LastWritenData); + } + + // Issue the Buffered Program Confirm command + SEND_NOR_COMMAND (TargetAddress, 0, CMD_WRITE_TO_BUFFER_CONFIRM); + + /* Wait for Write to Complete + Read the last written address twice to detect bit toggle and + to determine if date is wriiten successfully or not ? + Get the maximum timer ticks needed to complete the operation + Check if operation is complete or not in continous loop? + if complete, exit from loop + if not check the ticks that have been passed from the begining of loop + if Maximum Ticks allocated for operation has passed, then exit from l= oop **/ + SystemCounterVal =3D GetPerformanceCounter(); + Timeout +=3D SystemCounterVal; + while (SystemCounterVal < Timeout) { + if ((Read1 =3D FLASH_READ_DATA (LastWrittenAddress)) =3D=3D + (Read2 =3D FLASH_READ_DATA (LastWrittenAddress))) { + if (LastWritenData =3D=3D FLASH_READ_DATA (LastWrittenAddress)) { + break; + } + } + SystemCounterVal =3D GetPerformanceCounter (); + } + + if (SystemCounterVal >=3D Timeout) { + DEBUG ((DEBUG_ERROR, "%a: Failed to Write @LastWrittenAddress 0x%p, Ti= meout\n", + __FUNCTION__, LastWrittenAddress)); + return EFI_DEVICE_ERROR; + } else { + return EFI_SUCCESS; + } +} + +EFI_STATUS +NorFlashPlatformWriteWordAlignedAddressBuffer ( + IN NOR_FLASH_INSTANCE *Instance, + IN UINTN Offset, + IN UINTN NumWords, + IN FLASH_DATA *Buffer + ) +{ + EFI_STATUS Status; + UINTN MultiByteWordCount; + UINTN Mask; + UINTN IntWords; + + MultiByteWordCount =3D mNorFlashDevices[Instance->Media.MediaId].MultiBy= teWordCount; + Mask =3D MultiByteWordCount - 1; + IntWords =3D NumWords; + Status =3D EFI_SUCCESS; + + if (Offset & Mask) { + // program only as much as necessary, so pick the lower of the two num= bers + if (NumWords < (MultiByteWordCount - (Offset & Mask))) { + IntWords =3D NumWords; + } else { + IntWords =3D MultiByteWordCount - (Offset & Mask); + } + + // program the first few to get write buffer aligned + Status =3D NorFlashPlatformWritePageBuffer (Instance, Offset, IntWords= , Buffer); + if (EFI_ERROR (Status)) { + return Status; + } + + Offset +=3D IntWords; // adjust pointers and counter + NumWords -=3D IntWords; + Buffer +=3D IntWords; + + if (NumWords =3D=3D 0) { + return Status; + } + } + + while (NumWords >=3D MultiByteWordCount) {// while big chunks to do + Status =3D NorFlashPlatformWritePageBuffer (Instance, Offset, + MultiByteWordCount, Buffer); + if (EFI_ERROR (Status)) { + return (Status); + } + + Offset +=3D MultiByteWordCount; // adjust pointers and counter + NumWords -=3D MultiByteWordCount; + Buffer +=3D MultiByteWordCount; + } + if (NumWords =3D=3D 0) { + return (Status); + } + + Status =3D NorFlashPlatformWritePageBuffer (Instance, Offset, NumWords, = Buffer); + return (Status); +} + +/** + Writes data to the NOR Flash using the Buffered Programming method. + + Write Buffer Programming allows the system to write a maximum of 32 bytes + in one programming operation. Therefore this function will only handle + buffers up to 32 bytes. + To deal with larger buffers, call this function again. +**/ +EFI_STATUS +NorFlashPlatformWriteBuffer ( + IN NOR_FLASH_INSTANCE *Instance, + IN EFI_LBA Lba, + IN UINTN Offset, + IN OUT UINTN *NumBytes, + IN UINT8 *Buffer + ) +{ + EFI_STATUS Status; + FLASH_DATA *SrcBuffer; + UINTN TargetOffsetinBytes; + UINTN WordsToWrite; + UINTN Mask; + UINTN BufferSizeInBytes; + UINTN IntBytes; + UINT8 *CopyFrom; + UINT8 *CopyTo; + FLASH_DATA TempWrite; + + SrcBuffer =3D (FLASH_DATA *)Buffer; + TargetOffsetinBytes =3D 0; + WordsToWrite =3D 0; + Mask =3D sizeof (FLASH_DATA) - 1; + BufferSizeInBytes =3D *NumBytes; + IntBytes =3D BufferSizeInBytes; // Intermediate Bytes needed to copy for= alignment + TempWrite =3D 0; + + DEBUG ((DEBUG_BLKIO, "%a(Parameters: Lba=3D%ld, Offset=3D0x%x, " + "*NumBytes=3D0x%x, Buffer @ 0x%08x)\n", + __FUNCTION__, Lba, Offset, *NumBytes, Buffer)); + + TargetOffsetinBytes =3D GET_BLOCK_OFFSET (Lba) + (UINTN)(Offset); + + if (TargetOffsetinBytes & Mask) { + // Write only as much as necessary, so pick the lower of the two numbe= rs + // and call it Intermediate bytes to write to make alignment proper + if (BufferSizeInBytes < (sizeof (FLASH_DATA) - (TargetOffsetinBytes & = Mask))) { + IntBytes =3D BufferSizeInBytes; + } else { + IntBytes =3D sizeof (FLASH_DATA) - (TargetOffsetinBytes & Mask); + } + + // Read the first few to get Read buffer aligned + NorFlashPlatformRead (Instance, Lba, (TargetOffsetinBytes & ~Mask) - + GET_BLOCK_OFFSET (Lba), sizeof (TempWrite), (UINT8*)&TempWrite= ); + + CopyTo =3D (UINT8*)&TempWrite; + CopyTo +=3D (TargetOffsetinBytes & Mask); + CopyFrom =3D (UINT8*)Buffer; + + InternalMemCopyMem (CopyTo, CopyFrom, IntBytes); + + Status =3D NorFlashPlatformWriteWordAlignedAddressBuffer ( + Instance, + (UINTN)((TargetOffsetinBytes & ~Mask) / sizeof (FLA= SH_DATA)), + 1, + &TempWrite); + if (EFI_ERROR (Status)) { + DEBUG((DEBUG_ERROR, "%a : Failed to Write @TargetOffset 0x%x (0x%x)\= n", + __FUNCTION__, TargetOffsetinBytes, Status)); + goto EXIT; + } + + TargetOffsetinBytes +=3D IntBytes; /* adjust pointers and counter */ + BufferSizeInBytes -=3D IntBytes; + Buffer +=3D IntBytes; + + if (BufferSizeInBytes =3D=3D 0) { + goto EXIT; + } + } + + // Write the bytes to CFI width aligned address. + // Note we can Write number of bytes=3DCFI width in one operation + WordsToWrite =3D BufferSizeInBytes/sizeof (FLASH_DATA); + SrcBuffer =3D (FLASH_DATA*)Buffer; + + Status =3D NorFlashPlatformWriteWordAlignedAddressBuffer ( + Instance, + (UINTN)(TargetOffsetinBytes/sizeof (FLASH_DATA)), + WordsToWrite, + SrcBuffer); + if (EFI_ERROR(Status)) { + DEBUG((DEBUG_ERROR, "%a : Failed to Write @ TargetOffset 0x%x (0x%x)\n= ", + __FUNCTION__, TargetOffsetinBytes, Status)); + goto EXIT; + } + + BufferSizeInBytes -=3D (WordsToWrite * sizeof (FLASH_DATA)); + Buffer +=3D (WordsToWrite*sizeof (FLASH_DATA)); + TargetOffsetinBytes +=3D (WordsToWrite * sizeof (FLASH_DATA)); + + if (BufferSizeInBytes =3D=3D 0) { + goto EXIT; + } + + // Now Write bytes that are remaining and are less than CFI width. + // Read the first few to get Read buffer aligned + NorFlashPlatformRead ( + Instance, + Lba, + TargetOffsetinBytes - GET_BLOCK_OFFSET (Lba), + sizeof (TempWrite), + (UINT8*)&TempWrite); + + CopyFrom =3D (UINT8*)Buffer; + CopyTo =3D (UINT8*)&TempWrite; + + InternalMemCopyMem (CopyTo, CopyFrom, BufferSizeInBytes); + + Status =3D NorFlashPlatformWriteWordAlignedAddressBuffer (Instance, + (UINTN)(TargetOffsetinBytes/sizeof (FLASH_DATA= )), + 1, + &TempWrite); + if (EFI_ERROR(Status)) { + DEBUG((DEBUG_ERROR, "%a: Failed to Write @TargetOffset 0x%x Status=3D%= d\n", + __FUNCTION__, TargetOffsetinBytes, Status)); + goto EXIT; + } + +EXIT: + // Put device back into Read Array mode (via Reset) + NorFlashPlatformReset (Instance->DeviceBaseAddress); + return (Status); +} + +EFI_STATUS +NorFlashPlatformRead ( + IN NOR_FLASH_INSTANCE *Instance, + IN EFI_LBA Lba, + IN UINTN Offset, + IN UINTN BufferSizeInBytes, + OUT UINT8 *Buffer + ) +{ + UINTN IntBytes; + UINTN Mask; + FLASH_DATA TempRead; + UINT8 *CopyFrom; + UINT8 *CopyTo; + UINTN TargetOffsetinBytes; + FLASH_DATA *ReadData; + UINTN BlockSize; + + IntBytes =3D BufferSizeInBytes; //Intermediate Bytes needed to copy for = alignment + Mask =3D sizeof (FLASH_DATA) - 1; + TempRead =3D 0; + TargetOffsetinBytes =3D (UINTN)(GET_BLOCK_OFFSET (Lba) + Offset); + BlockSize =3D Instance->Media.BlockSize; + + DEBUG ((DEBUG_BLKIO, "%a(Parameters: Lba=3D%ld, Offset=3D0x%x," + " BufferSizeInBytes=3D0x%x, Buffer @ 0x%p)\n", + __FUNCTION__, Lba, Offset, BufferSizeInBytes, Buffer)); + + // The buffer must be valid + if (Buffer =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + // Return if we have not any byte to read + if (BufferSizeInBytes =3D=3D 0) { + return EFI_SUCCESS; + } + + if (((Lba * BlockSize) + BufferSizeInBytes) > Instance->Size) { + DEBUG ((DEBUG_ERROR, "%a : Read will exceed device size.\n", __FUNCTIO= N__)); + return EFI_INVALID_PARAMETER; + } + + // Put device back into Read Array mode (via Reset) + NorFlashPlatformReset (Instance->DeviceBaseAddress); + + // First Read bytes to make buffer aligned to CFI width + if (TargetOffsetinBytes & Mask) { + // Read only as much as necessary, so pick the lower of the two numbers + if (BufferSizeInBytes < (sizeof (FLASH_DATA) - (TargetOffsetinBytes & = Mask))) { + IntBytes =3D BufferSizeInBytes; + } else { + IntBytes =3D sizeof (FLASH_DATA) - (TargetOffsetinBytes & Mask); + } + + // Read the first few to get Read buffer aligned + TempRead =3D FLASH_READ_DATA (CREATE_NOR_ADDRESS ( + Instance->DeviceBaseAddress, + CREATE_BYTE_OFFSET ((TargetOffsetinBytes & ~Mask)/siz= eof (FLASH_DATA)))); + + CopyFrom =3D (UINT8*)&TempRead; + CopyFrom +=3D (TargetOffsetinBytes & Mask); + CopyTo =3D (UINT8*)Buffer; + + InternalMemCopyMem (CopyTo, CopyFrom, IntBytes); + + TargetOffsetinBytes +=3D IntBytes; // adjust pointers and counter + BufferSizeInBytes -=3D IntBytes; + Buffer +=3D IntBytes; + if (BufferSizeInBytes =3D=3D 0) { + return EFI_SUCCESS; + } + } + + ReadData =3D (FLASH_DATA*)Buffer; + + // Readout the bytes from CFI width aligned address. + // Note we can read number of bytes=3DCFI width in one operation + while (BufferSizeInBytes >=3D sizeof (FLASH_DATA)) { + *ReadData =3D FLASH_READ_DATA (CREATE_NOR_ADDRESS ( + Instance->DeviceBaseAddress, + CREATE_BYTE_OFFSET (TargetOffsetinBytes/sizeof (FLASH= _DATA)))); + ReadData +=3D 1; + BufferSizeInBytes -=3D sizeof (FLASH_DATA); + TargetOffsetinBytes +=3D sizeof (FLASH_DATA); + } + + if (BufferSizeInBytes =3D=3D 0) { + return EFI_SUCCESS; + } + + // Now read bytes that are remaining and are less than CFI width. + CopyTo =3D (UINT8*)ReadData; + // Read the first few to get Read buffer aligned + TempRead =3D FLASH_READ_DATA (CREATE_NOR_ADDRESS ( + Instance->DeviceBaseAddress, + CREATE_BYTE_OFFSET (TargetOffsetinBytes/sizeof (FLASH= _DATA)))); + CopyFrom =3D (UINT8*)&TempRead; + + InternalMemCopyMem (CopyTo, CopyFrom, BufferSizeInBytes); + + return EFI_SUCCESS; +} + +EFI_STATUS +NorFlashPlatformReset ( + IN UINTN DeviceBaseAddress + ) +{ + SEND_NOR_COMMAND (DeviceBaseAddress, CMD_UNLOCK_1_ADDR, + CMD_RESET_FIRST); + + SEND_NOR_COMMAND (DeviceBaseAddress, CMD_UNLOCK_2_ADDR, + CMD_RESET_SECOND); + + SEND_NOR_COMMAND (DeviceBaseAddress, 0, CMD_RESET); + + return EFI_SUCCESS; +} + +EFI_STATUS +NorFlashPlatformGetDevices ( + OUT NorFlashDescription **NorFlashDevices, + OUT UINT32 *Count + ) +{ + if ((NorFlashDevices =3D=3D NULL) || (Count =3D=3D NULL)) { + return EFI_INVALID_PARAMETER; + } + + // Get the number of NOR flash devices supported + *NorFlashDevices =3D mNorFlashDevices; + *Count =3D NOR_FLASH_DEVICE_COUNT; + + return EFI_SUCCESS; +} + +EFI_STATUS +NorFlashPlatformFlashGetAttributes ( + OUT NorFlashDescription *NorFlashDevices, + IN UINT32 Count + ) +{ + EFI_STATUS Status; + UINT32 Index; + + if ((NorFlashDevices =3D=3D NULL) || (Count =3D=3D 0)) { + return EFI_INVALID_PARAMETER; + } + + // Check the attributes of the NOR flash slave we are connected to. + // Currently we support only CFI flash devices. Bail-out otherwise. + Status =3D CfiNorFlashFlashGetAttributes (NorFlashDevices, Count); + if (EFI_ERROR (Status)) { + return Status; + } + + // Limit the Size of Nor Flash that can be programmed + for (Index =3D 0; Index < Count; Index++) { + NorFlashDevices[Index].RegionBaseAddress =3D PcdGet64 (PcdFlashReserve= dRegionBase64); + NorFlashDevices[Index].Size -=3D (NorFlashDevices[Index].RegionBaseAdd= ress - + NorFlashDevices[Index].DeviceBaseAddre= ss); + if((NorFlashDevices[Index].RegionBaseAddress - NorFlashDevices[Index].= DeviceBaseAddress) % + NorFlashDevices[Index].BlockSize) { + DEBUG ((DEBUG_ERROR, "%a : Reserved Region(0x%p) doesn't start " + "from block boundry(0x%08x)\n", __FUNCTION__, + (UINTN)NorFlashDevices[Index].RegionBaseAddress, + (UINT32)NorFlashDevices[Index].BlockSize)); + return EFI_DEVICE_ERROR; + } + } + return Status; +} diff --git a/Silicon/NXP/Library/NorFlashLib/NorFlashLib.inf b/Silicon/NXP/= Library/NorFlashLib/NorFlashLib.inf new file mode 100644 index 0000000..403766a --- /dev/null +++ b/Silicon/NXP/Library/NorFlashLib/NorFlashLib.inf @@ -0,0 +1,41 @@ +# @NorFlashLib.inf +# +# Component description file for NorFlashLib module +# +# Copyright 2017 NXP +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D NorFlashLib + FILE_GUID =3D f3176a49-dde1-450d-a909-8580c03b9ba8 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D NorFlashLib + +[Sources.common] + NorFlashLib.c + CfiNorFlashLib.c + +[LibraryClasses] + ArmLib + TimerLib + +[Packages] + ArmPkg/ArmPkg.dec + MdePkg/MdePkg.dec + Silicon/NXP/NxpQoriqLs.dec + +[Pcd.common] + gNxpQoriqLsTokenSpaceGuid.PcdFlashDeviceBase64 + gNxpQoriqLsTokenSpaceGuid.PcdFlashReservedRegionBase64 + gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian + gNxpQoriqLsTokenSpaceGuid.PcdIfcNandReservedSize --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun May 5 06:05:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Meenakshi Aggarwal Add NOR DXE phase driver, it installs BlockIO and Fvp protocol. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Meenakshi Aggarwal --- Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc | 98 +++ .../NXP/Drivers/NorFlashDxe/NorFlashBlockIoDxe.c | 258 +++++++ Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.c | 438 +++++++++++ Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.h | 146 ++++ Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf | 66 ++ Silicon/NXP/Drivers/NorFlashDxe/NorFlashFvbDxe.c | 805 +++++++++++++++++= ++++ 6 files changed, 1811 insertions(+) create mode 100644 Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc create mode 100644 Silicon/NXP/Drivers/NorFlashDxe/NorFlashBlockIoDxe.c create mode 100644 Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.c create mode 100644 Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.h create mode 100644 Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf create mode 100644 Silicon/NXP/Drivers/NorFlashDxe/NorFlashFvbDxe.c diff --git a/Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc b/Platform/NXP/LS1= 043aRdbPkg/VarStore.fdf.inc new file mode 100644 index 0000000..e254337 --- /dev/null +++ b/Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc @@ -0,0 +1,98 @@ +## @file +# FDF include file with FD definition that defines an empty variable stor= e. +# +# Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved. +# Copyright (C) 2014, Red Hat, Inc. +# Copyright (c) 2016, Linaro, Ltd. All rights reserved. +# Copyright (c) 2016, Freescale Semiconductor. All rights reserved. +# Copyright 2017 NXP +# +# This program and the accompanying materials are licensed and made avail= able +# under the terms and conditions of the BSD License which accompanies this +# distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR +# IMPLIED. +# +## + +[FD.LS1043aRdbNv_EFI] +BaseAddress =3D 0x60300000 #The base address of the FLASH device +Size =3D 0x000C0000 #The size in bytes of the FLASH device +ErasePolarity =3D 1 +BlockSize =3D 0x1 +NumBlocks =3D 0xC0000 + +# +# Place NV Storage just above Platform Data Base +# +DEFINE NVRAM_AREA_VARIABLE_BASE =3D 0x00000000 +DEFINE NVRAM_AREA_VARIABLE_SIZE =3D 0x00040000 +DEFINE FTW_WORKING_BASE =3D $(NVRAM_AREA_VARIABLE_B= ASE) + $(NVRAM_AREA_VARIABLE_SIZE) +DEFINE FTW_WORKING_SIZE =3D 0x00040000 +DEFINE FTW_SPARE_BASE =3D $(FTW_WORKING_BASE) + $= (FTW_WORKING_SIZE) +DEFINE FTW_SPARE_SIZE =3D 0x00040000 + +##########################################################################= ### +# LS1043ARDB NVRAM Area +# LS1043ARDB NVRAM Area contains: Variable + FTW Working + FTW Spare +##########################################################################= ### + + +$(NVRAM_AREA_VARIABLE_BASE)|$(NVRAM_AREA_VARIABLE_SIZE) +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|gEfiMdeModu= lePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize +#NV_VARIABLE_STORE +DATA =3D { + ## This is the EFI_FIRMWARE_VOLUME_HEADER + # ZeroVector [] + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + # FileSystemGuid: gEfiSystemNvDataFvGuid =3D + # { 0xFFF12B8D, 0x7696, 0x4C8B, + # { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }} + 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C, + 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50, + # FvLength: 0xC0000 + 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, + # Signature "_FVH" # Attributes + 0x5f, 0x46, 0x56, 0x48, 0x36, 0x0E, 0x00, 0x00, + # HeaderLength # CheckSum # ExtHeaderOffset #Reserved #Revision + 0x48, 0x00, 0xC2, 0xF9, 0x00, 0x00, 0x00, 0x02, + # Blockmap[0]: 0x3 Blocks * 0x40000 Bytes / Block + 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, + # Blockmap[1]: End + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + ## This is the VARIABLE_STORE_HEADER + # It is compatible with SECURE_BOOT_ENABLE =3D=3D FALSE as well. + # Signature: gEfiAuthenticatedVariableGuid =3D + # { 0xaaf32c78, 0x947b, 0x439a, + # { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }} + 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43, + 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92, + # Size: 0x40000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariabl= eSize) - + # 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) =3D 0x3ffb8 + # This can speed up the Variable Dispatch a bit. + 0xB8, 0xFF, 0x03, 0x00, + # FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32 + 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +} + +$(FTW_WORKING_BASE)|$(FTW_WORKING_SIZE) +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|gEfiMdeMo= dulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize +#NV_FTW_WORKING +DATA =3D { + # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature =3D gEdkiiWorkingBl= ockSignatureGuid =3D + # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0= x1b, 0x95 }} + 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49, + 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95, + # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Res= erved + 0x5b, 0xe7, 0xc6, 0x86, 0xFE, 0xFF, 0xFF, 0xFF, + # WriteQueueSize: UINT64 + 0xE0, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00 +} + +$(FTW_SPARE_BASE)|$(FTW_SPARE_SIZE) +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|gEfiMdeModu= lePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize +#NV_FTW_SPARE diff --git a/Silicon/NXP/Drivers/NorFlashDxe/NorFlashBlockIoDxe.c b/Silicon= /NXP/Drivers/NorFlashDxe/NorFlashBlockIoDxe.c new file mode 100644 index 0000000..efa2197 --- /dev/null +++ b/Silicon/NXP/Drivers/NorFlashDxe/NorFlashBlockIoDxe.c @@ -0,0 +1,258 @@ +/** @NorFlashBlockIoDxe.c + + Based on NorFlash implementation available in + ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashBlockIoDxe.c + + Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved. + Copyright 2017 NXP + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include +#include + +#include +#include "NorFlashDxe.h" + +// +// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.Reset +// +EFI_STATUS +EFIAPI +NorFlashBlockIoReset ( + IN EFI_BLOCK_IO_PROTOCOL *This, + IN BOOLEAN ExtendedVerification + ) +{ + NOR_FLASH_INSTANCE *Instance; + + Instance =3D INSTANCE_FROM_BLKIO_THIS (This); + + DEBUG ((DEBUG_INFO, "NorFlashBlockIoReset (MediaId=3D0x%x)\n", + This->Media->MediaId)); + + return NorFlashPlatformReset (Instance->DeviceBaseAddress); +} + +// +// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.ReadBlocks +// +EFI_STATUS +EFIAPI +NorFlashBlockIoReadBlocks ( + IN EFI_BLOCK_IO_PROTOCOL *This, + IN UINT32 MediaId, + IN EFI_LBA Lba, + IN UINTN BufferSizeInBytes, + OUT VOID *Buffer + ) +{ + NOR_FLASH_INSTANCE *Instance; + EFI_STATUS Status; + EFI_BLOCK_IO_MEDIA *Media; + UINTN NumBlocks; + UINT8 *ReadBuffer; + UINTN BlockCount; + UINTN BlockSizeInBytes; + EFI_LBA CurrentBlock; + + Status =3D EFI_SUCCESS; + + if ((This =3D=3D NULL) || (Buffer =3D=3D NULL)) { + return EFI_INVALID_PARAMETER; + } + + Instance =3D INSTANCE_FROM_BLKIO_THIS (This); + Media =3D This->Media; + + if (Media =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a : Media is NULL\n", __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + + NumBlocks =3D ((UINTN)BufferSizeInBytes) / Instance->Media.BlockSize ; + + DEBUG ((DEBUG_BLKIO, "%a : (MediaId=3D0x%x, Lba=3D%ld, " + "BufferSize=3D0x%x bytes (%d kB)" + ", BufferPtr @ 0x%p)\n", + __FUNCTION__,MediaId, Lba, + BufferSizeInBytes, Buffer)); + + if (!Media) { + Status =3D EFI_INVALID_PARAMETER; + } + else if (!Media->MediaPresent) { + Status =3D EFI_NO_MEDIA; + } + else if (Media->MediaId !=3D MediaId) { + Status =3D EFI_MEDIA_CHANGED; + } + else if ((Media->IoAlign >=3D 2) && + (((UINTN)Buffer & (Media->IoAlign - 1)) !=3D 0)) { + Status =3D EFI_INVALID_PARAMETER; + } + else if (BufferSizeInBytes =3D=3D 0) { + // Return if we have not any byte to read + Status =3D EFI_SUCCESS; + } + else if ((BufferSizeInBytes % Media->BlockSize) !=3D 0) { + // The size of the buffer must be a multiple of the block size + DEBUG ((DEBUG_ERROR, "%a : BlockSize in bytes =3D 0x%x\n",__FUNCTION__, + BufferSizeInBytes)); + Status =3D EFI_INVALID_PARAMETER; + } else if ((Lba + NumBlocks - 1) > Media->LastBlock) { + // All blocks must be within the device + DEBUG ((DEBUG_ERROR, "%a : Read will exceed last block %d, %d, %d \n", + __FUNCTION__, Lba, NumBlocks, Media->LastBlock)); + Status =3D EFI_INVALID_PARAMETER; + } else { + BlockSizeInBytes =3D Instance->Media.BlockSize; + + /* Because the target *Buffer is a pointer to VOID, + * we must put all the data into a pointer + * to a proper data type, so use *ReadBuffer */ + ReadBuffer =3D (UINT8 *)Buffer; + + CurrentBlock =3D Lba; + // Read data block by Block + for (BlockCount =3D 0; BlockCount < NumBlocks; BlockCount++, CurrentBl= ock++, + ReadBuffer =3D ReadBuffer + BlockSizeInBytes) { + DEBUG ((DEBUG_BLKIO, "%a: Reading block #%d\n", + __FUNCTION__,(UINTN)CurrentBlock)); + + Status =3D NorFlashPlatformRead (Instance, CurrentBlock, (UINTN)0 , + BlockSizeInBytes,ReadBuffer); + if (EFI_ERROR (Status)) { + break; + } + } + } + DEBUG ((DEBUG_BLKIO,"%a: Exit Status =3D \"%r\".\n",__FUNCTION__,Status)= ); + + return Status; +} + +// +// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.WriteBlocks +// +EFI_STATUS +EFIAPI +NorFlashBlockIoWriteBlocks ( + IN EFI_BLOCK_IO_PROTOCOL *This, + IN UINT32 MediaId, + IN EFI_LBA Lba, + IN UINTN BufferSizeInBytes, + IN VOID *Buffer + ) +{ + NOR_FLASH_INSTANCE *Instance; + EFI_STATUS Status; + EFI_BLOCK_IO_MEDIA *Media; + UINTN NumBlocks; + EFI_LBA CurrentBlock; + UINTN BlockSizeInBytes; + UINT32 BlockCount; + UINTN SectorAddress; + UINT8 *WriteBuffer; + + Status =3D EFI_SUCCESS; + + if ((This =3D=3D NULL) || (Buffer =3D=3D NULL)) { + return EFI_INVALID_PARAMETER; + } + + Instance =3D INSTANCE_FROM_BLKIO_THIS (This); + Media =3D This->Media; + + if (Media =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a : Media is NULL\n", __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + + NumBlocks =3D ((UINTN)BufferSizeInBytes) / Instance->Media.BlockSize ; + + DEBUG ((DEBUG_BLKIO, "%a : (MediaId=3D0x%x, Lba=3D%ld, BufferSize=3D0x%x= " + "bytes (%d kB) BufferPtr @ 0x%08x)\n", + __FUNCTION__,MediaId, Lba,BufferSizeInBytes, Buffer)); + + if (!Media->MediaPresent) { + Status =3D EFI_NO_MEDIA; + } + else if (Media->MediaId !=3D MediaId) { + Status =3D EFI_MEDIA_CHANGED; + } + else if (Media->ReadOnly) { + Status =3D EFI_WRITE_PROTECTED; + } + else if (BufferSizeInBytes =3D=3D 0) { + Status =3D EFI_BAD_BUFFER_SIZE; + } + else if ((BufferSizeInBytes % Media->BlockSize) !=3D 0) { + // The size of the buffer must be a multiple of the block size + DEBUG ((DEBUG_ERROR, "%a : BlockSize in bytes =3D 0x%x\n",__FUNCTION__, + BufferSizeInBytes)); + Status =3D EFI_INVALID_PARAMETER; + } else if ((Lba + NumBlocks - 1) > Media->LastBlock) { + // All blocks must be within the device + DEBUG ((DEBUG_ERROR, "%a: Write will exceed last block %d, %d, %d \n", + __FUNCTION__,Lba, NumBlocks, Media->LastBlock)); + Status =3D EFI_INVALID_PARAMETER; + } else { + BlockSizeInBytes =3D Instance->Media.BlockSize; + + WriteBuffer =3D (UINT8 *)Buffer; + + CurrentBlock =3D Lba; + // Program data block by Block + for (BlockCount =3D 0; BlockCount < NumBlocks; + BlockCount++, CurrentBlock++, + WriteBuffer =3D (WriteBuffer + BlockSizeInBytes)) { + DEBUG ((DEBUG_BLKIO, "%a: Writing block #%d\n", + __FUNCTION__,(UINTN)CurrentBlock)); + // Erase the Block(Sector) to be written to + SectorAddress =3D GET_NOR_BLOCK_ADDRESS ( + Instance->RegionBaseAddress, + CurrentBlock, + Instance->Media.BlockSize + ); + Status =3D NorFlashPlatformEraseSector (Instance, (UINTN)SectorAddre= ss); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Failed to erase Target 0x%x (0x%x) \n", + __FUNCTION__,SectorAddress, Status)); + break; + } + // Program Block(Sector) to be written to + Status =3D NorFlashWrite (Instance, CurrentBlock, (UINTN)0, + &BlockSizeInBytes, WriteBuffer); + if (EFI_ERROR (Status)) { + break; + } + } + } + DEBUG ((DEBUG_BLKIO, "%a: Exit Status =3D \"%r\".\n",__FUNCTION__,Status= )); + return Status; +} + +// +// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.FlushBlocks +// +EFI_STATUS +EFIAPI +NorFlashBlockIoFlushBlocks ( + IN EFI_BLOCK_IO_PROTOCOL *This + ) +{ + + DEBUG ((DEBUG_BLKIO, "%a NOT IMPLEMENTED (not required)\n", __FUNCTION__= )); + + // Nothing to do so just return without error + return EFI_SUCCESS; +} diff --git a/Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.c b/Silicon/NXP/Dr= ivers/NorFlashDxe/NorFlashDxe.c new file mode 100644 index 0000000..0e7703c --- /dev/null +++ b/Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.c @@ -0,0 +1,438 @@ +/** @file + + Based on NorFlash implementation available in + ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.c + + Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved. + Copyright 2017 NXP + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include +#include +#include +#include +#include +#include + +#include "NorFlashDxe.h" + +STATIC EFI_EVENT mNorFlashVirtualAddrChangeEvent; + +// +// Global variable declarations +// +NOR_FLASH_INSTANCE **mNorFlashInstances; +UINT32 mNorFlashDeviceCount; + +NOR_FLASH_INSTANCE mNorFlashInstanceTemplate =3D { + .Signature =3D NOR_FLASH_SIGNATURE, + .Initialized =3D FALSE, + .Initialize =3D NULL, + .StartLba =3D 0, + .BlockIoProtocol =3D { + .Revision =3D EFI_BLOCK_IO_PROTOCOL_REVISION2, + .Reset =3D NorFlashBlockIoReset, + .ReadBlocks =3D NorFlashBlockIoReadBlocks, + .WriteBlocks =3D NorFlashBlockIoWriteBlocks, + .FlushBlocks =3D NorFlashBlockIoFlushBlocks, + }, + + .Media =3D { + .RemovableMedia =3D FALSE, + .MediaPresent =3D TRUE, + .LogicalPartition =3D FALSE, + .ReadOnly =3D FALSE, + .WriteCaching =3D FALSE, + .IoAlign =3D 4, + .LowestAlignedLba =3D 0, + .LogicalBlocksPerPhysicalBlock =3D 1, + }, + + .FvbProtocol =3D { + .GetAttributes =3D FvbGetAttributes, + .SetAttributes =3D FvbSetAttributes, + .GetPhysicalAddress =3D FvbGetPhysicalAddress, + .GetBlockSize =3D FvbGetBlockSize, + .Read =3D FvbRead, + .Write =3D FvbWrite, + .EraseBlocks =3D FvbEraseBlocks, + .ParentHandle =3D NULL, + }, + .ShadowBuffer =3D NULL, + .DevicePath =3D { + .Vendor =3D { + .Header =3D { + .Type =3D HARDWARE_DEVICE_PATH, + .SubType =3D HW_VENDOR_DP, + .Length =3D {(UINT8)sizeof (VENDOR_DEVICE_PATH), + (UINT8)((sizeof (VENDOR_DEVICE_PATH)) >> 8) } + }, + .Guid =3D EFI_CALLER_ID_GUID, // GUID ... NEED TO BE FILLED + }, + .End =3D { + .Type =3D END_DEVICE_PATH_TYPE, + .SubType =3D END_ENTIRE_DEVICE_PATH_SUBTYPE, + .Length =3D { sizeof (EFI_DEVICE_PATH_PROTOCOL), 0 } + } + } +}; + +EFI_STATUS +NorFlashCreateInstance ( + IN UINTN NorFlashDeviceBase, + IN UINTN NorFlashRegionBase, + IN UINTN NorFlashSize, + IN UINT32 MediaId, + IN UINT32 BlockSize, + IN BOOLEAN SupportFvb, + OUT NOR_FLASH_INSTANCE** NorFlashInstance + ) +{ + EFI_STATUS Status; + NOR_FLASH_INSTANCE* Instance; + + ASSERT (NorFlashInstance !=3D NULL); + + Instance =3D AllocateRuntimeCopyPool (sizeof (NOR_FLASH_INSTANCE), + &mNorFlashInstanceTemplate); + if (Instance =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + Instance->DeviceBaseAddress =3D NorFlashDeviceBase; + Instance->RegionBaseAddress =3D NorFlashRegionBase; + Instance->Size =3D NorFlashSize; + + Instance->BlockIoProtocol.Media =3D &Instance->Media; + Instance->Media.MediaId =3D MediaId; + Instance->Media.BlockSize =3D BlockSize; + Instance->Media.LastBlock =3D (NorFlashSize / BlockSize)-1; + + Instance->ShadowBuffer =3D AllocateRuntimePool (BlockSize); + if (Instance->ShadowBuffer =3D=3D NULL) { + FreePool (Instance); + return EFI_OUT_OF_RESOURCES; + } + + if (SupportFvb) { + Instance->SupportFvb =3D TRUE; + Instance->Initialize =3D NorFlashFvbInitialize; + + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &Instance->Handle, + &gEfiDevicePathProtocolGuid, &Instance->DevicePath, + &gEfiBlockIoProtocolGuid, &Instance->BlockIoProtocol, + &gEfiFirmwareVolumeBlockProtocolGuid, &Instance->FvbProtocol, + NULL + ); + if (EFI_ERROR (Status)) { + FreePool (Instance->ShadowBuffer); + FreePool (Instance); + return Status; + } + } else { + Instance->Initialized =3D TRUE; + + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &Instance->Handle, + &gEfiDevicePathProtocolGuid, &Instance->DevicePath, + &gEfiBlockIoProtocolGuid, &Instance->BlockIoProtocol, + NULL + ); + if (EFI_ERROR (Status)) { + FreePool (Instance->ShadowBuffer); + FreePool (Instance); + return Status; + } + } + + *NorFlashInstance =3D Instance; + + return Status; +} + +/* + Write a full or portion of a block. + It must not span block boundaries; that is, + Offset + NumBytes <=3D Instance->Media.BlockSize. + */ +EFI_STATUS +NorFlashWrite ( + IN NOR_FLASH_INSTANCE *Instance, + IN EFI_LBA Lba, + IN UINTN Offset, + IN OUT UINTN *NumBytes, + IN UINT8 *Buffer +) +{ + EFI_STATUS Status; + UINTN BlockSize; + BOOLEAN DoErase; + VOID *Source; + UINTN SectorAddress; + + Status =3D EFI_SUCCESS; + Source =3D NULL; + + DEBUG ((DEBUG_BLKIO, "%a(Parameters: Lba=3D%ld, Offset=3D0x%x, NumBytes= =3D0x%x, " + "Buffer @ 0x%08x)\n", __FUNCTION__, + Lba, Offset, *NumBytes, Buffer)); + + // The buffer must be valid + if (Buffer =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + // Detect WriteDisabled state + if (Instance->Media.ReadOnly =3D=3D TRUE) { + DEBUG ((DEBUG_ERROR, "NorFlashWrite: ERROR - Can not write: " + "Device is in WriteDisabled state.\n")); + // It is in WriteDisabled state, return an error right away + return EFI_ACCESS_DENIED; + } + + // Cache the block size to avoid de-referencing pointers all the time + BlockSize =3D Instance->Media.BlockSize; + + // We must have some bytes to write + if ((*NumBytes =3D=3D 0) || (*NumBytes > BlockSize)) { + DEBUG ((DEBUG_ERROR, "NorFlashWrite: ERROR - EFI_BAD_BUFFER_SIZE: " + "(Offset=3D0x%x + NumBytes=3D0x%x) > BlockSize=3D= 0x%x\n", \ + Offset, *NumBytes, BlockSize )); + return EFI_BAD_BUFFER_SIZE; + } + + if (((Lba * BlockSize) + Offset + *NumBytes) > Instance->Size) { + DEBUG ((DEBUG_ERROR, "%a: ERROR - Write will exceed device size.\n", + __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + + // Check we did get some memory. Buffer is BlockSize. + if (Instance->ShadowBuffer =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "FvbWrite: ERROR - Buffer not ready\n")); + return EFI_DEVICE_ERROR; + } + + SectorAddress =3D GET_NOR_BLOCK_ADDRESS ( + Instance->RegionBaseAddress, + Lba, + Instance->Media.BlockSize); + + // Pick 128bytes as a good start for word operations as opposed to erasi= ng the + // block and writing the data regardless if an erase is really needed. + // It looks like most individual NV variable writes are smaller than 128= bytes. + if (*NumBytes <=3D 128) { + Source =3D Instance->ShadowBuffer; + //First Read the data into shadow buffer from location where data is t= o be written + Status =3D NorFlashPlatformRead ( + Instance, + Lba, + Offset, + *NumBytes, + Source); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR - Failed to " + "Read @ %p Status=3D%d\n", __FUNCTION__, + Offset + SectorAddress, Status)); + return Status; + } + // Check to see if we need to erase before programming the data into N= orFlash. + // If the destination bits are only changing from 1s to 0s we can + // just write. After a block is erased all bits in the block is set to= 1. + // If any byte requires us to erase we just give up and rewrite all of= it. + DoErase =3D TestBitSetClear (Source, Buffer, *NumBytes, TRUE); + + // if we got here then write all the data. Otherwise do the + // Erase-Write cycle. + if (!DoErase) { + Status =3D NorFlashPlatformWriteBuffer ( + Instance, + Lba, + Offset, + NumBytes, + Buffer); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR - Failed to " + "Write @ %p Status=3D%d\n", __FUNCTION__, + Offset + SectorAddress, Status)); + return Status; + } + return EFI_SUCCESS; + } + } + + // If we are not going to write full block, read block and then update b= ytes in it + if (*NumBytes !=3D BlockSize) { + // Read NorFlash Flash data into shadow buffer + Status =3D NorFlashBlockIoReadBlocks ( + &(Instance->BlockIoProtocol), + Instance->Media.MediaId, + Lba, + BlockSize, + Instance->ShadowBuffer); + if (EFI_ERROR (Status)) { + // Return one of the pre-approved error statuses + return EFI_DEVICE_ERROR; + } + // Put the data at the appropriate location inside the buffer area + CopyMem ((VOID *)((UINTN)Instance->ShadowBuffer + Offset), Buffer, *Nu= mBytes); + } + //Erase Block + Status =3D NorFlashPlatformEraseSector (Instance, SectorAddress); + if (EFI_ERROR (Status)) { + // Return one of the pre-approved error statuses + return EFI_DEVICE_ERROR; + } + if (*NumBytes !=3D BlockSize) { + // Write the modified shadow buffer back to the NorFlash + Status =3D NorFlashPlatformWriteBuffer ( + Instance, + Lba, + 0, + &BlockSize, + Instance->ShadowBuffer); + } else { + // Write the Buffer to an entire block in NorFlash + Status =3D NorFlashPlatformWriteBuffer ( + Instance, + Lba, + 0, + &BlockSize, + Buffer); + } + if (EFI_ERROR (Status)) { + // Return one of the pre-approved error statuses + return EFI_DEVICE_ERROR; + } + + return EFI_SUCCESS; +} + +/** + Fixup internal data so that EFI can be call in virtual mode. + Call the passed in Child Notify event and convert any pointers in + lib to virtual mode. + + @param[in] Event The Event that is being processed + @param[in] Context Event Context +**/ +VOID +EFIAPI +NorFlashVirtualNotifyEvent ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + UINTN Index; + + for (Index =3D 0; Index < mNorFlashDeviceCount; Index++) { + EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->DeviceBase= Address); + EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->RegionBase= Address); + + // Convert BlockIo protocol + EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->BlockIoPro= tocol.FlushBlocks); + EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->BlockIoPro= tocol.ReadBlocks); + EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->BlockIoPro= tocol.Reset); + EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->BlockIoPro= tocol.WriteBlocks); + + // Convert Fvb + EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->FvbProtoco= l.EraseBlocks); + EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->FvbProtoco= l.GetAttributes); + EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->FvbProtoco= l.GetBlockSize); + EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->FvbProtoco= l.GetPhysicalAddress); + EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->FvbProtoco= l.Read); + EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->FvbProtoco= l.SetAttributes); + EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->FvbProtoco= l.Write); + if (mNorFlashInstances[Index]->ShadowBuffer !=3D NULL) { + EfiConvertPointer (0x0, (VOID **)&mNorFlashInstances[Index]->ShadowB= uffer); + } + } + + return; +} + +EFI_STATUS +EFIAPI +NorFlashInitialise ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + UINT32 Index; + NorFlashDescription* NorFlashDevices; + BOOLEAN ContainVariableStorage; + + ContainVariableStorage =3D 0; + + Status =3D NorFlashPlatformGetDevices (&NorFlashDevices, &mNorFlashDevic= eCount); + if (EFI_ERROR(Status)) { + DEBUG((DEBUG_ERROR, "%a : Failed to get Nor devices (0x%x)\n", + __FUNCTION__, Status)); + return Status; + } + + Status =3D NorFlashPlatformFlashGetAttributes (NorFlashDevices, mNorFlas= hDeviceCount); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR, "%a : Failed to get NOR device attributes (0x%x)\= n", + __FUNCTION__, Status)); + ASSERT_EFI_ERROR (Status); // System becomes unusable if NOR flash is = not detected + return Status; + } + + mNorFlashInstances =3D AllocateRuntimePool ( + sizeof(NOR_FLASH_INSTANCE*) * mNorFlashDeviceC= ount); + if (mNorFlashInstances =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a : Failed to allocate runtime memory \n")); + return EFI_OUT_OF_RESOURCES; + } + + for (Index =3D 0; Index < mNorFlashDeviceCount; Index++) { + // Check if this NOR Flash device contain the variable storage region + ContainVariableStorage =3D + (NorFlashDevices[Index].RegionBaseAddress <=3D PcdGet64 (PcdFlashNvS= torageVariableBase64)) && + (PcdGet64 (PcdFlashNvStorageVariableBase64) + PcdGet32 (PcdFlashNvSt= orageVariableSize) <=3D + NorFlashDevices[Index].RegionBaseAddress + NorFlashDevices[Index].S= ize); + + Status =3D NorFlashCreateInstance ( + NorFlashDevices[Index].DeviceBaseAddress, + NorFlashDevices[Index].RegionBaseAddress, + NorFlashDevices[Index].Size, + Index, + NorFlashDevices[Index].BlockSize, + ContainVariableStorage, + &mNorFlashInstances[Index]); + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a : Failed to create instance for " + "NorFlash[%d] (0x%x)\n",Index, Status)); + } + } + + // + // Register for the virtual address change event + // + Status =3D gBS->CreateEventEx ( + EVT_NOTIFY_SIGNAL, + TPL_NOTIFY, + NorFlashVirtualNotifyEvent, + NULL, + &gEfiEventVirtualAddressChangeGuid, + &mNorFlashVirtualAddrChangeEvent); + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Failed to create VirtualAddressChange event 0x%x= \n", Status)); + } + + return Status; +} diff --git a/Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.h b/Silicon/NXP/Dr= ivers/NorFlashDxe/NorFlashDxe.h new file mode 100644 index 0000000..24504f2 --- /dev/null +++ b/Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.h @@ -0,0 +1,146 @@ +/** @NorFlashDxe.h + + Copyright 2017 NXP + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#ifndef __NOR_FLASH_DXE_H__ +#define __NOR_FLASH_DXE_H__ + +#include +#include + +#define GET_NOR_BLOCK_ADDRESS(BaseAddr,Lba,LbaSize) ( BaseAddr + (UINTN)((= Lba) * LbaSize) ) + +#define NOR_FLASH_SIGNATURE SIGNATURE_32('n', 'o', '= r', '0') + +#define INSTANCE_FROM_FVB_THIS(a) CR(a, NOR_FLASH_INSTANCE= , FvbProtocol, NOR_FLASH_SIGNATURE) + +#define INSTANCE_FROM_BLKIO_THIS(a) CR(a, NOR_FLASH_INSTANCE= , BlockIoProtocol, NOR_FLASH_SIGNATURE) + +EFI_STATUS +EFIAPI +NorFlashFvbInitialize ( + IN NOR_FLASH_INSTANCE* Instance + ); + +EFI_STATUS +EFIAPI +FvbGetAttributes( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + OUT EFI_FVB_ATTRIBUTES_2 *Attributes + ); + +EFI_STATUS +EFIAPI +FvbSetAttributes( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes + ); + +EFI_STATUS +EFIAPI +FvbGetPhysicalAddress( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + OUT EFI_PHYSICAL_ADDRESS *Address + ); + +EFI_STATUS +EFIAPI +FvbGetBlockSize( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + IN EFI_LBA Lba, + OUT UINTN *BlockSize, + OUT UINTN *NumberOfBlocks + ); + +EFI_STATUS +EFIAPI +FvbRead( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + IN EFI_LBA Lba, + IN UINTN Offset, + IN OUT UINTN *NumBytes, + IN OUT UINT8 *Buffer + ); + +EFI_STATUS +EFIAPI +FvbWrite( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + IN EFI_LBA Lba, + IN UINTN Offset, + IN OUT UINTN *NumBytes, + IN UINT8 *Buffer + ); + +EFI_STATUS +EFIAPI +FvbEraseBlocks( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + ... + ); + +// +// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.Reset +// +EFI_STATUS +EFIAPI +NorFlashBlockIoReset ( + IN EFI_BLOCK_IO_PROTOCOL *This, + IN BOOLEAN ExtendedVerification + ); + +// +// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.ReadBlocks +// +EFI_STATUS +EFIAPI +NorFlashBlockIoReadBlocks ( + IN EFI_BLOCK_IO_PROTOCOL *This, + IN UINT32 MediaId, + IN EFI_LBA Lba, + IN UINTN BufferSizeInBytes, + OUT VOID *Buffer +); + +// +// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.WriteBlocks +// +EFI_STATUS +EFIAPI +NorFlashBlockIoWriteBlocks ( + IN EFI_BLOCK_IO_PROTOCOL *This, + IN UINT32 MediaId, + IN EFI_LBA Lba, + IN UINTN BufferSizeInBytes, + IN VOID *Buffer +); + +// +// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.FlushBlocks +// +EFI_STATUS +EFIAPI +NorFlashBlockIoFlushBlocks ( + IN EFI_BLOCK_IO_PROTOCOL *This +); + +EFI_STATUS +NorFlashWrite ( + IN NOR_FLASH_INSTANCE *Instance, + IN EFI_LBA Lba, + IN UINTN Offset, + IN OUT UINTN *NumBytes, + IN UINT8 *Buffer +); + +#endif /* __NOR_FLASH_DXE_H__ */ diff --git a/Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf b/Silicon/NXP/= Drivers/NorFlashDxe/NorFlashDxe.inf new file mode 100644 index 0000000..4081619 --- /dev/null +++ b/Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf @@ -0,0 +1,66 @@ +# @file +# +# Component description file for NorFlashDxe module +# +# Copyright 2017 NXP +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +# + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D NorFlashDxe + FILE_GUID =3D 616fe8d8-f4aa-42e0-a393-b332bdb2d3c1 + MODULE_TYPE =3D DXE_RUNTIME_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D NorFlashInitialise + +[Sources.common] + NorFlashDxe.c + NorFlashFvbDxe.c + NorFlashBlockIoDxe.c + +[Packages] + ArmPlatformPkg/ArmPlatformPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/NXP/NxpQoriqLs.dec + +[LibraryClasses] + DxeServicesTableLib + HobLib + NorFlashLib + UefiDriverEntryPoint + UefiRuntimeLib + +[Guids] + gEfiSystemNvDataFvGuid + gEfiVariableGuid + gEfiAuthenticatedVariableGuid + gEfiEventVirtualAddressChangeGuid + +[Protocols] + gEfiBlockIoProtocolGuid + gEfiFirmwareVolumeBlockProtocolGuid + +[Pcd.common] + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize + gNxpQoriqLsTokenSpaceGuid.PcdIfcNandReservedSize + +[Depex] + # + # NorFlashDxe must be loaded before VariableRuntimeDxe in case empty fla= sh needs populating with default values + # + BEFORE gVariableRuntimeDxeFileGuid diff --git a/Silicon/NXP/Drivers/NorFlashDxe/NorFlashFvbDxe.c b/Silicon/NXP= /Drivers/NorFlashDxe/NorFlashFvbDxe.c new file mode 100644 index 0000000..378546d --- /dev/null +++ b/Silicon/NXP/Drivers/NorFlashDxe/NorFlashFvbDxe.c @@ -0,0 +1,805 @@ +/** @NorFlashFvbDxe.c + + Based on NorFlash implementation available in + ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashFvbDxe.c + + Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved. + Copyright 2017 NXP + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include "NorFlashDxe.h" + +STATIC EFI_EVENT mFvbVirtualAddrChangeEvent; +STATIC UINTN mFlashNvStorageVariableBase; + +/// +/// The Firmware Volume Block Protocol is the low-level interface +/// to a firmware volume. File-level access to a firmware volume +/// should not be done using the Firmware Volume Block Protocol. +/// Normal access to a firmware volume must use the Firmware +/// Volume Protocol. Typically, only the file system driver that +/// produces the Firmware Volume Protocol will bind to the +/// Firmware Volume Block Protocol. +/// + +/** + Initialises the FV Header and Variable Store Header + to support variable operations. + + @param[in] Ptr - Location to initialise the headers + +**/ +EFI_STATUS +InitializeFvAndVariableStoreHeaders ( + IN NOR_FLASH_INSTANCE *Instance + ) +{ + EFI_STATUS Status; + VOID* Headers; + UINTN HeadersLength; + EFI_FIRMWARE_VOLUME_HEADER *FirmwareVolumeHeader; + VARIABLE_STORE_HEADER *VariableStoreHeader; + + if (!Instance->Initialized && Instance->Initialize) { + Instance->Initialize (Instance); + } + + HeadersLength =3D sizeof (EFI_FIRMWARE_VOLUME_HEADER) + sizeof (EFI_FV_B= LOCK_MAP_ENTRY) + sizeof (VARIABLE_STORE_HEADER); + Headers =3D AllocateZeroPool (HeadersLength); + if (Headers =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "Memory allocation failed for Headers \n")); + return EFI_OUT_OF_RESOURCES; + } + + // FirmwareVolumeHeader->FvLength is declared to have the Variable area = AND the FTW working area AND the FTW Spare contiguous. + ASSERT (PcdGet64 (PcdFlashNvStorageVariableBase64) + PcdGet32 (PcdFlashN= vStorageVariableSize) =3D=3D PcdGet64 (PcdFlashNvStorageFtwWorkingBase64)); + ASSERT (PcdGet64 (PcdFlashNvStorageFtwWorkingBase64) + PcdGet32 (PcdFlas= hNvStorageFtwWorkingSize) =3D=3D PcdGet64 (PcdFlashNvStorageFtwSpareBase64)= ); + + // Check if the size of the area is at least one block size + ASSERT ((PcdGet32 (PcdFlashNvStorageVariableSize) > 0) && (PcdGet32 (Pcd= FlashNvStorageVariableSize) / Instance->Media.BlockSize > 0)); + ASSERT ((PcdGet32 (PcdFlashNvStorageFtwWorkingSize) > 0) && (PcdGet32 (P= cdFlashNvStorageFtwWorkingSize) / Instance->Media.BlockSize > 0)); + ASSERT ((PcdGet32 (PcdFlashNvStorageFtwSpareSize) > 0) && (PcdGet32 (Pcd= FlashNvStorageFtwSpareSize) / Instance->Media.BlockSize > 0)); + + // Ensure the Variable area Base Addresses are aligned on a block size b= oundaries + ASSERT (PcdGet64 (PcdFlashNvStorageVariableBase64) % Instance->Media.Blo= ckSize =3D=3D 0); + ASSERT (PcdGet64 (PcdFlashNvStorageFtwWorkingBase64) % Instance->Media.B= lockSize =3D=3D 0); + ASSERT (PcdGet64 (PcdFlashNvStorageFtwSpareBase64) % Instance->Media.Blo= ckSize =3D=3D 0); + + // + // EFI_FIRMWARE_VOLUME_HEADER + // + FirmwareVolumeHeader =3D (EFI_FIRMWARE_VOLUME_HEADER*)Headers; + CopyGuid (&FirmwareVolumeHeader->FileSystemGuid, &gEfiSystemNvDataFvGuid= ); + FirmwareVolumeHeader->FvLength =3D + PcdGet32 (PcdFlashNvStorageVariableSize) + + PcdGet32 (PcdFlashNvStorageFtwWorkingSize) + + PcdGet32 (PcdFlashNvStorageFtwSpareSize); + FirmwareVolumeHeader->Signature =3D EFI_FVH_SIGNATURE; + FirmwareVolumeHeader->Attributes =3D (EFI_FVB_ATTRIBUTES_2) ( + EFI_FVB2_READ_ENABLED_CAP | // Rea= ds may be enabled + EFI_FVB2_READ_STATUS | // Rea= ds are currently enabled + EFI_FVB2_STICKY_WRITE | // A b= lock erase is required to flip bits into EFI_FVB2_ERASE_POLARITY + EFI_FVB2_MEMORY_MAPPED | // It = is memory mapped + EFI_FVB2_ERASE_POLARITY | // Aft= er erasure all bits take this value (i.e. '1') + EFI_FVB2_WRITE_STATUS | // Wri= tes are currently enabled + EFI_FVB2_WRITE_ENABLED_CAP // Wri= tes may be enabled + ); + FirmwareVolumeHeader->HeaderLength =3D sizeof (EFI_FIRMWARE_VOLUME_HEADE= R) + sizeof (EFI_FV_BLOCK_MAP_ENTRY); + FirmwareVolumeHeader->Revision =3D EFI_FVH_REVISION; + //i.e. if blocks are 0-5 then last block =3D 5, total blocks =3D 6 + FirmwareVolumeHeader->BlockMap[0].NumBlocks =3D Instance->Media.LastBloc= k + 1; + FirmwareVolumeHeader->BlockMap[0].Length =3D Instance->Media.BlockS= ize; + FirmwareVolumeHeader->BlockMap[1].NumBlocks =3D 0; + FirmwareVolumeHeader->BlockMap[1].Length =3D 0; + FirmwareVolumeHeader->Checksum =3D CalculateCheckSum16 ((UINT16*)Firmwar= eVolumeHeader,FirmwareVolumeHeader->HeaderLength); + + // + // VARIABLE_STORE_HEADER + // + VariableStoreHeader =3D (VARIABLE_STORE_HEADER*)((UINTN)Headers + Firmwa= reVolumeHeader->HeaderLength); + CopyGuid (&VariableStoreHeader->Signature, &gEfiAuthenticatedVariableGui= d); + VariableStoreHeader->Size =3D PcdGet32(PcdFlashNvStorageVariableSize) - = FirmwareVolumeHeader->HeaderLength; + VariableStoreHeader->Format =3D VARIABLE_STORE_FORMATTED; + VariableStoreHeader->State =3D VARIABLE_STORE_HEALTHY; + + // Install the combined super-header in the NorFlash + Status =3D FvbWrite (&Instance->FvbProtocol, 0, 0, &HeadersLength, Heade= rs); + + FreePool (Headers); + return Status; +} + +/** + Check the integrity of firmware volume header. + + @param[in] FwVolHeader - A pointer to a firmware volume header + + @retval EFI_SUCCESS - The firmware volume is consistent + @retval EFI_NOT_FOUND - The firmware volume has been corrupted. + +**/ +EFI_STATUS +ValidateFvHeader ( + IN NOR_FLASH_INSTANCE *Instance + ) +{ + UINT16 Checksum; + EFI_FIRMWARE_VOLUME_HEADER *FwVolHeader; + VARIABLE_STORE_HEADER *VariableStoreHeader; + UINTN VariableStoreLength; + UINTN FvLength; + + FwVolHeader =3D (EFI_FIRMWARE_VOLUME_HEADER*)mFlashNvStorageVariableBase; + + FvLength =3D PcdGet32 (PcdFlashNvStorageVariableSize) + PcdGet32 (PcdFla= shNvStorageFtwWorkingSize) + + PcdGet32 (PcdFlashNvStorageFtwSpareSize); + + // + // Verify the header revision, header signature, length + // Length of FvBlock cannot be 2**64-1 + // HeaderLength cannot be an odd number + // + if ((FwVolHeader->Revision !=3D EFI_FVH_REVISION) + || (FwVolHeader->Signature !=3D EFI_FVH_SIGNATURE) + || (FwVolHeader->FvLength !=3D FvLength)) { + DEBUG ((DEBUG_ERROR, "%a: No Firmware Volume header present\n", __FUNC= TION__)); + return EFI_NOT_FOUND; + } + + // Check the Firmware Volume Guid + if (CompareGuid (&FwVolHeader->FileSystemGuid, &gEfiSystemNvDataFvGuid) = =3D=3D FALSE ) { + DEBUG ((DEBUG_ERROR, "%a: Firmware Volume Guid non-compatible\n", __FU= NCTION__)); + return EFI_NOT_FOUND; + } + + // Verify the header checksum + Checksum =3D CalculateSum16 ((UINT16*)FwVolHeader, FwVolHeader->HeaderLe= ngth); + if (Checksum !=3D 0) { + DEBUG ((DEBUG_ERROR, "%a: FV checksum is invalid (Checksum:0x%X)\n", _= _FUNCTION__, Checksum)); + return EFI_NOT_FOUND; + } + + VariableStoreHeader =3D (VARIABLE_STORE_HEADER*)((UINTN)FwVolHeader + + FwVolHeader->HeaderLength); + + // Check the Variable Store Guid + if (!CompareGuid (&VariableStoreHeader->Signature, &gEfiVariableGuid) && + !CompareGuid (&VariableStoreHeader->Signature, &gEfiAuthenticatedVar= iableGuid)) { + DEBUG ((DEBUG_ERROR, "%a: Variable Store Guid non-compatible\n", + __FUNCTION__)); + return EFI_NOT_FOUND; + } + + VariableStoreLength =3D PcdGet32 (PcdFlashNvStorageVariableSize) - FwVol= Header->HeaderLength; + if (VariableStoreHeader->Size !=3D VariableStoreLength) { + DEBUG ((DEBUG_ERROR, "%a: Variable Store Length does not match\n", __F= UNCTION__)); + return EFI_NOT_FOUND; + } + + return EFI_SUCCESS; +} + +/** + The GetAttributes() function retrieves the attributes and + current settings of the block. + + @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL in= stance. + + @param Attributes Pointer to EFI_FVB_ATTRIBUTES_2 in which the attribu= tes and + current settings are returned. + Type EFI_FVB_ATTRIBUTES_2 is defined in EFI_FIRMWARE= _VOLUME_HEADER. + + @retval EFI_SUCCESS The firmware volume attributes were returned. + +**/ +EFI_STATUS +EFIAPI +FvbGetAttributes( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + OUT EFI_FVB_ATTRIBUTES_2 *Attributes + ) +{ + EFI_FVB_ATTRIBUTES_2 FlashFvbAttributes; + NOR_FLASH_INSTANCE *Instance; + + Instance =3D INSTANCE_FROM_FVB_THIS (This); + + FlashFvbAttributes =3D (EFI_FVB_ATTRIBUTES_2) ( + EFI_FVB2_READ_ENABLED_CAP | // Reads may be enabled + EFI_FVB2_READ_STATUS | // Reads are currently= enabled + EFI_FVB2_STICKY_WRITE | // A block erase is re= quired to flip bits into EFI_FVB2_ERASE_POLARITY + EFI_FVB2_MEMORY_MAPPED | // It is memory mapped + EFI_FVB2_ERASE_POLARITY // After erasure all b= its take this value (i.e. '1') + ); + + // Check if it is write protected + if (Instance->Media.ReadOnly !=3D TRUE) { + FlashFvbAttributes =3D FlashFvbAttributes | + EFI_FVB2_WRITE_STATUS | // Writes are curren= tly enabled + EFI_FVB2_WRITE_ENABLED_CAP; // Writes may be ena= bled + } + + *Attributes =3D FlashFvbAttributes; + + DEBUG ((DEBUG_BLKIO, "FvbGetAttributes(0x%X)\n", *Attributes)); + + return EFI_SUCCESS; +} + +/** + The SetAttributes() function sets configurable firmware volume attributes + and returns the new settings of the firmware volume. + + @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2= _PROTOCOL instance. + + @param Attributes On input, Attributes is a pointer to EFI= _FVB_ATTRIBUTES_2 + that contains the desired firmware volum= e settings. + On successful return, it contains the ne= w settings of + the firmware volume. + Type EFI_FVB_ATTRIBUTES_2 is defined in = EFI_FIRMWARE_VOLUME_HEADER. + + @retval EFI_SUCCESS The firmware volume attributes were retu= rned. + + @retval EFI_INVALID_PARAMETER The attributes requested are in conflict= with the capabilities + as declared in the firmware volume header. + +**/ +EFI_STATUS +EFIAPI +FvbSetAttributes( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes + ) +{ + DEBUG ((DEBUG_BLKIO, "FvbSetAttributes(0x%X) is not supported\n",*Attrib= utes)); + return EFI_UNSUPPORTED; +} + +/** + The GetPhysicalAddress() function retrieves the base address of + a memory-mapped firmware volume. This function should be called + only for memory-mapped firmware volumes. + + @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTO= COL instance. + + @param Address Pointer to a caller-allocated + EFI_PHYSICAL_ADDRESS that, on successful + return from GetPhysicalAddress(), contains the + base address of the firmware volume. + + @retval EFI_SUCCESS The firmware volume base address was returned. + + @retval EFI_NOT_SUPPORTED The firmware volume is not memory mapped. + +**/ +EFI_STATUS +EFIAPI +FvbGetPhysicalAddress ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + OUT EFI_PHYSICAL_ADDRESS *Address + ) +{ + *Address =3D mFlashNvStorageVariableBase; + return EFI_SUCCESS; +} + +/** + The GetBlockSize() function retrieves the size of the requested + block. It also returns the number of additional blocks with + the identical size. The GetBlockSize() function is used to + retrieve the block map (see EFI_FIRMWARE_VOLUME_HEADER). + + @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2= _PROTOCOL instance. + + @param Lba Indicates the block for which to return = the size. + + @param BlockSize Pointer to a caller-allocated UINTN in w= hich + the size of the block is returned. + + @param NumberOfBlocks Pointer to a caller-allocated UINTN in + which the number of consecutive blocks, + starting with Lba, is returned. All + blocks in this range have a size of + BlockSize. + + @retval EFI_SUCCESS The firmware volume base address was ret= urned. + + @retval EFI_INVALID_PARAMETER The requested LBA is out of range. + +**/ +EFI_STATUS +EFIAPI +FvbGetBlockSize ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + IN EFI_LBA Lba, + OUT UINTN *BlockSize, + OUT UINTN *NumberOfBlocks + ) +{ + EFI_STATUS Status; + NOR_FLASH_INSTANCE *Instance; + + Instance =3D INSTANCE_FROM_FVB_THIS (This); + + DEBUG ((DEBUG_BLKIO, "FvbGetBlockSize(Lba=3D%ld, BlockSize=3D0x%x, LastB= lock=3D%ld)\n", + Lba, Instance->Media.BlockSize, Instance->Media.LastBlock)); + + if (Lba > Instance->Media.LastBlock) { + DEBUG ((DEBUG_ERROR, "%a : Parameter LBA %ld is beyond the last Lba (%= ld)\n", + __FUNCTION__, Lba, Instance->Media.LastBlock)); + Status =3D EFI_INVALID_PARAMETER; + } else { + // In this platform each NorFlash device has equal sized blocks. + *BlockSize =3D (UINTN) Instance->Media.BlockSize; + *NumberOfBlocks =3D (UINTN) (Instance->Media.LastBlock - Lba + 1); + + DEBUG ((DEBUG_BLKIO, "%a : *BlockSize=3D0x%x, *NumberOfBlocks=3D0x%x.\= n", + __FUNCTION__, *BlockSize, *NumberOfBlocks)); + + Status =3D EFI_SUCCESS; + } + + return Status; +} + +/** + Reads the specified number of bytes into a buffer from the specified blo= ck. + + The Read() function reads the requested number of bytes from the + requested block and stores them in the provided buffer. + Implementations should be mindful that the firmware volume + might be in the ReadDisabled state. If it is in this state, + the Read() function must return the status code + EFI_ACCESS_DENIED without modifying the contents of the + buffer. The Read() function must also prevent spanning block + boundaries. If a read is requested that would span a block + boundary, the read must read up to the boundary but not + beyond. The output parameter NumBytes must be set to correctly + indicate the number of bytes actually read. The caller must be + aware that a read may be partially completed. + + @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PRO= TOCOL instance. + + @param Lba The starting logical block index from which = to read. + + @param Offset Offset into the block at which to begin read= ing. + + @param NumBytes Pointer to a UINTN. + At entry, *NumBytes contains the total size = of the buffer. + At exit, *NumBytes contains the total number= of bytes read. + + @param Buffer Pointer to a caller-allocated buffer that wi= ll be used + to hold the data that is read. + + @retval EFI_SUCCESS The firmware volume was read successfully, = and contents are + in Buffer. + + @retval EFI_BAD_BUFFER_SIZE Read attempted across an LBA boundary. + On output, NumBytes contains the total numbe= r of bytes + returned in Buffer. + + @retval EFI_ACCESS_DENIED The firmware volume is in the ReadDisabled s= tate. + + @retval EFI_DEVICE_ERROR The block device is not functioning correctl= y and could not be read. + +**/ +EFI_STATUS +EFIAPI +FvbRead ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + IN EFI_LBA Lba, + IN UINTN Offset, + IN OUT UINTN *NumBytes, + IN OUT UINT8 *Buffer + ) +{ + UINTN BlockSize; + NOR_FLASH_INSTANCE *Instance; + + Instance =3D INSTANCE_FROM_FVB_THIS (This); + + DEBUG ((DEBUG_BLKIO, "FvbRead(Parameters: Lba=3D%ld, Offset=3D0x%x, " + "*NumBytes=3D0x%x, Buffer @ 0x%08x)\n", + Instance->StartLba + Lba, Offset, *NumBytes, Buffer)); + + if (!Instance->Initialized && Instance->Initialize) { + Instance->Initialize(Instance); + } + + // Cache the block size to avoid de-referencing pointers all the time + BlockSize =3D Instance->Media.BlockSize; + + DEBUG ((DEBUG_BLKIO, "FvbRead: Check if (Offset=3D0x%x + NumBytes=3D0x%x= ) <=3D " + "BlockSize=3D0x%x\n", Offset, *NumBytes, BlockSize )); + + // The read must not span block boundaries. + while (Offset >=3D BlockSize) { + Offset -=3D BlockSize; + Lba++; + } + + if ((Instance->StartLba + Lba) > Instance->Media.LastBlock) { + DEBUG ((DEBUG_ERROR, "%a : Parameter LBA %ld is beyond the last Lba (%= ld)\n", + __FUNCTION__, Lba, Instance->Media.LastBlock)); + return EFI_INVALID_PARAMETER; + } + + if ((Offset + *NumBytes) > BlockSize) { + *NumBytes =3D BlockSize-Offset; + } + + return NorFlashPlatformRead (Instance, Instance->StartLba + Lba, + Offset, *NumBytes, Buffer); +} + +/** + Writes the specified number of bytes from the input buffer to the block. + + The Write() function writes the specified number of bytes from + the provided buffer to the specified block and offset. If the + firmware volume is sticky write, the caller must ensure that + all the bits of the specified range to write are in the + EFI_FVB_ERASE_POLARITY state before calling the Write() + function, or else the result will be unpredictable. This + unpredictability arises because, for a sticky-write firmware + volume, a write may negate a bit in the EFI_FVB_ERASE_POLARITY + state but cannot flip it back again. Before calling the + Write() function, it is recommended for the caller to first call + the EraseBlocks() function to erase the specified block to + write. A block erase cycle will transition bits from the + (NOT)EFI_FVB_ERASE_POLARITY state back to the + EFI_FVB_ERASE_POLARITY state. Implementations should be + mindful that the firmware volume might be in the WriteDisabled + state. If it is in this state, the Write() function must + return the status code EFI_ACCESS_DENIED without modifying the + contents of the firmware volume. The Write() function must + also prevent spanning block boundaries. If a write is + requested that spans a block boundary, the write must store up + to the boundary but not beyond. The output parameter NumBytes + must be set to correctly indicate the number of bytes actually + written. The caller must be aware that a write may be + partially completed. All writes, partial or otherwise, must be + fully flushed to the hardware before the Write() service + returns. + + @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PRO= TOCOL instance. + + @param Lba The starting logical block index to write to. + + @param Offset Offset into the block at which to begin writ= ing. + + @param NumBytes The pointer to a UINTN. + At entry, *NumBytes contains the total size = of the buffer. + At exit, *NumBytes contains the total number= of bytes actually written. + + @param Buffer The pointer to a caller-allocated buffer tha= t contains the source for the write. + + @retval EFI_SUCCESS The firmware volume was written successfully. + + @retval EFI_BAD_BUFFER_SIZE The write was attempted across an LBA bounda= ry. + On output, NumBytes contains the total numbe= r of bytes + actually written. + + @retval EFI_ACCESS_DENIED The firmware volume is in the WriteDisabled = state. + + @retval EFI_DEVICE_ERROR The block device is malfunctioning and could= not be written. + +**/ +EFI_STATUS +EFIAPI +FvbWrite ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + IN EFI_LBA Lba, + IN UINTN Offset, + IN OUT UINTN *NumBytes, + IN UINT8 *Buffer + ) +{ + NOR_FLASH_INSTANCE *Instance; + UINTN BlockSize; + + Instance =3D INSTANCE_FROM_FVB_THIS (This); + // Cache the block size to avoid de-referencing pointers all the time + BlockSize =3D Instance->Media.BlockSize; + + if (!Instance->Initialized && Instance->Initialize) { + Instance->Initialize(Instance); + } + + // The write must not span block boundaries. + while(Offset >=3D BlockSize) { + Offset -=3D BlockSize; + Lba++; + } + + if ((Instance->StartLba + Lba) > Instance->Media.LastBlock) { + DEBUG ((DEBUG_ERROR, "%a : Parameter LBA %ld is beyond the last Lba (%= ld)\n", + __FUNCTION__, Lba, Instance->Media.LastBlock)); + return EFI_INVALID_PARAMETER; + } + + if ((Offset + *NumBytes) > BlockSize) { + *NumBytes =3D BlockSize-Offset; + } + + return NorFlashWrite (Instance, Instance->StartLba + Lba, + Offset, NumBytes, Buffer); +} + +/** + Erases and initialises a firmware volume block. + + The EraseBlocks() function erases one or more blocks as denoted + by the variable argument list. The entire parameter list of + blocks must be verified before erasing any blocks. If a block is + requested that does not exist within the associated firmware + volume (it has a larger index than the last block of the + firmware volume), the EraseBlocks() function must return the + status code EFI_INVALID_PARAMETER without modifying the contents + of the firmware volume. Implementations should be mindful that + the firmware volume might be in the WriteDisabled state. If it + is in this state, the EraseBlocks() function must return the + status code EFI_ACCESS_DENIED without modifying the contents of + the firmware volume. All calls to EraseBlocks() must be fully + flushed to the hardware before the EraseBlocks() service + returns. + + @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2= _PROTOCOL + instance. + + @param ... The variable argument list is a list of = tuples. + Each tuple describes a range of LBAs to = erase + and consists of the following: + - An EFI_LBA that indicates the starting= LBA + - A UINTN that indicates the number of b= locks to erase. + + The list is terminated with an EFI_LBA_L= IST_TERMINATOR. + For example, the following indicates tha= t two ranges of blocks + (5-7 and 10-11) are to be erased: + EraseBlocks (This, 5, 3, 10, 2, EFI_LBA_= LIST_TERMINATOR); + + @retval EFI_SUCCESS The erase request successfully completed. + + @retval EFI_ACCESS_DENIED The firmware volume is in the WriteDisab= led state. + + @retval EFI_DEVICE_ERROR The block device is not functioning corr= ectly and could not be written. + The firmware device may have been partia= lly erased. + + @retval EFI_INVALID_PARAMETER One or more of the LBAs listed in the va= riable argument list do + not exist in the firmware volume. + +**/ +EFI_STATUS +EFIAPI +FvbEraseBlocks ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + ... + ) +{ + EFI_STATUS Status; + VA_LIST Args; + UINTN BlockAddress; // Physical address of Lba to erase + EFI_LBA StartingLba; // Lba from which we start erasing + UINTN NumOfLba; // Number of Lba blocks to erase + NOR_FLASH_INSTANCE *Instance; + + Instance =3D INSTANCE_FROM_FVB_THIS (This); + + DEBUG ((DEBUG_BLKIO, "FvbEraseBlocks()\n")); + + Status =3D EFI_SUCCESS; + + // Detect WriteDisabled state + if (Instance->Media.ReadOnly =3D=3D TRUE) { + // Firmware volume is in WriteDisabled state + DEBUG ((DEBUG_ERROR, "%a : Device is in WriteDisabled state\n")); + return EFI_ACCESS_DENIED; + } + + // Before erasing, check the entire list of parameters to + // ensure all specified blocks are valid + + VA_START (Args, This); + do { + // Get the Lba from which we start erasing + StartingLba =3D VA_ARG (Args, EFI_LBA); + + // Have we reached the end of the list? + if (StartingLba =3D=3D EFI_LBA_LIST_TERMINATOR) { + //Exit the while loop + break; + } + + // How many Lba blocks are we requested to erase? + NumOfLba =3D VA_ARG (Args, UINT32); + + // All blocks must be within range + DEBUG ((DEBUG_BLKIO, "FvbEraseBlocks: Check if: ( StartingLba=3D%ld + " + "NumOfLba=3D%d - 1 ) > LastBlock=3D%ld.\n", + Instance->StartLba + StartingLba, NumOfLba, + Instance->Media.LastBlock)); + if ((NumOfLba =3D=3D 0) || + ((Instance->StartLba + StartingLba + NumOfLba - 1) > + Instance->Media.LastBlock)) { + VA_END (Args); + DEBUG ((DEBUG_ERROR, "%a : Lba range goes past the last Lba\n")); + Status =3D EFI_INVALID_PARAMETER; + goto EXIT; + } + } while (TRUE); + VA_END (Args); + + // + // To get here, all must be ok, so start erasing + // + VA_START (Args, This); + do { + // Get the Lba from which we start erasing + StartingLba =3D VA_ARG (Args, EFI_LBA); + + // Have we reached the end of the list? + if (StartingLba =3D=3D EFI_LBA_LIST_TERMINATOR) { + // Exit the while loop + break; + } + + // How many Lba blocks are we requested to erase? + NumOfLba =3D VA_ARG (Args, UINT32); + + // Go through each one and erase it + while (NumOfLba > 0) { + // Get the physical address of Lba to erase + BlockAddress =3D GET_NOR_BLOCK_ADDRESS ( + Instance->RegionBaseAddress, + Instance->StartLba + StartingLba, + Instance->Media.BlockSize + ); + + // Erase it + DEBUG ((DEBUG_BLKIO, "FvbEraseBlocks: Erasing Lba=3D%ld @ 0x%08x.\n", + Instance->StartLba + StartingLba, BlockAddress= )); + Status =3D NorFlashPlatformEraseSector(Instance, BlockAddress); + if (EFI_ERROR (Status)) { + VA_END (Args); + Status =3D EFI_DEVICE_ERROR; + goto EXIT; + } + + // Move to the next Lba + StartingLba++; + NumOfLba--; + } + } while (TRUE); + VA_END (Args); + +EXIT: + return Status; +} + +/** + Fixup internal data so that EFI can be call in virtual mode. + Call the passed in Child Notify event and convert any pointers in + lib to virtual mode. + + @param[in] Event The Event that is being processed + @param[in] Context Event Context +**/ +VOID +EFIAPI +FvbVirtualNotifyEvent ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + EfiConvertPointer (0x0, (VOID**)&mFlashNvStorageVariableBase); + return; +} + +EFI_STATUS +EFIAPI +NorFlashFvbInitialize ( + IN NOR_FLASH_INSTANCE *Instance + ) +{ + EFI_STATUS Status; + UINT32 FvbNumLba; + EFI_BOOT_MODE BootMode; + UINTN RuntimeMmioRegionSize; + + DEBUG ((DEBUG_BLKIO, "NorFlashFvbInitialize\n")); + + Instance->Initialized =3D TRUE; + mFlashNvStorageVariableBase =3D FixedPcdGet64 (PcdFlashNvStorageVariable= Base64); + + // Set the index of the first LBA for the FVB + Instance->StartLba =3D (PcdGet64 (PcdFlashNvStorageVariableBase64) - Ins= tance->RegionBaseAddress) / Instance->Media.BlockSize; + + BootMode =3D GetBootModeHob (); + if (BootMode =3D=3D BOOT_WITH_DEFAULT_SETTINGS) { + Status =3D EFI_INVALID_PARAMETER; + } else { + // Determine if there is a valid header at the beginning of the NorFla= sh + Status =3D ValidateFvHeader (Instance); + } + + // Install the Default FVB header if required + if (EFI_ERROR (Status)) { + // There is no valid header, so time to install one. + DEBUG ((DEBUG_INFO, "%a: The FVB Header is not valid.\n", __FUNCTION__= )); + DEBUG ((DEBUG_INFO, "%a: Installing a correct one for this volume.\n", + __FUNCTION__)); + + // Erase all the NorFlash that is reserved for variable storage + FvbNumLba =3D (PcdGet32 (PcdFlashNvStorageVariableSize) + + PcdGet32 (PcdFlashNvStorageFtwWorkingSize) + + PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / Instance->Med= ia.BlockSize; + + Status =3D FvbEraseBlocks (&Instance->FvbProtocol, (EFI_LBA)0, FvbNumL= ba, EFI_LBA_LIST_TERMINATOR); + if (EFI_ERROR (Status)) { + return Status; + } + + // Install all appropriate headers + Status =3D InitializeFvAndVariableStoreHeaders (Instance); + if (EFI_ERROR (Status)) { + return Status; + } + } + + // + // Declare the Non-Volatile storage as EFI_MEMORY_RUNTIME + // + + // Note: all the NOR Flash region needs to be reserved into the UEFI Run= time memory; + // even if we only use the small block region at the top of the NO= R Flash. + // The reason is when the NOR Flash memory is set into program mod= e, the command + // is written as the base of the flash region (ie: Instance->Devic= eBaseAddress) + RuntimeMmioRegionSize =3D (Instance->RegionBaseAddress - Instance->Devic= eBaseAddress) + Instance->Size; + + Status =3D gDS->AddMemorySpace ( + EfiGcdMemoryTypeMemoryMappedIo, + Instance->DeviceBaseAddress, RuntimeMmioRegionSize, + EFI_MEMORY_UC | EFI_MEMORY_RUNTIME); + ASSERT_EFI_ERROR (Status); + + Status =3D gDS->SetMemorySpaceAttributes ( + Instance->DeviceBaseAddress, RuntimeMmioRegionSize, + EFI_MEMORY_UC | EFI_MEMORY_RUNTIME); + ASSERT_EFI_ERROR (Status); + + // + // Register for the virtual address change event + // + Status =3D gBS->CreateEventEx ( + EVT_NOTIFY_SIGNAL, + TPL_NOTIFY, + FvbVirtualNotifyEvent, + NULL, + &gEfiEventVirtualAddressChangeGuid, + &mFvbVirtualAddrChangeEvent + ); + ASSERT_EFI_ERROR (Status); + + return Status; +} --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun May 5 06:05:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=nxp.com Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1518771232068311.8247153963342; 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X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Meenakshi Aggarwal Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Meenakshi Aggarwal --- Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 16 +++++++++++++++- Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 9 ++++++++- 2 files changed, 23 insertions(+), 2 deletions(-) diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS= 1043aRdbPkg/LS1043aRdbPkg.dsc index df4d917..7708e0a 100644 --- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc @@ -41,6 +41,7 @@ IfcLib|Silicon/NXP/Library/IfcLib/IfcLib.inf BoardLib|Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.inf FpgaLib|Platform/NXP/LS1043aRdbPkg/Library/FpgaLib/FpgaLib.inf + NorFlashLib|Silicon/NXP/Library/NorFlashLib/NorFlashLib.inf =20 [PcdsFixedAtBuild.common] =20 @@ -70,6 +71,13 @@ gDs1307RtcLibTokenSpaceGuid.PcdI2cSlaveAddress|0x68 gDs1307RtcLibTokenSpaceGuid.PcdI2cBusFrequency|100000 =20 + # + # NV Storage PCDs. + # + gArmTokenSpaceGuid.PcdVFPEnabled|1 + gNxpQoriqLsTokenSpaceGuid.PcdFlashDeviceBase64|0x060000000 + gNxpQoriqLsTokenSpaceGuid.PcdFlashReservedRegionBase64|0x60300000 + ##########################################################################= ###### # # Components Section - list of all EDK II Modules needed by this Platform @@ -79,9 +87,15 @@ # # Architectural Protocols # - MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf + + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf{ + + NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf + } + MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf =20 Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf + Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf =20 ## diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf b/Platform/NXP/LS= 1043aRdbPkg/LS1043aRdbPkg.fdf index fa6510c..6b5b63f 100644 --- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf @@ -55,6 +55,7 @@ gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.Pc= dFvSize FV =3D FVMAIN_COMPACT =20 !include ../FVRules.fdf.inc +!include VarStore.fdf.inc ##########################################################################= ###### # # FV Section @@ -103,7 +104,8 @@ READ_LOCK_STATUS =3D TRUE INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf - INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.= inf + INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf + INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.i= nf INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.i= nf =20 INF Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf @@ -123,6 +125,11 @@ READ_LOCK_STATUS =3D TRUE INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf =20 # + # NOR Driver + # + INF Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf + + # # Network modules # INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun May 5 06:05:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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VI1PR04MB1008; 6:vUdTcVuLYtc1BeeVvH8/M2x8b0EXZThXceRsNyckxwZe4USu91kHZKopJ8rtyHWqsAiHhMhWAr4WC6sKQPbdeEWJB7DEESiFJQBK0ZM6pFL4fkgiSCvXhuU0CRBL6pi6MtyyWgC+vYyxg/V72h+kERIZ9uVxpfYfKkHUD3KIkhWGmijV/HIU5JvtOFPW3OQb0zOYcP+MN5lCUhiF5AGRwl9c8O8JhYqS46yCfyQfB27IhcGQoznIdl/W8V3NRlGACtyz/JAH0sI2bqesvpKthdw2AtUVld82CiQ/62xT0eN/Dy38xpTNahBmQSp1Xl9Eq9mWiVuZiOaKyJuDsqwgULi/D+G2laLlppbovd08PXQ=; 5:aBmM9H/9INSk/a39hd85M6af119yLCXLUJtx9KFa5oT+Z5hXMu/4pT/TJ1hT9g7SG9QNFyj92VX+vs9zjMbsLCEjx1ODzXnRpw9f1P67njMG9xnNc52ATQPSsP99udF96soEQZSSb2ggpve2i8xu+HkQqO91pHDhhJQm/ZsIQiY=; 24:FPeXdhe9cmYvaxVeoW7ZX3lZ5JJAczhmN+L5jcsbhDnBsbMcoC6d0VRTKv61rDCPd3JxCU++YcEfGAbDENQf+3iZJdXOS84sxaKeE8DMoxQ=; 7:x11AMHnel6mYTLaTbb0D9iVD+2e8/ewtW5tmK43mx2YbGTuvRzQ1m4dnc9ATXZWQyKCV8S2IyShCeV8zYN5WnslaT9KPwId6yiioMCNmhubekowyuSXSWZdAqrpUxfrxE5OhS9HT0JhZ0gtmXzCfOzvZlUnmfbwqvFBUUFZiRBC7UByySn8IaDUImBr7AL86yOjZV09Em0Zr8lSMDj7Fqqs7g1YtJP22wu7L3m0woRPGjaAQHt2C4Kr44NkXhgwc SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Feb 2018 08:53:46.5454 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5104b042-16f1-42fe-9756-08d5751accba X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB1008 Subject: [edk2] [PATCH edk2-platforms 18/39] Silicon/NXP:Add LS1046ARDB SoCLib Support X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Meenakshi Aggarwal On LS1046A NXP SoC,Provide Functions to initialize peripherals ,print board, soc information. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Vabhav --- Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 1 + Silicon/NXP/Chassis/Chassis.c | 1 + Silicon/NXP/Chassis/Chassis.h | 1 + Silicon/NXP/Chassis/Chassis2/Soc.c | 51 ++++++++++++++++++++- Silicon/NXP/Chassis/LS1043aSocLib.inf | 2 + Silicon/NXP/Chassis/LS1046aSocLib.inf | 51 +++++++++++++++++++++ Silicon/NXP/LS1046A/Include/SocSerDes.h | 55 ++++++++++++++++++++++ Silicon/NXP/LS1046A/LS1046A.dec | 22 +++++++++ Silicon/NXP/LS1046A/LS1046A.dsc | 68 ++++++++++++++++++++++++= ++++ Silicon/NXP/NxpQoriqLs.dec | 2 + 10 files changed, 253 insertions(+), 1 deletion(-) create mode 100644 Silicon/NXP/Chassis/LS1046aSocLib.inf create mode 100644 Silicon/NXP/LS1046A/Include/SocSerDes.h create mode 100644 Silicon/NXP/LS1046A/LS1046A.dec create mode 100644 Silicon/NXP/LS1046A/LS1046A.dsc diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS= 1043aRdbPkg/LS1043aRdbPkg.dsc index 7708e0a..b2b514e 100644 --- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc @@ -59,6 +59,7 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500 gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x1 + gNxpQoriqLsTokenSpaceGuid.PcdMuxToUsb3|TRUE =20 # # I2C controller Pcds diff --git a/Silicon/NXP/Chassis/Chassis.c b/Silicon/NXP/Chassis/Chassis.c index 9f2928b..ce07fdc 100644 --- a/Silicon/NXP/Chassis/Chassis.c +++ b/Silicon/NXP/Chassis/Chassis.c @@ -44,6 +44,7 @@ GurRead ( */ STATIC CPU_TYPE CpuTypeList[] =3D { CPU_TYPE_ENTRY (LS1043A, LS1043A, 4), + CPU_TYPE_ENTRY (LS1046A, LS1046A, 4), }; =20 /* diff --git a/Silicon/NXP/Chassis/Chassis.h b/Silicon/NXP/Chassis/Chassis.h index 4bdb4d0..0beb44c 100644 --- a/Silicon/NXP/Chassis/Chassis.h +++ b/Silicon/NXP/Chassis/Chassis.h @@ -56,6 +56,7 @@ CpuMaskNext ( =20 #define SVR_WO_E 0xFFFFFE #define SVR_LS1043A 0x879200 +#define SVR_LS1046A 0x870700 =20 #define SVR_MAJOR(svr) (((svr) >> 4) & 0xf) #define SVR_MINOR(svr) (((svr) >> 0) & 0xf) diff --git a/Silicon/NXP/Chassis/Chassis2/Soc.c b/Silicon/NXP/Chassis/Chass= is2/Soc.c index 17de7e4..658df2d 100644 --- a/Silicon/NXP/Chassis/Chassis2/Soc.c +++ b/Silicon/NXP/Chassis/Chassis2/Soc.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -139,6 +140,44 @@ GetSysInfo ( } =20 /** + Function to select pins depending upon pcd using supplemental + configuration unit(SCFG) extended RCW controlled pinmux control + register which contains the bits to provide pin multiplexing control. + This register is reset on HRESET. + **/ +VOID +ConfigScfgMux (VOID) +{ + CCSR_SCFG *Scfg; + UINT32 UsbPwrFault; + + Scfg =3D (VOID *)PcdGet64 (PcdScfgBaseAddr); + // Configures functionality of the IIC3_SCL to USB2_DRVVBUS + // Configures functionality of the IIC3_SDA to USB2_PWRFAULT + + // LS1043A + // Configures functionality of the IIC4_SCL to USB3_DRVVBUS + // Configures functionality of the IIC4_SDA to USB3_PWRFAULT + + // LS1046A + // USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA + if (PcdGetBool (PcdMuxToUsb3)) { + BeMmioWrite32 ((UINTN)&Scfg->RcwPMuxCr0, CCSR_SCFG_RCWPMUXCRO_SELCR_US= B); + } else { + BeMmioWrite32 ((UINTN)&Scfg->RcwPMuxCr0, CCSR_SCFG_RCWPMUXCRO_NOT_SELC= R_USB); + } + BeMmioWrite32 ((UINTN)&Scfg->UsbDrvVBusSelCr, CCSR_SCFG_USBDRVVBUS_SELCR= _USB1); + UsbPwrFault =3D (CCSR_SCFG_USBPWRFAULT_DEDICATED << + CCSR_SCFG_USBPWRFAULT_USB3_SHIFT) | + (CCSR_SCFG_USBPWRFAULT_DEDICATED << + CCSR_SCFG_USBPWRFAULT_USB2_SHIFT) | + (CCSR_SCFG_USBPWRFAULT_SHARED << + CCSR_SCFG_USBPWRFAULT_USB1_SHIFT); + BeMmioWrite32 ((UINTN)&Scfg->UsbPwrFaultSelCr, UsbPwrFault); + BeMmioWrite32 ((UINTN)&Scfg->UsbPwrFaultSelCr, UsbPwrFault); +} + +/** Function to initialize SoC specific constructs CPU Info SoC Personality @@ -170,8 +209,18 @@ SocInit ( // PrintRCW (); PrintSoc (); - IfcInit(); + IfcInit (); PrintBoardPersonality (); + // + // Due to the extensive functionality present on the chip and the limite= d number of external + // signals available, several functional blocks share signal resources t= hrough multiplexing. + // In this case when there is alternate functionality between multiple f= unctional blocks, + // the signal's function is determined at the chip level (rather than at= the block level) + // typically by a reset configuration word (RCW) option. Some of the sig= nals' function are + // determined externel to RCW at Power-on Reset Sequence. + // + ConfigScfgMux (); + =20 return; } diff --git a/Silicon/NXP/Chassis/LS1043aSocLib.inf b/Silicon/NXP/Chassis/LS= 1043aSocLib.inf index d01b353..71fa0a8 100644 --- a/Silicon/NXP/Chassis/LS1043aSocLib.inf +++ b/Silicon/NXP/Chassis/LS1043aSocLib.inf @@ -47,3 +47,5 @@ gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdMuxToUsb3 diff --git a/Silicon/NXP/Chassis/LS1046aSocLib.inf b/Silicon/NXP/Chassis/LS= 1046aSocLib.inf new file mode 100644 index 0000000..11eeb97 --- /dev/null +++ b/Silicon/NXP/Chassis/LS1046aSocLib.inf @@ -0,0 +1,51 @@ +# @file +# +# Copyright 2017 NXP +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +# + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D SocLib + FILE_GUID =3D ddd5f950-8816-4d38-8f98-f42b07333f78 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SocLib + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/NXP/NxpQoriqLs.dec + Silicon/NXP/Chassis/Chassis2/Chassis2.dec + Silicon/NXP/LS1046A/LS1046A.dec + +[LibraryClasses] + BaseLib + BeIoLib + DebugLib + FpgaLib + IfcLib + SerialPortLib + +[Sources.common] + Chassis.c + Chassis2/Soc.c + SerDes.c + +[FixedPcd] + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString + gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv + gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled + gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian + gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdMuxToUsb3 diff --git a/Silicon/NXP/LS1046A/Include/SocSerDes.h b/Silicon/NXP/LS1046A/= Include/SocSerDes.h new file mode 100644 index 0000000..a0b5576 --- /dev/null +++ b/Silicon/NXP/LS1046A/Include/SocSerDes.h @@ -0,0 +1,55 @@ +/** @file + The Header file of SerDes Module + + Copyright 2017 NXP + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD= License + which accompanies this distribution. The full text of the license may be = found + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPL= IED. + +**/ + +#ifndef __LS1046A_SERDES_H__ +#define __LS1046A_SERDES_H__ + +#include + +SERDES_CONFIG SerDes1ConfigTbl[] =3D { + /* SerDes 1 */ + {0x3333, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC5, S= GMII_FM1_DTSEC6 } }, + {0x1133, {XFI_FM1_MAC9, XFI_FM1_MAC10, SGMII_FM1_DTSEC5, SGMII_FM1= _DTSEC6 } }, + {0x1333, {XFI_FM1_MAC9, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC5, SGMII= _FM1_DTSEC6 } }, + {0x2333, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC10, SGMII_FM1_DTSE= C5, SGMII_FM1_DTSEC6 } }, + {0x2233, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10, SGMII_FM1= _DTSEC5, SGMII_FM1_DTSEC6 } }, + {0x1040, {XFI_FM1_MAC9, NONE, QSGMII_FM1_A, NONE } }, + {0x2040, {SGMII_2500_FM1_DTSEC9, NONE, QSGMII_FM1_A, NONE } }, + {0x1163, {XFI_FM1_MAC9, XFI_FM1_MAC10, PCIE1, SGMII_FM1_DTSEC6 } }, + {0x2263, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10, PCIE1, SG= MII_FM1_DTSEC6 } }, + {0x3363, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, PCIE1, SGMII_FM1_DTS= EC6 } }, + {0x2223, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10, SGMII_250= 0_FM1_DTSEC5, SGMII_FM1_DTSEC6 } }, + {} +}; + +SERDES_CONFIG SerDes2ConfigTbl[] =3D { + /* SerDes 2 */ + {0x8888, {PCIE1, PCIE1, PCIE1, PCIE1 } }, + {0x5559, {PCIE1, PCIE2, PCIE3, SATA } }, + {0x5577, {PCIE1, PCIE2, PCIE3, PCIE3 } }, + {0x5506, {PCIE1, PCIE2, NONE, PCIE3 } }, + {0x0506, {NONE, PCIE2, NONE, PCIE3 } }, + {0x0559, {NONE, PCIE2, PCIE3, SATA } }, + {0x5A59, {PCIE1, SGMII_FM1_DTSEC2, PCIE3, SATA } }, + {0x5A06, {PCIE1, SGMII_FM1_DTSEC2, NONE, PCIE3 } }, + {} +}; + +SERDES_CONFIG *SerDesConfigTbl[] =3D { + SerDes1ConfigTbl, + SerDes2ConfigTbl +}; + +#endif /* __LS1046A_SERDES_H */ diff --git a/Silicon/NXP/LS1046A/LS1046A.dec b/Silicon/NXP/LS1046A/LS1046A.= dec new file mode 100644 index 0000000..e266aad --- /dev/null +++ b/Silicon/NXP/LS1046A/LS1046A.dec @@ -0,0 +1,22 @@ +# LS1046A.dec +# +# Copyright 2017 NXP +# +# This program and the accompanying materials are licensed and made availa= ble under +# the terms and conditions of the BSD License which accompanies this distr= ibution. +# The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. +# +# + +[Defines] + DEC_SPECIFICATION =3D 0x00010005 + +[Guids.common] + gNxpLs1046ATokenSpaceGuid =3D {0x8d7ffac8, 0xb4d5, 0x43c3, {0xaa, 0= x27, 0x84, 0xbc, 0x12, 0x01, 0x28, 0x10}} + +[Includes] + Include diff --git a/Silicon/NXP/LS1046A/LS1046A.dsc b/Silicon/NXP/LS1046A/LS1046A.= dsc new file mode 100644 index 0000000..9f87028 --- /dev/null +++ b/Silicon/NXP/LS1046A/LS1046A.dsc @@ -0,0 +1,68 @@ +# LS1046A.dsc +# LS1046A Soc package. +# +# Copyright 2017 NXP +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may b= e found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +# + +##########################################################################= ###### +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +##########################################################################= ###### +[PcdsDynamicDefault.common] + + # + # ARM General Interrupt Controller + gArmTokenSpaceGuid.PcdGicDistributorBase|0x01410000 + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x01420000 + +[PcdsFixedAtBuild.common] + + # + # CCSR Address Space and other attached Memories + # + gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x01000000 + gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0F000000 + gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr|0x01EE1000 + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr|0x60000000 + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size|0x20000000 + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr|0x0620000000 + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size|0x00E0000000 + gNxpQoriqLsTokenSpaceGuid.PcdIfcNandReservedSize|0x2EA + gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr|0x0500000000 + gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize|0x0080000000 + gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr|0x0508000000 + gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize|0x0080000000 + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr|0x4000000000 + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize|0x800000000 + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr|0x4800000000 + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize|0x800000000 + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr|0x5000000000 + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize|0x800000000 + gNxpQoriqLsTokenSpaceGuid.PcdDram1BaseAddr|0x0080000000 + gNxpQoriqLsTokenSpaceGuid.PcdDram1Size|0x0080000000 + gNxpQoriqLsTokenSpaceGuid.PcdDram2BaseAddr|0x0880000000 + gNxpQoriqLsTokenSpaceGuid.PcdDram2Size|0x0780000000 + gNxpQoriqLsTokenSpaceGuid.PcdDram3BaseAddr|0x8800000000 + gNxpQoriqLsTokenSpaceGuid.PcdDram3Size|0x7800000000 + gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr|0x1570000 + gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr|0x01EE0000 + gNxpQoriqLsTokenSpaceGuid.PcdWdog1BaseAddr|0x02AD0000 + gNxpQoriqLsTokenSpaceGuid.PcdSdxcBaseAddr|0x01560000 + gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr|0x02180000 + gNxpQoriqLsTokenSpaceGuid.PcdI2cSize|0x10000 + gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|4 + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x40000000 + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x20000000 + gNxpQoriqLsTokenSpaceGuid.PcdIfcBaseAddr|0x1530000 + +## diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec index 43d0a71..39753e7 100644 --- a/Silicon/NXP/NxpQoriqLs.dec +++ b/Silicon/NXP/NxpQoriqLs.dec @@ -30,6 +30,7 @@ gNxpQoriqLsTokenSpaceGuid.PcdI2cBus|0|UINT32|0x00000001 gNxpQoriqLsTokenSpaceGuid.PcdI2cSpeed|0|UINT32|0x00000002 gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|0|UINT32|0x00000003 + gNxpQoriqLsTokenSpaceGuid.PcdI2cSlaveAddress|0|UINT32|0x00000004 =20 # # Pcds for base address and size @@ -101,6 +102,7 @@ # gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x0|UINT32|0x00000250 gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE|BOOLEAN|0x00000251 + gNxpQoriqLsTokenSpaceGuid.PcdMuxToUsb3|FALSE|BOOLEAN|0x00000253 =20 # # Clock PCDs --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun May 5 06:05:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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VI1PR04MB1008; 6:K8ph9J8wuFHeCUZetImBcceWlBfO6AsNZJoTaAfqzsq4OA8H+9V6PQYOeS1qqzrMFdPiZIgLDsxiJmct8SXX6LGvvE8zfHyzj8aypJwQj7yHZtK9CjndFIxLtZnMqi8k+HZApf6YjbEEIetQLVTXML2+aRXfDtvJUBFRcvQvQ5ZXQ5WnUNrctGuIU2zFyPjwy/zJ3xQ3FrBxLr6r51r/GfVJ6H6PZKrUGTRl/lZUK/0n9rssFi3MKJmfA7jY/RMMsQf1v6XsutoqeFbTDxyT4MW2SaKMW/sc56lSin4OJjShfbe5BtYGs68TjNsabFv9KNjgfC/Pg0ObdZ/IN8EIMEEBoLAbj4XlMzkY5rAChuU=; 5:Rd1IHt/MBxwzYVRyMyXDVc2prxKSuEq3gjV6kp02w6pwKrADnSmvXm7eX9YRCF7+CloFMtb9ZGs8JUw3N8OzSGBPwMvbjnmeIhDiT/18cxUyHY/61gL2YyiZduHmyJ4LG/MQQyF77hbu3Q28vDTFgJRyfT3BrjGzah4ZnIyAJLI=; 24:r203g8RJ/gncEMOE4zFiCaEURoQLTDKbEjQvtKmbPom0WF7UIqO2BnqjhLIvXh+inXfkdDZbi0eONvTStVIbyIhQocRSU6LkORsupbhjjCU=; 7:7+Sw2B/nDeWGt5JKJ/tVuHUHcdBiEgs1I8zJ6KloiMeAPXKc3gfjDFntvEl73kEz0XZ7R1A2FMtAJqwI58DNKayCce/AHmUq8F0gnNDAIatF2MyBltd4lMNSHNusU1+cMEJiyEuPgBvJj3qgPQGIsuEwqrXBqzJ7lOxamXQsS3FG9qk91zNDRdZmwS9IN5szq6ZQfArpqwYTaMlvvat5YMsxRuMb+K7Vjav4Gr44RO1L/YiVLZzHEOtvnoKkgoWf SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Feb 2018 08:53:52.3891 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 501816ea-9079-4aa4-b1a3-08d5751acf7e X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB1008 Subject: [edk2] [PATCH edk2-platforms 19/39] Silicon/NXP:Add support for PCF2129 Real Time Clock Library X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Vabhav Library to provide functions for NXP pcf2129 real time clock library Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Vabhav --- Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129Rtc.h | 43 +++ Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.c | 330 +++++++++++++++++= ++++ .../NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.inf | 47 +++ 3 files changed, 420 insertions(+) create mode 100644 Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129Rtc.h create mode 100644 Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.c create mode 100644 Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.inf diff --git a/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129Rtc.h b/Silicon/NXP/L= ibrary/Pcf2129RtcLib/Pcf2129Rtc.h new file mode 100644 index 0000000..735f697 --- /dev/null +++ b/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129Rtc.h @@ -0,0 +1,43 @@ +/** Pcf2129Rtc.h +* +* Copyright 2017 NXP +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the B= SD License +* which accompanies this distribution. The full text of the license may = be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#ifndef __PCF2129RTC_H__ +#define __PCF2129RTC_H__ + +/* + * RTC register addresses + */ +#define PCF2129_CTRL1_REG_ADDR 0x00 // Control Register 1 +#define PCF2129_CTRL2_REG_ADDR 0x01 // Control Register 2 +#define PCF2129_CTRL3_REG_ADDR 0x02 // Control Register 3 +#define PCF2129_SEC_REG_ADDR 0x03 +#define PCF2129_MIN_REG_ADDR 0x04 +#define PCF2129_HR_REG_ADDR 0x05 +#define PCF2129_DAY_REG_ADDR 0x06 +#define PCF2129_WEEKDAY_REG_ADDR 0x07 +#define PCF2129_MON_REG_ADDR 0x08 +#define PCF2129_YR_REG_ADDR 0x09 + +#define PCF2129_CTRL3_BIT_BLF BIT2 /* Battery Low Flag*/ + +// Define EPOCH (1998-JANUARY-01) in the Julian Date representation +#define EPOCH_JULIAN_DATE 2450815 + +typedef struct { + UINTN OperationCount; + EFI_I2C_OPERATION SetAddressOp; + EFI_I2C_OPERATION GetSetDateTimeOp; +} RTC_I2C_REQUEST; + +#endif // __PCF2129RTC_H__ diff --git a/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.c b/Silicon/NX= P/Library/Pcf2129RtcLib/Pcf2129RtcLib.c new file mode 100644 index 0000000..2e21014 --- /dev/null +++ b/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.c @@ -0,0 +1,330 @@ +/** @PCF2129RtcLib.c + Implement EFI RealTimeClock with runtime services via RTC Lib for PCF212= 9 RTC. + + Based on RTC implementation available in + EmbeddedPkg/Library/TemplateRealTimeClockLib/RealTimeClockLib.c + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+ Copyright 2017 NXP + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "Pcf2129Rtc.h" + +STATIC EFI_I2C_MASTER_PROTOCOL *mI2cMaster; + +/** + returns Day of the week [0-6] 0=3DSunday + Don't try to provide a Year that's before 1998, please ! + **/ +UINTN +EfiTimeToWday ( + IN EFI_TIME *Time + ) +{ + UINTN MonthDiff; + UINTN Year; + UINTN Month; + UINTN JulianDate; // Absolute Julian Date representation of the supplie= d Time + UINTN EpochDays; // Number of days elapsed since EPOCH_JULIAN_DAY + + MonthDiff =3D (14 - Time->Month) / 12 ; + Year =3D Time->Year + 4800 - MonthDiff; + Month =3D Time->Month + (12*MonthDiff) - 3; + + JulianDate =3D Time->Day + ((153*Month + 2)/5) + (365*Year) + (Year/4) -= (Year/100) + (Year/400) - 32045; + + ASSERT (JulianDate >=3D EPOCH_JULIAN_DATE); + EpochDays =3D JulianDate - EPOCH_JULIAN_DATE; + + // 4=3D1/1/1998 was a Thursday + + return (EpochDays + 4) % 7; +} + +/** + Write RTC register. + + @param RtcRegAddr Register offset of RTC to write. + @param Val Value to be written + +**/ + +STATIC +VOID +RtcWrite ( + IN UINT8 RtcRegAddr, + IN UINT8 Val + ) +{ + RTC_I2C_REQUEST Req; + EFI_STATUS Status; + + Req.OperationCount =3D 2; + + Req.SetAddressOp.Flags =3D 0; + Req.SetAddressOp.LengthInBytes =3D 0; + Req.SetAddressOp.Buffer =3D &RtcRegAddr; + + Req.GetSetDateTimeOp.Flags =3D 0; + Req.GetSetDateTimeOp.LengthInBytes =3D sizeof (Val); + Req.GetSetDateTimeOp.Buffer =3D &Val; + + Status =3D mI2cMaster->StartRequest (mI2cMaster, FixedPcdGet8 (PcdI2cSla= veAddress), + (VOID *)&Req, + NULL, NULL); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "RTC write error at Addr:0x%x\n", RtcRegAddr)); + } + +} + +/** + Returns the current time and date information, and the time-keeping capa= bilities + of the hardware platform. + + @param Time A pointer to storage to receive a snapshot= of the current time. + @param Capabilities An optional pointer to a buffer to receive= the real time clock + device's capabilities. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_INVALID_PARAMETER Time is NULL. + @retval EFI_DEVICE_ERROR The time could not be retrieved due to har= dware error. + +**/ + +EFI_STATUS +EFIAPI +LibGetTime ( + OUT EFI_TIME *Time, + OUT EFI_TIME_CAPABILITIES *Capabilities + ) +{ + EFI_STATUS Status; + UINT8 Buffer[10]; + RTC_I2C_REQUEST Req; + UINT8 RtcRegAddr; + + Status =3D EFI_SUCCESS; + RtcRegAddr =3D PCF2129_CTRL1_REG_ADDR; + Buffer[0] =3D 0; + + if (mI2cMaster =3D=3D NULL) { + return EFI_DEVICE_ERROR; + } + + RtcWrite (PCF2129_CTRL1_REG_ADDR, Buffer[0]); + + if (Time =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + Req.OperationCount =3D 2; + + Req.SetAddressOp.Flags =3D 0; + Req.SetAddressOp.LengthInBytes =3D 0; + Req.SetAddressOp.Buffer =3D &RtcRegAddr; + + Req.GetSetDateTimeOp.Flags =3D I2C_FLAG_READ; + Req.GetSetDateTimeOp.LengthInBytes =3D sizeof (Buffer); + Req.GetSetDateTimeOp.Buffer =3D Buffer; + + Status =3D mI2cMaster->StartRequest (mI2cMaster, FixedPcdGet8 (PcdI2cSla= veAddress), + (VOID *)&Req, + NULL, NULL); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "RTC read error at Addr:0x%x\n", RtcRegAddr)); + } + + if (Buffer[PCF2129_CTRL3_REG_ADDR] & PCF2129_CTRL3_BIT_BLF) { + DEBUG((DEBUG_INFO, "### Warning: RTC battery status low, check/replace= RTC battery.\n")); + } + + Time->Nanosecond =3D 0; + Time->Second =3D BcdToDecimal8 (Buffer[PCF2129_SEC_REG_ADDR] & 0x7F); + Time->Minute =3D BcdToDecimal8 (Buffer[PCF2129_MIN_REG_ADDR] & 0x7F); + Time->Hour =3D BcdToDecimal8 (Buffer[PCF2129_HR_REG_ADDR] & 0x3F); + Time->Day =3D BcdToDecimal8 (Buffer[PCF2129_DAY_REG_ADDR] & 0x3F); + Time->Month =3D BcdToDecimal8 (Buffer[PCF2129_MON_REG_ADDR] & 0x1F); + Time->Year =3D BcdToDecimal8 (Buffer[PCF2129_YR_REG_ADDR]) + ( BcdToDeci= mal8 (Buffer[PCF2129_YR_REG_ADDR]) >=3D 98 ? 1900 : 2000); + + return Status; +} + +/** + Sets the current local time and date information. + + @param Time A pointer to the current time. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_INVALID_PARAMETER A time field is out of range. + @retval EFI_DEVICE_ERROR The time could not be set due due to hardw= are error. + +**/ + +EFI_STATUS +EFIAPI +LibSetTime ( + IN EFI_TIME *Time + ) +{ + UINT8 Buffer[8]; + UINT8 Index; + EFI_STATUS Status; + RTC_I2C_REQUEST Req; + UINT8 RtcRegAddr; + + Index =3D 0; + Status =3D EFI_SUCCESS; + RtcRegAddr =3D PCF2129_CTRL1_REG_ADDR; + + if (mI2cMaster =3D=3D NULL) { + return EFI_DEVICE_ERROR; + } + + // start register address + Buffer[Index++] =3D PCF2129_SEC_REG_ADDR; + + // hours, minutes and seconds + Buffer[Index++] =3D DecimalToBcd8 (Time->Second); + Buffer[Index++] =3D DecimalToBcd8 (Time->Minute); + Buffer[Index++] =3D DecimalToBcd8 (Time->Hour); + Buffer[Index++] =3D DecimalToBcd8 (Time->Day); + Buffer[Index++] =3D EfiTimeToWday (Time) & 0x07; + Buffer[Index++] =3D DecimalToBcd8 (Time->Month); + Buffer[Index++] =3D DecimalToBcd8 (Time->Year % 100); + + Req.OperationCount =3D 2; + Req.SetAddressOp.Flags =3D 0; + Req.SetAddressOp.LengthInBytes =3D 0; + Req.SetAddressOp.Buffer =3D &RtcRegAddr; + + Req.GetSetDateTimeOp.Flags =3D 0; + Req.GetSetDateTimeOp.LengthInBytes =3D sizeof (Buffer); + Req.GetSetDateTimeOp.Buffer =3D Buffer; + + Status =3D mI2cMaster->StartRequest (mI2cMaster, FixedPcdGet8 (PcdI2cSla= veAddress), + (VOID *)&Req, + NULL, NULL); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "RTC write error at Addr:0x%x\n", RtcRegAddr)); + return Status; + } + + return Status; +} + + +/** + Returns the current wakeup alarm clock setting. + + @param Enabled Indicates if the alarm is currently enable= d or disabled. + @param Pending Indicates if the alarm signal is pending a= nd requires acknowledgement. + @param Time The current alarm setting. + + @retval EFI_SUCCESS The alarm settings were returned. + @retval EFI_INVALID_PARAMETER Any parameter is NULL. + @retval EFI_DEVICE_ERROR The wakeup time could not be retrieved due= to a hardware error. + @retval EFI_UNSUPPORTED A wakeup timer is not supported on this pl= atform. + +**/ +EFI_STATUS +EFIAPI +LibGetWakeupTime ( + OUT BOOLEAN *Enabled, + OUT BOOLEAN *Pending, + OUT EFI_TIME *Time + ) +{ + // Not a required feature + return EFI_UNSUPPORTED; +} + + +/** + Sets the system wakeup alarm clock time. + + @param Enabled Enable or disable the wakeup alarm. + @param Time If Enable is TRUE, the time to set the wak= eup alarm for. + + @retval EFI_SUCCESS If Enable is TRUE, then the wakeup alarm w= as enabled. If + Enable is FALSE, then the wakeup alarm was= disabled. + @retval EFI_INVALID_PARAMETER A time field is out of range. + @retval EFI_DEVICE_ERROR The wakeup time could not be set due to a = hardware error. + @retval EFI_UNSUPPORTED A wakeup timer is not supported on this pl= atform. + +**/ +EFI_STATUS +EFIAPI +LibSetWakeupTime ( + IN BOOLEAN Enabled, + OUT EFI_TIME *Time + ) +{ + // Not a required feature + return EFI_UNSUPPORTED; +} + +/** + This is the declaration of an EFI image entry point. This can be the ent= ry point to an application + written to this specification, an EFI boot service driver, or an EFI run= time driver. + + @param ImageHandle Handle that identifies the loaded image. + @param SystemTable System Table for this image. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_DEVICE_ERROR The operation could not be started. + +**/ +EFI_STATUS +EFIAPI +LibRtcInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + + EFI_STATUS Status; + EFI_I2C_MASTER_PROTOCOL *I2cMaster; + UINTN BusFrequency; + + Status =3D gBS->LocateProtocol (&gEfiI2cMasterProtocolGuid, NULL, (VOID = **)&I2cMaster); + + ASSERT_EFI_ERROR (Status); + + Status =3D I2cMaster->Reset (I2cMaster); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: I2CMaster->Reset () failed - %r\n", + __FUNCTION__, Status)); + return Status; + } + + BusFrequency =3D FixedPcdGet32 (PcdI2cSpeed); + Status =3D I2cMaster->SetBusFrequency (I2cMaster, &BusFrequency); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: I2CMaster->SetBusFrequency () failed - %r\n", + __FUNCTION__, Status)); + return Status; + } + + mI2cMaster =3D I2cMaster; + + return EFI_SUCCESS; +} diff --git a/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.inf b/Silicon/= NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.inf new file mode 100644 index 0000000..873bcea --- /dev/null +++ b/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.inf @@ -0,0 +1,47 @@ +#/** @Pcf2129RtcLib.inf +# +# Copyright 2017 NXP +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may b= e found at +# http://opensource.org/licenses/bsd-license.php +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +# +#**/ + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D Pcf2129RtcLib + FILE_GUID =3D B661E02D-A90B-42AB-A5F9-CF841AAA43D9 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D RealTimeClockLib + + +[Sources.common] + Pcf2129RtcLib.c + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + Silicon/NXP/NxpQoriqLs.dec + +[LibraryClasses] + DebugLib + UefiBootServicesTableLib + UefiLib + +[Protocols] + gEfiDriverBindingProtocolGuid ## CONSUMES + gEfiI2cMasterProtocolGuid ## CONSUMES + +[Pcd] + gNxpQoriqLsTokenSpaceGuid.PcdI2cBus + gNxpQoriqLsTokenSpaceGuid.PcdI2cSpeed + gNxpQoriqLsTokenSpaceGuid.PcdI2cSlaveAddress + +[Depex] + gEfiI2cMasterProtocolGuid --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun May 5 06:05:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" From: Meenakshi Aggarwal Library to provide board specific timings for LS1046ARDB board with interfacing to IFC controller for accessing FPGA and NAND. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Vabhav Signed-off-by: Meenakshi Aggarwal --- .../NXP/LS1046aRdbPkg/Include/IfcBoardSpecific.h | 83 ++++++++++++++++++= ++++ .../NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.c | 61 ++++++++++++++++ .../LS1046aRdbPkg/Library/BoardLib/BoardLib.inf | 31 ++++++++ 3 files changed, 175 insertions(+) create mode 100644 Platform/NXP/LS1046aRdbPkg/Include/IfcBoardSpecific.h create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.c create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.inf diff --git a/Platform/NXP/LS1046aRdbPkg/Include/IfcBoardSpecific.h b/Platfo= rm/NXP/LS1046aRdbPkg/Include/IfcBoardSpecific.h new file mode 100644 index 0000000..e15100d --- /dev/null +++ b/Platform/NXP/LS1046aRdbPkg/Include/IfcBoardSpecific.h @@ -0,0 +1,83 @@ +/** IfcBoardSpecificLib.h + + IFC Flash Board Specific Macros and structure + + Copyright 2017 NXP + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may be= found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ +#ifndef __IFC__BOARD_SPECIFIC_H__ +#define __IFC__BOARD_SPECIFIC_H__ + +#include + +// On board flash support +#define IFC_NAND_BUF_BASE 0x7E800000 + +// On board Inegrated flash Controller chip select configuration +#define IFC_NOR_CS IFC_CS_MAX +#define IFC_NAND_CS IFC_CS0 +#define IFC_FPGA_CS IFC_CS2 + +// board-specific NAND timing +#define NAND_FTIM0 (IFC_FTIM0_NAND_TCCST(0x7) | \ + IFC_FTIM0_NAND_TWP(0x18) | \ + IFC_FTIM0_NAND_TWCHT(0x7) | \ + IFC_FTIM0_NAND_TWH(0xa)) + +#define NAND_FTIM1 (IFC_FTIM1_NAND_TADLE(0x32) | \ + IFC_FTIM1_NAND_TWBE(0x39) | \ + IFC_FTIM1_NAND_TRR(0xe) | \ + IFC_FTIM1_NAND_TRP(0x18)) + +#define NAND_FTIM2 (IFC_FTIM2_NAND_TRAD(0xf) | \ + IFC_FTIM2_NAND_TREH(0xa) | \ + IFC_FTIM2_NAND_TWHRE(0x1e)) + +#define NAND_FTIM3 0x0 + +#define NAND_CSPR (IFC_CSPR_PHYS_ADDR(IFC_NAND_BUF_BASE) \ + | IFC_CSPR_PORT_SIZE_8 \ + | IFC_CSPR_MSEL_NAND \ + | IFC_CSPR_V) + +#define NAND_CSPR_EXT 0x0 +#define NAND_AMASK 0xFFFF0000 + +#define NAND_CSOR (IFC_CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | IFC_CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | IFC_CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \ + | IFC_CSOR_NAND_RAL_3 /* RAL =3D 3 Bytes */ \ + | IFC_CSOR_NAND_PGS_4K /* Page Size =3D 4K */ \ + | IFC_CSOR_NAND_SPRZ_224 /* Spare size =3D 224 *= / \ + | IFC_CSOR_NAND_PB(6)) /* 2^6 Pages Per Block */ + +// board-specific fpga timing +#define FPGA_BASE_PHYS 0x7fb00000 +#define FPGA_CSPR_EXT 0x0 +#define FPGA_CSPR (IFC_CSPR_PHYS_ADDR(FPGA_BASE_PHYS) | \ + IFC_CSPR_PORT_SIZE_8 | \ + IFC_CSPR_MSEL_GPCM | \ + IFC_CSPR_V) + +#define FPGA_AMASK IFC_AMASK(64 * 1024) +#define FPGA_CSOR IFC_CSOR_NOR_ADM_SHIFT(16) + +#define FPGA_FTIM0 (IFC_FTIM0_GPCM_TACSE(0x0e) | \ + IFC_FTIM0_GPCM_TEADC(0x0e) | \ + IFC_FTIM0_GPCM_TEAHC(0x0e)) +#define FPGA_FTIM1 (IFC_FTIM1_GPCM_TACO(0xff) | \ + IFC_FTIM1_GPCM_TRAD(0x3f)) +#define FPGA_FTIM2 (IFC_FTIM2_GPCM_TCS(0xf) | \ + IFC_FTIM2_GPCM_TCH(0xf) | \ + IFC_FTIM2_GPCM_TWP(0x3E)) +#define FPGA_FTIM3 0x0 + +#endif //__IFC__BOARD_SPECIFIC_H__ diff --git a/Platform/NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.c b/Platf= orm/NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.c new file mode 100644 index 0000000..0971935 --- /dev/null +++ b/Platform/NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.c @@ -0,0 +1,61 @@ +/** @file + + Copyright 2018 NXP + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include + +VOID +GetIfcNorFlashTimings ( + IN IFC_TIMINGS * NorIfcTimings + ) +{ + NorIfcTimings->CS =3D IFC_NOR_CS; + + return ; +} + +VOID +GetIfcFpgaTimings ( + IN IFC_TIMINGS *FpgaIfcTimings + ) +{ + FpgaIfcTimings->Ftim[0] =3D FPGA_FTIM0; + FpgaIfcTimings->Ftim[1] =3D FPGA_FTIM1; + FpgaIfcTimings->Ftim[2] =3D FPGA_FTIM2; + FpgaIfcTimings->Ftim[3] =3D FPGA_FTIM3; + FpgaIfcTimings->Cspr =3D FPGA_CSPR; + FpgaIfcTimings->CsprExt =3D FPGA_CSPR_EXT; + FpgaIfcTimings->Amask =3D FPGA_AMASK; + FpgaIfcTimings->Csor =3D FPGA_CSOR; + FpgaIfcTimings->CS =3D IFC_FPGA_CS; + + return; +} + +VOID +GetIfcNandFlashTimings ( + IN IFC_TIMINGS * NandIfcTimings + ) +{ + NandIfcTimings->Ftim[0] =3D NAND_FTIM0; + NandIfcTimings->Ftim[1] =3D NAND_FTIM1; + NandIfcTimings->Ftim[2] =3D NAND_FTIM2; + NandIfcTimings->Ftim[3] =3D NAND_FTIM3; + NandIfcTimings->Cspr =3D NAND_CSPR; + NandIfcTimings->CsprExt =3D NAND_CSPR_EXT; + NandIfcTimings->Amask =3D NAND_AMASK; + NandIfcTimings->Csor =3D NAND_CSOR; + NandIfcTimings->CS =3D IFC_NAND_CS; + + return; +} diff --git a/Platform/NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.inf b/Pla= tform/NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.inf new file mode 100644 index 0000000..151c383 --- /dev/null +++ b/Platform/NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.inf @@ -0,0 +1,31 @@ +# @file +# +# Copyright 2018 NXP +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D BoardLib + FILE_GUID =3D 66041dab-97b4-4b45-b9b4-1209a2d55d7a + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D BoardLib + +[Sources.common] + BoardLib.c + +[Packages] + MdePkg/MdePkg.dec + Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dec + Silicon/NXP/NxpQoriqLs.dec + +[FixedPcd] + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun May 5 06:05:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; 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charset="utf-8" From: Vabhav Adding support of ArmPlatformLib for NXP LS1046ARDB board Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Vabhav Signed-off-by: Meenakshi Aggarwal --- .../Library/PlatformLib/ArmPlatformLib.c | 105 ++++++++++++++ .../Library/PlatformLib/ArmPlatformLib.inf | 66 +++++++++ .../Library/PlatformLib/NxpQoriqLsHelper.S | 35 +++++ .../Library/PlatformLib/NxpQoriqLsMem.c | 152 +++++++++++++++++= ++++ 4 files changed, 358 insertions(+) create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatf= ormLib.c create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatf= ormLib.inf create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriq= LsHelper.S create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriq= LsMem.c diff --git a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.= c b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.c new file mode 100644 index 0000000..a0bb01d --- /dev/null +++ b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.c @@ -0,0 +1,105 @@ +/** ArmPlatformLib.c +* +* Contains board initialization functions. +* +* Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoard.c +* +* Copyright (c) 2011-2012, ARM Limited. All rights reserved. +* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved. +* Copyright 2017 NXP +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the B= SD License +* which accompanies this distribution. The full text of the license may = be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#include +#include + +extern VOID SocInit (VOID); + +/** + Return the current Boot Mode + + This function returns the boot reason on the platform + +**/ +EFI_BOOT_MODE +ArmPlatformGetBootMode ( + VOID + ) +{ + return BOOT_WITH_FULL_CONFIGURATION; +} + +/** + Placeholder for Platform Initialization +**/ +EFI_STATUS +ArmPlatformInitialize ( + IN UINTN MpId + ) +{ + SocInit (); + + return EFI_SUCCESS; +} + +ARM_CORE_INFO LS1046aMpCoreInfoCTA72x4[] =3D { + { + // Cluster 0, Core 0 + 0x0, 0x0, + + // MP Core MailBox Set/Get/Clear Addresses and Clear Value + (EFI_PHYSICAL_ADDRESS)0, + (EFI_PHYSICAL_ADDRESS)0, + (EFI_PHYSICAL_ADDRESS)0, + (UINT64)0xFFFFFFFF + }, +}; + +EFI_STATUS +PrePeiCoreGetMpCoreInfo ( + OUT UINTN *CoreCount, + OUT ARM_CORE_INFO **ArmCoreTable + ) +{ + *CoreCount =3D sizeof (LS1046aMpCoreInfoCTA72x4) / sizeof (ARM_CORE_I= NFO); + *ArmCoreTable =3D LS1046aMpCoreInfoCTA72x4; + + return EFI_SUCCESS; +} + +ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi =3D { PrePeiCoreGetMpCoreInfo }; + +EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] =3D { + { + EFI_PEI_PPI_DESCRIPTOR_PPI, + &gArmMpCoreInfoPpiGuid, + &mMpCoreInfoPpi + } +}; + +VOID +ArmPlatformGetPlatformPpiList ( + OUT UINTN *PpiListSize, + OUT EFI_PEI_PPI_DESCRIPTOR **PpiList + ) +{ + *PpiListSize =3D sizeof (gPlatformPpiTable); + *PpiList =3D gPlatformPpiTable; +} + + +UINTN +ArmPlatformGetCorePosition ( + IN UINTN MpId + ) +{ + return 1; +} diff --git a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.= inf b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf new file mode 100644 index 0000000..49b57fc --- /dev/null +++ b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf @@ -0,0 +1,66 @@ +# @file +# +# Copyright 2017 NXP +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D PlatformLib + FILE_GUID =3D 05a9029b-266f-421d-bb46-0e8385c64aa0 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D ArmPlatformLib + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + Silicon/NXP/NxpQoriqLs.dec + +[LibraryClasses] + ArmLib + SocLib + +[Sources.common] + NxpQoriqLsHelper.S | GCC + NxpQoriqLsMem.c + ArmPlatformLib.c + +[Ppis] + gArmMpCoreInfoPpiGuid + +[FixedPcd] + gArmTokenSpaceGuid.PcdArmPrimaryCore + gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size + gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize + gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize + gNxpQoriqLsTokenSpaceGuid.PcdDram1BaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdDram1Size + gNxpQoriqLsTokenSpaceGuid.PcdDram2BaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdDram2Size + gNxpQoriqLsTokenSpaceGuid.PcdDram3BaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdDram3Size + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize diff --git a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsHelpe= r.S b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S new file mode 100644 index 0000000..6d54091 --- /dev/null +++ b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S @@ -0,0 +1,35 @@ +# @file +# +# Copyright (c) 2012-2013, ARM Limited. All rights reserved. +# Copyright 2017 NXP +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +# + +#include +#include + +.text +.align 2 + +GCC_ASM_IMPORT(ArmReadMpidr) + +ASM_FUNC(ArmPlatformIsPrimaryCore) + tst x0, #3 + cset x0, eq + ret + +ASM_FUNC(ArmPlatformPeiBootAction) + ret + +ASM_FUNC(ArmPlatformGetPrimaryCoreMpId) + MOV32 (x0, FixedPcdGet32(PcdArmPrimaryCore)) + ldrh w0, [x0] + ret diff --git a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c= b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c new file mode 100644 index 0000000..64c5612 --- /dev/null +++ b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c @@ -0,0 +1,152 @@ +/** NxpQoriqLsMem.c +* +* Board memory specific Library. +* +* Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoardMem.c +* +* Copyright (c) 2011, ARM Limited. All rights reserved. +* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved. +* Copyright 2017 NXP +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the B= SD License +* which accompanies this distribution. The full text of the license may b= e found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#include +#include +#include +#include + +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 25 + +/** + Return the Virtual Memory Map of your platform + + This Virtual Memory Map is used by MemoryInitPei Module to initialize th= e MMU on your platform. + + @param VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR descr= ibing a Physical-to- + Virtual Memory mapping. This array must be = ended by a zero-filled + entry + +**/ + +VOID +ArmPlatformGetVirtualMemoryMap ( + IN ARM_MEMORY_REGION_DESCRIPTOR **VirtualMemoryMap + ) +{ + UINTN Index; + ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; + + Index =3D 0; + + ASSERT (VirtualMemoryMap !=3D NULL); + + VirtualMemoryTable =3D (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages ( + EFI_SIZE_TO_PAGES (sizeof (ARM_MEMORY_REGION_DESCRIPTOR) * MAX_V= IRTUAL_MEMORY_MAP_DESCRIPTORS)); + + if (VirtualMemoryTable =3D=3D NULL) { + return; + } + + // DRAM1 (Must be 1st entry) + VirtualMemoryTable[Index].PhysicalBase =3D FixedPcdGet64 (PcdDram1BaseAd= dr); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdDram1BaseAd= dr); + VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdDram1Size); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_W= RITE_BACK; + + // CCSR Space + VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdCcsrBaseA= ddr); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdCcsrBaseAdd= r); + VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdCcsrSize); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + // IFC region 1 + // + // A-009241 : Unaligned write transactions to IFC may result in corrup= tion of data + // Affects : IFC + // Description: 16 byte unaligned write from system bus to IFC may resul= t in extra unintended + // writes on external IFC interface that can corrupt data o= n external flash. + // Impact : Data corruption on external flash may happen in case of = unaligned writes to + // IFC memory space. + // Workaround: Following are the workarounds: + // For write transactions from core, IFC interface memories = (including IFC SRAM) + // should be configured as device type memory in MMU. + // For write transactions from non-core masters (like system= DMA), the address + // should be 16 byte aligned and the data size should be = multiple of 16 bytes. + // + VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdIfcRegion= 1BaseAddr); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdIfcRegion1B= aseAddr); + VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdIfcRegion1S= ize); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + // QMAN SWP + VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdQmanSwpBa= seAddr); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdQmanSwpBase= Addr); + VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdQmanSwpSize= ); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_U= NCACHED_UNBUFFERED; + + // BMAN SWP + VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdBmanSwpBa= seAddr); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdBmanSwpBase= Addr); + VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdBmanSwpSize= ); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_U= NCACHED_UNBUFFERED; + + // IFC region 2 + VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdIfcRegion= 2BaseAddr); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdIfcRegion2B= aseAddr); + VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdIfcRegion2S= ize); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + // DRAM2 + VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdDram2Base= Addr); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdDram2BaseAd= dr); + VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdDram2Size); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_W= RITE_BACK; + + // PCIe1 + VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdPciExp1Ba= seAddr); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdPciExp1Base= Addr); + VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdPciExp1Base= Size); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + // PCIe2 + VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdPciExp2Ba= seAddr); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdPciExp2Base= Addr); + VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdPciExp2Base= Size); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + // PCIe3 + VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdPciExp3Ba= seAddr); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdPciExp3Base= Addr); + VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdPciExp3Base= Size); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + // DRAM3 + VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdDram3Base= Addr); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdDram3BaseAd= dr); + VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdDram3Size); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_W= RITE_BACK; + + // QSPI region + VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdQspiRegio= nBaseAddr); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdQspiRegionB= aseAddr); + VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdQspiRegionS= ize); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_U= NCACHED_UNBUFFERED; + + // End of Table + VirtualMemoryTable[++Index].PhysicalBase =3D 0; + VirtualMemoryTable[Index].VirtualBase =3D 0; + VirtualMemoryTable[Index].Length =3D 0; + VirtualMemoryTable[Index].Attributes =3D (ARM_MEMORY_REGION_ATTRIBUTES= )0; + + ASSERT ((Index + 1) <=3D MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS); + + *VirtualMemoryMap =3D VirtualMemoryTable; +} --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun May 5 06:05:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; 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charset="utf-8" From: Meenakshi Aggarwal Library to provide functions for accessing FPGA on LS1046ARDB board. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Vabhav Signed-off-by: Meenakshi Aggarwal --- .../NXP/LS1046aRdbPkg/Include/Library/FpgaLib.h | 97 ++++++++++++++ .../NXP/LS1046aRdbPkg/Library/FpgaLib/FpgaLib.c | 144 +++++++++++++++++= ++++ .../NXP/LS1046aRdbPkg/Library/FpgaLib/FpgaLib.inf | 32 +++++ 3 files changed, 273 insertions(+) create mode 100644 Platform/NXP/LS1046aRdbPkg/Include/Library/FpgaLib.h create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/FpgaLib/FpgaLib.c create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/FpgaLib/FpgaLib.inf diff --git a/Platform/NXP/LS1046aRdbPkg/Include/Library/FpgaLib.h b/Platfor= m/NXP/LS1046aRdbPkg/Include/Library/FpgaLib.h new file mode 100644 index 0000000..c8f7411 --- /dev/null +++ b/Platform/NXP/LS1046aRdbPkg/Include/Library/FpgaLib.h @@ -0,0 +1,97 @@ +/** FpgaLib.h +* Header defining the LS1046a Fpga specific constants (Base addresses, si= zes, flags) +* +* Copyright 2017 NXP +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the B= SD License +* which accompanies this distribution. The full text of the license may = be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#ifndef __LS1046A_FPGA_H__ +#define __LS1046A_FPGA_H__ + +/** + FPGA register set of LS1046ARDB board-specific. + **/ +typedef struct { + UINT8 FpgaVersionMajor; // 0x0 - FPGA Major Revision Register + UINT8 FpgaVersionMinor; // 0x1 - FPGA Minor Revision Register + UINT8 PcbaVersion; // 0x2 - PCBA Revision Register + UINT8 SystemReset; // 0x3 - system reset register + UINT8 SoftMuxOn; // 0x4 - Switch Control Enable Register + UINT8 RcwSource1; // 0x5 - Reset config word 1 + UINT8 RcwSource2; // 0x6 - Reset config word 1 + UINT8 Vbank; // 0x7 - Flash bank selection Control + UINT8 SysclkSelect; // 0x8 - System clock selection Control + UINT8 UartSel; // 0x9 - Uart selection Control + UINT8 Sd1RefClkSel; // 0xA - Serdes1 reference clock selection Cont= rol + UINT8 TdmClkMuxSel; // 0xB - TDM Clock Mux selection Control + UINT8 SdhcSpiCsSel; // 0xC - SDHC/SPI Chip select selection Control + UINT8 StatusLed; // 0xD - Status Led + UINT8 GlobalReset; // 0xE - Global reset + UINT8 SdEmmc; // 0xF - SD or EMMC Interface Control Regsiter + UINT8 VddEn; // 0x10 - VDD Voltage Control Enable Register + UINT8 VddSel; // 0x11 - VDD Voltage Control Register +} FPGA_REG_SET; + +/** + Function to read FPGA register. +**/ +UINT8 +FpgaRead ( + UINTN Reg + ); + +/** + Function to write FPGA register. +**/ +VOID +FpgaWrite ( + UINTN Reg, + UINT8 Value + ); + +/** + Function to read FPGA revision. +**/ +VOID +FpgaRevBit ( + UINT8 *Value + ); + +/** + Function to initialize FPGA timings. +**/ +VOID +FpgaInit ( + VOID + ); + +/** + Function to print board personality. +**/ +VOID +PrintBoardPersonality ( + VOID + ); + +#define FPGA_BASE_PHYS 0x7fb00000 + +#define SRC_VBANK 0x25 +#define SRC_NAND 0x106 +#define SRC_QSPI 0x44 +#define SRC_SD 0x40 + +#define SERDES_FREQ1 "100.00 MHz" +#define SERDES_FREQ2 "156.25 MHz" + +#define FPGA_READ(Reg) FpgaRead (OFFSET_OF (FPGA_REG_SET, Reg)) +#define FPGA_WRITE(Reg, Value) FpgaWrite (OFFSET_OF (FPGA_REG_SET, Reg), = Value) + +#endif diff --git a/Platform/NXP/LS1046aRdbPkg/Library/FpgaLib/FpgaLib.c b/Platfor= m/NXP/LS1046aRdbPkg/Library/FpgaLib/FpgaLib.c new file mode 100644 index 0000000..90cc1ea --- /dev/null +++ b/Platform/NXP/LS1046aRdbPkg/Library/FpgaLib/FpgaLib.c @@ -0,0 +1,144 @@ +/** @FpgaLib.c + Fpga Library for LS1046A-RDB board, containing functions to + program and read the Fpga registers. + + FPGA is connected to IFC Controller and so MMIO APIs are used + to read/write FPGA registers + + Copyright 2017 NXP + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may be= found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include +#include +#include +#include +#include + +/** + Function to read FPGA register. + + @param Reg Register offset of FPGA to read. + +**/ +UINT8 +FpgaRead ( + IN UINTN Reg + ) +{ + VOID *Base; + + Base =3D (VOID *)FPGA_BASE_PHYS; + + return MmioRead8 ((UINTN)(Base + Reg)); +} + +/** + Function to write FPGA register. + + @param Reg Register offset of FPGA to write. + @param Value Value to be written. + +**/ +VOID +FpgaWrite ( + IN UINTN Reg, + IN UINT8 Value + ) +{ + VOID *Base; + + Base =3D (VOID *)FPGA_BASE_PHYS; + + MmioWrite8 ((UINTN)(Base + Reg), Value); +} + +/** + Function to reverse the number. + + @param *Value pointer to number to reverse. + + @retval *Value reversed value. + +**/ +VOID +FpgaRevBit ( + OUT UINT8 *Value + ) +{ + UINT8 Rev; + UINT8 Val; + UINTN Index; + + Val =3D *Value; + Rev =3D Val & 1; + for (Index =3D 1; Index <=3D 7; Index++) { + Val >>=3D 1; + Rev <<=3D 1; + Rev |=3D Val & 1; + } + + *Value =3D Rev; +} + +/** + Function to print board personality. + +**/ +VOID +PrintBoardPersonality ( + VOID + ) +{ + UINT8 RcwSrc1; + UINT8 RcwSrc2; + UINT32 RcwSrc; + UINT32 Sd1RefClkSel; + + RcwSrc1 =3D FPGA_READ(RcwSource1); + RcwSrc2 =3D FPGA_READ(RcwSource2); + FpgaRevBit (&RcwSrc1); + RcwSrc =3D RcwSrc1; + RcwSrc =3D (RcwSrc << 1) | RcwSrc2; + + switch (RcwSrc) { + case SRC_VBANK: + DEBUG ((DEBUG_INFO, "vBank: %d\n", FPGA_READ(Vbank))); + break; + case SRC_NAND: + DEBUG ((DEBUG_INFO, "NAND\n")); + break; + case SRC_QSPI: + DEBUG ((DEBUG_INFO, "QSPI vBank %d\n", FPGA_READ(Vbank))); + break; + case SRC_SD: + DEBUG ((DEBUG_INFO, "SD\n")); + break; + default: + DEBUG ((DEBUG_INFO, "Invalid setting of SW5\n")); + break; + } + + DEBUG ((DEBUG_INFO, "FPGA: V%x.%x\nPCBA: V%x.0\n", + FPGA_READ(FpgaVersionMajor), + FPGA_READ(FpgaVersionMinor), + FPGA_READ(PcbaVersion))); + + DEBUG ((DEBUG_INFO, "SERDES Reference Clocks:\n")); + + Sd1RefClkSel =3D FPGA_READ(Sd1RefClkSel); + DEBUG((DEBUG_INFO, "SD1_CLK1 =3D %a, SD1_CLK2 =3D %a\n", + Sd1RefClkSel ? SERDES_FREQ2 : SERDES_FREQ1, SERDES_FREQ1)); + DEBUG((DEBUG_INFO, "SD2_CLK1 =3D %a, SD2_CLK2 =3D %a\n", + SERDES_FREQ1, SERDES_FREQ1)); + + return; +} diff --git a/Platform/NXP/LS1046aRdbPkg/Library/FpgaLib/FpgaLib.inf b/Platf= orm/NXP/LS1046aRdbPkg/Library/FpgaLib/FpgaLib.inf new file mode 100644 index 0000000..afc41e3 --- /dev/null +++ b/Platform/NXP/LS1046aRdbPkg/Library/FpgaLib/FpgaLib.inf @@ -0,0 +1,32 @@ +# @FpgaLib.inf +# +# Copyright 2017 NXP +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# + +[Defines] + INF_VERSION =3D 0x0001000A + BASE_NAME =3D FpgaLib + FILE_GUID =3D 6e06ebbf-3a1d-47be-b4f6-1d82f2a9ac73 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D FpgaLib + +[Sources.common] + FpgaLib.c + +[Packages] + MdePkg/MdePkg.dec + Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dec + Silicon/NXP/NxpQoriqLs.dec + +[LibraryClasses] + BaseLib + IoLib --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun May 5 06:05:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; 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charset="utf-8" From: Vabhav Adding firmware device,description and declaration files to enable compilation for NXP LS1046ARDB board. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Vabhav --- Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dec | 29 ++++ Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc | 94 +++++++++++++ Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf | 197 +++++++++++++++++++++++= ++++ 3 files changed, 320 insertions(+) create mode 100644 Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dec create mode 100644 Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc create mode 100644 Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf diff --git a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dec b/Platform/NXP/LS= 1046aRdbPkg/LS1046aRdbPkg.dec new file mode 100644 index 0000000..a872ade --- /dev/null +++ b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dec @@ -0,0 +1,29 @@ +# LS1046aRdbPkg.dec +# LS1046a board package. +# +# Copyright 2017 NXP +# +# This program and the accompanying materials are licensed and made avail= able under +# the terms and conditions of the BSD License which accompanies this dist= ribution. +# The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# + +[Defines] + PACKAGE_NAME =3D LS1046aRdbPkg + PACKAGE_GUID =3D c0c8d5e4-f63b-4470-89bc-73c13c13b247 + +##########################################################################= ###### +# +# Include Section - list of Include Paths that are provided by this packag= e. +# Comments are used for Keywords and Module Types. +# +# Supported Module Types: +# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_D= RIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION +# +##########################################################################= ###### +[Includes.common] + Include # Root include for the package diff --git a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc b/Platform/NXP/LS= 1046aRdbPkg/LS1046aRdbPkg.dsc new file mode 100644 index 0000000..36002d5 --- /dev/null +++ b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc @@ -0,0 +1,94 @@ +# LS1046aRdbPkg.dsc +# +# LS1046ARDB Board package. +# +# Copyright 2017 NXP +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may b= e found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# + +##########################################################################= ###### +# +# Defines Section - statements that will be processed to create a Makefile. +# +##########################################################################= ###### +[Defines] + # + # Defines for default states. These can be changed on the command line. + # -D FLAG=3DVALUE + # + PLATFORM_NAME =3D LS1046aRdbPkg + PLATFORM_GUID =3D 43920156-3f3b-4199-9b29-c6db1fb792b0 + OUTPUT_DIRECTORY =3D Build/LS1046aRdbPkg + FLASH_DEFINITION =3D Platform/NXP/LS1046aRdbPkg/LS1046aRdb= Pkg.fdf + +!include ../NxpQoriqLs.dsc +!include ../../../Silicon/NXP/LS1046A/LS1046A.dsc + +[LibraryClasses.common] + ArmPlatformLib|Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatfor= mLib.inf + ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSy= stemLib.inf + SerialPortLib|Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf + BeIoLib|Silicon/NXP/Library/BeIoLib/BeIoLib.inf + SocLib|Silicon/NXP/Chassis/LS1046aSocLib.inf + RealTimeClockLib|Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.inf + IfcLib|Silicon/NXP/Library/IfcLib/IfcLib.inf + BoardLib|Platform/NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.inf + FpgaLib|Platform/NXP/LS1046aRdbPkg/Library/FpgaLib/FpgaLib.inf + +[PcdsFixedAtBuild.common] + + # + # LS1046a board Specific PCDs + # XX (DRAM - Region 1 2GB) + # (NOR - IFC Region 1 512MB) + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000 + gArmTokenSpaceGuid.PcdSystemMemorySize|0x80000000 + gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x02000000 + + # + # Board Specific Pcds + # + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500 + gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|TRUE + gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x2 + + # + # Big Endian IPs + # + gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|TRUE + gNxpQoriqLsTokenSpaceGuid.PcdWdogBigEndian|TRUE + gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian|TRUE + + # + # I2C controller Pcds + # + gNxpQoriqLsTokenSpaceGuid.PcdI2cBus|3 + + # + # RTC Pcds + # + gNxpQoriqLsTokenSpaceGuid.PcdI2cSlaveAddress|0x51 + gNxpQoriqLsTokenSpaceGuid.PcdI2cSpeed|100000 + +##########################################################################= ###### +# +# Components Section - list of all EDK II Modules needed by this Platform +# +##########################################################################= ###### +[Components.common] + # + # Architectural Protocols + # + MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf + + Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf + Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf + + ## diff --git a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf b/Platform/NXP/LS= 1046aRdbPkg/LS1046aRdbPkg.fdf new file mode 100644 index 0000000..834e3a4 --- /dev/null +++ b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf @@ -0,0 +1,197 @@ +# LS1046aRdbPkg.fdf +# +# FLASH layout file for LS1046a board. +# +# Copyright (c) 2016, Freescale Ltd. All rights reserved. +# Copyright 2017 NXP +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may b= e found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# + +##########################################################################= ###### +# +# FD Section +# The [FD] Section is made up of the definition statements and a +# description of what goes into the Flash Device Image. Each FD section +# defines one flash "device" image. A flash device image may be one of +# the following: Removable media bootable image (like a boot floppy +# image,) an Option ROM image (that would be "flashed" into an add-in +# card,) a System "Flash" image (that would be burned into a system's +# flash) or an Update ("Capsule") image that will be used to update and +# existing system flash. +# +##########################################################################= ###### + +[FD.LS1046ARDB_EFI] +BaseAddress =3D 0x82000000|gArmTokenSpaceGuid.PcdFdBaseAddress #The bas= e address of the FLASH Device. +Size =3D 0x000EC890|gArmTokenSpaceGuid.PcdFdSize #The siz= e in bytes of the FLASH Device +ErasePolarity =3D 1 +BlockSize =3D 0x1 +NumBlocks =3D 0xEC890 + +##########################################################################= ###### +# +# Following are lists of FD Region layout which correspond to the location= s of different +# images within the flash device. +# +# Regions must be defined in ascending order and may not overlap. +# +# A Layout Region start with a eight digit hex offset (leading "0x" requir= ed) followed by +# the pipe "|" character, followed by the size of the region, also in hex = with the leading +# "0x" characters. Like: +# Offset|Size +# PcdOffsetCName|PcdSizeCName +# RegionType +# +##########################################################################= ###### +0x00000000|0x000EC890 +gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize +FV =3D FVMAIN_COMPACT + +!include ../FVRules.fdf.inc +##########################################################################= ###### +# +# FV Section +# +# [FV] section is used to define what components or modules are placed wit= hin a flash +# device file. This section also defines order the components and modules= are positioned +# within the image. The [FV] section consists of define statements, set s= tatements and +# module statements. +# +##########################################################################= ###### + +[FV.FvMain] +FvNameGuid =3D 1037c42b-8452-4c41-aac7-41e6c31468da +BlockSize =3D 0x1 +NumBlocks =3D 0 # This FV gets compressed so make it just= big enough +FvAlignment =3D 8 # FV alignment and FV attributes setting. +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE + + INF MdeModulePkg/Core/Dxe/DxeMain.inf + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + + # + # PI DXE Drivers producing Architectural Protocols (EFI Services) + # + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf + + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf + INF Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf + INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.= inf + INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.i= nf + + INF Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf + + INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + + # + # Multiple Console IO support + # + INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe= .inf + INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + + INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf + + # + # Network modules + # + INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf + INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf + INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf + INF MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf + INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf + INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf + INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf + INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf + INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf + INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf + INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf +!if $(NETWORK_IP6_ENABLE) =3D=3D TRUE + INF NetworkPkg/Ip6Dxe/Ip6Dxe.inf + INF NetworkPkg/TcpDxe/TcpDxe.inf + INF NetworkPkg/Udp6Dxe/Udp6Dxe.inf + INF NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf + INF NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf + INF NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf +!else + INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf +!endif + + # + # FAT filesystem + GPT/MBR partitioning + # + INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.i= nf + INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + INF FatPkg/FatPei/FatPei.inf + INF FatPkg/EnhancedFatDxe/Fat.inf + + # + # UEFI application (Shell Embedded Boot Loader) + # + INF ShellPkg/Application/Shell/Shell.inf + + # + # Bds + # + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + INF MdeModulePkg/Application/UiApp/UiApp.inf + +[FV.FVMAIN_COMPACT] +FvAlignment =3D 8 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE + + INF ArmPlatformPkg/PrePi/PeiUniCore.inf + + FILE FV_IMAGE =3D c1c1e1a2-3879-4b5e-9dd1-3df2ce60d8ec { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRE= D =3D TRUE { + SECTION FV_IMAGE =3D FVMAIN + } + } --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun May 5 06:05:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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VI1PR04MB1008; 6:KOMMlAqvkzk9DUg1g6WHK+IKG8Q7iBqOeSReZpRUQPefGZmQbaZbDhVPP1Okrv6a57MY2EZTlIGZhqq/Ksmupd+FO1pBNFrqwfeImioHKAnx+/vOeOTCM7F4YYryWpr60Tu1OtSX507w13zcYeYXCHUdQdudTpusrkJXuZGvzqggxdvR+QOIDl9pp3vSlNcJGIyKzWFtV52WBLExNTNucEKHVwYxo1r3yGM9i4U6lN6VBcDAGYv0ffCIf1Dcaxga9sk1Jry524HWARGCWvIzyGWRyrlrCS/HKOweB9Wau/PoAnGMhjf1rI4Zk0ZxWn7w3nqBGgdW7UhlH4TzqjIds96gB61B8pQkwWSjrWHvxEM=; 5:ja+92p347/L2HBn2R/S7j+9u4BetDIEAX3Nb5vOCHPVarmcqUmNNuEkQG+aDWLUjSTl7aYjRgI6duEpI9DCYRLkO9x/ffmRrzxq9qFRjybaJXLRBDvqzF8FS7cFXpBvcYuUmQ4MoIoXDyEzh1aF9eGg1CR9C05MI4NpiOfsjbis=; 24:bfuTM0178AJXvn7CbAM2CXx3Y3s8zCVwoms5jdp8blHX0iaRZTVo7x3wWcNMNDVGH2HOIl5BqqUjFQ2NzPjHVspc1WQ/1eEAWELbs7JOUvY=; 7:Omj+7bMiweKm+IX35zWkLFvU4SwKwaHxmPQm7PQXsG+tbW6/ACuIUinFrU3miacao90N+N4pBONtBroJR248KW2FHysMlL3eJUukeGzcLIiwr4q/AMrChKlaun1mYFvu9NRbrhnYz7YW3hIKv0rNuoWuPxApk2DDlNcPbhLGhzgkPhPOyivgHEZ91gF9atDdPw4LKiNvFZ3M/jnpL2cJmcp/42zEsG3P8BNfpa2Vyr+cezus6IWnh4aeCHZl7F4K SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Feb 2018 08:54:17.0923 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 65b6d4c4-a21b-4047-b49a-08d5751ade35 X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB1008 Subject: [edk2] [PATCH edk2-platforms 24/39] Silicon/NXP:SocLib support for initialization of peripherals X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Wasim Khan Added SocInit function that initializes peripherals and print board and soc information for LS2088ARDB Board. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Wasim Khan --- Silicon/NXP/Chassis/Chassis.c | 35 ++++++ Silicon/NXP/Chassis/Chassis.h | 17 +++ Silicon/NXP/Chassis/Chassis3/Chassis3.dec | 19 ++++ Silicon/NXP/Chassis/Chassis3/SerDes.h | 91 +++++++++++++++ Silicon/NXP/Chassis/Chassis3/Soc.c | 180 ++++++++++++++++++++++++++= ++++ Silicon/NXP/Chassis/Chassis3/Soc.h | 150 +++++++++++++++++++++++++ Silicon/NXP/Chassis/LS2088aSocLib.inf | 48 ++++++++ Silicon/NXP/LS2088A/Include/SocSerDes.h | 67 +++++++++++ 8 files changed, 607 insertions(+) create mode 100644 Silicon/NXP/Chassis/Chassis3/Chassis3.dec create mode 100644 Silicon/NXP/Chassis/Chassis3/SerDes.h create mode 100644 Silicon/NXP/Chassis/Chassis3/Soc.c create mode 100644 Silicon/NXP/Chassis/Chassis3/Soc.h create mode 100644 Silicon/NXP/Chassis/LS2088aSocLib.inf create mode 100644 Silicon/NXP/LS2088A/Include/SocSerDes.h diff --git a/Silicon/NXP/Chassis/Chassis.c b/Silicon/NXP/Chassis/Chassis.c index ce07fdc..b63efdc 100644 --- a/Silicon/NXP/Chassis/Chassis.c +++ b/Silicon/NXP/Chassis/Chassis.c @@ -45,6 +45,7 @@ GurRead ( STATIC CPU_TYPE CpuTypeList[] =3D { CPU_TYPE_ENTRY (LS1043A, LS1043A, 4), CPU_TYPE_ENTRY (LS1046A, LS1046A, 4), + CPU_TYPE_ENTRY (LS2088A, LS2088A, 8), }; =20 /* @@ -142,6 +143,40 @@ CpuNumCores ( } =20 /* + * Return core's cluster + */ +UINT32 +QoriqCoreToCluster ( + IN UINTN Core + ) +{ + CCSR_GUR *GurBase; + UINTN ClusterIndex; + UINTN Count; + UINT32 Cluster; + UINT32 Type; + UINTN InitiatorIndex; + + GurBase =3D (VOID *)PcdGet64 (PcdGutsBaseAddr); + ClusterIndex =3D 0; + Count =3D 0; + do { + Cluster =3D GurRead ((UINTN)&GurBase->TpCluster[ClusterIndex].Lower); + for (InitiatorIndex =3D 0; InitiatorIndex < TP_INIT_PER_CLUSTER; Initi= atorIndex++) { + Type =3D InitiatorType (Cluster, InitiatorIndex); + if (Type) { + if (Count =3D=3D Core) + return ClusterIndex; + Count++; + } + } + ClusterIndex++; + } while (CHECK_CLUSTER (Cluster)); + + return -1; // cannot identify the cluster +} + +/* * Return the type of core i.e. A53, A57 etc of inputted * core number. */ diff --git a/Silicon/NXP/Chassis/Chassis.h b/Silicon/NXP/Chassis/Chassis.h index 0beb44c..974fefb 100644 --- a/Silicon/NXP/Chassis/Chassis.h +++ b/Silicon/NXP/Chassis/Chassis.h @@ -57,6 +57,7 @@ CpuMaskNext ( #define SVR_WO_E 0xFFFFFE #define SVR_LS1043A 0x879200 #define SVR_LS1046A 0x870700 +#define SVR_LS2088A 0x870901 =20 #define SVR_MAJOR(svr) (((svr) >> 4) & 0xf) #define SVR_MINOR(svr) (((svr) >> 0) & 0xf) @@ -142,4 +143,20 @@ CpuNumCores ( VOID ); =20 +/* + * Return the type of initiator for core/hardware accelerator for given co= re index. + */ +UINT32 +QoriqCoreToType ( + IN UINTN Core + ); + +/* + * Return the cluster of initiator for core/hardware accelerator for give= n core index. + */ +UINT32 +QoriqCoreToCluster ( + IN UINTN Core + ); + #endif /* __CHASSIS_H__ */ diff --git a/Silicon/NXP/Chassis/Chassis3/Chassis3.dec b/Silicon/NXP/Chassi= s/Chassis3/Chassis3.dec new file mode 100644 index 0000000..cf41b3c --- /dev/null +++ b/Silicon/NXP/Chassis/Chassis3/Chassis3.dec @@ -0,0 +1,19 @@ +# @file +# +# Copyright 2017 NXP +# +# This program and the accompanying materials are licensed and made availa= ble under +# the terms and conditions of the BSD License which accompanies this distr= ibution. +# The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. +# +# + +[Defines] + DEC_SPECIFICATION =3D 0x00010005 + +[Includes] + . diff --git a/Silicon/NXP/Chassis/Chassis3/SerDes.h b/Silicon/NXP/Chassis/Ch= assis3/SerDes.h new file mode 100644 index 0000000..a77ddd5 --- /dev/null +++ b/Silicon/NXP/Chassis/Chassis3/SerDes.h @@ -0,0 +1,91 @@ +/** SerDes.h + The Header file of SerDes Module for Chassis 3 + + Copyright 2017 NXP + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD= License + which accompanies this distribution. The full text of the license may be = found + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPL= IED. + +**/ + +#ifndef __SERDES_H__ +#define __SERDES_H__ + +#include + +#define SRDS_MAX_LANES 8 + +// +// SerDes lane protocols/devices +// +typedef enum { + NONE =3D 0, + PCIE1, + PCIE2, + PCIE3, + PCIE4, + SATA1, + SATA2, + XAUI1, + XAUI2, + XFI1, + XFI2, + XFI3, + XFI4, + XFI5, + XFI6, + XFI7, + XFI8, + SGMII1, + SGMII2, + SGMII3, + SGMII4, + SGMII5, + SGMII6, + SGMII7, + SGMII8, + SGMII9, + SGMII10, + SGMII11, + SGMII12, + SGMII13, + SGMII14, + SGMII15, + SGMII16, + QSGMII_A, + QSGMII_B, + QSGMII_C, + QSGMII_D, + // Number of entries in this enum + SERDES_PRTCL_COUNT +} SERDES_PROTOCOL; + +typedef enum { + SRDS_1 =3D 0, + SRDS_2, + SRDS_MAX_NUM +} SERDES_NUMBER; + +typedef struct { + UINT16 Protocol; + UINT8 SrdsLane[SRDS_MAX_LANES]; +} SERDES_CONFIG; + +typedef VOID +(*SERDES_PROBE_LANES_CALLBACK) ( + IN SERDES_PROTOCOL LaneProtocol, + IN VOID *Arg + ); + +VOID +SerDesProbeLanes( + IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback, + IN VOID *Arg + ); + +#endif /* __SERDES_H */ diff --git a/Silicon/NXP/Chassis/Chassis3/Soc.c b/Silicon/NXP/Chassis/Chass= is3/Soc.c new file mode 100644 index 0000000..ed6c3cc --- /dev/null +++ b/Silicon/NXP/Chassis/Chassis3/Soc.c @@ -0,0 +1,180 @@ +/** @Soc.c + SoC specific Library containg functions to initialize various SoC compon= ents + + Copyright 2017 NXP + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may be= found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "Soc.h" + +VOID +GetSysInfo ( + OUT SYS_INFO *PtrSysInfo + ) +{ + UINT32 Index; + CCSR_GUR *GurBase; + CCSR_CLT_CTRL *ClkBase; + CCSR_CLK_CLUSTER *ClkGrp[2] =3D { + (VOID *) (FSL_CLK_GRPA_ADDR), + (VOID *) (FSL_CLK_GRPB_ADDR) + }; + + const UINT8 CoreCplxPll[16] =3D { + [0] =3D 0, // CC1 PPL / 1 + [1] =3D 0, // CC1 PPL / 2 + [2] =3D 0, // CC1 PPL / 4 + [4] =3D 1, // CC2 PPL / 1 + [5] =3D 1, // CC2 PPL / 2 + [6] =3D 1, // CC2 PPL / 4 + [8] =3D 2, // CC3 PPL / 1 + [9] =3D 2, // CC3 PPL / 2 + [10] =3D 2, // CC3 PPL / 4 + [12] =3D 3, // CC4 PPL / 1 + [13] =3D 3, // CC4 PPL / 2 + [14] =3D 3, // CC4 PPL / 4 + }; + + const UINT8 CoreCplxPllDivisor[16] =3D { + [0] =3D 1, // CC1 PPL / 1 + [1] =3D 2, // CC1 PPL / 2 + [2] =3D 4, // CC1 PPL / 4 + [4] =3D 1, // CC2 PPL / 1 + [5] =3D 2, // CC2 PPL / 2 + [6] =3D 4, // CC2 PPL / 4 + [8] =3D 1, // CC3 PPL / 1 + [9] =3D 2, // CC3 PPL / 2 + [10] =3D 4, // CC3 PPL / 4 + [12] =3D 1, // CC4 PPL / 1 + [13] =3D 2, // CC4 PPL / 2 + [14] =3D 4, // CC4 PPL / 4 + }; + + INT32 CcGroup[12] =3D FSL_CLUSTER_CLOCKS; + UINTN PllCount; + UINTN Cluster; + UINTN FreqCPll[NUM_CC_PLLS]; + UINTN PllRatio[NUM_CC_PLLS]; + UINTN SysClk; + UINT32 Cpu; + UINT32 CPllSel; + UINT32 CplxPll; + VOID *Offset; + + SetMem (PtrSysInfo, sizeof (SYS_INFO), 0); + + GurBase =3D (VOID *)PcdGet64 (PcdGutsBaseAddr); + ClkBase =3D (VOID *)PcdGet64 (PcdClkBaseAddr); + SysClk =3D CLK_FREQ; + + PtrSysInfo->FreqSystemBus =3D SysClk; + PtrSysInfo->FreqDdrBus =3D PcdGet64 (PcdDdrClk); + PtrSysInfo->FreqDdrBus2 =3D PcdGet64 (PcdDdrClk); + + // + // selects the platform clock:SYSCLK ratio and calculate + // system frequency + // + PtrSysInfo->FreqSystemBus *=3D (GurRead ((UINTN)&GurBase->RcwSr[0]) >> + CHASSIS3_RCWSR_0_SYS_PLL_RAT_SHIFT) & + CHASSIS3_RCWSR_0_SYS_PLL_RAT_MASK; + + // + // Platform clock is half of platform PLL + // + PtrSysInfo->FreqSystemBus /=3D PcdGet32 (PcdPlatformFreqDiv); + + // + // selects the DDR PLL:SYSCLK Ratio and calculate DDR frequency + // + PtrSysInfo->FreqDdrBus *=3D (GurRead ((UINTN)&GurBase->RcwSr[0]) >> + CHASSIS3_RCWSR_0_MEM_PLL_RAT_SHIFT) & + CHASSIS3_RCWSR_0_MEM_PLL_RAT_MASK; + PtrSysInfo->FreqDdrBus2 *=3D (GurRead ((UINTN)&GurBase->RcwSr[0]) >> + CHASSIS3_RCWSR_0_MEM2_PLL_RAT_SHIFT) & + CHASSIS3_RCWSR_0_MEM2_PLL_RAT_MASK; + + for (PllCount =3D 0; PllCount < NUM_CC_PLLS; PllCount++) { + Offset =3D (VOID *)((UINTN)ClkGrp[PllCount/3] + + __builtin_offsetof (CCSR_CLK_CLUSTER, PllnGsr[PllCount%3].Gsr)); + PllRatio[PllCount] =3D (GurRead ((UINTN)Offset) >> 1) & 0x3f; + FreqCPll[PllCount] =3D SysClk * PllRatio[PllCount]; + } + + // + // Calculate Core frequency + // + ForEachCpu (Index, Cpu, CpuNumCores (), CpuMask ()) { + Cluster =3D QoriqCoreToCluster (Cpu); + ASSERT_EFI_ERROR (Cluster); + CPllSel =3D (GurRead ((UINTN)&ClkBase->ClkCnCsr[Cluster].Csr) >> 27) &= 0xf; + CplxPll =3D CoreCplxPll[CPllSel]; + CplxPll +=3D CcGroup[Cluster] - 1; + PtrSysInfo->FreqProcessor[Cpu] =3D FreqCPll[CplxPll] / CoreCplxPllDivi= sor[CPllSel]; + } + PtrSysInfo->FreqSdhc =3D PtrSysInfo->FreqSystemBus/PcdGet32 (PcdPlatform= FreqDiv); +} + +/** + Perform the early initialization. + This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/= PlatformPeim + +**/ +VOID +SocInit ( + VOID + ) +{ + CHAR8 Buffer[100]; + UINTN CharCount; + + // + // Initialize SMMU + // + SmmuInit (); + + // + // Initialize the Serial Port. + // Early serial port initialization is required to print RCW, Soc and C= PU infomation at + // the begining of UEFI boot. + // + SerialPortInitialize (); + + CharCount =3D AsciiSPrint (Buffer, sizeof (Buffer), "\nUEFI firmware (ve= rsion %s built at %a on %a)\n\r", + (CHAR16*)PcdGetPtr (PcdFirmwareVersionString), __TIME__, __DATE__); + SerialPortWrite ((UINT8 *) Buffer, CharCount); + + // + // Print CPU information + // + PrintCpuInfo (); + + // + // Print Reset Controll Word + // + PrintRCW (); + + // + // Print Soc Personality information + // + PrintSoc (); +} + diff --git a/Silicon/NXP/Chassis/Chassis3/Soc.h b/Silicon/NXP/Chassis/Chass= is3/Soc.h new file mode 100644 index 0000000..0e892fb --- /dev/null +++ b/Silicon/NXP/Chassis/Chassis3/Soc.h @@ -0,0 +1,150 @@ +/** Soc.h +* Header defining the Base addresses, sizes, flags etc for chassis 1 +* +* Copyright (c) 2017 NXP +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the B= SD License +* which accompanies this distribution. The full text of the license may = be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#ifndef __SOC_H__ +#define __SOC_H__ + +#define MAX_CPUS 16 +#define FSL_CLK_GRPA_ADDR 0x01300000 +#define FSL_CLK_GRPB_ADDR 0x01310000 +#define NUM_CC_PLLS 6 +#define CLK_FREQ 100000000 + +#define FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } /* LS208x */ +#define TP_CLUSTER_EOC_MASK 0x80000000 /* Mask for End of clu= sters */ +#define CHECK_CLUSTER(Cluster) ((Cluster & TP_CLUSTER_EOC_MASK) !=3D = TP_CLUSTER_EOC_MASK) + +// RCW SERDES MACRO +#define RCWSR_INDEX 28 +#define RCWSR_SRDS1_PRTCL_MASK 0x00ff0000 +#define RCWSR_SRDS1_PRTCL_SHIFT 16 +#define RCWSR_SRDS2_PRTCL_MASK 0xff000000 +#define RCWSR_SRDS2_PRTCL_SHIFT 24 + +// SMMU Defintions +#define SMMU_BASE_ADDR 0x05000000 +#define SMMU_REG_SCR0 (SMMU_BASE_ADDR + 0x0) +#define SMMU_REG_SACR (SMMU_BASE_ADDR + 0x10) +#define SMMU_REG_IDR1 (SMMU_BASE_ADDR + 0x24) +#define SMMU_REG_NSCR0 (SMMU_BASE_ADDR + 0x400) +#define SMMU_REG_NSACR (SMMU_BASE_ADDR + 0x410) + +#define SACR_PAGESIZE_MASK 0x00010000 +#define SCR0_CLIENTPD_MASK 0x00000001 +#define SCR0_USFCFG_MASK 0x00000400 + +typedef struct { + UINTN FreqProcessor[MAX_CPUS]; + UINTN FreqSystemBus; + UINTN FreqDdrBus; + UINTN FreqDdrBus2; + UINTN FreqLocalBus; + UINTN FreqSdhc; + UINTN FreqFman[1]; + UINTN FreqQman; + UINTN FreqPme; +}SYS_INFO; + +/// +/// Device Configuration and Pin Control +/// +typedef struct { + UINT32 PorSr1; // POR status register 1 + UINT32 PorSr2; // POR status register 2 + UINT8 Res008[0x20-0x8]; + UINT32 GppOrCr1; // General-purpose POR configuration register + UINT32 GppOrCr2; // General-purpose POR configuration registe= r 2 + UINT32 DcfgFuseSr; // Fuse status register */ + UINT32 GppOrCr3; + UINT32 GppOrCr4; + UINT8 Res034[0x70-0x34]; + UINT32 DevDisr; // Device disable control register + UINT32 DevDisr2; // Device disable control register 2 + UINT32 DevDisr3; // Device disable control register 3 + UINT32 DevDisr4; // Device disable control register 4 + UINT32 DevDisr5; // Device disable control register 5 + UINT32 DevDisr6; // Device disable control register 6 + UINT32 DevDisr7; // Device disable control register 7 + UINT8 Res08c[0x90-0x8c]; + UINT32 CoreDisrUpper; // CORE DISR Uppper for support of 64 cores + UINT32 CoreDisrLower; // CORE DISR Lower for support of 64 cores + UINT8 Res098[0xa0-0x98]; + UINT32 Pvr; // Processor version + UINT32 Svr; // System version + UINT32 Mvr; // Manufacturing version + UINT8 Res0ac[0x100-0xac]; + UINT32 RcwSr[32]; // Reset control word status +#define CHASSIS3_RCWSR_0_SYS_PLL_RAT_SHIFT 2 +#define CHASSIS3_RCWSR_0_SYS_PLL_RAT_MASK 0x1f +#define CHASSIS3_RCWSR_0_MEM_PLL_RAT_SHIFT 10 +#define CHASSIS3_RCWSR_0_MEM_PLL_RAT_MASK 0x3f +#define CHASSIS3_RCWSR_0_MEM2_PLL_RAT_SHIFT 18 +#define CHASSIS3_RCWSR_0_MEM2_PLL_RAT_MASK 0x3f + UINT8 Res180[0x200-0x180]; + UINT32 ScratchRw[32]; // Scratch Read/Write + UINT8 Res280[0x300-0x280]; + UINT32 ScratchW1R[4]; // Scratch Read (Write once) + UINT8 Res310[0x400-0x310]; + UINT32 BootLocPtrL; // Low addr : Boot location pointer + UINT32 BootLocPtrH; // High addr : Boot location pointer + UINT8 Res408[0x500-0x408]; + UINT8 Res500[0x740-0x500]; + UINT32 TpItyp[64]; + struct { + UINT32 Upper; + UINT32 Lower; + } TpCluster[3]; + UINT8 Res858[0x1000-0x858]; +} CCSR_GUR; + +/// +/// Clocking +/// +typedef struct { + struct { + UINT32 Csr; // core cluster n clock control status + UINT8 Res04[0x20-0x04]; + } ClkCnCsr[8]; +} CCSR_CLT_CTRL; + +/// +/// Clock Cluster +/// +typedef struct { + struct { + UINT8 Res00[0x10]; + UINT32 Csr; // core cluster n clock control status + UINT8 Res14[0x20-0x14]; + } HwnCsr[3]; + UINT8 Res60[0x80-0x60]; + struct { + UINT32 Gsr; // core cluster n clock general status + UINT8 Res84[0xa0-0x84]; + } PllnGsr[3]; + UINT8 Rese0[0x100-0xe0]; +} CCSR_CLK_CLUSTER; + +VOID +GetSysInfo ( + OUT SYS_INFO * + ); + +UINT32 +EFIAPI +GurRead ( + IN UINTN Address + ); + +#endif /* __SOC_H__ */ diff --git a/Silicon/NXP/Chassis/LS2088aSocLib.inf b/Silicon/NXP/Chassis/LS= 2088aSocLib.inf new file mode 100644 index 0000000..8a4da50 --- /dev/null +++ b/Silicon/NXP/Chassis/LS2088aSocLib.inf @@ -0,0 +1,48 @@ +# @file +# +# Copyright 2017 NXP +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +# + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D SocLib + FILE_GUID =3D 3b233a6a-0ee1-42a3-a7f7-c285b5ba80dc + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SocLib + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/NXP/NxpQoriqLs.dec + Silicon/NXP/Chassis/Chassis3/Chassis3.dec + Silicon/NXP/LS2088A/LS2088A.dec + +[LibraryClasses] + BaseLib + BeIoLib + DebugLib + SerialPortLib + +[Sources.common] + Chassis.c + Chassis3/Soc.c + SerDes.c + +[FixedPcd] + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString + gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv + gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled + gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian + gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdDdrClk diff --git a/Silicon/NXP/LS2088A/Include/SocSerDes.h b/Silicon/NXP/LS2088A/= Include/SocSerDes.h new file mode 100644 index 0000000..f631ccb --- /dev/null +++ b/Silicon/NXP/LS2088A/Include/SocSerDes.h @@ -0,0 +1,67 @@ +/** @file + The Header file of SerDes Module for LS2088A + + Copyright 2017 NXP + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD= License + which accompanies this distribution. The full text of the license may be = found + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPL= IED. + +**/ + +#ifndef __SOC_SERDES_H__ +#define __SOC_SERDES_H__ + +#include + +SERDES_CONFIG SerDes1ConfigTbl[] =3D { + // SerDes 1 + { 0x03, { PCIE2, PCIE2, PCIE2, PCIE2, PCIE1, PCIE1, PCIE1, PCIE1 } }, + { 0x05, { PCIE2, PCIE2, PCIE2, PCIE2, SGMII4, SGMII3, SGMII2, SGMII1 } }, + { 0x07, { SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2, SGMII1= } }, + { 0x09, { SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2, SGMII1= } }, + { 0x0A, { SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2, SGMII1= } }, + { 0x0C, { SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2, SGMII1= } }, + { 0x0E, { SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2, SGMII1= } }, + { 0x26, { SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, XFI2, XFI1 } }, + { 0x28, { SGMII8, SGMII7, SGMII6, SGMII5, XFI4, XFI3, XFI2, XFI1 } }, + { 0x2A, { XFI8, XFI7, XFI6, XFI5, XFI4, XFI3, XFI2, XFI1 } }, + { 0x2B, { SGMII8, SGMII7, SGMII6, SGMII5, XAUI1, XAUI1, XAUI1, XAUI1 } }, + { 0x32, { XAUI2, XAUI2, XAUI2, XAUI2, XAUI1, XAUI1, XAUI1, XAUI1 } }, + { 0x33, { PCIE2, PCIE2, PCIE2, PCIE2, QSGMII_D, QSGMII_C, QSGMII_B, QSGM= II_A } }, + { 0x35, { QSGMII_D, QSGMII_C, QSGMII_B, PCIE2, XFI4, XFI3, XFI2, XFI1 } = }, + {} +}; + +SERDES_CONFIG SerDes2ConfigTbl[] =3D { + // SerDes 2 + { 0x07, { SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15, = SGMII16 } }, + { 0x09, { SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15, = SGMII16 } }, + { 0x0A, { SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15, = SGMII16 } }, + { 0x0C, { SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15, = SGMII16 } }, + { 0x0E, { SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15, = SGMII16 } }, + { 0x3D, { PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3 } }, + { 0x3E, { PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3 } }, + { 0x3F, { PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4 } }, + { 0x40, { PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4 } }, + { 0x41, { PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2 } }, + { 0x42, { PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2 } }, + { 0x43, { PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE, SATA1, SATA2 } }, + { 0x44, { PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE, SATA1, SATA2 } }, + { 0x45, { SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, PCIE4, PCIE4 = } }, + { 0x47, { PCIE3, SGMII10, SGMII11, SGMII12, PCIE4, SGMII14, SGMII15, SGM= II16 } }, + { 0x49, { SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, SATA1, SATA2 = } }, + { 0x4A, { SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, SATA1, SATA2 = } }, + {} +}; + +SERDES_CONFIG *SerDesConfigTbl[] =3D { + SerDes1ConfigTbl, + SerDes2ConfigTbl +}; + +#endif /* __SOC_SERDES_H */ --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun May 5 06:05:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=nxp.com Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1518771271351100.2614952454453; Fri, 16 Feb 2018 00:54:31 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 5DB4122161161; Fri, 16 Feb 2018 00:48:36 -0800 (PST) Received: from EUR02-AM5-obe.outbound.protection.outlook.com (mail-eopbgr00076.outbound.protection.outlook.com [40.107.0.76]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id EEB75223230CB for ; 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charset="utf-8" From: Wasim Khan Add support of ArmPlatformLib for NXP LS2088ARDB board Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Wasim Khan Signed-off-by: Meenakshi Aggarwal --- .../Library/PlatformLib/ArmPlatformLib.c | 106 ++++++++++++ .../Library/PlatformLib/ArmPlatformLib.inf | 77 +++++++++ .../Library/PlatformLib/NxpQoriqLsHelper.S | 35 ++++ .../Library/PlatformLib/NxpQoriqLsMem.c | 189 +++++++++++++++++= ++++ 4 files changed, 407 insertions(+) create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatf= ormLib.c create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatf= ormLib.inf create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriq= LsHelper.S create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriq= LsMem.c diff --git a/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.= c b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.c new file mode 100644 index 0000000..90f14ba --- /dev/null +++ b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.c @@ -0,0 +1,106 @@ +/** ArmPlatformLib.c +* +* Contains board initialization functions. +* +* Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoard.c +* +* Copyright (c) 2011-2012, ARM Limited. All rights reserved. +* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved. +* Copyright 2017 NXP +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the B= SD License +* which accompanies this distribution. The full text of the license may = be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#include +#include + +extern VOID SocInit (VOID); + +/** + Return the current Boot Mode + + This function returns the boot reason on the platform + +**/ +EFI_BOOT_MODE +ArmPlatformGetBootMode ( + VOID + ) +{ + return BOOT_WITH_FULL_CONFIGURATION; +} + +/** + Placeholder for Platform Initialization + +**/ +EFI_STATUS +ArmPlatformInitialize ( + IN UINTN MpId + ) +{ + SocInit (); + + return EFI_SUCCESS; +} + +ARM_CORE_INFO LS2088aMpCoreInfoCTA72x4[] =3D { + { + // Cluster 0, Core 0 + 0x0, 0x0, + + // MP Core MailBox Set/Get/Clear Addresses and Clear Value + (EFI_PHYSICAL_ADDRESS)0, + (EFI_PHYSICAL_ADDRESS)0, + (EFI_PHYSICAL_ADDRESS)0, + (UINT64)0xFFFFFFFF + }, +}; + +EFI_STATUS +PrePeiCoreGetMpCoreInfo ( + OUT UINTN *CoreCount, + OUT ARM_CORE_INFO **ArmCoreTable + ) +{ + *CoreCount =3D sizeof (LS2088aMpCoreInfoCTA72x4) / sizeof (ARM_CORE_I= NFO); + *ArmCoreTable =3D LS2088aMpCoreInfoCTA72x4; + + return EFI_SUCCESS; +} + +ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi =3D { PrePeiCoreGetMpCoreInfo }; + +EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] =3D { + { + EFI_PEI_PPI_DESCRIPTOR_PPI, + &gArmMpCoreInfoPpiGuid, + &mMpCoreInfoPpi + } +}; + +VOID +ArmPlatformGetPlatformPpiList ( + OUT UINTN *PpiListSize, + OUT EFI_PEI_PPI_DESCRIPTOR **PpiList + ) +{ + *PpiListSize =3D sizeof (gPlatformPpiTable); + *PpiList =3D gPlatformPpiTable; +} + + +UINTN +ArmPlatformGetCorePosition ( + IN UINTN MpId + ) +{ + return 1; +} diff --git a/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.= inf b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf new file mode 100644 index 0000000..f5e5abd --- /dev/null +++ b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf @@ -0,0 +1,77 @@ +#/** @file +# +# Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved. +# Copyright 2017 NXP +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +#**/ + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D PlatformLib + FILE_GUID =3D d1361285-8a47-421c-9efd-6b262c9093fc + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D ArmPlatformLib + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + Silicon/NXP/NxpQoriqLs.dec + +[LibraryClasses] + ArmLib + SocLib + +[Sources.common] + ArmPlatformLib.c + NxpQoriqLsHelper.S | GCC + NxpQoriqLsMem.c + + +[Ppis] + gArmMpCoreInfoPpiGuid + +[FixedPcd] + gArmTokenSpaceGuid.PcdArmPrimaryCore + gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2BaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2Size + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize + gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseSize + gNxpQoriqLsTokenSpaceGuid.PcdDram1BaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdDram1Size + gNxpQoriqLsTokenSpaceGuid.PcdDramMemSize + gNxpQoriqLsTokenSpaceGuid.PcdDram2BaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdDram2Size + gNxpQoriqLsTokenSpaceGuid.PcdMcHighMemSupport + gNxpQoriqLsTokenSpaceGuid.PcdDpaa2McRamSize + gNxpQoriqLsTokenSpaceGuid.PcdDpaa2McPortalBaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdDpaa2McPortalSize + gNxpQoriqLsTokenSpaceGuid.PcdDpaa2NiPortalsBaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdDpaa2NiPortalsSize + gNxpQoriqLsTokenSpaceGuid.PcdDpaa2QBmanPortalsBaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdDpaa2QBmanPortalSize + gNxpQoriqLsTokenSpaceGuid.PcdDpaa2QBmanPortalsCacheSize + diff --git a/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsHelpe= r.S b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S new file mode 100644 index 0000000..1917b02 --- /dev/null +++ b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S @@ -0,0 +1,35 @@ +#/** @file +# +# Copyright (c) 2012-2013, ARM Limited. All rights reserved. +# Copyright 2017 NXP +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +#**/ + +#include +#include + +.text +.align 2 + +GCC_ASM_IMPORT(ArmReadMpidr) + +ASM_FUNC(ArmPlatformIsPrimaryCore) + tst x0, #3 + cset x0, eq + ret + +ASM_FUNC(ArmPlatformPeiBootAction) + ret + +ASM_FUNC(ArmPlatformGetPrimaryCoreMpId) + MOV32 (x0, FixedPcdGet32(PcdArmPrimaryCore)) + ldrh w0, [x0] + ret diff --git a/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c= b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c new file mode 100644 index 0000000..ccb49f6 --- /dev/null +++ b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c @@ -0,0 +1,189 @@ +/** NxpQoriqLsMem.c +* +* Board memory specific Library. +* +* Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoardMem.c +* +* Copyright (c) 2011, ARM Limited. All rights reserved. +* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved. +* Copyright 2017 NXP +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the B= SD License +* which accompanies this distribution. The full text of the license may b= e found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#include +#include +#include +#include + +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 25 + +// +// Calculate the MC (Management Complex) base address and DDR size based on +// if the MC is loaded in DDR low memory region or in DDR high memory regi= on. +// +#if FixedPcdGetBool (PcdMcHighMemSupport) +#define DDR_MEM_SIZE FixedPcdGet64 (PcdDramMemS= ize) - FixedPcdGet64 (PcdDpaa2McRamSize) +#define MC_BASE_ADDR FixedPcdGet64 (PcdDram2Bas= eAddr) + DDR_MEM_SIZE +#else +#define DDR_MEM_SIZE FixedPcdGet64 (PcdDramMemS= ize) +#define MC_BASE_ADDR FixedPcdGet64 (PcdDram1Bas= eAddr) - FixedPcdGet64 (PcdDpaa2McRamSize) +#endif + + +/** + Return the Virtual Memory Map of your platform + + This Virtual Memory Map is used by MemoryInitPei Module to initialize th= e MMU on your platform. + + @param VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR descr= ibing a Physical-to- + Virtual Memory mapping. This array must be = ended by a zero-filled + entry + +**/ + +VOID +ArmPlatformGetVirtualMemoryMap ( + IN ARM_MEMORY_REGION_DESCRIPTOR ** VirtualMemoryMap + ) +{ + UINTN Index; + ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; + + Index =3D 0; + + ASSERT (VirtualMemoryMap !=3D NULL); + + VirtualMemoryTable =3D (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages ( + EFI_SIZE_TO_PAGES (sizeof (ARM_MEMORY_REGION_DESCRIPTOR) * MAX_V= IRTUAL_MEMORY_MAP_DESCRIPTORS)); + + if (VirtualMemoryTable =3D=3D NULL) { + return; + } + + // DRAM1 (Must be 1st entry) + VirtualMemoryTable[Index].PhysicalBase =3D FixedPcdGet64 (PcdDram1BaseAd= dr); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdDram1BaseAd= dr); + VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdDram1Size); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_W= RITE_BACK ; + + // CCSR Space + VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdCcsrBaseA= ddr); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdCcsrBaseAdd= r); + VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdCcsrSize); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + // IFC region 1 + // + // A-009241 : Unaligned write transactions to IFC may result in corrup= tion of data + // Affects : IFC + // Description: 16 byte unaligned write from system bus to IFC may resul= t in extra unintended + // writes on external IFC interface that can corrupt data o= n external flash. + // Impact : Data corruption on external flash may happen in case of = unaligned writes to + // IFC memory space. + // Workaround: Following are the workarounds: + // For write transactions from core, IFC interface memories = (including IFC SRAM) + // should be configured as device type memory in MMU. + // For write transactions from non-core masters (like system= DMA), the address + // should be 16 byte aligned and the data size should be = multiple of 16 bytes. + // + VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdIfcRegion= 1BaseAddr); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdIfcRegion1B= aseAddr); + VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdIfcRegion1S= ize); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + // IFC region 2 + VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdIfcRegion= 2BaseAddr); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdIfcRegion2B= aseAddr); + VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdIfcRegion2S= ize); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + // QSPI region 1 + VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdQspiRegio= nBaseAddr); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdQspiRegionB= aseAddr); + VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdQspiRegionS= ize); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_U= NCACHED_UNBUFFERED; + + // QSPI region 2 + VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdQspiRegio= n2BaseAddr); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdQspiRegion2= BaseAddr); + VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdQspiRegion2= Size); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_U= NCACHED_UNBUFFERED; + + // DRAM2 + VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdDram2Base= Addr); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdDram2BaseAd= dr); + VirtualMemoryTable[Index].Length =3D DDR_MEM_SIZE; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_W= RITE_BACK ; + + // MC private DRAM + VirtualMemoryTable[++Index].PhysicalBase =3D MC_BASE_ADDR; + VirtualMemoryTable[Index].VirtualBase =3D MC_BASE_ADDR; + VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdDpaa2McRamS= ize); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + // PCIe1 + VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdPciExp1Ba= seAddr); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdPciExp1Base= Addr); + VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdPciExp1Base= Size); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + // PCIe2 + VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdPciExp2Ba= seAddr); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdPciExp2Base= Addr); + VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdPciExp2Base= Size); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + // PCIe3 + VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdPciExp3Ba= seAddr); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdPciExp3Base= Addr); + VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdPciExp3Base= Size); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + // PCIe4 + VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdPciExp4Ba= seAddr); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdPciExp4Base= Addr); + VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdPciExp4Base= Size); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + // DPAA2 MC Portals region + VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdDpaa2McPo= rtalBaseAddr); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdDpaa2McPort= alBaseAddr); + VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdDpaa2McPort= alSize); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + // DPAA2 NI Portals region + VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdDpaa2NiPo= rtalsBaseAddr); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdDpaa2NiPort= alsBaseAddr); + VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdDpaa2NiPort= alsSize); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + // DPAA2 QBMAN Portals - cache enabled region + VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdDpaa2QBma= nPortalsBaseAddr); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdDpaa2QBmanP= ortalsBaseAddr); + VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdDpaa2QBmanP= ortalsCacheSize); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_W= RITE_BACK ; + + // DPAA2 QBMAN Portals - cache inhibited region + VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdDpaa2QBma= nPortalsBaseAddr) + FixedPcdGet64 (PcdDpaa2QBmanPortalsCacheSize); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdDpaa2QBmanP= ortalsBaseAddr) + FixedPcdGet64 (PcdDpaa2QBmanPortalsCacheSize); + VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdDpaa2QBmanP= ortalSize) - FixedPcdGet64 (PcdDpaa2QBmanPortalsCacheSize); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + // End of Table + VirtualMemoryTable[++Index].PhysicalBase =3D 0; + VirtualMemoryTable[Index].VirtualBase =3D 0; + VirtualMemoryTable[Index].Length =3D 0; + VirtualMemoryTable[Index].Attributes =3D (ARM_MEMORY_REGION_ATTRIBUTES= )0; + + ASSERT ((Index + 1) <=3D MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS); + + *VirtualMemoryMap =3D VirtualMemoryTable; +} --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun May 5 06:05:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=nxp.com Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1518771275636436.3792099268369; Fri, 16 Feb 2018 00:54:35 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id BF5E121E0BA16; Fri, 16 Feb 2018 00:48:40 -0800 (PST) Received: from EUR02-AM5-obe.outbound.protection.outlook.com (mail-eopbgr00080.outbound.protection.outlook.com [40.107.0.80]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id CCB04223230CE for ; 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charset="utf-8" From: Wasim Khan Add Maxim DS3232 RTC Library support Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Wasim Khan --- Silicon/Maxim/Library/Ds3232RtcLib/Ds3232Rtc.h | 49 +++ Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.c | 370 +++++++++++++++++= ++++ .../Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.dec | 31 ++ .../Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.inf | 49 +++ 4 files changed, 499 insertions(+) create mode 100644 Silicon/Maxim/Library/Ds3232RtcLib/Ds3232Rtc.h create mode 100644 Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.c create mode 100644 Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.dec create mode 100644 Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.inf diff --git a/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232Rtc.h b/Silicon/Maxim= /Library/Ds3232RtcLib/Ds3232Rtc.h new file mode 100644 index 0000000..cd1a321 --- /dev/null +++ b/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232Rtc.h @@ -0,0 +1,49 @@ +/** Ds3232Rtc.h +* +* Copyright 2017 NXP +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the B= SD License +* which accompanies this distribution. The full text of the license may = be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#ifndef __DS3232RTC_H__ +#define __DS3232RTC_H__ + +//RTC time register +#define DS3232_SEC_REG_ADDR 0x00 +#define DS3232_MIN_REG_ADDR 0x01 +#define DS3232_HR_REG_ADDR 0x02 +#define DS3232_DAY_REG_ADDR 0x03 +#define DS3232_DATE_REG_ADDR 0x04 +#define DS3232_MON_REG_ADDR 0x05 +#define DS3232_YR_REG_ADDR 0x06 + +#define DS3232_SEC_BIT_CH 0x80 // Clock Halt (in Register 0) + +//RTC control register +#define DS3232_CTL_REG_ADDR 0x0e +#define DS3232_STAT_REG_ADDR 0x0f + +#define START_YEAR 1970 +#define END_YEAR 2070 + +//TIME MASKS +#define MASK_SEC 0x7F +#define MASK_MIN 0x7F +#define MASK_HOUR 0x3F +#define MASK_DAY 0x3F +#define MASK_MONTH 0x1F + +typedef struct { + UINTN OperationCount; + EFI_I2C_OPERATION SetAddressOp; + EFI_I2C_OPERATION GetSetDateTimeOp; +} RTC_I2C_REQUEST; + +#endif // __DS3232RTC_H__ diff --git a/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.c b/Silicon/Ma= xim/Library/Ds3232RtcLib/Ds3232RtcLib.c new file mode 100644 index 0000000..1a852e9 --- /dev/null +++ b/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.c @@ -0,0 +1,370 @@ +/** Ds3232RtcLib.c +* Implement EFI RealTimeClock via RTC Lib for DS3232 RTC. +* +* Based on RTC implementation available in +* EmbeddedPkg/Library/TemplateRealTimeClockLib/RealTimeClockLib.c +* +* Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+* Copyright 2017 NXP +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the B= SD License +* which accompanies this distribution. The full text of the license may = be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "Ds3232Rtc.h" + +STATIC VOID *mDriverEventRegistration; +STATIC EFI_I2C_MASTER_PROTOCOL *mI2cMaster; + +/** + Read RTC register. + + @param SlaveDeviceAddress Slave device address offset of RTC to be re= ad. + @param RtcRegAddr Register offset of RTC to be read. + + @retval Register Value read + +**/ +STATIC +UINT8 +RtcRead ( + IN UINT8 SlaveDeviceAddress, + IN UINT8 RtcRegAddr + ) +{ + RTC_I2C_REQUEST Req; + EFI_STATUS Status; + UINT8 Val; + + Val =3D 0; + + Req.OperationCount =3D 2; + + Req.SetAddressOp.Flags =3D 0; + Req.SetAddressOp.LengthInBytes =3D sizeof (RtcRegAddr); + Req.SetAddressOp.Buffer =3D &RtcRegAddr; + + Req.GetSetDateTimeOp.Flags =3D I2C_FLAG_READ; + Req.GetSetDateTimeOp.LengthInBytes =3D sizeof (Val); + Req.GetSetDateTimeOp.Buffer =3D &Val; + + Status =3D mI2cMaster->StartRequest (mI2cMaster, SlaveDeviceAddress, + (VOID *)&Req, + NULL, NULL); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "RTC read error at Addr:0x%x\n", RtcRegAddr)); + } + + return Val; +} + +/** + Write RTC register. + + @param SlaveDeviceAddress Slave device address offset of RTC to be re= ad. + @param RtcRegAddr Register offset of RTC to write. + @param Val Value to be written + +**/ +STATIC +VOID +RtcWrite ( + IN UINT8 SlaveDeviceAddress, + IN UINT8 RtcRegAddr, + IN UINT8 Val + ) +{ + RTC_I2C_REQUEST Req; + EFI_STATUS Status; + + Req.OperationCount =3D 2; + + Req.SetAddressOp.Flags =3D 0; + Req.SetAddressOp.LengthInBytes =3D sizeof (RtcRegAddr); + Req.SetAddressOp.Buffer =3D &RtcRegAddr; + + Req.GetSetDateTimeOp.Flags =3D 0; + Req.GetSetDateTimeOp.LengthInBytes =3D sizeof (Val); + Req.GetSetDateTimeOp.Buffer =3D &Val; + + Status =3D mI2cMaster->StartRequest (mI2cMaster, SlaveDeviceAddress, + (VOID *)&Req, + NULL, NULL); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "RTC write error at Addr:0x%x\n", RtcRegAddr)); + } +} + +/** + Configure the MUX device connected to I2C. + + @param RegValue Value to write on mux device register add= ress + +**/ +VOID +ConfigureMuxDevice ( + IN UINT8 RegValue + ) +{ + RtcWrite (FixedPcdGet8 (PcdMuxDeviceAddress), FixedPcdGet8 (PcdMuxContro= lRegOffset), RegValue); +} + +/** + Returns the current time and date information, and the time-keeping capa= bilities + of the hardware platform. + + @param Time A pointer to storage to receive a snapshot= of the current time. + @param Capabilities An optional pointer to a buffer to receive= the real time clock + device's capabilities. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_INVALID_PARAMETER Time is NULL. + @retval EFI_DEVICE_ERROR The time could not be retrieved due to har= dware error. + +**/ +EFI_STATUS +EFIAPI +LibGetTime ( + OUT EFI_TIME *Time, + OUT EFI_TIME_CAPABILITIES *Capabilities + ) +{ + EFI_STATUS Status; + UINT8 Second; + UINT8 Minute; + UINT8 Hour; + UINT8 Day; + UINT8 Month; + UINT8 Year; + + if (mI2cMaster =3D=3D NULL) { + return EFI_DEVICE_ERROR; + } + + Status =3D EFI_SUCCESS; + + // + // Check if the I2C device is connected though a MUX device. + // + if (FixedPcdGetBool (PcdIsRtcDeviceMuxed)) { + // Switch to the channel connected to Ds3232 RTC + ConfigureMuxDevice (FixedPcdGet8 (PcdMuxRtcChannelValue)); + } + + Second =3D RtcRead (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_SEC_REG_AD= DR); + Minute =3D RtcRead (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_MIN_REG_AD= DR); + Hour =3D RtcRead (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_HR_REG_ADDR); + Day =3D RtcRead (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_DATE_REG_ADDR= ); + Month =3D RtcRead (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_MON_REG_ADD= R); + Year =3D RtcRead (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_YR_REG_ADDR); + + if (Second & DS3232_SEC_BIT_CH) { + DEBUG ((DEBUG_ERROR, "### Warning: RTC oscillator has stopped\n")); + /* clear the CH flag */ + RtcWrite (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_SEC_REG_ADDR, + RtcRead (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_SEC_REG_A= DDR) & ~DS3232_SEC_BIT_CH); + Status =3D EFI_DEVICE_ERROR; + goto EXIT; + } + + Time->Second =3D BcdToDecimal8 (Second & MASK_SEC); + Time->Minute =3D BcdToDecimal8 (Minute & MASK_MIN); + Time->Hour =3D BcdToDecimal8 (Hour & MASK_HOUR); + Time->Day =3D BcdToDecimal8 (Day & MASK_DAY); + Time->Month =3D BcdToDecimal8 (Month & MASK_MONTH); + + // + // RTC can save year 1970 to 2069 + // On writing Year, save year % 100 + // On Reading reversing the operation e.g. 2012 + // write =3D 12 (2012 % 100) + // read =3D 2012 (12 + 2000) + // + Time->Year =3D BcdToDecimal8 (Year) + + (BcdToDecimal8 (Year) >=3D 70 ? START_YEAR - 70 : END_YEAR = -70); + +EXIT: + if (FixedPcdGetBool (PcdIsRtcDeviceMuxed)) { + // Switch to the default channel + ConfigureMuxDevice (FixedPcdGet8 (PcdMuxDefaultChannelValue)); + } + + return Status; +} + +/** + Sets the current local time and date information. + + @param Time A pointer to the current time. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_INVALID_PARAMETER A time field is out of range. + +**/ +EFI_STATUS +EFIAPI +LibSetTime ( + IN EFI_TIME *Time + ) +{ + if (mI2cMaster =3D=3D NULL) { + return EFI_DEVICE_ERROR; + } + + if (Time->Year < START_YEAR || Time->Year >=3D END_YEAR){ + DEBUG ((DEBUG_ERROR, "WARNING: Year should be between 1970 and 2069!\n= ")); + return EFI_INVALID_PARAMETER; + } + + // + // Check if the I2C device is connected though a MUX device. + // + if (FixedPcdGetBool (PcdIsRtcDeviceMuxed)) { + // Switch to the channel connected to Ds3232 RTC + ConfigureMuxDevice (FixedPcdGet8 (PcdMuxRtcChannelValue)); + } + + RtcWrite (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_YR_REG_ADDR, Decimal= ToBcd8 (Time->Year % 100)); + RtcWrite (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_MON_REG_ADDR, Decima= lToBcd8 (Time->Month)); + RtcWrite (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_DATE_REG_ADDR, Decim= alToBcd8 (Time->Day)); + RtcWrite (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_HR_REG_ADDR, Decimal= ToBcd8 (Time->Hour)); + RtcWrite (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_MIN_REG_ADDR, Decima= lToBcd8 (Time->Minute)); + RtcWrite (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_SEC_REG_ADDR, Decima= lToBcd8 (Time->Second)); + + if (FixedPcdGetBool (PcdIsRtcDeviceMuxed)) { + // Switch to the default channel + ConfigureMuxDevice (FixedPcdGet8 (PcdMuxDefaultChannelValue)); + } + + return EFI_SUCCESS; +} + +/** + Returns the current wakeup alarm clock setting. + + @param Enabled Indicates if the alarm is currently enable= d or disabled. + @param Pending Indicates if the alarm signal is pending a= nd requires acknowledgement. + @param Time The current alarm setting. + + @retval EFI_SUCCESS The alarm settings were returned. + @retval EFI_INVALID_PARAMETER Any parameter is NULL. + @retval EFI_DEVICE_ERROR The wakeup time could not be retrieved due= to a hardware error. + +**/ +EFI_STATUS +EFIAPI +LibGetWakeupTime ( + OUT BOOLEAN *Enabled, + OUT BOOLEAN *Pending, + OUT EFI_TIME *Time + ) +{ + // Currently not supporting this feature. + return EFI_UNSUPPORTED; +} + +/** + Sets the system wakeup alarm clock time. + + @param Enabled Enable or disable the wakeup alarm. + @param Time If Enable is TRUE, the time to set the wak= eup alarm for. + + @retval EFI_SUCCESS If Enable is TRUE, then the wakeup alarm w= as enabled. If + Enable is FALSE, then the wakeup alarm was= disabled. + @retval EFI_INVALID_PARAMETER A time field is out of range. + @retval EFI_DEVICE_ERROR The wakeup time could not be set due to a = hardware error. + @retval EFI_UNSUPPORTED A wakeup timer is not supported on this pl= atform. + +**/ +EFI_STATUS +EFIAPI +LibSetWakeupTime ( + IN BOOLEAN Enabled, + OUT EFI_TIME *Time + ) +{ + // Currently not supporting this feature. + return EFI_UNSUPPORTED; +} + +STATIC +VOID +I2cDriverRegistrationEvent ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + EFI_STATUS Status; + EFI_I2C_MASTER_PROTOCOL *I2cMaster; + UINTN BusFrequency; + + Status =3D gBS->LocateProtocol (&gEfiI2cMasterProtocolGuid, NULL, (VOID = **)&I2cMaster); + + gBS->CloseEvent (Event); + + ASSERT_EFI_ERROR (Status); + + Status =3D I2cMaster->Reset (I2cMaster); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: I2CMaster->Reset () failed - %r\n", + __FUNCTION__, Status)); + return; + } + + BusFrequency =3D FixedPcdGet16 (PcdI2cBusFrequency); + Status =3D I2cMaster->SetBusFrequency (I2cMaster, &BusFrequency); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: I2CMaster->SetBusFrequency () failed - %r\n", + __FUNCTION__, Status)); + return; + } + + mI2cMaster =3D I2cMaster; +} + +/** + This is the declaration of an EFI image entry point. This can be the ent= ry point to an application + written to this specification, an EFI boot service driver. + + @param ImageHandle Handle that identifies the loaded image. + @param SystemTable System Table for this image. + + @retval EFI_SUCCESS The operation completed successfully. + +**/ +EFI_STATUS +EFIAPI +LibRtcInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + // + // Register a protocol registration notification callback on the driver + // binding protocol so we can attempt to connect our I2C master to it + // as soon as it appears. + // + EfiCreateProtocolNotifyEvent ( + &gEfiI2cMasterProtocolGuid, + TPL_CALLBACK, + I2cDriverRegistrationEvent, + NULL, + &mDriverEventRegistration); + + return EFI_SUCCESS; +} diff --git a/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.dec b/Silicon/= Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.dec new file mode 100644 index 0000000..4471d57 --- /dev/null +++ b/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.dec @@ -0,0 +1,31 @@ +#/** @file +# +# Copyright 2017 NXP +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BS= D License +# which accompanies this distribution. The full text of the license may b= e found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. +# +#**/ + +[Defines] + DEC_SPECIFICATION =3D 0x0001001A + PACKAGE_NAME =3D Ds3232RtcLib + PACKAGE_GUID =3D 0b4192f7-e404-4019-b2e5-1e6004da3313 + PACKAGE_VERSION =3D 0.1 + +[Guids] + gDs3232RtcLibTokenSpaceGuid =3D { 0x7960fc51, 0x0832, 0x4f0b, { 0xb4, 0x= 22, 0x53, 0x87, 0x03, 0xaa, 0x85, 0xda }} + +[PcdsFixedAtBuild] + gDs3232RtcLibTokenSpaceGuid.PcdI2cSlaveAddress|0|UINT8|0x00000001 + gDs3232RtcLibTokenSpaceGuid.PcdI2cBusFrequency|0|UINT32|0x00000002 + gDs3232RtcLibTokenSpaceGuid.PcdIsRtcDeviceMuxed|FALSE|BOOLEAN|0x00000003 + gDs3232RtcLibTokenSpaceGuid.PcdMuxDeviceAddress|0|UINT8|0x00000004 + gDs3232RtcLibTokenSpaceGuid.PcdMuxControlRegOffset|0|UINT8|0x00000005 + gDs3232RtcLibTokenSpaceGuid.PcdMuxRtcChannelValue|0|UINT8|0x00000006 + gDs3232RtcLibTokenSpaceGuid.PcdMuxDefaultChannelValue|0|UINT8|0x00000007 diff --git a/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.inf b/Silicon/= Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.inf new file mode 100644 index 0000000..9cac100 --- /dev/null +++ b/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.inf @@ -0,0 +1,49 @@ +# @Ds3232RtcLib.inf +# +# Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved. +# Copyright 2017 NXP +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may b= e found at +# http://opensource.org/licenses/bsd-license.php +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +# + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D Ds3232RtcLib + FILE_GUID =3D 97f1f2c2-51e1-47ad-9660-70b33da1fe71 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D RealTimeClockLib + +[Sources.common] + Ds3232RtcLib.c + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.dec + +[LibraryClasses] + DebugLib + UefiBootServicesTableLib + UefiLib + +[Protocols] + gEfiI2cMasterProtocolGuid ## CONSUMES + +[FixedPcd] + gDs3232RtcLibTokenSpaceGuid.PcdI2cSlaveAddress + gDs3232RtcLibTokenSpaceGuid.PcdI2cBusFrequency + gDs3232RtcLibTokenSpaceGuid.PcdIsRtcDeviceMuxed + gDs3232RtcLibTokenSpaceGuid.PcdMuxDeviceAddress + gDs3232RtcLibTokenSpaceGuid.PcdMuxControlRegOffset + gDs3232RtcLibTokenSpaceGuid.PcdMuxRtcChannelValue + gDs3232RtcLibTokenSpaceGuid.PcdMuxDefaultChannelValue + +[Depex] + gEfiI2cMasterProtocolGuid --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun May 5 06:05:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" From: Wasim Khan The firmware device, description and declaration files for LS2088 board Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Wasim Khan --- Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dec | 29 ++++ Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc | 100 ++++++++++++++ Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf | 198 +++++++++++++++++++++++= ++++ Silicon/NXP/LS2088A/LS2088A.dec | 22 +++ Silicon/NXP/LS2088A/LS2088A.dsc | 71 ++++++++++ Silicon/NXP/NxpQoriqLs.dec | 13 ++ 6 files changed, 433 insertions(+) create mode 100644 Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dec create mode 100755 Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc create mode 100644 Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf create mode 100644 Silicon/NXP/LS2088A/LS2088A.dec create mode 100644 Silicon/NXP/LS2088A/LS2088A.dsc diff --git a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dec b/Platform/NXP/LS= 2088aRdbPkg/LS2088aRdbPkg.dec new file mode 100644 index 0000000..93d2e5a --- /dev/null +++ b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dec @@ -0,0 +1,29 @@ +# LS2088aRdbPkg.dec +# LS2088a board package. +# +# Copyright 2017 NXP +# +# This program and the accompanying materials are licensed and made avail= able under +# the terms and conditions of the BSD License which accompanies this dist= ribution. +# The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# + +[Defines] + PACKAGE_NAME =3D LS2088aRdbPkg + PACKAGE_GUID =3D 474e0c59-5f77-4060-82dd-9025ee4f4939 + +##########################################################################= ###### +# +# Include Section - list of Include Paths that are provided by this packag= e. +# Comments are used for Keywords and Module Types. +# +# Supported Module Types: +# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_D= RIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION +# +##########################################################################= ###### +[Includes.common] + Include # Root include for the package diff --git a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc b/Platform/NXP/LS= 2088aRdbPkg/LS2088aRdbPkg.dsc new file mode 100755 index 0000000..c0a802d --- /dev/null +++ b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc @@ -0,0 +1,100 @@ +# LS2088aRdbPkg.dsc +# +# LS2088ARDB Board package. +# +# Copyright 2017 NXP +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may b= e found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# + +##########################################################################= ###### +# +# Defines Section - statements that will be processed to create a Makefile. +# +##########################################################################= ###### +[Defines] + # + # Defines for default states. These can be changed on the command line. + # -D FLAG=3DVALUE + # + PLATFORM_NAME =3D LS2088aRdbPkg + PLATFORM_GUID =3D be06d8bc-05eb-44d6-b39f-191e93617ebd + OUTPUT_DIRECTORY =3D Build/LS2088aRdbPkg + FLASH_DEFINITION =3D Platform/NXP/LS2088aRdbPkg/LS2088aRdb= Pkg.fdf + DEFINE MC_HIGH_MEM =3D TRUE + +!include ../NxpQoriqLs.dsc +!include ../../../Silicon/NXP/LS2088A/LS2088A.dsc + +[LibraryClasses.common] + ArmPlatformLib|Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatfor= mLib.inf + ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSy= stemLib.inf + SerialPortLib|Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf + BeIoLib|Silicon/NXP/Library/BeIoLib/BeIoLib.inf + SocLib|Silicon/NXP/Chassis/LS2088aSocLib.inf + RealTimeClockLib|Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.inf + +[PcdsFixedAtBuild.common] + +!if $(MC_HIGH_MEM) =3D=3D TRUE # Ma= nagement Complex loaded at the end of DDR2 + gNxpQoriqLsTokenSpaceGuid.PcdDram1BaseAddr|0x0080000000 # Actual= base address (0x0080000000) + gNxpQoriqLsTokenSpaceGuid.PcdDram1Size|0x0080000000 # 2 GB + gNxpQoriqLsTokenSpaceGuid.PcdDpaa2McRamSize|0x80000000 # 2GB (P= cdDpaa2McRamSize must be 512MB aligned) + gNxpQoriqLsTokenSpaceGuid.PcdMcHighMemSupport|1 + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x0080000000 # Actual= base + gArmTokenSpaceGuid.PcdSystemMemorySize|0x0080000000 # 2G +!else + gNxpQoriqLsTokenSpaceGuid.PcdDram1BaseAddr|0x00A0000000 # Actual= base address (0x0080000000) + 512MB + gNxpQoriqLsTokenSpaceGuid.PcdDram1Size|0x0060000000 # 2GB - = 512MB + gNxpQoriqLsTokenSpaceGuid.PcdDpaa2McRamSize|0x20000000 # 512MB = (Fixed) + gNxpQoriqLsTokenSpaceGuid.PcdMcHighMemSupport|0 + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x00A0000000 # Actual= base + 512MB + gArmTokenSpaceGuid.PcdSystemMemorySize|0x0060000000 # 2G - 5= 12MB +!endif + gNxpQoriqLsTokenSpaceGuid.PcdDramMemSize|0x380000000 # 14 GB + gNxpQoriqLsTokenSpaceGuid.PcdDram2BaseAddr|0x8080000000 + gNxpQoriqLsTokenSpaceGuid.PcdDram2Size|0x8800000000 # 512 GB + gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x02000000 + + # + # Board Specific Pcds + # + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x21c0600 + gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|TRUE + gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x2 + gNxpQoriqLsTokenSpaceGuid.PcdDdrClk|133333333 + + # + # I2C controller Pcds + # + gNxpQoriqLsTokenSpaceGuid.PcdI2cBus|0 + + # + # RTC Pcds + # + gDs3232RtcLibTokenSpaceGuid.PcdI2cSlaveAddress|0x68 + gDs3232RtcLibTokenSpaceGuid.PcdI2cBusFrequency|100000 + gDs3232RtcLibTokenSpaceGuid.PcdIsRtcDeviceMuxed|TRUE + gDs3232RtcLibTokenSpaceGuid.PcdMuxDeviceAddress|0x75 + gDs3232RtcLibTokenSpaceGuid.PcdMuxControlRegOffset|0x09 + gDs3232RtcLibTokenSpaceGuid.PcdMuxRtcChannelValue|0x09 + gDs3232RtcLibTokenSpaceGuid.PcdMuxDefaultChannelValue|0x08 + +##########################################################################= ###### +# +# Components Section - list of all EDK II Modules needed by this Platform +# +##########################################################################= ###### +[Components.common] + # + # Architectural Protocols + # + MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf + ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf + Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf diff --git a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf b/Platform/NXP/LS= 2088aRdbPkg/LS2088aRdbPkg.fdf new file mode 100644 index 0000000..14072a6 --- /dev/null +++ b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf @@ -0,0 +1,198 @@ +# LS2088aRdbPkg.fdf +# +# FLASH layout file for LS2088a board. +# +# Copyright (c) 2016, Freescale Ltd. All rights reserved. +# Copyright 2017 NXP +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may b= e found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# + +##########################################################################= ###### +# +# FD Section +# The [FD] Section is made up of the definition statements and a +# description of what goes into the Flash Device Image. Each FD section +# defines one flash "device" image. A flash device image may be one of +# the following: Removable media bootable image (like a boot floppy +# image,) an Option ROM image (that would be "flashed" into an add-in +# card,) a System "Flash" image (that would be burned into a system's +# flash) or an Update ("Capsule") image that will be used to update and +# existing system flash. +# +##########################################################################= ###### + +[FD.LS2088aRdb_EFI] +BaseAddress =3D 0x82000000|gArmTokenSpaceGuid.PcdFdBaseAddress #The bas= e address of the FLASH Device. +Size =3D 0x00100000|gArmTokenSpaceGuid.PcdFdSize #The s= ize in bytes of the FLASH Device +ErasePolarity =3D 1 +BlockSize =3D 0x1 +NumBlocks =3D 0x00100000 + +##########################################################################= ###### +# +# Following are lists of FD Region layout which correspond to the location= s of different +# images within the flash device. +# +# Regions must be defined in ascending order and may not overlap. +# +# A Layout Region start with a eight digit hex offset (leading "0x" requir= ed) followed by +# the pipe "|" character, followed by the size of the region, also in hex = with the leading +# "0x" characters. Like: +# Offset|Size +# PcdOffsetCName|PcdSizeCName +# RegionType +# +##########################################################################= ###### +0x00000000|0x00100000 +gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize +FV =3D FVMAIN_COMPACT + +!include ../FVRules.fdf.inc +##########################################################################= ###### +# +# FV Section +# +# [FV] section is used to define what components or modules are placed wit= hin a flash +# device file. This section also defines order the components and modules= are positioned +# within the image. The [FV] section consists of define statements, set s= tatements and +# module statements. +# +##########################################################################= ###### + +[FV.FvMain] +FvNameGuid =3D 1037c42b-8452-4c41-aac7-41e6c31468da +BlockSize =3D 0x1 +NumBlocks =3D 0 # This FV gets compressed so make it just= big enough +FvAlignment =3D 8 # FV alignment and FV attributes setting. +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE + + INF MdeModulePkg/Core/Dxe/DxeMain.inf + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + + # + # PI DXE Drivers producing Architectural Protocols (EFI Services) + # + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf + + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf + INF ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf + INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.= inf + INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.i= nf + + INF Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf + + INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + + # + # Multiple Console IO support + # + INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe= .inf + INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + + INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf + + # + # Network modules + # + INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf + INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf + INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf + INF MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf + INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf + INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf + INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf + INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf + INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf + INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf + INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf +!if $(NETWORK_IP6_ENABLE) =3D=3D TRUE + INF NetworkPkg/Ip6Dxe/Ip6Dxe.inf + INF NetworkPkg/TcpDxe/TcpDxe.inf + INF NetworkPkg/Udp6Dxe/Udp6Dxe.inf + INF NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf + INF NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf + INF NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf +!else + INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf +!endif + + # + # FAT filesystem + GPT/MBR partitioning + # + INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.i= nf + INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + INF FatPkg/FatPei/FatPei.inf + INF FatPkg/EnhancedFatDxe/Fat.inf + + # + # UEFI application (Shell Embedded Boot Loader) + # + INF ShellPkg/Application/Shell/Shell.inf + + # + # Bds + # + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + INF MdeModulePkg/Application/UiApp/UiApp.inf + +[FV.FVMAIN_COMPACT] +FvAlignment =3D 8 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE + + INF ArmPlatformPkg/PrePi/PeiUniCore.inf + + FILE FV_IMAGE =3D 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRE= D =3D TRUE { + SECTION FV_IMAGE =3D FVMAIN + } + } + diff --git a/Silicon/NXP/LS2088A/LS2088A.dec b/Silicon/NXP/LS2088A/LS2088A.= dec new file mode 100644 index 0000000..8539c63 --- /dev/null +++ b/Silicon/NXP/LS2088A/LS2088A.dec @@ -0,0 +1,22 @@ +# LS2088A.dec +# +# Copyright 2017 NXP +# +# This program and the accompanying materials are licensed and made availa= ble under +# the terms and conditions of the BSD License which accompanies this distr= ibution. +# The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. +# +# + +[Defines] + DEC_SPECIFICATION =3D 0x00010005 + +[Guids.common] + gNxpLs2088ATokenSpaceGuid =3D {0xaf770da7, 0x264c, 0x4857, {0x9d, 0= xed, 0x56, 0x5e, 0x2c, 0x08, 0x7e, 0x26}} + +[Includes] + Include diff --git a/Silicon/NXP/LS2088A/LS2088A.dsc b/Silicon/NXP/LS2088A/LS2088A.= dsc new file mode 100644 index 0000000..8f7dbb5 --- /dev/null +++ b/Silicon/NXP/LS2088A/LS2088A.dsc @@ -0,0 +1,71 @@ +# LS2088A.dsc +# LS2088A Soc package. +# +# Copyright 2017 NXP +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may b= e found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +# + +##########################################################################= ###### +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +##########################################################################= ###### +[PcdsDynamicDefault.common] + + # + # ARM General Interrupt Controller + gArmTokenSpaceGuid.PcdGicDistributorBase|0x6000000 + gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x6100000 + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x00 + +[PcdsFixedAtBuild.common] + + gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x0C000000 + gArmPlatformTokenSpaceGuid.PcdSP805WatchdogClockFrequencyInHz|266666666 = #266MHz + + # + # ARM L2x0 PCDs + gArmTokenSpaceGuid.PcdL2x0ControllerBase|0x10900000 + + # + # CCSR Address Space and other attached Memories + # + gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x01000000 + gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0F000000 + gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr|0x1370000 + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr|0x30000000 + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size|0x10000000 + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr|0x510000000 + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size|0xF0000000 + gNxpQoriqLsTokenSpaceGuid.PcdIfcNandReservedSize|0x3EEA + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x20000000 + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x10000000 + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2BaseAddr|0x400000000 + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2Size|0x10000000 + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr|0x2000000000 + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize|0x800000000 # 32 GB + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr|0x2800000000 + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize|0x800000000 # 32 GB + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr|0x3000000000 + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize|0x800000000 # 32 GB + gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseAddr|0x3800000000 + gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseSize|0x800000000 # 32 GB + gNxpQoriqLsTokenSpaceGuid.PcdSystemMemoryExBase|0x8080000000 # Extend= ed System Memory Base + gNxpQoriqLsTokenSpaceGuid.PcdSystemMemoryExSize|0x0380000000 # 14GB E= xtended System Memory Size + gNxpQoriqLsTokenSpaceGuid.PcdUsbBaseAddr|0x3100000 + gNxpQoriqLsTokenSpaceGuid.PcdUsbSize|0x10000 + gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr|0x1E00000 + gNxpQoriqLsTokenSpaceGuid.PcdSdxcBaseAddr|0x02140000 + gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr|0x02000000 + gNxpQoriqLsTokenSpaceGuid.PcdI2cSize|0x10000 + gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|4 + +## diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec index 39753e7..3cb476d 100644 --- a/Silicon/NXP/NxpQoriqLs.dec +++ b/Silicon/NXP/NxpQoriqLs.dec @@ -92,6 +92,18 @@ gNxpQoriqLsTokenSpaceGuid.PcdFlashReservedRegionBase64|0x0|UINT64|0x0000= 0196 =20 # + # DPAA2 PCDs + # + gNxpQoriqLsTokenSpaceGuid.PcdDpaa2McRamSize|0x0|UINT64|0x000001E0 + gNxpQoriqLsTokenSpaceGuid.PcdDpaa2McPortalBaseAddr|0x0|UINT64|0x000001E1 + gNxpQoriqLsTokenSpaceGuid.PcdDpaa2McPortalSize|0x0|UINT64|0x000001E2 + gNxpQoriqLsTokenSpaceGuid.PcdDpaa2NiPortalsBaseAddr|0x0|UINT64|0x000001E3 + gNxpQoriqLsTokenSpaceGuid.PcdDpaa2NiPortalsSize|0x0|UINT64|0x000001E4 + gNxpQoriqLsTokenSpaceGuid.PcdDpaa2QBmanPortalsBaseAddr|0x0|UINT64|0x0000= 01E5 + gNxpQoriqLsTokenSpaceGuid.PcdDpaa2QBmanPortalSize|0x0|UINT64|0x000001E6 + gNxpQoriqLsTokenSpaceGuid.PcdDpaa2QBmanPortalsCacheSize|0x0|UINT64|0x000= 001E7 + + # # NV Pcd # gNxpQoriqLsTokenSpaceGuid.PcdNvFdBase|0x0|UINT64|0x00000210 @@ -102,6 +114,7 @@ # gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x0|UINT32|0x00000250 gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE|BOOLEAN|0x00000251 + gNxpQoriqLsTokenSpaceGuid.PcdMcHighMemSupport|FALSE|BOOLEAN|0x00000252 gNxpQoriqLsTokenSpaceGuid.PcdMuxToUsb3|FALSE|BOOLEAN|0x00000253 =20 # --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun May 5 06:05:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" From: Wasim Khan Library to provide board specific timings for LS2088ARDB board with interfacing to IFC controller for accessing NOR, NAND and FPGA. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Wasim Khan --- .../NXP/LS2088aRdbPkg/Include/IfcBoardSpecific.h | 114 +++++++++++++++++= ++++ .../NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.c | 69 +++++++++++++ .../LS2088aRdbPkg/Library/BoardLib/BoardLib.inf | 28 +++++ 3 files changed, 211 insertions(+) create mode 100644 Platform/NXP/LS2088aRdbPkg/Include/IfcBoardSpecific.h create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.c create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.inf diff --git a/Platform/NXP/LS2088aRdbPkg/Include/IfcBoardSpecific.h b/Platfo= rm/NXP/LS2088aRdbPkg/Include/IfcBoardSpecific.h new file mode 100644 index 0000000..174a242 --- /dev/null +++ b/Platform/NXP/LS2088aRdbPkg/Include/IfcBoardSpecific.h @@ -0,0 +1,114 @@ +/** IfcBoardSpecificLib.h + + IFC Flash Board Specific Macros and structure + + Copyright 2017-2018 NXP + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may be= found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ +#ifndef __IFC__BOARD_SPECIFIC_H__ +#define __IFC__BOARD_SPECIFIC_H__ + +#include + +// On board flash support +#define IFC_NAND_BUF_BASE 0x530000000ULL + +// On board Inegrated flash Controller chip select configuration +#define IFC_NOR_CS IFC_CS0 +#define IFC_NAND_CS IFC_CS2 +#define IFC_FPGA_CS IFC_CS3 + + +/* board-specific NAND timing */ +#define NAND_FTIM0 (IFC_FTIM0_NAND_TCCST(0x0e) | \ + IFC_FTIM0_NAND_TWP(0x30) | \ + IFC_FTIM0_NAND_TWCHT(0x0e) | \ + IFC_FTIM0_NAND_TWH(0x14)) + +#define NAND_FTIM1 (IFC_FTIM1_NAND_TADLE(0x64) | \ + IFC_FTIM1_NAND_TWBE(0xab) | \ + IFC_FTIM1_NAND_TRR(0x1c) | \ + IFC_FTIM1_NAND_TRP(0x30)) + +#define NAND_FTIM2 (IFC_FTIM2_NAND_TRAD(0x1e) | \ + IFC_FTIM2_NAND_TREH(0x14) | \ + IFC_FTIM2_NAND_TWHRE(0x3c)) + +#define NAND_FTIM3 0x0 + +#define IFC_NAND_BASE_PHYS 0x30000000 +#define NAND_CSPR (IFC_CSPR_PHYS_ADDR(IFC_NAND_BASE_PHYS) \ + | IFC_CSPR_PORT_SIZE_8 \ + | IFC_CSPR_MSEL_NAND \ + | IFC_CSPR_V) + +#define NAND_CSPR_EXT 0x0 +#define NAND_AMASK 0xFFFF0000 + +#define NAND_CSOR (IFC_CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | IFC_CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | IFC_CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ + | IFC_CSOR_NAND_RAL_3 /* RAL =3D 3 Bytes */ \ + | IFC_CSOR_NAND_PGS_4K /* Page Size =3D 4K */ \ + | IFC_CSOR_NAND_SPRZ_224 /* Spare size =3D 224 = */ \ + | IFC_CSOR_NAND_PB(7)) /* 2^7 Pages Per Block */ + +// board-specific NOR timing +#define NOR_FTIM0 (IFC_FTIM0_NOR_TACSE(0x4) | \ + IFC_FTIM0_NOR_TEADC(0x5) | \ + IFC_FTIM0_NOR_TEAHC(0x5)) + +#define NOR_FTIM1 (IFC_FTIM1_NOR_TACO(0x35) | \ + IFC_FTIM1_NOR_TRAD_NOR(0x1a) | \ + IFC_FTIM1_NOR_TSEQRAD_NOR(0x13)) + +#define NOR_FTIM2 (IFC_FTIM2_NOR_TCS(0x4) | \ + IFC_FTIM2_NOR_TCH(0x4) | \ + IFC_FTIM2_NOR_TWPH(0xe) | \ + IFC_FTIM2_NOR_TWP(0x1c)) + +#define NOR_FTIM3 0x04000000 + +#define IFC_FLASH_BASE_PHYS 0x80000000 +#define NOR_CSPR (IFC_CSPR_PHYS_ADDR(IFC_FLASH_BASE_PHYS) \ + | IFC_CSPR_PORT_SIZE_16 \ + | IFC_CSPR_MSEL_NOR \ + | IFC_CSPR_V) + +#define NOR_CSPR_EXT 0x0 +#define NOR_AMASK IFC_AMASK(128*1024*1024) +#define NOR_CSOR IFC_CSOR_NOR_ADM_SHIFT(12) + +// board-specific fpga timing +#define FPGA_BASE_PHYS 0x20000000 +#define FPGA_CSPR_EXT 0x0 +#define FPGA_CSPR (IFC_CSPR_PHYS_ADDR(FPGA_BASE_PHYS) | \ + IFC_CSPR_PORT_SIZE_8 | \ + IFC_CSPR_MSEL_GPCM | \ + IFC_CSPR_V) + +#define FPGA_AMASK IFC_AMASK(64 * 1024) +#define FPGA_CSOR IFC_CSOR_NOR_ADM_SHIFT(12) + +#define FPGA_FTIM0 (IFC_FTIM0_GPCM_TACSE(0xe) | \ + IFC_FTIM0_GPCM_TEADC(0xe) | \ + IFC_FTIM0_GPCM_TEAHC(0xe)) + +#define FPGA_FTIM1 (IFC_FTIM1_GPCM_TACO(0xff) | \ + IFC_FTIM1_GPCM_TRAD(0x3f)) + +#define FPGA_FTIM2 (IFC_FTIM2_GPCM_TCS(0xf) | \ + IFC_FTIM2_GPCM_TCH(0xf) | \ + IFC_FTIM2_GPCM_TWP(0x3e)) + +#define FPGA_FTIM3 0x0 + +#endif //__IFC__BOARD_SPECIFIC_H__ diff --git a/Platform/NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.c b/Platf= orm/NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.c new file mode 100644 index 0000000..936b789 --- /dev/null +++ b/Platform/NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.c @@ -0,0 +1,69 @@ +/** @file + + Copyright 2017-2018 NXP + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include + +VOID +GetIfcNorFlashTimings ( + IN IFC_TIMINGS * NorIfcTimings + ) +{ + NorIfcTimings->Ftim[0] =3D NOR_FTIM0; + NorIfcTimings->Ftim[1] =3D NOR_FTIM1; + NorIfcTimings->Ftim[2] =3D NOR_FTIM2; + NorIfcTimings->Ftim[3] =3D NOR_FTIM3; + NorIfcTimings->Cspr =3D NOR_CSPR; + NorIfcTimings->CsprExt =3D NOR_CSPR_EXT; + NorIfcTimings->Amask =3D NOR_AMASK; + NorIfcTimings->Csor =3D NOR_CSOR; + NorIfcTimings->CS =3D IFC_NOR_CS; + + return ; +} + +VOID +GetIfcFpgaTimings ( + IN IFC_TIMINGS *FpgaIfcTimings + ) +{ + FpgaIfcTimings->Ftim[0] =3D FPGA_FTIM0; + FpgaIfcTimings->Ftim[1] =3D FPGA_FTIM1; + FpgaIfcTimings->Ftim[2] =3D FPGA_FTIM2; + FpgaIfcTimings->Ftim[3] =3D FPGA_FTIM3; + FpgaIfcTimings->Cspr =3D FPGA_CSPR; + FpgaIfcTimings->CsprExt =3D FPGA_CSPR_EXT; + FpgaIfcTimings->Amask =3D FPGA_AMASK; + FpgaIfcTimings->Csor =3D FPGA_CSOR; + FpgaIfcTimings->CS =3D IFC_FPGA_CS; + + return; +} + +VOID +GetIfcNandFlashTimings ( + IN IFC_TIMINGS * NandIfcTimings + ) +{ + NandIfcTimings->Ftim[0] =3D NAND_FTIM0; + NandIfcTimings->Ftim[1] =3D NAND_FTIM1; + NandIfcTimings->Ftim[2] =3D NAND_FTIM2; + NandIfcTimings->Ftim[3] =3D NAND_FTIM3; + NandIfcTimings->Cspr =3D NAND_CSPR; + NandIfcTimings->CsprExt =3D NAND_CSPR_EXT; + NandIfcTimings->Amask =3D NAND_AMASK; + NandIfcTimings->Csor =3D NAND_CSOR; + NandIfcTimings->CS =3D IFC_NAND_CS; + + return; +} diff --git a/Platform/NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.inf b/Pla= tform/NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.inf new file mode 100644 index 0000000..5df84b1 --- /dev/null +++ b/Platform/NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.inf @@ -0,0 +1,28 @@ +# @file +# +# Copyright 2017-2018 NXP +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D BoardLib + FILE_GUID =3D 13eacf2a-4338-48f4-88de-6ce4618e1a53 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D BoardLib + +[Sources.common] + BoardLib.c + +[Packages] + MdePkg/MdePkg.dec + Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dec + Silicon/NXP/NxpQoriqLs.dec --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun May 5 06:05:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; 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charset="utf-8" From: Wasim Khan Library to provide functions for accessing FPGA on LS2088ARDB board. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Wasim Khan --- .../NXP/LS2088aRdbPkg/Include/Library/FpgaLib.h | 166 +++++++++++++++++= ++++ .../NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.c | 115 ++++++++++++++ .../NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.inf | 31 ++++ 3 files changed, 312 insertions(+) create mode 100644 Platform/NXP/LS2088aRdbPkg/Include/Library/FpgaLib.h create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.c create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.inf diff --git a/Platform/NXP/LS2088aRdbPkg/Include/Library/FpgaLib.h b/Platfor= m/NXP/LS2088aRdbPkg/Include/Library/FpgaLib.h new file mode 100644 index 0000000..84d1f02 --- /dev/null +++ b/Platform/NXP/LS2088aRdbPkg/Include/Library/FpgaLib.h @@ -0,0 +1,166 @@ +/** FpgaLib.h +* Header defining the LS2088a Fpga specific constants (Base addresses, si= zes, flags) +* +* Copyright 2017-2018 NXP +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the B= SD License +* which accompanies this distribution. The full text of the license may = be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#ifndef __LS2088A_FPGA_H__ +#define __LS2088A_FPGA_H__ + +typedef enum { + CLK_66, + CLK_83, + CLK_100, + CLK_125, + CLK_133 +} SYSTEM_CLOCK; + +/* + * FPGA register set of LS2088ARDB board-specific. + */ +typedef struct { + UINT8 Id; // ID value uniquely identifying each QorIQ board ty= pe + UINT8 Arch; // Board Version + UINT8 Ver; // FPGA Version + UINT8 Model; // Programming Model + UINT8 Minor; // Minor Revision Number + UINT8 CtlSys; + UINT8 Aux; + UINT8 ClkSpd; + UINT8 StatDut; + UINT8 StatSys; + UINT8 StatAlrm; + UINT8 Present; + UINT8 Present2; + UINT8 RcwCtl; + UINT8 CtlLed; + UINT8 I2cBlk; + UINT8 RcfgCtl; + UINT8 RcfgSt; + UINT8 DcmAd; + UINT8 DcmDa; + UINT8 Dcmd; + UINT8 Dmsg; + UINT8 Gdc; + UINT8 Gdd; + UINT8 Dmack; + UINT8 Res1[6]; + UINT8 Watch; + UINT8 PwrCtl[2]; + UINT8 Res2[2]; + UINT8 PwrStat[4]; + UINT8 Res3[8]; + UINT8 ClkSpd2[2]; + UINT8 Res4[2]; + UINT8 Sclk[3]; + UINT8 Res5; + UINT8 Dclk[3]; + UINT8 Res6; + UINT8 ClkDspd[3]; + UINT8 Res7; + UINT8 RstCtl; + UINT8 RstStat; + UINT8 RstRsn; + UINT8 RstFrc[2]; + UINT8 Res8[11]; + UINT8 BrdCfg[16]; + UINT8 DutCfg[16]; + UINT8 RcwAd[2]; + UINT8 RcwData; + UINT8 Res9[5]; + UINT8 PostCtl; + UINT8 PostStat; + UINT8 PostDat[2]; + UINT8 Pid[4]; + UINT8 GpioIo[4]; + UINT8 GpioDir[4]; + UINT8 Res10[20]; + UINT8 RjtagCtl; + UINT8 RjtagDat; + UINT8 Res11[2]; + UINT8 TrigSrc[4]; + UINT8 TrigDst[4]; + UINT8 TrigStat; + UINT8 Res12[3]; + UINT8 TrigCtr[4]; + UINT8 Res13[16]; + UINT8 ClkFreq[6]; + UINT8 ResC6[8]; + UINT8 ClkBase[2]; + UINT8 ResD0[8]; + UINT8 Cms[2]; + UINT8 ResC0[6]; + UINT8 Aux2[4]; + UINT8 Res14[10]; + UINT8 AuxAd; + UINT8 AuxDa; + UINT8 Res15[16]; +} FPGA_REG_SET; + +/** + Function to read FPGA register. +**/ +UINT8 +FpgaRead ( + UINTN Reg + ); + +/** + Function to write FPGA register. +**/ +VOID +FpgaWrite ( + UINTN Reg, + UINT8 Value + ); + +/** + Function to initialize FPGA timings. +**/ +VOID +FpgaInit ( + VOID + ); + +/** + Function to get system clock frequency. +**/ +UINTN +GetBoardSysClk ( + VOID + ); + +/** + Function to print board personality. +**/ +VOID +PrintBoardPersonality ( + VOID + ); + +#define FPGA_BASE_PHYS 0x520000000 + +//SYSCLK +#define FPGA_CLK_MASK 0x0F // FPGA Clock Mask +#define SYSCLK_66_MHZ 66000000 +#define SYSCLK_83_MHZ 83000000 +#define SYSCLK_100_MHZ 100000000 +#define SYSCLK_125_MHZ 125000000 +#define SYSCLK_133_MHZ 133000000 + +#define FPGA_VBANK_MASK 0x07 +#define FPGA_CS_MASK 0x08 + +#define FPGA_READ(Reg) FpgaRead (OFFSET_OF (FPGA_REG_SET, Reg)) +#define FPGA_WRITE(Reg, Value) FpgaWrite (OFFSET_OF (FPGA_REG_SET, Reg),= Value) + +#endif // __LS2088A_FPGA_H__ diff --git a/Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.c b/Platfor= m/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.c new file mode 100644 index 0000000..8948c21 --- /dev/null +++ b/Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.c @@ -0,0 +1,115 @@ +/** @FpgaLib.c + Fpga Library for LS2088A-RDB board, containing functions to + program and read the Fpga registers. + + FPGA is connected to IFC Controller and so MMIO APIs are used + to read/write FPGA registers + + Copyright 2017-2018 NXP + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may be= found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include +#include +#include +#include +#include + +/** + Function to read FPGA register. + + @param Reg Register offset of FPGA to read. + +**/ +UINT8 +FpgaRead ( + IN UINTN Reg + ) +{ + VOID *Base; + + Base =3D (VOID *)FPGA_BASE_PHYS; + + return MmioRead8 ((UINTN)(Base + Reg)); +} + +/** + Function to write FPGA register. + + @param Reg Register offset of FPGA to write. + @param Value Value to be written. + +**/ +VOID +FpgaWrite ( + IN UINTN Reg, + IN UINT8 Value + ) +{ + VOID *Base; + + Base =3D (VOID *)FPGA_BASE_PHYS; + + MmioWrite8 ((UINTN)(Base + Reg), Value); +} + +/** + Function to get board system clock frequency. + +**/ +UINTN +GetBoardSysClk ( + VOID + ) +{ + UINT8 SysclkConf; + SysclkConf =3D FPGA_READ (BrdCfg[1]); + switch (SysclkConf & FPGA_CLK_MASK) { + case CLK_66: + return SYSCLK_66_MHZ; + case CLK_83: + return SYSCLK_83_MHZ; + case CLK_100: + return SYSCLK_100_MHZ; + case CLK_125: + return SYSCLK_125_MHZ; + case CLK_133: + return SYSCLK_133_MHZ; + } + return SYSCLK_100_MHZ; +} + +/** + Function to print board personality. + +**/ +VOID +PrintBoardPersonality ( + VOID + ) +{ + UINT8 SwitchConf; + SwitchConf =3D FPGA_READ (Arch); + + DEBUG ((DEBUG_INFO, "Board Arch: V%d, ", SwitchConf >> 4)); + DEBUG ((DEBUG_INFO, "Board version: %c, boot from ", + (SwitchConf & 0xf) + 'A')); + + SwitchConf =3D FPGA_READ (BrdCfg[0]); + + if (SwitchConf & FPGA_CS_MASK) + DEBUG ((DEBUG_INFO, "NAND\n")); + else + DEBUG ((DEBUG_INFO, "vBank: %d\n", (SwitchConf & FPGA_VBANK_MASK))); + + DEBUG ((DEBUG_INFO, "FPGA: v%d.%d\n", FPGA_READ (Ver), + FPGA_READ (Minor))); +} diff --git a/Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.inf b/Platf= orm/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.inf new file mode 100644 index 0000000..e70723a --- /dev/null +++ b/Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.inf @@ -0,0 +1,31 @@ +# @FpgaLib.inf +# +# Copyright 2017-2018 NXP +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# + +[Defines] + INF_VERSION =3D 0x0001000A + BASE_NAME =3D FpgaLib + FILE_GUID =3D dd2ce2f3-f219-4b57-82fd-f1ff8ae8bf5a + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D FpgaLib + +[Sources.common] + FpgaLib.c + +[Packages] + MdePkg/MdePkg.dec + Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dec + Silicon/NXP/NxpQoriqLs.dec + +[LibraryClasses] + BaseLib + IoLib --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun May 5 06:05:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; 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charset="utf-8" From: Wasim Khan Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Wasim Khan --- Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc | 3 +++ Silicon/NXP/Chassis/Chassis3/Soc.c | 18 +++++++++++++++++- Silicon/NXP/Chassis/Chassis3/Soc.h | 1 - Silicon/NXP/Chassis/LS2088aSocLib.inf | 2 ++ Silicon/NXP/LS2088A/LS2088A.dsc | 1 + 5 files changed, 23 insertions(+), 2 deletions(-) diff --git a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc b/Platform/NXP/LS= 2088aRdbPkg/LS2088aRdbPkg.dsc index c0a802d..7894925 100755 --- a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc +++ b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc @@ -39,6 +39,9 @@ BeIoLib|Silicon/NXP/Library/BeIoLib/BeIoLib.inf SocLib|Silicon/NXP/Chassis/LS2088aSocLib.inf RealTimeClockLib|Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.inf + IfcLib|Silicon/NXP/Library/IfcLib/IfcLib.inf + BoardLib|Platform/NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.inf + FpgaLib|Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.inf =20 [PcdsFixedAtBuild.common] =20 diff --git a/Silicon/NXP/Chassis/Chassis3/Soc.c b/Silicon/NXP/Chassis/Chass= is3/Soc.c index ed6c3cc..dbb1884 100644 --- a/Silicon/NXP/Chassis/Chassis3/Soc.c +++ b/Silicon/NXP/Chassis/Chassis3/Soc.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -25,6 +26,9 @@ =20 #include "Soc.h" =20 +extern VOID PrintBoardPersonality (VOID); +extern UINTN GetBoardSysClk (VOID); + VOID GetSysInfo ( OUT SYS_INFO *PtrSysInfo @@ -83,7 +87,7 @@ GetSysInfo ( =20 GurBase =3D (VOID *)PcdGet64 (PcdGutsBaseAddr); ClkBase =3D (VOID *)PcdGet64 (PcdClkBaseAddr); - SysClk =3D CLK_FREQ; + SysClk =3D GetBoardSysClk (); =20 PtrSysInfo->FreqSystemBus =3D SysClk; PtrSysInfo->FreqDdrBus =3D PcdGet64 (PcdDdrClk); @@ -152,6 +156,13 @@ SocInit ( SmmuInit (); =20 // + // Perform IFC Initialization. + // Early IFC initialization is required to set timings required for fpga= initilzation to + // get system clock frequency, board info etc. + // + IfcInit (); + + // // Initialize the Serial Port. // Early serial port initialization is required to print RCW, Soc and C= PU infomation at // the begining of UEFI boot. @@ -176,5 +187,10 @@ SocInit ( // Print Soc Personality information // PrintSoc (); + + // + // Print Board Personality information + // + PrintBoardPersonality (); } =20 diff --git a/Silicon/NXP/Chassis/Chassis3/Soc.h b/Silicon/NXP/Chassis/Chass= is3/Soc.h index 0e892fb..c3ac1d5 100644 --- a/Silicon/NXP/Chassis/Chassis3/Soc.h +++ b/Silicon/NXP/Chassis/Chassis3/Soc.h @@ -20,7 +20,6 @@ #define FSL_CLK_GRPA_ADDR 0x01300000 #define FSL_CLK_GRPB_ADDR 0x01310000 #define NUM_CC_PLLS 6 -#define CLK_FREQ 100000000 =20 #define FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } /* LS208x */ #define TP_CLUSTER_EOC_MASK 0x80000000 /* Mask for End of clu= sters */ diff --git a/Silicon/NXP/Chassis/LS2088aSocLib.inf b/Silicon/NXP/Chassis/LS= 2088aSocLib.inf index 8a4da50..3111d49 100644 --- a/Silicon/NXP/Chassis/LS2088aSocLib.inf +++ b/Silicon/NXP/Chassis/LS2088aSocLib.inf @@ -31,6 +31,8 @@ BaseLib BeIoLib DebugLib + FpgaLib + IfcLib SerialPortLib =20 [Sources.common] diff --git a/Silicon/NXP/LS2088A/LS2088A.dsc b/Silicon/NXP/LS2088A/LS2088A.= dsc index 8f7dbb5..2cff40f 100644 --- a/Silicon/NXP/LS2088A/LS2088A.dsc +++ b/Silicon/NXP/LS2088A/LS2088A.dsc @@ -67,5 +67,6 @@ gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr|0x02000000 gNxpQoriqLsTokenSpaceGuid.PcdI2cSize|0x10000 gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|4 + gNxpQoriqLsTokenSpaceGuid.PcdIfcBaseAddr|0x02240000 =20 ## --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun May 5 06:05:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" From: Wasim Khan Enable NOR driver and Runtime Services for LS2088ARDB Platform Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Wasim Khan --- Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc | 15 ++++- Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf | 6 +- Platform/NXP/LS2088aRdbPkg/VarStore.fdf.inc | 99 ++++++++++++++++++++++++= ++++ 3 files changed, 118 insertions(+), 2 deletions(-) create mode 100644 Platform/NXP/LS2088aRdbPkg/VarStore.fdf.inc diff --git a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc b/Platform/NXP/LS= 2088aRdbPkg/LS2088aRdbPkg.dsc index 7894925..60449b5 100755 --- a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc +++ b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc @@ -42,6 +42,7 @@ IfcLib|Silicon/NXP/Library/IfcLib/IfcLib.inf BoardLib|Platform/NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.inf FpgaLib|Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.inf + NorFlashLib|Silicon/NXP/Library/NorFlashLib/NorFlashLib.inf =20 [PcdsFixedAtBuild.common] =20 @@ -89,6 +90,13 @@ gDs3232RtcLibTokenSpaceGuid.PcdMuxRtcChannelValue|0x09 gDs3232RtcLibTokenSpaceGuid.PcdMuxDefaultChannelValue|0x08 =20 + # + # NV Storage PCDs. + # + gArmTokenSpaceGuid.PcdVFPEnabled|1 + gNxpQoriqLsTokenSpaceGuid.PcdFlashDeviceBase64|0x580000000 + gNxpQoriqLsTokenSpaceGuid.PcdFlashReservedRegionBase64|0x580300000 + ##########################################################################= ###### # # Components Section - list of all EDK II Modules needed by this Platform @@ -98,6 +106,11 @@ # # Architectural Protocols # - MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf{ + + NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf + } + MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf + Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf diff --git a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf b/Platform/NXP/LS= 2088aRdbPkg/LS2088aRdbPkg.fdf index 14072a6..785f88b 100644 --- a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf +++ b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf @@ -55,6 +55,7 @@ gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.Pc= dFvSize FV =3D FVMAIN_COMPACT =20 !include ../FVRules.fdf.inc +!include VarStore.fdf.inc ##########################################################################= ###### # # FV Section @@ -103,7 +104,8 @@ READ_LOCK_STATUS =3D TRUE INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf - INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.= inf + INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf + INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.i= nf INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.i= nf =20 INF Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf @@ -122,6 +124,8 @@ READ_LOCK_STATUS =3D TRUE INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf =20 + INF Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf + # # Network modules # diff --git a/Platform/NXP/LS2088aRdbPkg/VarStore.fdf.inc b/Platform/NXP/LS2= 088aRdbPkg/VarStore.fdf.inc new file mode 100644 index 0000000..7d35042 --- /dev/null +++ b/Platform/NXP/LS2088aRdbPkg/VarStore.fdf.inc @@ -0,0 +1,99 @@ +## @file +# FDF include file with FD definition that defines an empty variable stor= e. +# +# Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved. +# Copyright (C) 2014, Red Hat, Inc. +# Copyright (c) 2016, Linaro, Ltd. All rights reserved. +# Copyright (c) 2016, Freescale Semiconductor. All rights reserved. +# Copyright 2017-2018 NXP. +# +# This program and the accompanying materials are licensed and made avail= able +# under the terms and conditions of the BSD License which accompanies this +# distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR +# IMPLIED. +# +## + +[FD.LS2088aRdbNv_EFI] + +BaseAddress =3D 0x580300000|gNxpQoriqLsTokenSpaceGuid.PcdNvFdBase #The bas= e address of the FLASH device +Size =3D 0x000C0000|gNxpQoriqLsTokenSpaceGuid.PcdNvFdSize #The size in byt= es of the FLASH device +ErasePolarity =3D 1 +BlockSize =3D 0x1 +NumBlocks =3D 0xC0000 + +# +# Place NV Storage just above Platform Data Base +# +DEFINE NVRAM_AREA_VARIABLE_BASE =3D 0x00000000 +DEFINE NVRAM_AREA_VARIABLE_SIZE =3D 0x00040000 +DEFINE FTW_WORKING_BASE =3D $(NVRAM_AREA_VARIABLE_B= ASE) + $(NVRAM_AREA_VARIABLE_SIZE) +DEFINE FTW_WORKING_SIZE =3D 0x00040000 +DEFINE FTW_SPARE_BASE =3D $(FTW_WORKING_BASE) + $= (FTW_WORKING_SIZE) +DEFINE FTW_SPARE_SIZE =3D 0x00040000 + +##########################################################################= ### +# LS2088ARDB NVRAM Area +# LS2088ARDB NVRAM Area contains: Variable + FTW Working + FTW Spare +##########################################################################= ### + + +$(NVRAM_AREA_VARIABLE_BASE)|$(NVRAM_AREA_VARIABLE_SIZE) +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|gEfiMdeModu= lePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize +#NV_VARIABLE_STORE +DATA =3D { + ## This is the EFI_FIRMWARE_VOLUME_HEADER + # ZeroVector [] + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + # FileSystemGuid: gEfiSystemNvDataFvGuid =3D + # { 0xFFF12B8D, 0x7696, 0x4C8B, + # { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }} + 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C, + 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50, + # FvLength: 0xC0000 + 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, + # Signature "_FVH" # Attributes + 0x5f, 0x46, 0x56, 0x48, 0x36, 0x0E, 0x00, 0x00, + # HeaderLength # CheckSum # ExtHeaderOffset #Reserved #Revision + 0x48, 0x00, 0xFA, 0xF5, 0x00, 0x00, 0x00, 0x02, + # Blockmap[0]: 0x3 Blocks * 0x40000 Bytes / Block + 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, + # Blockmap[1]: End + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + ## This is the VARIABLE_STORE_HEADER + # It is compatible with SECURE_BOOT_ENABLE =3D=3D FALSE as well. + # Signature: gEfiAuthenticatedVariableGuid =3D + # { 0xaaf32c78, 0x947b, 0x439a, + # { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }} + 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43, + 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92, + # Size: 0x40000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariabl= eSize) - + # 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) =3D 0x3ffb8 + # This can speed up the Variable Dispatch a bit. + 0xB8, 0xFF, 0x03, 0x00, + # FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32 + 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +} + +$(FTW_WORKING_BASE)|$(FTW_WORKING_SIZE) +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|gEfiMdeMo= dulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize +#NV_FTW_WORKING +DATA =3D { + # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature =3D gEdkiiWorkingBl= ockSignatureGuid =3D + # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0= x1b, 0x95 }} + 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49, + 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95, + # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Res= erved + 0x5b, 0xe7, 0xc6, 0x86, 0xFE, 0xFF, 0xFF, 0xFF, + # WriteQueueSize: UINT64 + 0xE0, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00 +} + +$(FTW_SPARE_BASE)|$(FTW_SPARE_SIZE) +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|gEfiMdeModu= lePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize +#NV_FTW_SPARE --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun May 5 06:05:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" From: Vabhav Multiple root complex support is not provided by standard library PciLib/PciExpressLib/PciSegmentLib, Reimplementing it and provide function for reading/writing into PCIe configuration Space. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Vabhav Signed-off-by: Meenakshi Aggarwal --- Silicon/NXP/Include/Pcie.h | 143 +++++ Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c | 604 +++++++++++++++++= ++++ .../NXP/Library/PciSegmentLib/PciSegmentLib.inf | 41 ++ 3 files changed, 788 insertions(+) create mode 100644 Silicon/NXP/Include/Pcie.h create mode 100644 Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c create mode 100644 Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf diff --git a/Silicon/NXP/Include/Pcie.h b/Silicon/NXP/Include/Pcie.h new file mode 100644 index 0000000..a7e6f9b --- /dev/null +++ b/Silicon/NXP/Include/Pcie.h @@ -0,0 +1,143 @@ +/** @file + PCI memory configuration for NXP + + Copyright 2018 NXP + + This program and the accompanying materials are licensed and made availa= ble + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WI= THOUT + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __PCI_H__ +#define __PCI_H__ + +// Segment 0 +#define PCI_SEG0_NUM 0 + +#define PCI_SEG0_BUSNUM_MIN 0x0 +#define PCI_SEG0_BUSNUM_MAX 0xff + +#define PCI_SEG0_PORTIO_MIN 0x0 +#define PCI_SEG0_PORTIO_MAX 0xffff + +#define PCI_SEG0_MMIO32_MIN 0x40000000 +#define PCI_SEG0_MMIO32_MAX 0x4fffffff +#define PCI_SEG0_MMIO64_MIN PCI_SEG0_MMIO_MEMBASE + SEG_MEM_SIZE +#define PCI_SEG0_MMIO64_MAX PCI_SEG0_MMIO_MEMBASE + SEG_MEM_LIMIT +#define PCI_SEG0_MMIO_MEMBASE FixedPcdGet64 (PcdPciExp1BaseAddr) + +#define PCI_SEG0_DBI_BASE 0x03400000 + +// Segment 1 +#define PCI_SEG1_NUM 1 + +#define PCI_SEG1_BUSNUM_MIN 0x0 +#define PCI_SEG1_BUSNUM_MAX 0xff + +#define PCI_SEG1_PORTIO_MIN 0x10000 +#define PCI_SEG1_PORTIO_MAX 0x1ffff + +#define PCI_SEG1_MMIO32_MIN 0x50000000 +#define PCI_SEG1_MMIO32_MAX 0x5fffffff +#define PCI_SEG1_MMIO64_MIN PCI_SEG1_MMIO_MEMBASE + SEG_MEM_SIZE +#define PCI_SEG1_MMIO64_MAX PCI_SEG1_MMIO_MEMBASE + SEG_MEM_LIMIT +#define PCI_SEG1_MMIO_MEMBASE FixedPcdGet64 (PcdPciExp2BaseAddr) + +#define PCI_SEG1_DBI_BASE 0x03500000 + +// Segment 2 +#define PCI_SEG2_NUM 2 + +#define PCI_SEG2_BUSNUM_MIN 0x0 +#define PCI_SEG2_BUSNUM_MAX 0xff + +#define PCI_SEG2_PORTIO_MIN 0x20000 +#define PCI_SEG2_PORTIO_MAX 0x2ffff + +#define PCI_SEG2_MMIO32_MIN 0x60000000 +#define PCI_SEG2_MMIO32_MAX 0x6fffffff +#define PCI_SEG2_MMIO64_MIN PCI_SEG2_MMIO_MEMBASE + SEG_MEM_SIZE +#define PCI_SEG2_MMIO64_MAX PCI_SEG2_MMIO_MEMBASE + SEG_MEM_LIMIT +#define PCI_SEG2_MMIO_MEMBASE FixedPcdGet64 (PcdPciExp3BaseAddr) + +#define PCI_SEG2_DBI_BASE 0x03600000 + +// Segment 3 +#define PCI_SEG3_NUM 3 + +#define PCI_SEG3_BUSNUM_MIN 0x0 +#define PCI_SEG3_BUSNUM_MAX 0xff + +#define PCI_SEG3_PORTIO_MIN 0x30000 +#define PCI_SEG3_PORTIO_MAX 0x3ffff + +#define PCI_SEG3_MMIO32_MIN 0x70000000 +#define PCI_SEG3_MMIO32_MAX 0x7fffffff +#define PCI_SEG3_MMIO64_MIN PCI_SEG3_MMIO_MEMBASE + SEG_MEM_SIZE +#define PCI_SEG3_MMIO64_MAX PCI_SEG3_MMIO_MEMBASE + SEG_MEM_LIMIT +#define PCI_SEG3_MMIO_MEMBASE FixedPcdGet64 (PcdPciExp4BaseAddr) + +#define PCI_SEG3_DBI_BASE 0x03700000 + +// Segment configuration +#define SEG_CFG_SIZE 0x00001000 +#define SEG_CFG_BUS 0x00000000 +#define SEG_MEM_SIZE 0x40000000 +#define SEG_MEM_LIMIT 0x7fffffff +#define SEG_MEM_BUS 0x40000000 +#define SEG_IO_SIZE 0x00010000 +#define SEG_IO_BUS 0x00000000 +#define PCI_BASE_DIFF 0x800000000 +#define PCI_DBI_SIZE_DIFF 0x100000 +#define PCI_SEG0_PHY_CFG0_BASE PCI_SEG0_MMIO_MEMBASE +#define PCI_SEG0_PHY_CFG1_BASE PCI_SEG0_PHY_CFG0_BASE + SEG_CFG_SIZE +#define PCI_SEG0_PHY_MEM_BASE PCI_SEG0_MMIO64_MIN +#define PCI_SEG0_PHY_IO_BASE PCI_SEG0_MMIO_MEMBASE + SEG_IO_SIZE + +// iATU configuration +#define IATU_VIEWPORT_OFF 0x900 +#define IATU_VIEWPORT_OUTBOUND 0 + +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0 0x904 +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM 0x0 +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_IO 0x2 +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG0 0x4 +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG1 0x5 + +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0 0x908 +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN BIT31 + +#define IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0 0x90C +#define IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0 0x910 +#define IATU_LIMIT_ADDR_OFF_OUTBOUND_0 0x914 +#define IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0 0x918 +#define IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0 0x91C + +#define IATU_REGION_INDEX0 0x0 +#define IATU_REGION_INDEX1 0x1 +#define IATU_REGION_INDEX2 0x2 +#define IATU_REGION_INDEX3 0x3 + +// PCIe Controller configuration +#define NUM_PCIE_CONTROLLER FixedPcdGet32 (PcdNumPciController) +#define PCI_LUT_DBG FixedPcdGet32 (PcdPcieLutDbg) +#define PCI_LUT_BASE FixedPcdGet32 (PcdPcieLutBase) +#define LTSSM_STATE_MASK 0x3f +#define LTSSM_PCIE_L0 0x11 +#define PCI_LINK_CAP 0x7c +#define PCI_LINK_SPEED_MASK 0xf +#define PCI_CLASS_BRIDGE_PCI 0x6040010 +#define PCI_CLASS_DEVICE 0x8 +#define PCI_DBI_RO_WR_EN 0x8bc +#define PCI_BASE_ADDRESS_0 0x10 + +VOID GetSerdesProtocolMaps (UINT64 *); + +BOOLEAN IsSerDesLaneProtocolConfigured (UINT64, UINT16); + +#endif diff --git a/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c b/Silicon/NX= P/Library/PciSegmentLib/PciSegmentLib.c new file mode 100644 index 0000000..acb614d --- /dev/null +++ b/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c @@ -0,0 +1,604 @@ +/** @file + PCI Segment Library for NXP SoCs with multiple RCs + + Copyright 2018 NXP + + This program and the accompanying materials are + licensed and made available under the terms and conditions of + the BSD License which accompanies this distribution. The full + text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include +#include +#include +#include +#include +#include +#include + +typedef enum { + PciCfgWidthUint8 =3D 0, + PciCfgWidthUint16, + PciCfgWidthUint32, + PciCfgWidthMax +} PCI_CFG_WIDTH; + +/** + Assert the validity of a PCI Segment address. + A valid PCI Segment address should not contain 1's in bits 28..31 and 48= ..63 + + @param A The address to validate. + @param M Additional bits to assert to be zero. + +**/ +#define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A,M) \ + ASSERT (((A) & (0xffff0000f0000000ULL | (M))) =3D=3D 0) + +/** + Function to return PCIe Physical Address(PCIe view) or Controller + Address(CPU view) for different RCs + + @param Address Address passed from bus layer. + @param Segment Segment number for Root Complex. + + @return Return PCIe CPU or Controller address. + +**/ +STATIC +UINT64 +PciSegmentLibGetConfigBase ( + IN UINT64 Address, + IN UINT16 Segment + ) +{ + + switch (Segment) { + // Root Complex 1 + case PCI_SEG0_NUM: + // Reading bus number(bits 20-27) + if ((Address >> 20) & 1) { + return PCI_SEG0_MMIO_MEMBASE; + } else { + // On Bus 0 RCs are connected + return PCI_SEG0_DBI_BASE; + } + // Root Complex 2 + case PCI_SEG1_NUM: + // Reading bus number(bits 20-27) + if ((Address >> 20) & 1) { + return PCI_SEG1_MMIO_MEMBASE; + } else { + // On Bus 0 RCs are connected + return PCI_SEG1_DBI_BASE; + } + // Root Complex 3 + case PCI_SEG2_NUM: + // Reading bus number(bits 20-27) + if ((Address >> 20) & 1) { + return PCI_SEG2_MMIO_MEMBASE; + } else { + // On Bus 0 RCs are connected + return PCI_SEG2_DBI_BASE; + } + // Root Complex 4 + case PCI_SEG3_NUM: + // Reading bus number(bits 20-27) + if ((Address >> 20) & 1) { + return PCI_SEG3_MMIO_MEMBASE; + } else { + // On Bus 0 RCs are connected + return PCI_SEG3_DBI_BASE; + } + default: + return 0; + } + +} + +/** + Internal worker function to read a PCI configuration register. + + @param Address The address that encodes the Segment, PCI Bus, Device, + Function and Register. + @param Width The width of data to read + + @return The value read from the PCI configuration register. + +**/ +STATIC +UINT32 +PciSegmentLibReadWorker ( + IN UINT64 Address, + IN PCI_CFG_WIDTH Width + ) +{ + UINT64 Base; + UINT16 Offset; + UINT16 Segment; + + // + // Reading Segment number(47-32) bits in Address + // + Segment =3D (Address >> 32); + // + // Reading Function(12-0) bits in Address + // + Offset =3D (Address & 0xfff ); + + Base =3D PciSegmentLibGetConfigBase (Address, Segment); + + // + // ignore devices > 0 on bus 0 + // + if ((Address & 0xff00000) =3D=3D 0 && (Address & 0xf8000) !=3D 0) { + return MAX_UINT32; + } + + // + // ignore device > 0 on bus 1 + // + if ((Address & 0xfe00000) =3D=3D 0 && (Address & 0xf8000) !=3D 0) { + return MAX_UINT32; + } + + switch (Width) { + case PciCfgWidthUint8: + return MmioRead8 (Base + (UINT8)Offset); + case PciCfgWidthUint16: + return MmioRead16 (Base + (UINT16)Offset); + case PciCfgWidthUint32: + return MmioRead32 (Base + (UINT32)Offset); + default: + ASSERT (FALSE); + } + + return CHAR_NULL; +} + +/** + Internal worker function to writes a PCI configuration register. + + @param Address The address that encodes the Segment, PCI Bus, Device, + Function and Register. + @param Width The width of data to write + @param Data The value to write. + + @return The value written to the PCI configuration register. + +**/ +STATIC +UINT32 +PciSegmentLibWriteWorker ( + IN UINT64 Address, + IN PCI_CFG_WIDTH Width, + IN UINT32 Data + ) +{ + UINT64 Base; + UINT32 Offset; + UINT16 Segment; + + // + // Reading Segment number(47-32 bits) in Address + Segment =3D (Address >> 32); + // + // Reading Function(12-0 bits) in Address + // + Offset =3D (Address & 0xfff ); + + Base =3D PciSegmentLibGetConfigBase (Address, Segment); + + // + // ignore devices > 0 on bus 0 + // + if ((Address & 0xff00000) =3D=3D 0 && (Address & 0xf8000) !=3D 0) { + return Data; + } + + // + // ignore device > 0 on bus 1 + // + if ((Address & 0xfe00000) =3D=3D 0 && (Address & 0xf8000) !=3D 0) { + return MAX_UINT32; + } + + switch (Width) { + case PciCfgWidthUint8: + MmioWrite8 (Base + (UINT8)Offset, Data); + break; + case PciCfgWidthUint16: + MmioWrite16 (Base + (UINT16)Offset, Data); + break; + case PciCfgWidthUint32: + MmioWrite32 (Base + (UINT16)Offset, Data); + break; + default: + ASSERT (FALSE); + } + + return Data; +} + +/** + Register a PCI device so PCI configuration registers may be accessed aft= er + SetVirtualAddressMap(). + + If any reserved bits in Address are set, then ASSERT(). + + @param Address The address that encodes the PCI Bus, D= evice, + Function and Register. + + @retval RETURN_SUCCESS The PCI device was registered for runti= me access. + @retval RETURN_UNSUPPORTED An attempt was made to call this functi= on + after ExitBootServices(). + @retval RETURN_UNSUPPORTED The resources required to access the PC= I device + at runtime could not be mapped. + @retval RETURN_OUT_OF_RESOURCES There are not enough resources availabl= e to + complete the registration. + +**/ +RETURN_STATUS +EFIAPI +PciSegmentRegisterForRuntimeAccess ( + IN UINTN Address + ) +{ + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0); + return RETURN_UNSUPPORTED; +} + +/** + Reads an 8-bit PCI configuration register. + + Reads and returns the 8-bit PCI configuration register specified by Addr= ess. + + If any reserved bits in Address are set, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Device,= Function, + and Register. + + @return The 8-bit PCI configuration register specified by Address. + +**/ +UINT8 +EFIAPI +PciSegmentRead8 ( + IN UINT64 Address + ) +{ + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0); + + return (UINT8) PciSegmentLibReadWorker (Address, PciCfgWidthUint8); +} + +/** + Writes an 8-bit PCI configuration register. + + Writes the 8-bit PCI configuration register specified by Address with th= e value specified by Value. + Value is returned. This function must guarantee that all PCI read and w= rite operations are serialized. + + If any reserved bits in Address are set, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Devic= e, Function, and Register. + @param Value The value to write. + + @return The value written to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciSegmentWrite8 ( + IN UINT64 Address, + IN UINT8 Value + ) +{ + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0); + + return (UINT8) PciSegmentLibWriteWorker (Address, PciCfgWidthUint8, Valu= e); +} + +/** + Reads a 16-bit PCI configuration register. + + Reads and returns the 16-bit PCI configuration register specified by Add= ress. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Device,= Function, and Register. + + @return The 16-bit PCI configuration register specified by Address. + +**/ +UINT16 +EFIAPI +PciSegmentRead16 ( + IN UINT64 Address + ) +{ + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1); + + return (UINT16) PciSegmentLibReadWorker (Address, PciCfgWidthUint16); +} + +/** + Writes a 16-bit PCI configuration register. + + Writes the 16-bit PCI configuration register specified by Address with t= he + value specified by Value. + + Value is returned. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Devic= e, Function, and Register. + @param Value The value to write. + + @return The parameter of Value. + +**/ +UINT16 +EFIAPI +PciSegmentWrite16 ( + IN UINT64 Address, + IN UINT16 Value + ) +{ + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1); + + return (UINT16) PciSegmentLibWriteWorker (Address, PciCfgWidthUint16, Va= lue); +} + +/** + Reads a 32-bit PCI configuration register. + + Reads and returns the 32-bit PCI configuration register specified by Add= ress. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Device,= Function, + and Register. + + @return The 32-bit PCI configuration register specified by Address. + +**/ +UINT32 +EFIAPI +PciSegmentRead32 ( + IN UINT64 Address + ) +{ + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3); + + return PciSegmentLibReadWorker (Address, PciCfgWidthUint32); +} + +/** + Writes a 32-bit PCI configuration register. + + Writes the 32-bit PCI configuration register specified by Address with t= he + value specified by Value. + + Value is returned. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Devic= e, + Function, and Register. + @param Value The value to write. + + @return The parameter of Value. + +**/ +UINT32 +EFIAPI +PciSegmentWrite32 ( + IN UINT64 Address, + IN UINT32 Value + ) +{ + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3); + + return PciSegmentLibWriteWorker (Address, PciCfgWidthUint32, Value); +} + +/** + Reads a range of PCI configuration registers into a caller supplied buff= er. + + Reads the range of PCI configuration registers specified by StartAddress= and + Size into the buffer specified by Buffer. This function only allows the = PCI + configuration registers from a single PCI function to be read. Size is + returned. + + If any reserved bits in StartAddress are set, then ASSERT(). + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). + If Size > 0 and Buffer is NULL, then ASSERT(). + + @param StartAddress The starting address that encodes the PCI Segment,= Bus, + Device, Function and Register. + @param Size The size in bytes of the transfer. + @param Buffer The pointer to a buffer receiving the data read. + + @return Size + +**/ +UINTN +EFIAPI +PciSegmentReadBuffer ( + IN UINT64 StartAddress, + IN UINTN Size, + OUT VOID *Buffer + ) +{ + UINTN ReturnValue; + + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0); + // 0xFFF is used as limit for 4KB config space + ASSERT (((StartAddress & 0xFFF) + Size) <=3D SIZE_4KB); + + if (Size =3D=3D 0) { + return Size; + } + + ASSERT (Buffer !=3D NULL); + + // + // Save Size for return + // + ReturnValue =3D Size; + + if ((StartAddress & BIT0) !=3D 0) { + // + // Read a byte if StartAddress is byte aligned + // + *(volatile UINT8 *)Buffer =3D PciSegmentRead8 (StartAddress); + StartAddress +=3D sizeof (UINT8); + Size -=3D sizeof (UINT8); + Buffer =3D (UINT8*)Buffer + BIT0; + } + + if (Size >=3D sizeof (UINT16) && (StartAddress & BIT1) !=3D 0) { + // + // Read a word if StartAddress is word aligned + // + WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress)); + StartAddress +=3D sizeof (UINT16); + Size -=3D sizeof (UINT16); + Buffer =3D (UINT16*)Buffer + BIT0; + } + + while (Size >=3D sizeof (UINT32)) { + // + // Read as many double words as possible + // + WriteUnaligned32 (Buffer, PciSegmentRead32 (StartAddress)); + StartAddress +=3D sizeof (UINT32); + Size -=3D sizeof (UINT32); + Buffer =3D (UINT32*)Buffer + BIT0; + } + + if (Size >=3D sizeof (UINT16)) { + // + // Read the last remaining word if exist + // + WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress)); + StartAddress +=3D sizeof (UINT16); + Size -=3D sizeof (UINT16); + Buffer =3D (UINT16*)Buffer + BIT0; + } + + if (Size >=3D sizeof (UINT8)) { + // + // Read the last remaining byte if exist + // + *(volatile UINT8 *)Buffer =3D PciSegmentRead8 (StartAddress); + } + + return ReturnValue; +} + + +/** + Copies the data in a caller supplied buffer to a specified range of PCI + configuration space. + + Writes the range of PCI configuration registers specified by StartAddres= s and + Size from the buffer specified by Buffer. This function only allows the = PCI + configuration registers from a single PCI function to be written. Size is + returned. + + If any reserved bits in StartAddress are set, then ASSERT(). + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). + If Size > 0 and Buffer is NULL, then ASSERT(). + + @param StartAddress The starting address that encodes the PCI Segment,= Bus, + Device, Function and Register. + @param Size The size in bytes of the transfer. + @param Buffer The pointer to a buffer containing the data to wri= te. + + @return The parameter of Size. + +**/ +UINTN +EFIAPI +PciSegmentWriteBuffer ( + IN UINT64 StartAddress, + IN UINTN Size, + IN VOID *Buffer + ) +{ + UINTN ReturnValue; + + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0); + // 0xFFF is used as limit for 4KB config space + ASSERT (((StartAddress & 0xFFF) + Size) <=3D SIZE_4KB); + + if (Size =3D=3D 0) { + return Size; + } + + ASSERT (Buffer !=3D NULL); + + // + // Save Size for return + // + ReturnValue =3D Size; + + if ((StartAddress & BIT0) !=3D 0) { + // + // Write a byte if StartAddress is byte aligned + // + PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer); + StartAddress +=3D sizeof (UINT8); + Size -=3D sizeof (UINT8); + Buffer =3D (UINT8*)Buffer + BIT0; + } + + if (Size >=3D sizeof (UINT16) && (StartAddress & BIT1) !=3D 0) { + // + // Write a word if StartAddress is word aligned + // + PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer)); + StartAddress +=3D sizeof (UINT16); + Size -=3D sizeof (UINT16); + Buffer =3D (UINT16*)Buffer + BIT0; + } + + while (Size >=3D sizeof (UINT32)) { + // + // Write as many double words as possible + // + PciSegmentWrite32 (StartAddress, ReadUnaligned32 (Buffer)); + StartAddress +=3D sizeof (UINT32); + Size -=3D sizeof (UINT32); + Buffer =3D (UINT32*)Buffer + BIT0; + } + + if (Size >=3D sizeof (UINT16)) { + // + // Write the last remaining word if exist + // + PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer)); + StartAddress +=3D sizeof (UINT16); + Size -=3D sizeof (UINT16); + Buffer =3D (UINT16*)Buffer + BIT0; + } + + if (Size >=3D sizeof (UINT8)) { + // + // Write the last remaining byte if exist + // + PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer); + } + + return ReturnValue; +} diff --git a/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf b/Silicon/= NXP/Library/PciSegmentLib/PciSegmentLib.inf new file mode 100644 index 0000000..1ac83d4 --- /dev/null +++ b/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf @@ -0,0 +1,41 @@ +## @file +# PCI Segment Library for NXP SoCs with multiple RCs +# +# Copyright 2018 NXP +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may b= e found at +# http://opensource.org/licenses/bsd-license.php. +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +# +## + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D PciSegmentLib + FILE_GUID =3D c9f59261-5a60-4a4c-82f6-1f520442e100 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D PciSegmentLib + +[Sources] + PciSegmentLib.c + +[Packages] + MdePkg/MdePkg.dec + Silicon/NXP/NxpQoriqLs.dec + +[LibraryClasses] + BaseLib + DebugLib + IoLib + PcdLib + +[Pcd] + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseAddr --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun May 5 06:05:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" From: Vabhav Implement the library that exposes the PCIe root complexes to the generic PCI host bridge driver,Putting SoC Specific low level init code for the RCs. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Vabhav Signed-off-by: Meenakshi Aggarwal --- .../Library/PciHostBridgeLib/PciHostBridgeLib.c | 618 +++++++++++++++++= ++++ .../Library/PciHostBridgeLib/PciHostBridgeLib.inf | 50 ++ 2 files changed, 668 insertions(+) create mode 100644 Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c create mode 100644 Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.i= nf diff --git a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c b/Sili= con/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c new file mode 100644 index 0000000..e6f9b7c --- /dev/null +++ b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c @@ -0,0 +1,618 @@ +/** @file + PCI Host Bridge Library instance for NXP SoCs + + Copyright 2018 NXP + + This program and the accompanying materials are licensed and made availa= ble + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WI= THOUT + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#pragma pack(1) +typedef struct { + ACPI_HID_DEVICE_PATH AcpiDevicePath; + EFI_DEVICE_PATH_PROTOCOL EndDevicePath; +} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH; +#pragma pack () + +STATIC CONST EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[]= =3D { + { + { + { + ACPI_DEVICE_PATH, + ACPI_DP, + { + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH)), + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8) + } + }, + EISA_PNP_ID (0x0A08), // PCI Express + PCI_SEG0_NUM + }, + + { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { + END_DEVICE_PATH_LENGTH, + 0 + } + } + }, + { + { + { + ACPI_DEVICE_PATH, + ACPI_DP, + { + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH)), + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8) + } + }, + EISA_PNP_ID (0x0A08), // PCI Express + PCI_SEG1_NUM + }, + + { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { + END_DEVICE_PATH_LENGTH, + 0 + } + } + }, + { + { + { + ACPI_DEVICE_PATH, + ACPI_DP, + { + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH)), + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8) + } + }, + EISA_PNP_ID (0x0A08), // PCI Express + PCI_SEG2_NUM + }, + + { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { + END_DEVICE_PATH_LENGTH, + 0 + } + } + }, + { + { + { + ACPI_DEVICE_PATH, + ACPI_DP, + { + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH)), + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8) + } + }, + EISA_PNP_ID (0x0A08), // PCI Express + PCI_SEG3_NUM + }, + + { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { + END_DEVICE_PATH_LENGTH, + 0 + } + } + } +}; + +STATIC +GLOBAL_REMOVE_IF_UNREFERENCED +CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] =3D { + L"Mem", L"I/O", L"Bus" +}; + +#define PCI_ALLOCATION_ATTRIBUTES EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PM= EM | \ + EFI_PCI_HOST_BRIDGE_MEM64_DECODE + +#define PCI_SUPPORT_ATTRIBUTES EFI_PCI_ATTRIBUTE_ISA_IO_16 | \ + EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_= IO | \ + EFI_PCI_ATTRIBUTE_VGA_MEMORY | \ + EFI_PCI_ATTRIBUTE_VGA_IO_16 | \ + EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16 + +PCI_ROOT_BRIDGE mPciRootBridges[] =3D { + { + PCI_SEG0_NUM, // Segment + PCI_SUPPORT_ATTRIBUTES, // Supports + PCI_SUPPORT_ATTRIBUTES, // Attributes + FALSE, // DmaAbove4G + FALSE, // NoExtendedConfigSpace + FALSE, // ResourceAssigned + PCI_ALLOCATION_ATTRIBUTES, // AllocationAttributes + { PCI_SEG0_BUSNUM_MIN, + PCI_SEG0_BUSNUM_MAX }, // Bus + { PCI_SEG0_PORTIO_MIN, + PCI_SEG0_PORTIO_MAX }, // Io + { PCI_SEG0_MMIO32_MIN, + PCI_SEG0_MMIO32_MAX }, // Mem + { PCI_SEG0_MMIO64_MIN, + PCI_SEG0_MMIO64_MAX }, // MemAbove4G + { MAX_UINT64, 0x0 }, // PMem + { MAX_UINT64, 0x0 }, // PMemAbove4G + (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[PCI_SEG0_NUM] + }, { + PCI_SEG1_NUM, // Segment + PCI_SUPPORT_ATTRIBUTES, // Supports + PCI_SUPPORT_ATTRIBUTES, // Attributes + FALSE, // DmaAbove4G + FALSE, // NoExtendedConfigSpace + FALSE, // ResourceAssigned + PCI_ALLOCATION_ATTRIBUTES, // AllocationAttributes + { PCI_SEG1_BUSNUM_MIN, + PCI_SEG1_BUSNUM_MAX }, // Bus + { PCI_SEG1_PORTIO_MIN, + PCI_SEG1_PORTIO_MAX }, // Io + { PCI_SEG1_MMIO32_MIN, + PCI_SEG1_MMIO32_MAX }, // Mem + { PCI_SEG1_MMIO64_MIN, + PCI_SEG1_MMIO64_MAX }, // MemAbove4G + { MAX_UINT64, 0x0 }, // PMem + { MAX_UINT64, 0x0 }, // PMemAbove4G + (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[PCI_SEG1_NUM] + }, { + PCI_SEG2_NUM, // Segment + PCI_SUPPORT_ATTRIBUTES, // Supports + PCI_SUPPORT_ATTRIBUTES, // Attributes + FALSE, // DmaAbove4G + FALSE, // NoExtendedConfigSpace + FALSE, // ResourceAssigned + PCI_ALLOCATION_ATTRIBUTES, // AllocationAttributes + { PCI_SEG2_BUSNUM_MIN, + PCI_SEG2_BUSNUM_MAX }, // Bus + { PCI_SEG2_PORTIO_MIN, + PCI_SEG2_PORTIO_MAX }, // Io + { PCI_SEG2_MMIO32_MIN, + PCI_SEG2_MMIO32_MAX }, // Mem + { PCI_SEG2_MMIO64_MIN, + PCI_SEG2_MMIO64_MAX }, // MemAbove4G + { MAX_UINT64, 0x0 }, // PMem + { MAX_UINT64, 0x0 }, // PMemAbove4G + (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[PCI_SEG2_NUM] + }, { + PCI_SEG3_NUM, // Segment + PCI_SUPPORT_ATTRIBUTES, // Supports + PCI_SUPPORT_ATTRIBUTES, // Attributes + FALSE, // DmaAbove4G + FALSE, // NoExtendedConfigSpace + FALSE, // ResourceAssigned + PCI_ALLOCATION_ATTRIBUTES, // AllocationAttributes + { PCI_SEG3_BUSNUM_MIN, + PCI_SEG3_BUSNUM_MAX }, // Bus + { PCI_SEG3_PORTIO_MIN, + PCI_SEG3_PORTIO_MAX }, // Io + { PCI_SEG3_MMIO32_MIN, + PCI_SEG3_MMIO32_MAX }, // Mem + { PCI_SEG3_MMIO64_MIN, + PCI_SEG3_MMIO64_MAX }, // MemAbove4G + { MAX_UINT64, 0x0 }, // PMem + { MAX_UINT64, 0x0 }, // PMemAbove4G + (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[PCI_SEG3_NUM] + } +}; + +/** + Function to set-up iATU outbound window for PCIe controller + + @param Dbi Address of PCIe host controller. + @param Idx Index of iATU outbound window. + @param Type Type(Cfg0/Cfg1/Mem/IO) of iATU outbound window. + @param Phys PCIe controller phy address for outbound window. + @param BusAdr PCIe controller bus address for outbound window. + @param Pcie Size of PCIe controller space(Cfg0/Cfg1/Mem/IO). + +**/ +STATIC +VOID +PcieIatuOutboundSet ( + IN EFI_PHYSICAL_ADDRESS Dbi, + IN UINT32 Idx, + IN UINT32 Type, + IN UINT64 Phys, + IN UINT64 BusAddr, + IN UINT64 Size + ) +{ + MmioWrite32 (Dbi + IATU_VIEWPORT_OFF, + (UINT32)(IATU_VIEWPORT_OUTBOUND | Idx)); + MmioWrite32 (Dbi + IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0, + (UINT32)Phys); + MmioWrite32 (Dbi + IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0, + (UINT32)(Phys >> 32)); + MmioWrite32 (Dbi + IATU_LIMIT_ADDR_OFF_OUTBOUND_0, + (UINT32)(Phys + Size - BIT0)); + MmioWrite32 (Dbi + IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0, + (UINT32)BusAddr); + MmioWrite32 (Dbi + IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0, + (UINT32)(BusAddr >> 32)); + MmioWrite32 (Dbi + IATU_REGION_CTRL_1_OFF_OUTBOUND_0, + (UINT32)Type); + MmioWrite32 (Dbi + IATU_REGION_CTRL_2_OFF_OUTBOUND_0, + IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN); +} + +/** + Function to check PCIe controller LTSSM state + + @param Pcie Address of PCIe host controller. + +**/ +STATIC +INTN +PcieLinkState ( + IN EFI_PHYSICAL_ADDRESS Pcie + ) +{ + UINT32 State; + + // + // Reading PCIe controller LTSSM state + // + if (FeaturePcdGet (PcdPciLutBigEndian)) { + State =3D BeMmioRead32 ((UINTN)Pcie + PCI_LUT_BASE + PCI_LUT_DBG) & + LTSSM_STATE_MASK; + } else { + State =3D MmioRead32 ((UINTN)Pcie + PCI_LUT_BASE + PCI_LUT_DBG) & + LTSSM_STATE_MASK; + } + + if (State < LTSSM_PCIE_L0) { + DEBUG ((DEBUG_INFO," Pcie Link error. LTSSM=3D0x%2x\n", State)); + return EFI_SUCCESS; + } + + return EFI_UNSUPPORTED; +} + +/** + Helper function to check PCIe link state + + @param Pcie Address of PCIe host controller. + +**/ +STATIC +INTN +PcieLinkUp ( + IN EFI_PHYSICAL_ADDRESS Pcie + ) +{ + INTN State; + UINT32 Cap; + + State =3D PcieLinkState (Pcie); + if (State) { + return State; + } + + // + // Try to download speed to gen1 + // + Cap =3D MmioRead32 ((UINTN)Pcie + PCI_LINK_CAP); + MmioWrite32 ((UINTN)Pcie + PCI_LINK_CAP, (UINT32)(Cap & (~PCI_LINK_SPEED= _MASK)) | BIT0); + State =3D PcieLinkState (Pcie); + if (State) { + return State; + } + + MmioWrite32 ((UINTN)Pcie + PCI_LINK_CAP, Cap); + + return EFI_SUCCESS; +} + +/** + This function checks whether PCIe is enabled or not + depending upon SoC serdes protocol map + + @param PcieNum PCIe number. + + @return The PCIe number enabled in map. + @return FALSE PCIe number is disabled in map. + +**/ +STATIC +BOOLEAN +IsPcieNumEnabled( + IN UINTN PcieNum + ) +{ + UINT64 SerDes1ProtocolMap; + + SerDes1ProtocolMap =3D 0x0; + + // + // Reading serdes map + // + GetSerdesProtocolMaps (&SerDes1ProtocolMap); + + // + // Verify serdes line is configured in the map + // + if (PcieNum < NUM_PCIE_CONTROLLER) { + return IsSerDesLaneProtocolConfigured (SerDes1ProtocolMap, (PcieNum + = BIT0)); + } else { + DEBUG ((DEBUG_ERROR, "Device not supported\n")); + } + + return FALSE; +} + +/** + Function to set-up iATU outbound window for PCIe controller + + @param Pcie Address of PCIe host controller + @param Cfg0Base PCIe controller phy address Type0 Configuration Space. + @param Cfg1Base PCIe controller phy address Type1 Configuration Space. + @param MemBase PCIe controller phy address Memory Space. + @param IoBase PCIe controller phy address IO Space. +**/ +STATIC +VOID +PcieSetupAtu ( + IN EFI_PHYSICAL_ADDRESS Pcie, + IN EFI_PHYSICAL_ADDRESS Cfg0Base, + IN EFI_PHYSICAL_ADDRESS Cfg1Base, + IN EFI_PHYSICAL_ADDRESS MemBase, + IN EFI_PHYSICAL_ADDRESS IoBase + ) +{ + + // + // iATU : OUTBOUND WINDOW 0 : CFG0 + // + PcieIatuOutboundSet (Pcie, IATU_REGION_INDEX0, + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG0, + Cfg0Base, + SEG_CFG_BUS, + SEG_CFG_SIZE); + + // + // iATU : OUTBOUND WINDOW 1 : CFG1 + PcieIatuOutboundSet (Pcie, IATU_REGION_INDEX1, + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG1, + Cfg1Base, + SEG_CFG_BUS, + SEG_CFG_SIZE); + // + // iATU 2 : OUTBOUND WINDOW 2 : MEM + // + PcieIatuOutboundSet (Pcie, IATU_REGION_INDEX2, + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM, + MemBase, + SEG_MEM_BUS, + SEG_MEM_SIZE); + + // + // iATU 3 : OUTBOUND WINDOW 3: IO + // + PcieIatuOutboundSet (Pcie, IATU_REGION_INDEX3, + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_IO, + IoBase, + SEG_IO_BUS, + SEG_IO_SIZE); + +} + +/** + Helper function to set-up PCIe controller + + @param Pcie Address of PCIe host controller + @param Cfg0Base PCIe controller phy address Type0 Configuration Space. + @param Cfg1Base PCIe controller phy address Type1 Configuration Space. + @param MemBase PCIe controller phy address Memory Space. + @param IoBase PCIe controller phy address IO Space. + +**/ +STATIC +VOID +PcieSetupCntrl ( + IN EFI_PHYSICAL_ADDRESS Pcie, + IN EFI_PHYSICAL_ADDRESS Cfg0Base, + IN EFI_PHYSICAL_ADDRESS Cfg1Base, + IN EFI_PHYSICAL_ADDRESS MemBase, + IN EFI_PHYSICAL_ADDRESS IoBase + ) +{ + // + // iATU outbound set-up + // + PcieSetupAtu (Pcie, Cfg0Base, Cfg1Base, MemBase, IoBase); + + // + // program correct class for RC + // + MmioWrite32 ((UINTN)Pcie + PCI_BASE_ADDRESS_0, (BIT0 - BIT0)); + MmioWrite32 ((UINTN)Pcie + PCI_DBI_RO_WR_EN, (UINT32)BIT0); + MmioWrite32 ((UINTN)Pcie + PCI_CLASS_DEVICE, (UINT32)PCI_CLASS_BRIDGE_PC= I); + MmioWrite32 ((UINTN)Pcie + PCI_DBI_RO_WR_EN, (UINT32)(BIT0 - BIT0)); +} + +/** + Return all the root bridge instances in an array. + + @param Count Return the count of root bridge instances. + + @return All the root bridge instances in an array. + +**/ +PCI_ROOT_BRIDGE * +EFIAPI +PciHostBridgeGetRootBridges ( + OUT UINTN *Count + ) +{ + UINTN Idx; + INTN LinkUp; + UINT64 PciPhyMemAddr[NUM_PCIE_CONTROLLER]; + UINT64 PciPhyCfg0Addr[NUM_PCIE_CONTROLLER]; + UINT64 PciPhyCfg1Addr[NUM_PCIE_CONTROLLER]; + UINT64 PciPhyIoAddr[NUM_PCIE_CONTROLLER]; + UINT64 Regs[NUM_PCIE_CONTROLLER]; + + *Count =3D 0; + + // + // Filling local array for + // PCIe controller Physical address space for Cfg0,Cfg1,Mem,IO + // Host Contoller address + // + for (Idx =3D 0; Idx < NUM_PCIE_CONTROLLER; Idx++) { + PciPhyMemAddr[Idx] =3D PCI_SEG0_PHY_MEM_BASE + (PCI_BASE_DIFF * Idx); + PciPhyCfg0Addr[Idx] =3D PCI_SEG0_PHY_CFG0_BASE + (PCI_BASE_DIFF * Idx); + PciPhyCfg1Addr[Idx] =3D PCI_SEG0_PHY_CFG1_BASE + (PCI_BASE_DIFF * Idx); + PciPhyIoAddr [Idx] =3D PCI_SEG0_PHY_IO_BASE + (PCI_BASE_DIFF * Idx); + Regs[Idx] =3D PCI_SEG0_DBI_BASE + (PCI_DBI_SIZE_DIFF * Idx); + } + + for (Idx =3D 0; Idx < NUM_PCIE_CONTROLLER; Idx++) { + // + // Verify PCIe controller is enabled in Soc Serdes Map + // + if (!IsPcieNumEnabled (Idx)) { + DEBUG ((DEBUG_ERROR, "PCIE%d is disabled\n", (Idx + BIT0))); + // + // Continue with other PCIe controller + // + continue; + } + DEBUG ((DEBUG_INFO, "PCIE%d is Enabled\n", Idx + BIT0)); + + // + // Verify PCIe controller LTSSM state + // + LinkUp =3D PcieLinkUp(Regs[Idx]); + if (!LinkUp) { + // + // Let the user know there's no PCIe link + // + DEBUG ((DEBUG_INFO,"no link, regs @ 0x%lx\n", Regs[Idx])); + // + // Continue with other PCIe controller + // + continue; + } + DEBUG ((DEBUG_INFO, "PCIE%d Passed Linkup Phase\n", Idx + BIT0)); + + // + // Function to set up address translation unit outbound window for + // PCIe Controller + // + PcieSetupCntrl (Regs[Idx], + PciPhyCfg0Addr[Idx], + PciPhyCfg1Addr[Idx], + PciPhyMemAddr[Idx], + PciPhyIoAddr[Idx]); + *Count +=3D BIT0; + break; + } + + if (*Count =3D=3D 0) { + return NULL; + } else { + return &mPciRootBridges[Idx]; + } +} + +/** + Free the root bridge instances array returned from PciHostBridgeGetRootB= ridges(). + + @param Bridges The root bridge instances array. + @param Count The count of the array. +**/ +VOID +EFIAPI +PciHostBridgeFreeRootBridges ( + PCI_ROOT_BRIDGE *Bridges, + UINTN Count + ) +{ +} + +/** + Inform the platform that the resource conflict happens. + + @param HostBridgeHandle Handle of the Host Bridge. + @param Configuration Pointer to PCI I/O and PCI memory resource + descriptors. The Configuration contains the reso= urces + for all the root bridges. The resource for each = root + bridge is terminated with END descriptor and an + additional END is appended indicating the end of= the + entire resources. The resource descriptor field + values follow the description in + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL + .SubmitResources(). + +**/ +VOID +EFIAPI +PciHostBridgeResourceConflict ( + EFI_HANDLE HostBridgeHandle, + VOID *Configuration + ) +{ + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor; + UINTN RootBridgeIndex; + DEBUG ((DEBUG_ERROR, "PciHostBridge: Resource conflict happens!\n")); + + RootBridgeIndex =3D 0; + Descriptor =3D (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration; + while (Descriptor->Desc =3D=3D ACPI_ADDRESS_SPACE_DESCRIPTOR) { + DEBUG ((DEBUG_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++)); + for (; Descriptor->Desc =3D=3D ACPI_ADDRESS_SPACE_DESCRIPTOR; Descript= or++) { + ASSERT (Descriptor->ResType < + ARRAY_SIZE (mPciHostBridgeLibAcpiAddressSpaceTypeStr)); + DEBUG ((DEBUG_ERROR, " %s: Length/Alignment =3D 0x%lx / 0x%lx\n", + mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType= ], + Descriptor->AddrLen, Descriptor->AddrRangeMax + )); + if (Descriptor->ResType =3D=3D ACPI_ADDRESS_SPACE_TYPE_MEM) { + DEBUG ((DEBUG_ERROR, " Granularity/SpecificFlag =3D %ld / %02x= %s\n", + Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag, + ((Descriptor->SpecificFlag & + EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETC= HABLE + ) !=3D 0) ? L" (Prefetchable)" : L"" + )); + } + } + // + // Skip the END descriptor for root bridge + // + ASSERT (Descriptor->Desc =3D=3D ACPI_END_TAG_DESCRIPTOR); + Descriptor =3D (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)( + (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1 + ); + } + + return; +} diff --git a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf b/Si= licon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf new file mode 100644 index 0000000..f08ac60 --- /dev/null +++ b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf @@ -0,0 +1,50 @@ +## @file +# PCI Host Bridge Library instance for NXP ARM SOC +# +# Copyright 2018 NXP +# +# This program and the accompanying materials are licensed and made avail= able +# under the terms and conditions of the BSD License which accompanies this +# distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR +# IMPLIED. +# +# +## + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D PciHostBridgeLib + FILE_GUID =3D f4c99bcc-5c95-49ad-b0f3-fc5b611dc9c1 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D PciHostBridgeLib + +[Sources] + PciHostBridgeLib.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/NXP/NxpQoriqLs.dec + Silicon/NXP/Chassis/Chassis2/Chassis2.dec + +[LibraryClasses] + DebugLib + DevicePathLib + MemoryAllocationLib + PcdLib + SocLib + UefiBootServicesTableLib + +[Pcd] + gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian + gNxpQoriqLsTokenSpaceGuid.PcdNumPciController + gNxpQoriqLsTokenSpaceGuid.PcdPcieLutBase + gNxpQoriqLsTokenSpaceGuid.PcdPcieLutDbg + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseAddr --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun May 5 06:05:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" From: Vabhav NXP SOC has mutiple PCIe RCs,Adding respective implementation of EFI_CPU_IO2_PROTOCOL to provide Memory Space Read/Write functions used by generic Host Bridge Driver including correct value for the translation offset during MMIO accesses Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Vabhav Signed-off-by: Meenakshi Aggarwal --- Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c | 529 ++++++++++++++++++= ++++ Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf | 48 ++ 2 files changed, 577 insertions(+) create mode 100644 Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c create mode 100644 Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf diff --git a/Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c b/Silicon/NXP/= Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c new file mode 100644 index 0000000..b5fb72c --- /dev/null +++ b/Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c @@ -0,0 +1,529 @@ +/** @file + Produces the CPU I/O 2 Protocol. + + Copyright (c) 2009 - 2012, Intel Corporation. All rights reserved.
+ Copyright (c) 2016, Linaro Ltd. All rights reserved.
+ Copyright 2018 NXP + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include +#include +#include +#include +#include +#include +#include + +#define MAX_IO_PORT_ADDRESS PCI_SEG2_PORTIO_MAX + +// +// Handle for the CPU I/O 2 Protocol +// +STATIC EFI_HANDLE mHandle; + +// +// Lookup table for increment values based on transfer widths +// +STATIC CONST UINT8 mInStride[] =3D { + 1, // EfiCpuIoWidthUint8 + 2, // EfiCpuIoWidthUint16 + 4, // EfiCpuIoWidthUint32 + 8, // EfiCpuIoWidthUint64 + 0, // EfiCpuIoWidthFifoUint8 + 0, // EfiCpuIoWidthFifoUint16 + 0, // EfiCpuIoWidthFifoUint32 + 0, // EfiCpuIoWidthFifoUint64 + 1, // EfiCpuIoWidthFillUint8 + 2, // EfiCpuIoWidthFillUint16 + 4, // EfiCpuIoWidthFillUint32 + 8 // EfiCpuIoWidthFillUint64 +}; + +// +// Lookup table for increment values based on transfer widths +// +STATIC CONST UINT8 mOutStride[] =3D { + 1, // EfiCpuIoWidthUint8 + 2, // EfiCpuIoWidthUint16 + 4, // EfiCpuIoWidthUint32 + 8, // EfiCpuIoWidthUint64 + 1, // EfiCpuIoWidthFifoUint8 + 2, // EfiCpuIoWidthFifoUint16 + 4, // EfiCpuIoWidthFifoUint32 + 8, // EfiCpuIoWidthFifoUint64 + 0, // EfiCpuIoWidthFillUint8 + 0, // EfiCpuIoWidthFillUint16 + 0, // EfiCpuIoWidthFillUint32 + 0 // EfiCpuIoWidthFillUint64 +}; + +/** + Check parameters to a CPU I/O 2 Protocol service request. + + The I/O operations are carried out exactly as requested. The caller is r= esponsible + for satisfying any alignment and I/O width restrictions that a PI System= on a + platform might require. For example on some platforms, width requests of + EfiCpuIoWidthUint64 do not work. + + @param[in] MmioOperation TRUE for an MMIO operation, FALSE for I/O Port= operation. + @param[in] Width Signifies the width of the I/O or Memory opera= tion. + @param[in] Address The base address of the I/O operation. + @param[in] Count The number of I/O operations to perform. The n= umber of + bytes moved is Width size * Count, starting at= Address. + @param[in] Buffer For read operations, the destination buffer to= store the results. + For write operations, the source buffer from w= hich to write data. + + @retval EFI_SUCCESS The parameters for this request pass the = checks. + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given W= idth. + @retval EFI_UNSUPPORTED The address range specified by Address, W= idth, + and Count is not valid for this PI system. + +**/ +STATIC +EFI_STATUS +CpuIoCheckParameter ( + IN BOOLEAN MmioOperation, + IN EFI_CPU_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN VOID *Buffer + ) +{ + UINT64 MaxCount; + UINT64 Limit; + + // + // Check to see if Buffer is NULL + // + if (Buffer =3D=3D NULL) { + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + // + // Check to see if Width is in the valid range + // + if ((UINT32)Width >=3D EfiCpuIoWidthMaximum) { + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + // + // For FIFO type, the target address won't increase during the access, + // so treat Count as 1 + // + if (Width >=3D EfiCpuIoWidthFifoUint8 && Width <=3D EfiCpuIoWidthFifoUin= t64) { + Count =3D 1; + } + + // + // Check to see if Width is in the valid range for I/O Port operations + // + Width =3D (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03); + if (!MmioOperation && (Width =3D=3D EfiCpuIoWidthUint64)) { + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + // + // Check to see if Address is aligned + // + if ((Address & (UINT64)(mInStride[Width] - 1)) !=3D 0) { + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + + // + // Check to see if any address associated with this transfer exceeds the= maximum + // allowed address. The maximum address implied by the parameters passe= d in is + // Address + Size * Count. If the following condition is met, then the = transfer + // is not supported. + // + // Address + Size * Count > (MmioOperation ? MAX_ADDRESS : MAX_IO_POR= T_ADDRESS) + 1 + // + // Since MAX_ADDRESS can be the maximum integer value supported by the C= PU and Count + // can also be the maximum integer value supported by the CPU, this range + // check must be adjusted to avoid all oveflow conditions. + // + Limit =3D (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS); + if (Count =3D=3D 0) { + if (Address > Limit) { + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + } else { + MaxCount =3D RShiftU64 (Limit, Width); + if (MaxCount < (Count - 1)) { + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + if (Address > LShiftU64 (MaxCount - Count + 1, Width)) { + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + } + + // + // Check to see if Buffer is aligned + // + if (((UINTN)Buffer & ((MIN (sizeof (UINTN), mInStride[Width]) - 1))) != =3D 0) { + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + + return EFI_SUCCESS; +} + +/** + Reads memory-mapped registers. + + The I/O operations are carried out exactly as requested. The caller is r= esponsible + for satisfying any alignment and I/O width restrictions that a PI System= on a + platform might require. For example on some platforms, width requests of + EfiCpuIoWidthUint64 do not work. + + If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, + or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for + each of the Count operations that is performed. + + If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, + EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is + incremented for each of the Count operations that is performed. The read= or + write operation is performed Count times on the same Address. + + If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, + EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is + incremented for each of the Count operations that is performed. The read= or + write operation is performed Count times from the first element of Buffe= r. + + @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance. + @param[in] Width Signifies the width of the I/O or Memory operation. + @param[in] Address The base address of the I/O operation. + @param[in] Count The number of I/O operations to perform. The number= of + bytes moved is Width size * Count, starting at Addr= ess. + @param[out] Buffer For read operations, the destination buffer to stor= e the results. + For write operations, the source buffer from which = to write data. + + @retval EFI_SUCCESS The data was read from or written to the = PI system. + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given W= idth. + @retval EFI_UNSUPPORTED The address range specified by Address, W= idth, + and Count is not valid for this PI system. + +**/ +STATIC +EFI_STATUS +EFIAPI +CpuMemoryServiceRead ( + IN EFI_CPU_IO2_PROTOCOL *This, + IN EFI_CPU_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + OUT VOID *Buffer + ) +{ + EFI_STATUS Status; + UINT8 InStride; + UINT8 OutStride; + EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth; + UINT8 *Uint8Buffer; + + Status =3D CpuIoCheckParameter (TRUE, Width, Address, Count, Buffer); + if (EFI_ERROR (Status)) { + return Status; + } + + if ((Address >=3D PCI_SEG0_MMIO32_MIN) && + (Address <=3D PCI_SEG0_MMIO32_MAX)) { + Address +=3D PCI_SEG0_MMIO_MEMBASE; + } else if ((Address >=3D PCI_SEG1_MMIO32_MIN) && + (Address <=3D PCI_SEG1_MMIO32_MAX)) { + Address +=3D PCI_SEG1_MMIO_MEMBASE; + } else if ((Address >=3D PCI_SEG2_MMIO32_MIN) && + (Address <=3D PCI_SEG2_MMIO32_MAX)) { + Address +=3D PCI_SEG2_MMIO_MEMBASE; + } else if ((Address >=3D PCI_SEG3_MMIO32_MIN) && + (Address <=3D PCI_SEG3_MMIO32_MAX)) { + Address +=3D PCI_SEG3_MMIO_MEMBASE; + } else { + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + // + // Select loop based on the width of the transfer + // + InStride =3D mInStride[Width]; + OutStride =3D mOutStride[Width]; + OperationWidth =3D (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03); + for (Uint8Buffer =3D Buffer; Count > 0; Address +=3D InStride, Uint8Buff= er +=3D OutStride, Count--) { + if (OperationWidth =3D=3D EfiCpuIoWidthUint8) { + *Uint8Buffer =3D MmioRead8 ((UINTN)Address); + } else if (OperationWidth =3D=3D EfiCpuIoWidthUint16) { + *((UINT16 *)Uint8Buffer) =3D MmioRead16 ((UINTN)Address); + } else if (OperationWidth =3D=3D EfiCpuIoWidthUint32) { + *((UINT32 *)Uint8Buffer) =3D MmioRead32 ((UINTN)Address); + } else if (OperationWidth =3D=3D EfiCpuIoWidthUint64) { + *((UINT64 *)Uint8Buffer) =3D MmioRead64 ((UINTN)Address); + } + } + return EFI_SUCCESS; +} + +/** + Writes memory-mapped registers. + + The I/O operations are carried out exactly as requested. The caller is r= esponsible + for satisfying any alignment and I/O width restrictions that a PI System= on a + platform might require. For example on some platforms, width requests of + EfiCpuIoWidthUint64 do not work. + + If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, + or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for + each of the Count operations that is performed. + + If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, + EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is + incremented for each of the Count operations that is performed. The read= or + write operation is performed Count times on the same Address. + + If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, + EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is + incremented for each of the Count operations that is performed. The read= or + write operation is performed Count times from the first element of Buffe= r. + + @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance. + @param[in] Width Signifies the width of the I/O or Memory operation. + @param[in] Address The base address of the I/O operation. + @param[in] Count The number of I/O operations to perform. The number= of + bytes moved is Width size * Count, starting at Addr= ess. + @param[in] Buffer For read operations, the destination buffer to stor= e the results. + For write operations, the source buffer from which = to write data. + + @retval EFI_SUCCESS The data was read from or written to the = PI system. + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given W= idth. + @retval EFI_UNSUPPORTED The address range specified by Address, W= idth, + and Count is not valid for this PI system. + +**/ +STATIC +EFI_STATUS +EFIAPI +CpuMemoryServiceWrite ( + IN EFI_CPU_IO2_PROTOCOL *This, + IN EFI_CPU_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN VOID *Buffer + ) +{ + EFI_STATUS Status; + UINT8 InStride; + UINT8 OutStride; + EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth; + UINT8 *Uint8Buffer; + + Status =3D CpuIoCheckParameter (TRUE, Width, Address, Count, Buffer); + if (EFI_ERROR (Status)) { + return Status; + } + + if ((Address >=3D PCI_SEG0_MMIO32_MIN) && + (Address <=3D PCI_SEG0_MMIO32_MAX)) { + Address +=3D PCI_SEG0_MMIO_MEMBASE; + } else if ((Address >=3D PCI_SEG1_MMIO32_MIN) && + (Address <=3D PCI_SEG1_MMIO32_MAX)) { + Address +=3D PCI_SEG1_MMIO_MEMBASE; + } else if ((Address >=3D PCI_SEG2_MMIO32_MIN) && + (Address <=3D PCI_SEG2_MMIO32_MAX)) { + Address +=3D PCI_SEG2_MMIO_MEMBASE; + } else if ((Address >=3D PCI_SEG3_MMIO32_MIN) && + (Address <=3D PCI_SEG3_MMIO32_MAX)) { + Address +=3D PCI_SEG3_MMIO_MEMBASE; + } else { + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + // + // Select loop based on the width of the transfer + // + InStride =3D mInStride[Width]; + OutStride =3D mOutStride[Width]; + OperationWidth =3D (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03); + for (Uint8Buffer =3D Buffer; Count > 0; Address +=3D InStride, Uint8Buff= er +=3D OutStride, Count--) { + if (OperationWidth =3D=3D EfiCpuIoWidthUint8) { + MmioWrite8 ((UINTN)Address, *Uint8Buffer); + } else if (OperationWidth =3D=3D EfiCpuIoWidthUint16) { + MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer)); + } else if (OperationWidth =3D=3D EfiCpuIoWidthUint32) { + MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer)); + } else if (OperationWidth =3D=3D EfiCpuIoWidthUint64) { + MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer)); + } + } + return EFI_SUCCESS; +} + +/** + Reads I/O registers. + + The I/O operations are carried out exactly as requested. The caller is r= esponsible + for satisfying any alignment and I/O width restrictions that a PI System= on a + platform might require. For example on some platforms, width requests of + EfiCpuIoWidthUint64 do not work. + + If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, + or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for + each of the Count operations that is performed. + + If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, + EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is + incremented for each of the Count operations that is performed. The read= or + write operation is performed Count times on the same Address. + + If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, + EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is + incremented for each of the Count operations that is performed. The read= or + write operation is performed Count times from the first element of Buffe= r. + + @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance. + @param[in] Width Signifies the width of the I/O or Memory operation. + @param[in] Address The base address of the I/O operation. + @param[in] Count The number of I/O operations to perform. The number= of + bytes moved is Width size * Count, starting at Addr= ess. + @param[out] Buffer For read operations, the destination buffer to stor= e the results. + For write operations, the source buffer from which = to write data. + + @retval EFI_SUCCESS The data was read from or written to the = PI system. + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given W= idth. + @retval EFI_UNSUPPORTED The address range specified by Address, W= idth, + and Count is not valid for this PI system. + +**/ +STATIC +EFI_STATUS +EFIAPI +CpuIoServiceRead ( + IN EFI_CPU_IO2_PROTOCOL *This, + IN EFI_CPU_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + OUT VOID *Buffer + ) +{ + return EFI_SUCCESS; +} + +/** + Write I/O registers. + + The I/O operations are carried out exactly as requested. The caller is r= esponsible + for satisfying any alignment and I/O width restrictions that a PI System= on a + platform might require. For example on some platforms, width requests of + EfiCpuIoWidthUint64 do not work. + + If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, + or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for + each of the Count operations that is performed. + + If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, + EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is + incremented for each of the Count operations that is performed. The read= or + write operation is performed Count times on the same Address. + + If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, + EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is + incremented for each of the Count operations that is performed. The read= or + write operation is performed Count times from the first element of Buffe= r. + + @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance. + @param[in] Width Signifies the width of the I/O or Memory operation. + @param[in] Address The base address of the I/O operation. + @param[in] Count The number of I/O operations to perform. The number= of + bytes moved is Width size * Count, starting at Addr= ess. + @param[in] Buffer For read operations, the destination buffer to stor= e the results. + For write operations, the source buffer from which = to write data. + + @retval EFI_SUCCESS The data was read from or written to the = PI system. + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given W= idth. + @retval EFI_UNSUPPORTED The address range specified by Address, W= idth, + and Count is not valid for this PI system. + +**/ +STATIC +EFI_STATUS +EFIAPI +CpuIoServiceWrite ( + IN EFI_CPU_IO2_PROTOCOL *This, + IN EFI_CPU_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN VOID *Buffer + ) +{ + return EFI_SUCCESS; +} + +// +// CPU I/O 2 Protocol instance +// +STATIC EFI_CPU_IO2_PROTOCOL mCpuIo2 =3D { + { + CpuMemoryServiceRead, + CpuMemoryServiceWrite + }, + { + CpuIoServiceRead, + CpuIoServiceWrite + } +}; + + +/** + The user Entry Point for module CpuIo2Dxe. The user code starts with thi= s function. + + @param[in] ImageHandle The firmware allocated handle for the EFI imag= e. + @param[in] SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS The entry point is executed successfully. + @retval other Some error occurs when executing this entry po= int. + +**/ +EFI_STATUS +EFIAPI +PciCpuIo2Initialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiCpuIo2ProtocolGuid); + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &mHandle, + &gEfiCpuIo2ProtocolGuid, &mCpuIo2, + NULL + ); + ASSERT_EFI_ERROR (Status); + + return Status; +} diff --git a/Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf b/Silicon/NX= P/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf new file mode 100644 index 0000000..25a1db1 --- /dev/null +++ b/Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf @@ -0,0 +1,48 @@ +## @file +# Produces the CPU I/O 2 Protocol by using the services of the I/O Librar= y. +# +# Copyright 2018 NXP +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BS= D License +# which accompanies this distribution. The full text of the license may b= e found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. +# +## + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D PciCpuIo2Dxe + FILE_GUID =3D 7bff18d7-9aae-434b-9c06-f10a7e157eac + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D PciCpuIo2Initialize + +[Sources] + PciCpuIo2Dxe.c + +[Packages] + MdePkg/MdePkg.dec + Silicon/NXP/NxpQoriqLs.dec + +[LibraryClasses] + BaseLib + DebugLib + IoLib + UefiBootServicesTableLib + UefiDriverEntryPoint + +[Pcd] + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseAddr + +[Protocols] + gEfiCpuIo2ProtocolGuid ## PRODUCES + +[Depex] + TRUE --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun May 5 06:05:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Meenakshi Aggarwal LS1043A PCIe compilation and update firmware device, description and declaration files.Defining Embedded Package PCD which should be at least 20 for 64K PCIe IO size required for CPU hob during PEI phase to Add IO space post PEI phase. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Vabhav Signed-off-by: Meenakshi Aggarwal --- Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 16 ++++++++++++= ++++ Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 9 +++++++++ .../LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf | 2 ++ .../LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c | 6 ++++++ Platform/NXP/NxpQoriqLs.dsc | 7 +++++++ Silicon/NXP/LS1043A/LS1043A.dsc | 4 ++++ Silicon/NXP/NxpQoriqLs.dec | 10 ++++++++++ 7 files changed, 54 insertions(+) diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS= 1043aRdbPkg/LS1043aRdbPkg.dsc index b2b514e..8cbaf88 100644 --- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc @@ -42,6 +42,8 @@ BoardLib|Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.inf FpgaLib|Platform/NXP/LS1043aRdbPkg/Library/FpgaLib/FpgaLib.inf NorFlashLib|Silicon/NXP/Library/NorFlashLib/NorFlashLib.inf + PciSegmentLib|Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf + PciHostBridgeLib|Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.i= nf =20 [PcdsFixedAtBuild.common] =20 @@ -79,6 +81,13 @@ gNxpQoriqLsTokenSpaceGuid.PcdFlashDeviceBase64|0x060000000 gNxpQoriqLsTokenSpaceGuid.PcdFlashReservedRegionBase64|0x60300000 =20 + # + # PCI PCDs. + # + gNxpQoriqLsTokenSpaceGuid.PcdPciDebug|FALSE + gNxpQoriqLsTokenSpaceGuid.PcdPcieLutBase|0x10000 + gNxpQoriqLsTokenSpaceGuid.PcdPcieLutDbg|0x7FC + ##########################################################################= ###### # # Components Section - list of all EDK II Modules needed by this Platform @@ -99,4 +108,11 @@ Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf =20 + Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf + MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf { + + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8010004F + } + MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + ## diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf b/Platform/NXP/LS= 1043aRdbPkg/LS1043aRdbPkg.fdf index 6b5b63f..7993bf1 100644 --- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf @@ -130,6 +130,13 @@ READ_LOCK_STATUS =3D TRUE INF Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf =20 # + # PCI + # + INF Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf + INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf + INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + + # # Network modules # INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf @@ -154,6 +161,8 @@ READ_LOCK_STATUS =3D TRUE INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf !endif =20 + INF ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf + # # FAT filesystem + GPT/MBR partitioning # diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.= inf b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf index 7feac56..f2c8b66 100644 --- a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf +++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf @@ -65,3 +65,5 @@ gNxpQoriqLsTokenSpaceGuid.PcdDram3Size gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize + gNxpQoriqLsTokenSpaceGuid.PcdRomBaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdRomSize diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c= b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c index 64c5612..1ef3292 100644 --- a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c +++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c @@ -67,6 +67,12 @@ ArmPlatformGetVirtualMemoryMap ( VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdCcsrSize); VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; =20 + // ROM Space + VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdRomBaseAd= dr); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdRomBaseAddr= ); + VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdRomSize); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + // IFC region 1 // // A-009241 : Unaligned write transactions to IFC may result in corrup= tion of data diff --git a/Platform/NXP/NxpQoriqLs.dsc b/Platform/NXP/NxpQoriqLs.dsc index 5987cd6..f5bb2e9 100644 --- a/Platform/NXP/NxpQoriqLs.dsc +++ b/Platform/NXP/NxpQoriqLs.dsc @@ -244,6 +244,8 @@ =20 gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 =20 + gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|20 + # # Optional feature to help prevent EFI memory map fragments # Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob @@ -409,4 +411,9 @@ !endif #$(NO_SHELL_PROFILES) } =20 + # + # TFTP Shell Command + # + ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf + ## diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc b/Silicon/NXP/LS1043A/LS1043A.= dsc index a4eb117..f3220fa 100644 --- a/Silicon/NXP/LS1043A/LS1043A.dsc +++ b/Silicon/NXP/LS1043A/LS1043A.dsc @@ -64,6 +64,9 @@ gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x40000000 gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x20000000 gNxpQoriqLsTokenSpaceGuid.PcdIfcBaseAddr|0x1530000 + gNxpQoriqLsTokenSpaceGuid.PcdNumPciController|3 + gNxpQoriqLsTokenSpaceGuid.PcdRomBaseAddr|0x00000000 + gNxpQoriqLsTokenSpaceGuid.PcdRomSize|0x00100000 =20 # # Big Endian IPs @@ -71,5 +74,6 @@ gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|TRUE gNxpQoriqLsTokenSpaceGuid.PcdWdogBigEndian|TRUE gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian|TRUE + gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian|TRUE =20 ## diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec index 3cb476d..a3508b5 100644 --- a/Silicon/NXP/NxpQoriqLs.dec +++ b/Silicon/NXP/NxpQoriqLs.dec @@ -79,6 +79,16 @@ gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0|UINT64|0x00000129 gNxpQoriqLsTokenSpaceGuid.PcdDramMemSize|0x0|UINT64|0x0000012A gNxpQoriqLsTokenSpaceGuid.PcdIfcBaseAddr|0x0|UINT64|0x0000012B + gNxpQoriqLsTokenSpaceGuid.PcdRomBaseAddr|0x0|UINT64|0x0000012C + gNxpQoriqLsTokenSpaceGuid.PcdRomSize|0x0|UINT64|0x0000012D + + # + # PCI PCDs + # + gNxpQoriqLsTokenSpaceGuid.PcdPcieLutBase|0x0|UINT32|0x000001D0 + gNxpQoriqLsTokenSpaceGuid.PcdPcieLutDbg|0x0|UINT32|0x000001D1 + gNxpQoriqLsTokenSpaceGuid.PcdPciDebug|FALSE|BOOLEAN|0x000001D2 + gNxpQoriqLsTokenSpaceGuid.PcdNumPciController|0|UINT32|0x000001D3 =20 # # IFC PCDs --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun May 5 06:05:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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VI1PR04MB1008; 6:ZcIAJwBC/ARIs2/oQxtLojlPmrSXbgedOoMpiaSWkiOli1EsGk6t9UI9QiQP0E5e6rGLkxwEQs/QD30pApNMHrUxgBzoJd4UW1Mvha4poJgzxeXGVm3a1bbqd4MezxtUbkxblyZwaT5te7hDakref5qgMThiMF5y6OgXh/ZS5I0+Tby3sJEXrv3TSig5KAkW+qmqn2bfLuQNONAokeLKYN853DLQRr2CyEewM18dLnD/tXIDc9yoqYLIve/xDeHgrfRbEYBbQhaqiYKJwMkwSjrxc1q/zgAqEcSu0zHmcjq/YfM1+pVUxZ0Qis3FQEqSHUtl1YPuzHwA6wMErbxVmmYoiUjWhaTCr0L3ioqhDb8=; 5:kCzUGzQfej25Z3HkVSpdoTNxM805Ru21UsTsTYn1GPi9SEN8KAtJVKDT64IaSs0MEm/ZgolD5zKmZOJkWadfiX1QeJzSjQNjDU96vfpuG6zJ51m0nydU7JdIsTR8BTnr1sIKn/lHPlyjValxbJJcgibwEPpLezQgY7bOmy5i3jU=; 24:7ohCVVuOX3UWo3Ysfc0EsGZPHxzfOTjoEfpKSmpHJbEPL0+e2414dc0MhjQhdCmfa0SNmMplUdbf/nm8MCY/hliUpYJOeDCiq+krpAopaRs=; 7:1wE2ik/MwZkEJFf3zc27JGNxqRO0BHQ8ezKeXH8sjtJsWZQgQYtGpDjSZnIAtn9Qq39gCbZwoKHTAmdO0wO3nLcHOX+VNcc4KJnynpBWCJTKWa1aAPptvYXOyI6gbAYfcZmpZLtwxOBEYRBf3tSiRvs54gcn9LGrmFFW8up3q1gCmkOy8tyVp2uOyNFrzuZquu7lgIOt/ViicZxJO4Da1Ox0a3mLluLQouGNoC+OEWG19ZHvG6PGxmASUek//XJy SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Feb 2018 08:55:23.7487 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 07b00d4f-8798-46a5-2400-08d5751b05e7 X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB1008 Subject: [edk2] [PATCH edk2-platforms 36/39] DWC3 : Add DWC3 USB controller initialization driver. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Meenakshi Aggarwal Add support of DWC3 controller driver which Performs DWC3 controller initialization and Register itself as NonDiscoverableMmioDevice Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Meenakshi Aggarwal --- Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.c | 219 +++++++++++++++++++++++= ++++ Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.h | 142 +++++++++++++++++ Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf | 48 ++++++ Silicon/NXP/NxpQoriqLs.dec | 5 + 4 files changed, 414 insertions(+) create mode 100644 Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.c create mode 100644 Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.h create mode 100644 Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf diff --git a/Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.c b/Silicon/NXP/Drive= rs/UsbHcdInitDxe/UsbHcd.c new file mode 100644 index 0000000..b08e19c --- /dev/null +++ b/Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.c @@ -0,0 +1,219 @@ +/** @file + + Copyright 2017 NXP + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include +#include +#include +#include + +#include "UsbHcd.h" + +STATIC +VOID +XhciSetBeatBurstLength ( + IN UINTN UsbReg + ) +{ + Dwc3 *Dwc3Reg; + + Dwc3Reg =3D (VOID *)(UsbReg + DWC3_REG_OFFSET); + + MmioAndThenOr32 ((UINTN)&Dwc3Reg->GSBusCfg0, ~USB3_ENABLE_BEAT_BURST_MAS= K, + USB3_ENABLE_BEAT_BURST); + MmioOr32 ((UINTN)&Dwc3Reg->GSBusCfg1, USB3_SET_BEAT_BURST_LIMIT); + + return; +} + +STATIC +VOID +Dwc3SetFladj ( + IN Dwc3 *Dwc3Reg, + IN UINT32 Val + ) +{ + MmioOr32 ((UINTN)&Dwc3Reg->GFLAdj, GFLADJ_30MHZ_REG_SEL | + GFLADJ_30MHZ(Val)); +} + +VOID +Dwc3SetMode ( + IN Dwc3 *Dwc3Reg, + IN UINT32 Mode + ) +{ + MmioAndThenOr32 ((UINTN)&Dwc3Reg->GCtl, + ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)), + DWC3_GCTL_PRTCAPDIR(Mode)); +} + +STATIC +VOID +Dwc3CoreSoftReset ( + IN Dwc3 *Dwc3Reg + ) +{ + MmioOr32 ((UINTN)&Dwc3Reg->GCtl, DWC3_GCTL_CORESOFTRESET); + MmioOr32 ((UINTN)&Dwc3Reg->GUsb3PipeCtl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST= ); + MmioOr32 ((UINTN)&Dwc3Reg->GUsb2PhyCfg, DWC3_GUSB2PHYCFG_PHYSOFTRST); + MmioAnd32 ((UINTN)&Dwc3Reg->GUsb3PipeCtl[0], ~DWC3_GUSB3PIPECTL_PHYSOFTR= ST); + MmioAnd32 ((UINTN)&Dwc3Reg->GUsb2PhyCfg, ~DWC3_GUSB2PHYCFG_PHYSOFTRST); + MmioAnd32 ((UINTN)&Dwc3Reg->GCtl, ~DWC3_GCTL_CORESOFTRESET); + + return; +} + +STATIC +EFI_STATUS +Dwc3CoreInit ( + IN Dwc3 *Dwc3Reg + ) +{ + UINT32 Revision; + UINT32 Reg; + UINTN Dwc3Hwparams1; + + Revision =3D MmioRead32 ((UINTN)&Dwc3Reg->GSnpsId); + // + // This should read as 0x5533, ascii of U3(DWC_usb3) followed by revisio= n number + // + if ((Revision & DWC3_GSNPSID_MASK) !=3D DWC3_SYNOPSIS_ID) { + DEBUG ((DEBUG_ERROR,"This is not a DesignWare USB3 DRD Core.\n")); + return EFI_NOT_FOUND; + } + + Dwc3CoreSoftReset (Dwc3Reg); + + Reg =3D MmioRead32 ((UINTN)&Dwc3Reg->GCtl); + Reg &=3D ~DWC3_GCTL_SCALEDOWN_MASK; + Reg &=3D ~DWC3_GCTL_DISSCRAMBLE; + + Dwc3Hwparams1 =3D MmioRead32 ((UINTN)&Dwc3Reg->GHwParams1); + + if (DWC3_GHWPARAMS1_EN_PWROPT(Dwc3Hwparams1) =3D=3D DWC3_GHWPARAMS1_EN_P= WROPT_CLK) { + Reg &=3D ~DWC3_GCTL_DSBLCLKGTNG; + } else { + DEBUG ((DEBUG_ERROR,"No power optimization available.\n")); + } + + if ((Revision & DWC3_RELEASE_MASK) < DWC3_RELEASE_190a) { + Reg |=3D DWC3_GCTL_U2RSTECN; + } + + MmioWrite32 ((UINTN)&Dwc3Reg->GCtl, Reg); + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +XhciCoreInit ( + IN UINTN UsbReg + ) +{ + EFI_STATUS Status; + Dwc3 *Dwc3Reg; + + Dwc3Reg =3D (VOID *)(UsbReg + DWC3_REG_OFFSET); + + Status =3D Dwc3CoreInit (Dwc3Reg); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Dwc3CoreInit Failed for controller 0x%x (0x%x) \= n", + UsbReg, Status)); + return Status; + } + + Dwc3SetMode (Dwc3Reg, DWC3_GCTL_PRTCAP_HOST); + + Dwc3SetFladj (Dwc3Reg, GFLADJ_30MHZ_DEFAULT); + + return Status; +} + +STATIC +EFI_STATUS +EFIAPI +InitializeUsbController ( + IN UINTN UsbReg + ) +{ + EFI_STATUS Status; + + Status =3D XhciCoreInit (UsbReg); + + if (EFI_ERROR (Status)) { + return Status; + } + + // + // Change beat burst and outstanding pipelined transfers requests + // + XhciSetBeatBurstLength (UsbReg); + + return Status; +} + +/** + The Entry Point of module. It follows the standard UEFI driver model. + + @param[in] ImageHandle The firmware allocated handle for the EFI image. + @param[in] SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS The entry point is executed successfully. + @retval other Some error occurs when executing this entry poi= nt. + +**/ +EFI_STATUS +EFIAPI +InitializeUsbHcd ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + UINT32 NumUsbController; + UINT32 ControllerAddr; + + Status =3D EFI_SUCCESS; + NumUsbController =3D PcdGet32 (PcdNumUsbController); + + while (NumUsbController) { + NumUsbController--; + ControllerAddr =3D PcdGet32 (PcdUsbBaseAddr) + + (NumUsbController * PcdGet32 (PcdUsbSize)); + + Status =3D InitializeUsbController (ControllerAddr); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "USB Controller initialization Failed for %d (0= x%x)\n", + ControllerAddr, Status)); + continue; + } + + Status =3D RegisterNonDiscoverableMmioDevice ( + NonDiscoverableDeviceTypeXhci, + NonDiscoverableDeviceDmaTypeNonCoherent, + NULL, + NULL, + 1, + ControllerAddr, PcdGet32 (PcdUsbSize) + ); + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Failed to register USB device (0x%x) with erro= r 0x%x \n", + ControllerAddr, Status)); + } + } + + return Status; +} diff --git a/Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.h b/Silicon/NXP/Drive= rs/UsbHcdInitDxe/UsbHcd.h new file mode 100644 index 0000000..3237f5d --- /dev/null +++ b/Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.h @@ -0,0 +1,142 @@ +/** @file + + Copyright 2017 NXP + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#ifndef __USB_HCD__ +#define __USB_HCD__ + +/* Global constants */ +#define DWC3_GSNPSID_MASK 0xffff0000 +#define DWC3_SYNOPSIS_ID 0x55330000 +#define DWC3_RELEASE_MASK 0xffff +#define DWC3_REG_OFFSET 0xC100 +#define DWC3_RELEASE_190a 0x190a + +/* Global Configuration Register */ +#define DWC3_GCTL_U2RSTECN BIT(16) +#define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12) +#define DWC3_GCTL_PRTCAP_HOST 1 +#define DWC3_GCTL_PRTCAP_OTG 3 +#define DWC3_GCTL_CORESOFTRESET BIT(11) +#define DWC3_GCTL_SCALEDOWN(n) ((n) << 4) +#define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3) +#define DWC3_GCTL_DISSCRAMBLE BIT(3) +#define DWC3_GCTL_DSBLCLKGTNG BIT(0) + +/* Global HWPARAMS1 Register */ +#define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24) +#define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1 + +/* Global USB2 PHY Configuration Register */ +#define DWC3_GUSB2PHYCFG_PHYSOFTRST BIT(31) + +/* Global USB3 PIPE Control Register */ +#define DWC3_GUSB3PIPECTL_PHYSOFTRST BIT(31) + +/* Global Frame Length Adjustment Register */ +#define GFLADJ_30MHZ_REG_SEL BIT(7) +#define GFLADJ_30MHZ(n) ((n) & 0x3f) +#define GFLADJ_30MHZ_DEFAULT 0x20 + +/* Default to the FSL XHCI defines */ +#define USB3_ENABLE_BEAT_BURST 0xF +#define USB3_ENABLE_BEAT_BURST_MASK 0xFF +#define USB3_SET_BEAT_BURST_LIMIT 0xF00 + +typedef struct { + UINT32 GEvntAdrLo; + UINT32 GEvntAdrHi; + UINT32 GEvntSiz; + UINT32 GEvntCount; +} GEventBuffer; + +typedef struct { + UINT32 DDepCmdPar2; + UINT32 DDepCmdPar1; + UINT32 DDepCmdPar0; + UINT32 DDepCmd; +} DPhysicalEndpoint; + +typedef struct { + UINT32 GSBusCfg0; + UINT32 GSBusCfg1; + UINT32 GTxThrCfg; + UINT32 GRxThrCfg; + UINT32 GCtl; + UINT32 Res1; + UINT32 GSts; + UINT32 Res2; + UINT32 GSnpsId; + UINT32 GGpio; + UINT32 GUid; + UINT32 GUctl; + UINT64 GBusErrAddr; + UINT64 GPrtbImap; + UINT32 GHwParams0; + UINT32 GHwParams1; + UINT32 GHwParams2; + UINT32 GHwParams3; + UINT32 GHwParams4; + UINT32 GHwParams5; + UINT32 GHwParams6; + UINT32 GHwParams7; + UINT32 GDbgFifoSpace; + UINT32 GDbgLtssm; + UINT32 GDbgLnmcc; + UINT32 GDbgBmu; + UINT32 GDbgLspMux; + UINT32 GDbgLsp; + UINT32 GDbgEpInfo0; + UINT32 GDbgEpInfo1; + UINT64 GPrtbImapHs; + UINT64 GPrtbImapFs; + UINT32 Res3[28]; + UINT32 GUsb2PhyCfg[16]; + UINT32 GUsb2I2cCtl[16]; + UINT32 GUsb2PhyAcc[16]; + UINT32 GUsb3PipeCtl[16]; + UINT32 GTxFifoSiz[32]; + UINT32 GRxFifoSiz[32]; + GEventBuffer GEvntBuf[32]; + UINT32 GHwParams8; + UINT32 Res4[11]; + UINT32 GFLAdj; + UINT32 Res5[51]; + UINT32 DCfg; + UINT32 DCtl; + UINT32 DEvten; + UINT32 DSts; + UINT32 DGCmdPar; + UINT32 DGCmd; + UINT32 Res6[2]; + UINT32 DAlepena; + UINT32 Res7[55]; + DPhysicalEndpoint DPhyEpCmd[32]; + UINT32 Res8[128]; + UINT32 OCfg; + UINT32 OCtl; + UINT32 OEvt; + UINT32 OEvtEn; + UINT32 OSts; + UINT32 Res9[3]; + UINT32 AdpCfg; + UINT32 AdpCtl; + UINT32 AdpEvt; + UINT32 AdpEvten; + UINT32 BcCfg; + UINT32 Res10; + UINT32 BcEvt; + UINT32 BcEvten; +} Dwc3; + +#endif diff --git a/Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf b/Silicon/NXP/Dri= vers/UsbHcdInitDxe/UsbHcd.inf new file mode 100644 index 0000000..cefb8bd --- /dev/null +++ b/Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf @@ -0,0 +1,48 @@ +# UsbHcd.inf +# +# Copyright 2017 NXP +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may b= e found +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +# + +[Defines] + INF_VERSION =3D 0x0001000A + BASE_NAME =3D UsbHcdDxe + FILE_GUID =3D 196e7c2a-37b2-4b85-8683-718588952449 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D InitializeUsbHcd + +[Sources.common] + UsbHcd.c + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/NXP/NxpQoriqLs.dec + +[LibraryClasses] + BaseLib + BaseMemoryLib + DebugLib + IoLib + MemoryAllocationLib + NonDiscoverableDeviceRegistrationLib + UefiBootServicesTableLib + UefiDriverEntryPoint + +[FixedPcd] + gNxpQoriqLsTokenSpaceGuid.PcdNumUsbController + gNxpQoriqLsTokenSpaceGuid.PcdUsbBaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdUsbSize + +[Depex] + TRUE diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec index a3508b5..90e9957 100644 --- a/Silicon/NXP/NxpQoriqLs.dec +++ b/Silicon/NXP/NxpQoriqLs.dec @@ -83,6 +83,11 @@ gNxpQoriqLsTokenSpaceGuid.PcdRomSize|0x0|UINT64|0x0000012D =20 # + # USB PCDs + # + gNxpQoriqLsTokenSpaceGuid.PcdNumUsbController|0|UINT32|0x00000170 + + # # PCI PCDs # gNxpQoriqLsTokenSpaceGuid.PcdPcieLutBase|0x0|UINT32|0x000001D0 --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun May 5 06:05:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" From: Meenakshi Aggarwal Enable support of USB drives on ls2088 board. LS2088 has DWC3 controller Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Meenakshi Aggarwal --- Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc | 1 + Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf | 13 +++++++++++++ Platform/NXP/NxpQoriqLs.dsc | 12 ++++++++++++ Silicon/NXP/LS2088A/LS2088A.dsc | 1 + 4 files changed, 27 insertions(+) diff --git a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc b/Platform/NXP/LS= 2088aRdbPkg/LS2088aRdbPkg.dsc index 60449b5..4d32ea5 100755 --- a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc +++ b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc @@ -114,3 +114,4 @@ ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf + Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf diff --git a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf b/Platform/NXP/LS= 2088aRdbPkg/LS2088aRdbPkg.fdf index 785f88b..8688d85 100644 --- a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf +++ b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf @@ -151,6 +151,19 @@ READ_LOCK_STATUS =3D TRUE INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf !endif =20 + INF MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciD= eviceDxe.inf + + # + # USB Support + # + INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf + INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf + INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf + INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf + INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + + INF Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf + # # FAT filesystem + GPT/MBR partitioning # diff --git a/Platform/NXP/NxpQoriqLs.dsc b/Platform/NXP/NxpQoriqLs.dsc index f5bb2e9..18e8cde 100644 --- a/Platform/NXP/NxpQoriqLs.dsc +++ b/Platform/NXP/NxpQoriqLs.dsc @@ -99,6 +99,7 @@ VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf + NonDiscoverableDeviceRegistrationLib|MdeModulePkg/Library/NonDiscoverabl= eDeviceRegistrationLib/NonDiscoverableDeviceRegistrationLib.inf =20 [LibraryClasses.common.SEC] PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf @@ -367,6 +368,17 @@ !endif =20 # + # USB Support + # + MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf + MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf + MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf + MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf + MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + + MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDevic= eDxe.inf + + # # FAT filesystem + GPT/MBR partitioning # MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf diff --git a/Silicon/NXP/LS2088A/LS2088A.dsc b/Silicon/NXP/LS2088A/LS2088A.= dsc index 2cff40f..0d8fd82 100644 --- a/Silicon/NXP/LS2088A/LS2088A.dsc +++ b/Silicon/NXP/LS2088A/LS2088A.dsc @@ -68,5 +68,6 @@ gNxpQoriqLsTokenSpaceGuid.PcdI2cSize|0x10000 gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|4 gNxpQoriqLsTokenSpaceGuid.PcdIfcBaseAddr|0x02240000 + gNxpQoriqLsTokenSpaceGuid.PcdNumUsbController|2 =20 ## --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun May 5 06:05:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" From: Vabhav Compilation: Update the fdf, dsc and dec files. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Vabhav --- Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc | 15 +++++++++++= ++++ Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf | 9 +++++++++ .../LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf | 2 ++ .../NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c | 6 ++++++ Silicon/NXP/LS1046A/LS1046A.dsc | 3 +++ 5 files changed, 35 insertions(+) diff --git a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc b/Platform/NXP/LS= 1046aRdbPkg/LS1046aRdbPkg.dsc index 36002d5..231207d 100644 --- a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc +++ b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc @@ -41,6 +41,8 @@ IfcLib|Silicon/NXP/Library/IfcLib/IfcLib.inf BoardLib|Platform/NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.inf FpgaLib|Platform/NXP/LS1046aRdbPkg/Library/FpgaLib/FpgaLib.inf + PciSegmentLib|Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf + PciHostBridgeLib|Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.i= nf =20 [PcdsFixedAtBuild.common] =20 @@ -65,6 +67,7 @@ gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|TRUE gNxpQoriqLsTokenSpaceGuid.PcdWdogBigEndian|TRUE gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian|TRUE + gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian|TRUE =20 # # I2C controller Pcds @@ -77,6 +80,12 @@ gNxpQoriqLsTokenSpaceGuid.PcdI2cSlaveAddress|0x51 gNxpQoriqLsTokenSpaceGuid.PcdI2cSpeed|100000 =20 + # + # PCI PCDs. + # + gNxpQoriqLsTokenSpaceGuid.PcdPciDebug|FALSE + gNxpQoriqLsTokenSpaceGuid.PcdPcieLutBase|0x80000 + gNxpQoriqLsTokenSpaceGuid.PcdPcieLutDbg|0x407FC ##########################################################################= ###### # # Components Section - list of all EDK II Modules needed by this Platform @@ -90,5 +99,11 @@ =20 Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf + Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf + MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf { + + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8010004F + } + MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf =20 ## diff --git a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf b/Platform/NXP/LS= 1046aRdbPkg/LS1046aRdbPkg.fdf index 834e3a4..3351a06 100644 --- a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf +++ b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf @@ -123,6 +123,13 @@ READ_LOCK_STATUS =3D TRUE INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf =20 # + # PCI + # + INF Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf + INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf + INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + + # # Network modules # INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf @@ -147,6 +154,8 @@ READ_LOCK_STATUS =3D TRUE INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf !endif =20 + INF ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf + # # FAT filesystem + GPT/MBR partitioning # diff --git a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.= inf b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf index 49b57fc..5e09757 100644 --- a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf +++ b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf @@ -42,6 +42,8 @@ gArmTokenSpaceGuid.PcdArmPrimaryCore gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize + gNxpQoriqLsTokenSpaceGuid.PcdRomBaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdRomSize gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr diff --git a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c= b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c index 64c5612..1ef3292 100644 --- a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c +++ b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c @@ -67,6 +67,12 @@ ArmPlatformGetVirtualMemoryMap ( VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdCcsrSize); VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; =20 + // ROM Space + VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdRomBaseAd= dr); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdRomBaseAddr= ); + VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdRomSize); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + // IFC region 1 // // A-009241 : Unaligned write transactions to IFC may result in corrup= tion of data diff --git a/Silicon/NXP/LS1046A/LS1046A.dsc b/Silicon/NXP/LS1046A/LS1046A.= dsc index 9f87028..59a6150 100644 --- a/Silicon/NXP/LS1046A/LS1046A.dsc +++ b/Silicon/NXP/LS1046A/LS1046A.dsc @@ -64,5 +64,8 @@ gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x40000000 gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x20000000 gNxpQoriqLsTokenSpaceGuid.PcdIfcBaseAddr|0x1530000 + gNxpQoriqLsTokenSpaceGuid.PcdNumPciController|3 + gNxpQoriqLsTokenSpaceGuid.PcdRomBaseAddr|0x00000000 + gNxpQoriqLsTokenSpaceGuid.PcdRomSize|0x00100000 =20 ## --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun May 5 06:05:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" From: Vabhav Compilation: Update the fdf, dsc and dec files. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Vabhav --- Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc | 17 +++++++++++++= ++++ Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf | 9 +++++++++ .../Library/PlatformLib/ArmPlatformLib.inf | 2 ++ .../LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c | 6 ++++++ Silicon/NXP/LS2088A/LS2088A.dsc | 3 +++ 5 files changed, 37 insertions(+) diff --git a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc b/Platform/NXP/LS= 2088aRdbPkg/LS2088aRdbPkg.dsc index 4d32ea5..1ae55d4 100755 --- a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc +++ b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc @@ -43,6 +43,8 @@ BoardLib|Platform/NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.inf FpgaLib|Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.inf NorFlashLib|Silicon/NXP/Library/NorFlashLib/NorFlashLib.inf + PciSegmentLib|Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf + PciHostBridgeLib|Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.i= nf =20 [PcdsFixedAtBuild.common] =20 @@ -97,6 +99,13 @@ gNxpQoriqLsTokenSpaceGuid.PcdFlashDeviceBase64|0x580000000 gNxpQoriqLsTokenSpaceGuid.PcdFlashReservedRegionBase64|0x580300000 =20 + # + # PCI PCDs. + # + gNxpQoriqLsTokenSpaceGuid.PcdPciDebug|FALSE + gNxpQoriqLsTokenSpaceGuid.PcdPcieLutBase|0x80000 + gNxpQoriqLsTokenSpaceGuid.PcdPcieLutDbg|0x407FC + ##########################################################################= ###### # # Components Section - list of all EDK II Modules needed by this Platform @@ -115,3 +124,11 @@ Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf + Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf + MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf { + + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8010004F + } + MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + + ## diff --git a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf b/Platform/NXP/LS= 2088aRdbPkg/LS2088aRdbPkg.fdf index 8688d85..35a79bd 100644 --- a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf +++ b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf @@ -127,6 +127,13 @@ READ_LOCK_STATUS =3D TRUE INF Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf =20 # + # PCI + # + INF Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf + INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf + INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + + # # Network modules # INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf @@ -153,6 +160,8 @@ READ_LOCK_STATUS =3D TRUE =20 INF MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciD= eviceDxe.inf =20 + INF ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf + # # USB Support # diff --git a/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.= inf b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf index f5e5abd..0b836a8 100644 --- a/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf +++ b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf @@ -44,6 +44,8 @@ gArmTokenSpaceGuid.PcdArmPrimaryCore gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize + gNxpQoriqLsTokenSpaceGuid.PcdRomBaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdRomSize gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr diff --git a/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c= b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c index ccb49f6..8b2145b 100644 --- a/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c +++ b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c @@ -80,6 +80,12 @@ ArmPlatformGetVirtualMemoryMap ( VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdCcsrSize); VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; =20 + // ROM Space + VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdRomBaseAd= dr); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdRomBaseAddr= ); + VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdRomSize); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + // IFC region 1 // // A-009241 : Unaligned write transactions to IFC may result in corrup= tion of data diff --git a/Silicon/NXP/LS2088A/LS2088A.dsc b/Silicon/NXP/LS2088A/LS2088A.= dsc index 0d8fd82..831edea 100644 --- a/Silicon/NXP/LS2088A/LS2088A.dsc +++ b/Silicon/NXP/LS2088A/LS2088A.dsc @@ -69,5 +69,8 @@ gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|4 gNxpQoriqLsTokenSpaceGuid.PcdIfcBaseAddr|0x02240000 gNxpQoriqLsTokenSpaceGuid.PcdNumUsbController|2 + gNxpQoriqLsTokenSpaceGuid.PcdNumPciController|4 + gNxpQoriqLsTokenSpaceGuid.PcdRomBaseAddr|0x00000000 + gNxpQoriqLsTokenSpaceGuid.PcdRomSize|0x00100000 =20 ## --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel