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Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR03MB2694 Subject: [edk2] [PATCH 3/4] Platform/NXP: Add support for ArmPlatformLib X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: multipart/mixed; boundary="===============1189107970882970158==" Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 --===============1189107970882970158== Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch adds support of adding ArmPlatformLib for NXP LS1046ARDB board Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Vabhav --- .../Library/PlatformLib/ArmPlatformLib.c | 106 ++++++++++++ .../Library/PlatformLib/ArmPlatformLib.inf | 70 ++++++++ .../Library/PlatformLib/NxpQoriqLsHelper.S | 39 +++++ .../Library/PlatformLib/NxpQoriqLsMem.c | 181 +++++++++++++++++= ++++ 4 files changed, 396 insertions(+) create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatf= ormLib.c create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatf= ormLib.inf create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriq= LsHelper.S create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriq= LsMem.c diff --git a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.= c b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.c new file mode 100644 index 0000000..e2b645f --- /dev/null +++ b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.c @@ -0,0 +1,106 @@ +/** ArmPlatformLib.c +* +* Contains board initialization functions. +* +* Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoard.c +* +* Copyright (c) 2011-2012, ARM Limited. All rights reserved. +* Copyright 2017 NXP +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the B= SD License +* which accompanies this distribution. The full text of the license may = be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#include +#include +#include +#include +#include + +extern VOID SocInit(VOID); + +/** + Return the current Boot Mode + + This function returns the boot reason on the platform + +**/ +EFI_BOOT_MODE +ArmPlatformGetBootMode ( + VOID + ) +{ + return BOOT_WITH_FULL_CONFIGURATION; +} + +/** + Placeholder for Platform Initialization +**/ +RETURN_STATUS +ArmPlatformInitialize ( + IN UINTN MpId + ) +{ + SocInit(); + return RETURN_SUCCESS; +} + +ARM_CORE_INFO LS1046aMpCoreInfoCTA72x4[] =3D { + { + // Cluster 0, Core 0 + 0x0, 0x0, + + // MP Core MailBox Set/Get/Clear Addresses and Clear Value + (EFI_PHYSICAL_ADDRESS)0, + (EFI_PHYSICAL_ADDRESS)0, + (EFI_PHYSICAL_ADDRESS)0, + (UINT64)0xFFFFFFFF + }, +}; + +EFI_STATUS +PrePeiCoreGetMpCoreInfo ( + OUT UINTN *CoreCount, + OUT ARM_CORE_INFO **ArmCoreTable + ) +{ + *CoreCount =3D sizeof(LS1046aMpCoreInfoCTA72x4) / sizeof(ARM_CORE_INF= O); + *ArmCoreTable =3D LS1046aMpCoreInfoCTA72x4; + + return EFI_SUCCESS; +} + +ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi =3D { PrePeiCoreGetMpCoreInfo }; + +EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] =3D { + { + EFI_PEI_PPI_DESCRIPTOR_PPI, + &gArmMpCoreInfoPpiGuid, + &mMpCoreInfoPpi + } +}; + +VOID +ArmPlatformGetPlatformPpiList ( + OUT UINTN *PpiListSize, + OUT EFI_PEI_PPI_DESCRIPTOR **PpiList + ) +{ + *PpiListSize =3D sizeof(gPlatformPpiTable); + *PpiList =3D gPlatformPpiTable; +} + + +UINTN +ArmPlatformGetCorePosition ( + IN UINTN MpId + ) +{ + return 1; +} diff --git a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.= inf b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf new file mode 100644 index 0000000..033f77a --- /dev/null +++ b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf @@ -0,0 +1,70 @@ +#/* @file +# Copyright (c) 2011-2013, ARM Limited. All rights reserved. +# Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +#*/ + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D ArmPlatformLib + FILE_GUID =3D 177a95a8-27c2-4582-8ba9-c87aa3e0ba75 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D ArmPlatformLib + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + Platform/NXP/NxpQoriqLs.dec + +[LibraryClasses] + ArmLib + SocLib + +[Sources.common] + NxpQoriqLsHelper.S | GCC + ArmPlatformLib.c + NxpQoriqLsMem.c + +[Ppis] + gArmMpCoreInfoPpiGuid + +[FeaturePcd] + gEmbeddedTokenSpaceGuid.PcdCacheEnable + +[FixedPcd] + gArmTokenSpaceGuid.PcdArmPrimaryCore + gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size + gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize + gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize + gNxpQoriqLsTokenSpaceGuid.PcdDram1BaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdDram1Size + gNxpQoriqLsTokenSpaceGuid.PcdDram2BaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdDram2Size + gNxpQoriqLsTokenSpaceGuid.PcdDram3BaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdDram3Size + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize diff --git a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsHelpe= r.S b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S new file mode 100644 index 0000000..55e750f --- /dev/null +++ b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S @@ -0,0 +1,39 @@ +# @file +# +# Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoardHelper.S +# +# Copyright 2017 NXP +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +# + +#include +#include + +.text +.align 2 + +GCC_ASM_IMPORT(ArmReadMpidr) + +ASM_FUNC(ArmPlatformIsPrimaryCore) + tst x0, #3 + cset x0, eq + ret + +ASM_FUNC(ArmPlatformPeiBootAction) +EL1_OR_EL2(x0) +1: +2: + ret + +ASM_FUNC(ArmPlatformGetPrimaryCoreMpId) + MOV32 (x0, FixedPcdGet32(PcdArmPrimaryCore)) + ldrh w0, [x0] + ret diff --git a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c= b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c new file mode 100644 index 0000000..613ff04 --- /dev/null +++ b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c @@ -0,0 +1,181 @@ +/** NxpQoriqLsMem.c +* +* Board memory specific Library. +* +* Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoardMem.c +* +* Copyright (c) 2011, ARM Limited. All rights reserved. +* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved. +* Copyright 2017 NXP +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the B= SD License +* which accompanies this distribution. The full text of the license may b= e found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#include +#include +#include +#include + +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 25 + +#define CCSR_BASE_ADDR FixedPcdGet64 (PcdCcsrBaseAddr) +#define CCSR_SIZE FixedPcdGet64 (PcdCcsrSize) +#define IFC_REGION1_BASE_ADDR FixedPcdGet64 (PcdIfcRegion1BaseAddr) +#define IFC_REGION1_SIZE FixedPcdGet64 (PcdIfcRegion1Size) +#define IFC_REGION2_BASE_ADDR FixedPcdGet64 (PcdIfcRegion2BaseAddr) +#define IFC_REGION2_SIZE FixedPcdGet64 (PcdIfcRegion2Size) +#define QMAN_SWP_BASE_ADDR FixedPcdGet64 (PcdQmanSwpBaseAddr) +#define QMAN_SWP_SIZE FixedPcdGet64 (PcdQmanSwpSize) +#define BMAN_SWP_BASE_ADDR FixedPcdGet64 (PcdBmanSwpBaseAddr) +#define BMAN_SWP_SIZE FixedPcdGet64 (PcdBmanSwpSize) +#define PCI_EXP1_BASE_ADDR FixedPcdGet64 (PcdPciExp1BaseAddr) +#define PCI_EXP1_BASE_SIZE FixedPcdGet64 (PcdPciExp1BaseSize) +#define PCI_EXP2_BASE_ADDR FixedPcdGet64 (PcdPciExp2BaseAddr) +#define PCI_EXP2_BASE_SIZE FixedPcdGet64 (PcdPciExp2BaseSize) +#define PCI_EXP3_BASE_ADDR FixedPcdGet64 (PcdPciExp3BaseAddr) +#define PCI_EXP3_BASE_SIZE FixedPcdGet64 (PcdPciExp3BaseSize) +#define DRAM1_BASE_ADDR FixedPcdGet64 (PcdDram1BaseAddr) +#define DRAM1_SIZE FixedPcdGet64 (PcdDram1Size) +#define DRAM2_BASE_ADDR FixedPcdGet64 (PcdDram2BaseAddr) +#define DRAM2_SIZE FixedPcdGet64 (PcdDram2Size) +#define DRAM3_BASE_ADDR FixedPcdGet64 (PcdDram3BaseAddr) +#define DRAM3_SIZE FixedPcdGet64 (PcdDram3Size) +#define QSPI_REGION_BASE_ADDR FixedPcdGet64 (PcdQspiRegionBaseAddr) +#define QSPI_REGION_SIZE FixedPcdGet64 (PcdQspiRegionSize) + + +/** + Return the Virtual Memory Map of your platform + + This Virtual Memory Map is used by MemoryInitPei Module to initialize th= e MMU on your platform. + + @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR = describing a Physical-to- + Virtual Memory mapping. This array mus= t be ended by a zero-filled + entry + +**/ + +VOID +ArmPlatformGetVirtualMemoryMap ( + IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap + ) +{ + ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes; + UINTN Index =3D 0; + ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; + + ASSERT(VirtualMemoryMap !=3D NULL); + + VirtualMemoryTable =3D (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_= SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MA= P_DESCRIPTORS)); + if (VirtualMemoryTable =3D=3D NULL) { + return; + } + + if (FeaturePcdGet(PcdCacheEnable) =3D=3D TRUE) { + CacheAttributes =3D ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK; + } else { + CacheAttributes =3D ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED; + } + + // DRAM1 (Must be 1st entry) + VirtualMemoryTable[Index].PhysicalBase =3D DRAM1_BASE_ADDR; + VirtualMemoryTable[Index].VirtualBase =3D DRAM1_BASE_ADDR; + VirtualMemoryTable[Index].Length =3D DRAM1_SIZE; + VirtualMemoryTable[Index].Attributes =3D CacheAttributes; + + // CCSR Space + VirtualMemoryTable[++Index].PhysicalBase =3D CCSR_BASE_ADDR; + VirtualMemoryTable[Index].VirtualBase =3D CCSR_BASE_ADDR; + VirtualMemoryTable[Index].Length =3D CCSR_SIZE; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + // IFC region 1 + // + // A-009241 : Unaligned write transactions to IFC may result in corrup= tion of data + // Affects : IFC + // Description: 16 byte unaligned write from system bus to IFC may resul= t in extra unintended + // writes on external IFC interface that can corrupt data o= n external flash. + // Impact : Data corruption on external flash may happen in case of = unaligned writes to + // IFC memory space. + // Workaround: Following are the workarounds: + // =EF=BF=BD For write transactions from core, IFC interface= memories (including IFC SRAM) + // should be configured as =EF=BF=BDdevice type" memory i= n MMU. + // =EF=BF=BD For write transactions from non-core masters (l= ike system DMA), the address + // should be 16 byte aligned and the data size should be = multiple of 16 bytes. + // + VirtualMemoryTable[++Index].PhysicalBase =3D IFC_REGION1_BASE_ADDR; + VirtualMemoryTable[Index].VirtualBase =3D IFC_REGION1_BASE_ADDR; + VirtualMemoryTable[Index].Length =3D IFC_REGION1_SIZE; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + // QMAN SWP + VirtualMemoryTable[++Index].PhysicalBase =3D QMAN_SWP_BASE_ADDR; + VirtualMemoryTable[Index].VirtualBase =3D QMAN_SWP_BASE_ADDR; + VirtualMemoryTable[Index].Length =3D QMAN_SWP_SIZE; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_U= NCACHED_UNBUFFERED; + + // BMAN SWP + VirtualMemoryTable[++Index].PhysicalBase =3D BMAN_SWP_BASE_ADDR; + VirtualMemoryTable[Index].VirtualBase =3D BMAN_SWP_BASE_ADDR; + VirtualMemoryTable[Index].Length =3D BMAN_SWP_SIZE; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_U= NCACHED_UNBUFFERED; + + // IFC region 2 + VirtualMemoryTable[++Index].PhysicalBase =3D IFC_REGION2_BASE_ADDR; + VirtualMemoryTable[Index].VirtualBase =3D IFC_REGION2_BASE_ADDR; + VirtualMemoryTable[Index].Length =3D IFC_REGION2_SIZE; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + // DRAM2 + VirtualMemoryTable[++Index].PhysicalBase =3D DRAM2_BASE_ADDR; + VirtualMemoryTable[Index].VirtualBase =3D DRAM2_BASE_ADDR; + VirtualMemoryTable[Index].Length =3D DRAM2_SIZE; + VirtualMemoryTable[Index].Attributes =3D CacheAttributes; + + // PCIe1 + VirtualMemoryTable[++Index].PhysicalBase =3D PCI_EXP1_BASE_ADDR; + VirtualMemoryTable[Index].VirtualBase =3D PCI_EXP1_BASE_ADDR; + VirtualMemoryTable[Index].Length =3D PCI_EXP1_BASE_SIZE; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + // PCIe2 + VirtualMemoryTable[++Index].PhysicalBase =3D PCI_EXP2_BASE_ADDR; + VirtualMemoryTable[Index].VirtualBase =3D PCI_EXP2_BASE_ADDR; + VirtualMemoryTable[Index].Length =3D PCI_EXP2_BASE_SIZE; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + // PCIe3 + VirtualMemoryTable[++Index].PhysicalBase =3D PCI_EXP3_BASE_ADDR; + VirtualMemoryTable[Index].VirtualBase =3D PCI_EXP3_BASE_ADDR; + VirtualMemoryTable[Index].Length =3D PCI_EXP3_BASE_SIZE; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + // DRAM3 + VirtualMemoryTable[++Index].PhysicalBase =3D DRAM3_BASE_ADDR; + VirtualMemoryTable[Index].VirtualBase =3D DRAM3_BASE_ADDR; + VirtualMemoryTable[Index].Length =3D DRAM3_SIZE; + VirtualMemoryTable[Index].Attributes =3D CacheAttributes; + + // QSPI region + VirtualMemoryTable[++Index].PhysicalBase =3D QSPI_REGION_BASE_ADDR; + VirtualMemoryTable[Index].VirtualBase =3D QSPI_REGION_BASE_ADDR; + VirtualMemoryTable[Index].Length =3D QSPI_REGION_SIZE; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_U= NCACHED_UNBUFFERED; + + // End of Table + VirtualMemoryTable[++Index].PhysicalBase =3D 0; + VirtualMemoryTable[Index].VirtualBase =3D 0; + VirtualMemoryTable[Index].Length =3D 0; + VirtualMemoryTable[Index].Attributes =3D (ARM_MEMORY_REGION_ATTRIBUTES= )0; + + ASSERT((Index + 1) <=3D MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS); + + *VirtualMemoryMap =3D VirtualMemoryTable; +} --=20 1.9.1 --===============1189107970882970158== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel --===============1189107970882970158==--