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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id f21sm107393lja.25.2017.10.30.20.59.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 30 Oct 2017 20:59:53 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::243; helo=mail-lf0-x243.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=FLqZd3APi0rOGqRVP3RPOeMdPQWA3TluZEW+IpzBijY=; b=IOyCT5PJHAtepXEiyxANvXpeX/dzC3BsxHEnVakNC6vhrVkF8+2/6z7C/i42yMVle3 lJCvLqZ9eoo6noZXY7m4+cGFXjtxXI0POfCqJ0HFstOa/FtEUw7RBjwoXFtB0R3vHetj Dzmc7Do3Wv8NP9V+bigMEZuDHj4FJzBXCObogTP07vSpJFTbx7nm60Ll27VhVlcv1iEj UpDbop596kveFHZK3pK1crMdljKSQ8p01z6sbiBWxlEBlXn2BZvlo8fZl3T4/ZySqs/o UL9oMS31NIbQE2LrpXomBFhEa6tftNBVZDmz2X/vEydLKU+k3GTN+G/luFc9BAAgF5/c rXWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=FLqZd3APi0rOGqRVP3RPOeMdPQWA3TluZEW+IpzBijY=; b=cxMgUNfkbBS+gynFk9Dp0PCg546LQMujg1HGH5lqqE1VWpQqLwCwpBlke9ZfyTgui1 1pichoXLkSWpH/pcvVOhQ2ctV8yrFRbRFwU8z2foan6GJz5VVeH/zZ2vdi4ckcX/jTQS x8FP9Jo8wTFWF2I+gIxG9CyEn8LGQyec1s3hT8oDSkyqwPXT2fIKEqPm4xbVrJq4RCqv ZZD0LxWZM5PMr8LNbaTTiOdmPZJMLJh1X1eVYwTRq0WIMfQbPtZ1FmQrprGUtgONA8hd Q/4fNE5FSadYxXbZvmh3HC+AsAm/tFB06vH3EKzVGalptY+5osc0RiPxeoGlZoD1rHPl milg== X-Gm-Message-State: AMCzsaVoMCO02YXQdm/xBn1P4KEZ63N1Ho98NZkYo5VtoKN6o0HyMD7S b5GKu8MUV96Vu8sJdl2HcDnIJYnMnT0= X-Google-Smtp-Source: ABhQp+RCLnRl5CmzRXfjm8N6ekFbACPISkhc7R6u5MyIxtr7/Fq3nQxbOFr6Hj7SX17fpr8NwTPxeA== X-Received: by 10.25.115.14 with SMTP id o14mr151965lfc.79.1509422394628; Mon, 30 Oct 2017 20:59:54 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Tue, 31 Oct 2017 04:59:30 +0100 Message-Id: <1509422375-20198-2-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509422375-20198-1-git-send-email-mw@semihalf.com> References: <1509422375-20198-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 1/6] Marvell/Drivers: MvSpiFlash: Improve ReadId X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Fix the ReadId routine by using master's ReadWrite callback instead of the raw Transfer - no longer swapping and byte shifting is needed. Simplify code by using local array instead of dynamic allocation. Moreover store the FlashId in an UINT8 array PCD instead of the concatenated UINT32 format - this way less overhead in the driver is needed for comparing the buffers. The new handling allowed for cleaning Fupdate and Sf shell commands FlashProbe routines. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Platform/Marvell/Applications/FirmwareUpdate/FUpdate.c | 22 +++-------- Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c | 37 ++++++--------= ---- Platform/Marvell/Armada/Armada70x0.dsc | 2 +- Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.c | 41 ++++++++++++--= ------ Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.h | 2 + Platform/Marvell/Include/Protocol/SpiFlash.h | 3 ++ Platform/Marvell/Marvell.dec | 2 +- 7 files changed, 48 insertions(+), 61 deletions(-) diff --git a/Platform/Marvell/Applications/FirmwareUpdate/FUpdate.c b/Platf= orm/Marvell/Applications/FirmwareUpdate/FUpdate.c index 664411a..d70645d 100644 --- a/Platform/Marvell/Applications/FirmwareUpdate/FUpdate.c +++ b/Platform/Marvell/Applications/FirmwareUpdate/FUpdate.c @@ -94,28 +94,16 @@ SpiFlashProbe ( ) { EFI_STATUS Status; - UINT32 IdBuffer, Id, RefId; + UINT8 *FlashId; =20 - Id =3D PcdGet32 (PcdSpiFlashId); - - IdBuffer =3D CMD_READ_ID & 0xff; + FlashId =3D (UINT8 *)PcdGetPtr (PcdSpiFlashId); =20 // Read SPI flash ID - SpiFlashProtocol->ReadId (Slave, sizeof (UINT32), (UINT8 *)&IdBuffer); - - // Swap and extract 3 bytes of the ID - RefId =3D SwapBytes32 (IdBuffer) >> 8; - - if (RefId =3D=3D 0) { - Print (L"%s: No SPI flash detected"); - return EFI_DEVICE_ERROR; - } else if (RefId !=3D Id) { - Print (L"%s: Unsupported SPI flash detected with ID=3D%2x\n", CMD_NAME= _STRING, RefId); - return EFI_DEVICE_ERROR; + Status =3D SpiFlashProtocol->ReadId (Slave, NOR_FLASH_ID_DEFAULT_LEN, Fl= ashId); + if (EFI_ERROR (Status)) { + return SHELL_ABORTED; } =20 - Print (L"%s: Detected supported SPI flash with ID=3D%3x\n", CMD_NAME_STR= ING, RefId); - Status =3D SpiFlashProtocol->Init (SpiFlashProtocol, Slave); if (EFI_ERROR(Status)) { Print (L"%s: Cannot initialize flash device\n", CMD_NAME_STRING); diff --git a/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c b/Platform= /Marvell/Applications/SpiTool/SpiFlashCmd.c index 9321f6b..a12f2ec 100644 --- a/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c +++ b/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c @@ -166,37 +166,24 @@ FlashProbe ( ) { EFI_STATUS Status; - UINT8 IdBuffer[4]; - UINT32 Id, RefId; + UINT8 *FlashId; =20 - Id =3D PcdGet32 (PcdSpiFlashId); + FlashId =3D (UINT8 *)PcdGetPtr (PcdSpiFlashId); =20 - IdBuffer[0] =3D CMD_READ_ID; - - SpiFlashProtocol->ReadId ( - Slave, - 4, - IdBuffer - ); - - RefId =3D (IdBuffer[0] << 16) + (IdBuffer[1] << 8) + IdBuffer[2]; + Status =3D SpiFlashProtocol->ReadId (Slave, NOR_FLASH_ID_DEFAULT_LEN, Fl= ashId); + if (EFI_ERROR (Status)) { + return SHELL_ABORTED; + } =20 - if (RefId =3D=3D Id) { - Print (L"sf: Detected supported SPI flash with ID=3D%3x\n", RefId); - Status =3D SpiFlashProtocol->Init (SpiFlashProtocol, Slave); - if (EFI_ERROR(Status)) { - Print (L"sf: Cannot initialize flash device\n"); - return SHELL_ABORTED; - } - InitFlag =3D 0; - return EFI_SUCCESS; - } else if (RefId !=3D 0) { - Print (L"sf: Unsupported SPI flash detected with ID=3D%2x\n", RefId); + Status =3D SpiFlashProtocol->Init (SpiFlashProtocol, Slave); + if (EFI_ERROR (Status)) { + Print (L"sf: Cannot initialize flash device\n"); return SHELL_ABORTED; } =20 - Print (L"sf: No SPI flash detected"); - return SHELL_ABORTED; + InitFlag =3D 0; + + return SHELL_SUCCESS; } =20 SHELL_STATUS diff --git a/Platform/Marvell/Armada/Armada70x0.dsc b/Platform/Marvell/Arma= da/Armada70x0.dsc index 0396e8e..4d5f55f 100644 --- a/Platform/Marvell/Armada/Armada70x0.dsc +++ b/Platform/Marvell/Armada/Armada70x0.dsc @@ -94,7 +94,7 @@ gMarvellTokenSpaceGuid.PcdSpiFlashAddressCycles|3 gMarvellTokenSpaceGuid.PcdSpiFlashEraseSize|65536 gMarvellTokenSpaceGuid.PcdSpiFlashPageSize|256 - gMarvellTokenSpaceGuid.PcdSpiFlashId|0x20BA18 + gMarvellTokenSpaceGuid.PcdSpiFlashId|{ 0x20, 0xBA, 0x18 } gMarvellTokenSpaceGuid.PcdSpiFlashMode|3 gMarvellTokenSpaceGuid.PcdSpiFlashCs|0 =20 diff --git a/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.c b/Platform/M= arvell/Drivers/Spi/Devices/MvSpiFlash.c index 6f7d9c7..ab3ed6a 100755 --- a/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.c +++ b/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.c @@ -409,28 +409,35 @@ MvSpiFlashReadId ( ) { EFI_STATUS Status; - UINT8 *DataOut; + UINT8 Id[NOR_FLASH_MAX_ID_LEN]; + UINT8 Cmd; + + Cmd =3D CMD_READ_ID; + Status =3D SpiMasterProtocol->ReadWrite (SpiMasterProtocol, + SpiDev, + &Cmd, + SPI_CMD_LEN, + NULL, + Id, + NOR_FLASH_MAX_ID_LEN); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "ReadId: Spi transfer error\n")); + return Status; + } =20 - DataOut =3D (UINT8 *) AllocateZeroPool (DataByteCount); - if (DataOut =3D=3D NULL) { - DEBUG((DEBUG_ERROR, "SpiFlash: Cannot allocate memory\n")); - return EFI_OUT_OF_RESOURCES; + if (CompareMem (Id, Buffer, DataByteCount) !=3D 0) { + Status =3D EFI_NOT_FOUND; } - Status =3D SpiMasterProtocol->Transfer (SpiMasterProtocol, SpiDev, - DataByteCount, Buffer, DataOut, SPI_TRANSFER_BEGIN | SPI_TRANSFER_END); - if (EFI_ERROR(Status)) { - FreePool (DataOut); - DEBUG((DEBUG_ERROR, "SpiFlash: Spi transfer error\n")); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, + "%a: Unrecognized JEDEC Id bytes: 0x%02x%02x%02x\n", + __FUNCTION__, + Id[0], + Id[1], + Id[2])); return Status; } =20 - // Bytes 1,2 and 3 contain SPI flash ID - Buffer[0] =3D DataOut[1]; - Buffer[1] =3D DataOut[2]; - Buffer[2] =3D DataOut[3]; - - FreePool (DataOut); - return EFI_SUCCESS; } =20 diff --git a/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.h b/Platform/M= arvell/Drivers/Spi/Devices/MvSpiFlash.h index f90abb7..2583484 100755 --- a/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.h +++ b/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.h @@ -62,6 +62,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. #define CMD_ERASE_64K 0xd8 #define CMD_4B_ADDR_ENABLE 0xb7 =20 +#define SPI_CMD_LEN 1 + #define STATUS_REG_POLL_WIP (1 << 0) #define STATUS_REG_POLL_PEC (1 << 7) =20 diff --git a/Platform/Marvell/Include/Protocol/SpiFlash.h b/Platform/Marvel= l/Include/Protocol/SpiFlash.h index 743bb87..e0d62cc 100644 --- a/Platform/Marvell/Include/Protocol/SpiFlash.h +++ b/Platform/Marvell/Include/Protocol/SpiFlash.h @@ -47,6 +47,9 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. #define CMD_ERASE_64K 0xd8 #define CMD_4B_ADDR_ENABLE 0xb7 =20 +#define NOR_FLASH_MAX_ID_LEN 6 +#define NOR_FLASH_ID_DEFAULT_LEN 3 + extern EFI_GUID gMarvellSpiFlashProtocolGuid; =20 typedef struct _MARVELL_SPI_FLASH_PROTOCOL MARVELL_SPI_FLASH_PROTOCOL; diff --git a/Platform/Marvell/Marvell.dec b/Platform/Marvell/Marvell.dec index cd800c8..679a9d0 100644 --- a/Platform/Marvell/Marvell.dec +++ b/Platform/Marvell/Marvell.dec @@ -133,7 +133,7 @@ gMarvellTokenSpaceGuid.PcdSpiFlashEraseSize|0|UINT64|0x3000054 gMarvellTokenSpaceGuid.PcdSpiFlashPageSize|0|UINT32|0x3000055 gMarvellTokenSpaceGuid.PcdSpiFlashSectorSize|65536|UINT64|0x3000059 - gMarvellTokenSpaceGuid.PcdSpiFlashId|0|UINT32|0x3000056 + gMarvellTokenSpaceGuid.PcdSpiFlashId|{ 0x0 }|VOID*|0x3000056 gMarvellTokenSpaceGuid.PcdSpiFlashCs|0|UINT32|0x3000057 gMarvellTokenSpaceGuid.PcdSpiFlashMode|0|UINT32|0x3000058 =20 --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Fri May 3 19:15:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1509422403358176.22000632513436; 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id f21sm107393lja.25.2017.10.30.20.59.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 30 Oct 2017 20:59:55 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::244; helo=mail-lf0-x244.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=oC1KaiksmPCL2Z3CKCjkKrhNBWr77ganiSUK3dz8a/I=; b=KXSiLFqucLmL4+z/5MwaDPBbzAH7x0CTBra6WJZfw6DosidZUIunLwSGJRMtHqW9u0 /rEbzdKsf0DMLnmDXTeUZVXkTiklZVW2Hs9J7z/ZLH0rY8rdU9WJaog5DBHRELT+7tZm CjW7XEukjImFwDuF6IPKi6V7N+6f3RKf6fbSq+xKNKUrJBVCaBrosBwvWE5hWmVvfI/v 3sgOBV+5jR0rliv+3oh+czf+eTrBBZNeEBUsNDq8awYNLGG5btibq39kR884HSxFP9bo eD8q2UlER7uvSYIqbq7j9k9nY8RMQOIo+4Iz3mzOHwYDkWT1AMRXX9Zis7qKvBvtUjcg VgHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=oC1KaiksmPCL2Z3CKCjkKrhNBWr77ganiSUK3dz8a/I=; b=d/1xGnzNZKdwjNOaIRSBkPjeWcNCkKA5B/JWBOsRVPztyz2MdKaZ4wQmqFyw0pRVaD wx1MokEWGvbadh33IhqUi83LCD1KY4POIEnaKwLAM6+oaExTjKNPDSRTWA5u83yk2UP1 XAojtM++SmyORKpFWeCZISuuGqD0IxAmeSPjSUYHsnUhnegzwOO0i2XBCFaKujTzYNcv WoV3cEWWuDLn3pRE7BepNnU+6fvriJPCHVQ7CtKqi1in6P/+d9i69VGee6w4RBTSLoq7 6aFBEqA7SCVdrtmjHKAVhHCOjmnIWlXWze3IqZS2k/JtFsh2sJCsr9aCrLrkZbwxA3ZM LO8A== X-Gm-Message-State: AMCzsaWCkoLaPdQsnjnQVmKXUjo+YRW81n9Vm7dn2WPE3xjemVkG0zId 9Fdi+qSgtMiyDHhMuEEgh9qHB5eptqY= X-Google-Smtp-Source: ABhQp+T62j5AzsRECNHlONnuc49U4R4nQgEP/03VWEGdn0xyj3tzGcJchMke93OK38dX92EiBROPRg== X-Received: by 10.46.22.83 with SMTP id 19mr225866ljw.147.1509422396400; Mon, 30 Oct 2017 20:59:56 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Tue, 31 Oct 2017 04:59:31 +0100 Message-Id: <1509422375-20198-3-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509422375-20198-1-git-send-email-mw@semihalf.com> References: <1509422375-20198-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 2/6] Marvell/Drivers: MvSpiFlash: Enable dynamic SPI Flash detection X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Hitherto mechanism of fixing SPI flash model in the PCDs, occured to be very inefficient and problematic. Enable dynamic detection by reworking MvSpiFlashReadId() command, which now uses newly added NorFlashInfoLib, that helps to obtain description of the JEDEC compliant devices. This patch updates the MvSpiFlashProtocol ReadId() protocol callback on both producer's (MvFlashDxe) and consumers' sides (FirmwareUpdate and SpiTool applications). Because all information about detected SPI NOR flash is now stored in the obtained NorFlashInfo structure fields, use them instead of the PCDs. Enable compilation of the NorFlashInfoLib and update PortingGuide documentation accordingly. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Platform/Marvell/Applications/FirmwareUpdate/FUpdate.c | 5 +- Platform/Marvell/Applications/FirmwareUpdate/FUpdate.inf | 4 +- Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c | 5 +- Platform/Marvell/Applications/SpiTool/SpiFlashCmd.inf | 2 +- Platform/Marvell/Armada/Armada.dsc.inc | 1 + Platform/Marvell/Armada/Armada70x0.dsc | 5 -- Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.c | 68 +++++++++++-= -------- Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.inf | 9 +-- Platform/Marvell/Drivers/Spi/MvSpiDxe.inf | 2 + Platform/Marvell/Include/Protocol/Spi.h | 3 + Platform/Marvell/Include/Protocol/SpiFlash.h | 6 +- Platform/Marvell/Marvell.dec | 6 -- Silicon/Marvell/Documentation/PortingGuide.txt | 18 ------ 13 files changed, 51 insertions(+), 83 deletions(-) diff --git a/Platform/Marvell/Applications/FirmwareUpdate/FUpdate.c b/Platf= orm/Marvell/Applications/FirmwareUpdate/FUpdate.c index d70645d..750e52a 100644 --- a/Platform/Marvell/Applications/FirmwareUpdate/FUpdate.c +++ b/Platform/Marvell/Applications/FirmwareUpdate/FUpdate.c @@ -94,12 +94,9 @@ SpiFlashProbe ( ) { EFI_STATUS Status; - UINT8 *FlashId; - - FlashId =3D (UINT8 *)PcdGetPtr (PcdSpiFlashId); =20 // Read SPI flash ID - Status =3D SpiFlashProtocol->ReadId (Slave, NOR_FLASH_ID_DEFAULT_LEN, Fl= ashId); + Status =3D SpiFlashProtocol->ReadId (Slave, FALSE); if (EFI_ERROR (Status)) { return SHELL_ABORTED; } diff --git a/Platform/Marvell/Applications/FirmwareUpdate/FUpdate.inf b/Pla= tform/Marvell/Applications/FirmwareUpdate/FUpdate.inf index 92c3333..53ea491 100644 --- a/Platform/Marvell/Applications/FirmwareUpdate/FUpdate.inf +++ b/Platform/Marvell/Applications/FirmwareUpdate/FUpdate.inf @@ -44,6 +44,7 @@ FUpdate.uni =20 [Packages] + EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec Platform/Marvell/Marvell.dec @@ -64,9 +65,6 @@ UefiLib UefiRuntimeServicesTableLib =20 -[Pcd] - gMarvellTokenSpaceGuid.PcdSpiFlashId - [Protocols] gMarvellSpiFlashProtocolGuid gMarvellSpiMasterProtocolGuid diff --git a/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c b/Platform= /Marvell/Applications/SpiTool/SpiFlashCmd.c index a12f2ec..68a6cf7 100644 --- a/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c +++ b/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c @@ -166,11 +166,8 @@ FlashProbe ( ) { EFI_STATUS Status; - UINT8 *FlashId; =20 - FlashId =3D (UINT8 *)PcdGetPtr (PcdSpiFlashId); - - Status =3D SpiFlashProtocol->ReadId (Slave, NOR_FLASH_ID_DEFAULT_LEN, Fl= ashId); + Status =3D SpiFlashProtocol->ReadId (Slave, FALSE); if (EFI_ERROR (Status)) { return SHELL_ABORTED; } diff --git a/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.inf b/Platfo= rm/Marvell/Applications/SpiTool/SpiFlashCmd.inf index 887b9a5..a52906b 100644 --- a/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.inf +++ b/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.inf @@ -44,6 +44,7 @@ SpiFlashCmd.uni =20 [Packages] + EmbeddedPkg/EmbeddedPkg.dec MdePkg/MdePkg.dec ShellPkg/ShellPkg.dec MdeModulePkg/MdeModulePkg.dec @@ -66,7 +67,6 @@ =20 [Pcd] gMarvellTokenSpaceGuid.PcdSpiFlashCs - gMarvellTokenSpaceGuid.PcdSpiFlashId gMarvellTokenSpaceGuid.PcdSpiFlashMode =20 [Protocols] diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Arma= da/Armada.dsc.inc index b9fc384..2cd96e6 100644 --- a/Platform/Marvell/Armada/Armada.dsc.inc +++ b/Platform/Marvell/Armada/Armada.dsc.inc @@ -33,6 +33,7 @@ ArmPlatformLib|Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0L= ib.inf ComPhyLib|Platform/Marvell/Library/ComPhyLib/ComPhyLib.inf MppLib|Platform/Marvell/Library/MppLib/MppLib.inf + NorFlashInfoLib|EmbeddedPkg/Library/NorFlashInfoLib/NorFlashInfoLib.inf UtmiPhyLib|Platform/Marvell/Library/UtmiPhyLib/UtmiPhyLib.inf =20 DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf diff --git a/Platform/Marvell/Armada/Armada70x0.dsc b/Platform/Marvell/Arma= da/Armada70x0.dsc index 4d5f55f..8e4cdb2 100644 --- a/Platform/Marvell/Armada/Armada70x0.dsc +++ b/Platform/Marvell/Armada/Armada70x0.dsc @@ -90,11 +90,6 @@ gMarvellTokenSpaceGuid.PcdSpiMaxFrequency|10000000 gMarvellTokenSpaceGuid.PcdSpiClockFrequency|200000000 =20 - gMarvellTokenSpaceGuid.PcdSpiFlashPollCmd|0x70 - gMarvellTokenSpaceGuid.PcdSpiFlashAddressCycles|3 - gMarvellTokenSpaceGuid.PcdSpiFlashEraseSize|65536 - gMarvellTokenSpaceGuid.PcdSpiFlashPageSize|256 - gMarvellTokenSpaceGuid.PcdSpiFlashId|{ 0x20, 0xBA, 0x18 } gMarvellTokenSpaceGuid.PcdSpiFlashMode|3 gMarvellTokenSpaceGuid.PcdSpiFlashCs|0 =20 diff --git a/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.c b/Platform/M= arvell/Drivers/Spi/Devices/MvSpiFlash.c index ab3ed6a..703994c 100755 --- a/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.c +++ b/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.c @@ -107,10 +107,10 @@ MvSpiFlashWriteCommon ( UINT8 PollBit =3D STATUS_REG_POLL_WIP; UINT8 CheckStatus =3D 0x0; =20 - CmdStatus =3D (UINT8)PcdGet32 (PcdSpiFlashPollCmd); - if (CmdStatus =3D=3D CMD_FLAG_STATUS) { + if (Slave->Info->Flags & NF_WRITE_FSR) { + CmdStatus =3D CMD_FLAG_STATUS; PollBit =3D STATUS_REG_POLL_PEC; - CheckStatus =3D PollBit; + CheckStatus =3D STATUS_REG_POLL_PEC; } =20 // Send command @@ -181,8 +181,19 @@ MvSpiFlashErase ( UINTN EraseSize; UINT8 Cmd[5]; =20 - AddrSize =3D PcdGet32 (PcdSpiFlashAddressCycles); - EraseSize =3D PcdGet64 (PcdSpiFlashEraseSize); + if (Slave->Info->Flags & NF_4B_ADDR) { + AddrSize =3D 4; + } else { + AddrSize =3D 3; + } + + if (Slave->Info->Flags & NF_ERASE_4K) { + Cmd[0] =3D CMD_ERASE_4K; + EraseSize =3D SIZE_4KB; + } else { + Cmd[0] =3D CMD_ERASE_64K; + EraseSize =3D Slave->Info->SectorSize; + } =20 // Check input parameters if (Offset % EraseSize || Length % EraseSize) { @@ -191,21 +202,6 @@ MvSpiFlashErase ( return EFI_DEVICE_ERROR; } =20 - switch (EraseSize) { - case SIZE_4KB: - Cmd[0] =3D CMD_ERASE_4K; - break; - case SIZE_32KB: - Cmd[0] =3D CMD_ERASE_32K; - break; - case SIZE_64KB: - Cmd[0] =3D CMD_ERASE_64K; - break; - default: - DEBUG ((DEBUG_ERROR, "MvSpiFlash: Invalid EraseSize parameter\n")); - return EFI_INVALID_PARAMETER; - } - while (Length) { EraseAddr =3D Offset; =20 @@ -239,7 +235,11 @@ MvSpiFlashRead ( UINT32 AddrSize, ReadAddr, ReadLength, RemainLength; UINTN BankSel =3D 0; =20 - AddrSize =3D PcdGet32 (PcdSpiFlashAddressCycles); + if (Slave->Info->Flags & NF_4B_ADDR) { + AddrSize =3D 4; + } else { + AddrSize =3D 3; + } =20 Cmd[0] =3D CMD_READ_ARRAY_FAST; =20 @@ -282,8 +282,13 @@ MvSpiFlashWrite ( UINT32 WriteAddr; UINT8 Cmd[5], AddrSize; =20 - AddrSize =3D PcdGet32 (PcdSpiFlashAddressCycles); - PageSize =3D PcdGet32 (PcdSpiFlashPageSize); + if (Slave->Info->Flags & NF_4B_ADDR) { + AddrSize =3D 4; + } else { + AddrSize =3D 3; + } + + PageSize =3D Slave->Info->PageSize; =20 Cmd[0] =3D CMD_PAGE_PROGRAM; =20 @@ -370,7 +375,7 @@ MvSpiFlashUpdate ( UINT64 SectorSize, ToUpdate, Scale =3D 1; UINT8 *TmpBuf, *End; =20 - SectorSize =3D PcdGet64 (PcdSpiFlashSectorSize); + SectorSize =3D Slave->Info->SectorSize; =20 End =3D Buf + ByteCount; =20 @@ -404,8 +409,7 @@ EFI_STATUS EFIAPI MvSpiFlashReadId ( IN SPI_DEVICE *SpiDev, - IN UINT32 DataByteCount, - IN OUT UINT8 *Buffer + IN BOOLEAN UseInRuntime ) { EFI_STATUS Status; @@ -425,9 +429,7 @@ MvSpiFlashReadId ( return Status; } =20 - if (CompareMem (Id, Buffer, DataByteCount) !=3D 0) { - Status =3D EFI_NOT_FOUND; - } + Status =3D GetNorFlashInfo (Id, &SpiDev->Info, UseInRuntime); if (EFI_ERROR (Status)) { DEBUG ((DEBUG_ERROR, "%a: Unrecognized JEDEC Id bytes: 0x%02x%02x%02x\n", @@ -438,6 +440,8 @@ MvSpiFlashReadId ( return Status; } =20 + PrintNorFlashInfo (SpiDev->Info); + return EFI_SUCCESS; } =20 @@ -452,7 +456,11 @@ MvSpiFlashInit ( UINT8 Cmd, StatusRegister; UINT32 AddrSize; =20 - AddrSize =3D PcdGet32 (PcdSpiFlashAddressCycles); + if (Slave->Info->Flags & NF_4B_ADDR) { + AddrSize =3D 4; + } else { + AddrSize =3D 3; + } =20 if (AddrSize =3D=3D 4) { // Set 4 byte address mode diff --git a/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.inf b/Platform= /Marvell/Drivers/Spi/Devices/MvSpiFlash.inf index 4519b02..6587f69 100644 --- a/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.inf +++ b/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.inf @@ -42,10 +42,12 @@ MvSpiFlash.h =20 [Packages] + EmbeddedPkg/EmbeddedPkg.dec MdePkg/MdePkg.dec Platform/Marvell/Marvell.dec =20 [LibraryClasses] + NorFlashInfoLib UefiBootServicesTableLib UefiDriverEntryPoint TimerLib @@ -53,13 +55,6 @@ DebugLib MemoryAllocationLib =20 -[FixedPcd] - gMarvellTokenSpaceGuid.PcdSpiFlashAddressCycles - gMarvellTokenSpaceGuid.PcdSpiFlashEraseSize - gMarvellTokenSpaceGuid.PcdSpiFlashPageSize - gMarvellTokenSpaceGuid.PcdSpiFlashPollCmd - gMarvellTokenSpaceGuid.PcdSpiFlashSectorSize - [Protocols] gMarvellSpiMasterProtocolGuid gMarvellSpiFlashProtocolGuid diff --git a/Platform/Marvell/Drivers/Spi/MvSpiDxe.inf b/Platform/Marvell/D= rivers/Spi/MvSpiDxe.inf index d38d331..08c6c04 100644 --- a/Platform/Marvell/Drivers/Spi/MvSpiDxe.inf +++ b/Platform/Marvell/Drivers/Spi/MvSpiDxe.inf @@ -42,10 +42,12 @@ MvSpiDxe.h =20 [Packages] + EmbeddedPkg/EmbeddedPkg.dec MdePkg/MdePkg.dec Platform/Marvell/Marvell.dec =20 [LibraryClasses] + NorFlashInfoLib UefiBootServicesTableLib UefiDriverEntryPoint TimerLib diff --git a/Platform/Marvell/Include/Protocol/Spi.h b/Platform/Marvell/Inc= lude/Protocol/Spi.h index ae78a31..93a8ec0 100644 --- a/Platform/Marvell/Include/Protocol/Spi.h +++ b/Platform/Marvell/Include/Protocol/Spi.h @@ -34,6 +34,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. #ifndef __MARVELL_SPI_MASTER_PROTOCOL_H__ #define __MARVELL_SPI_MASTER_PROTOCOL_H__ =20 +#include + extern EFI_GUID gMarvellSpiMasterProtocolGuid; =20 typedef struct _MARVELL_SPI_MASTER_PROTOCOL MARVELL_SPI_MASTER_PROTOCOL; @@ -49,6 +51,7 @@ typedef struct { INTN Cs; INTN MaxFreq; SPI_MODE Mode; + NOR_FLASH_INFO *Info; } SPI_DEVICE; =20 typedef diff --git a/Platform/Marvell/Include/Protocol/SpiFlash.h b/Platform/Marvel= l/Include/Protocol/SpiFlash.h index e0d62cc..4a3053e 100644 --- a/Platform/Marvell/Include/Protocol/SpiFlash.h +++ b/Platform/Marvell/Include/Protocol/SpiFlash.h @@ -47,9 +47,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. #define CMD_ERASE_64K 0xd8 #define CMD_4B_ADDR_ENABLE 0xb7 =20 -#define NOR_FLASH_MAX_ID_LEN 6 -#define NOR_FLASH_ID_DEFAULT_LEN 3 - extern EFI_GUID gMarvellSpiFlashProtocolGuid; =20 typedef struct _MARVELL_SPI_FLASH_PROTOCOL MARVELL_SPI_FLASH_PROTOCOL; @@ -65,8 +62,7 @@ typedef EFI_STATUS (EFIAPI *MV_SPI_FLASH_READ_ID) ( IN SPI_DEVICE *SpiDev, - IN UINT32 DataByteCount, - IN OUT UINT8 *Buffer + IN BOOLEAN UseInRuntime ); =20 typedef diff --git a/Platform/Marvell/Marvell.dec b/Platform/Marvell/Marvell.dec index 679a9d0..8255895 100644 --- a/Platform/Marvell/Marvell.dec +++ b/Platform/Marvell/Marvell.dec @@ -128,12 +128,6 @@ gMarvellTokenSpaceGuid.PcdSpiMaxFrequency|0|UINT32|0x30000052 gMarvellTokenSpaceGuid.PcdSpiClockFrequency|0|UINT32|0x30000053 =20 - gMarvellTokenSpaceGuid.PcdSpiFlashPollCmd|0|UINT32|0x3000052 - gMarvellTokenSpaceGuid.PcdSpiFlashAddressCycles|0|UINT32|0x3000053 - gMarvellTokenSpaceGuid.PcdSpiFlashEraseSize|0|UINT64|0x3000054 - gMarvellTokenSpaceGuid.PcdSpiFlashPageSize|0|UINT32|0x3000055 - gMarvellTokenSpaceGuid.PcdSpiFlashSectorSize|65536|UINT64|0x3000059 - gMarvellTokenSpaceGuid.PcdSpiFlashId|{ 0x0 }|VOID*|0x3000056 gMarvellTokenSpaceGuid.PcdSpiFlashCs|0|UINT32|0x3000057 gMarvellTokenSpaceGuid.PcdSpiFlashMode|0|UINT32|0x3000058 =20 diff --git a/Silicon/Marvell/Documentation/PortingGuide.txt b/Silicon/Marve= ll/Documentation/PortingGuide.txt index cbe3bed..d5deed5 100644 --- a/Silicon/Marvell/Documentation/PortingGuide.txt +++ b/Silicon/Marvell/Documentation/PortingGuide.txt @@ -312,24 +312,6 @@ SpiFlash configuration =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Folowing PCDs for spi flash driver configuration must be set properly: =20 - - gMarvellTokenSpaceGuid.PcdSpiFlashAddressCycles - (Size of SPI flash address in bytes (3 or 4) ) - - - gMarvellTokenSpaceGuid.PcdSpiFlashEraseSize - (Size of minimal erase block in bytes) - - - gMarvellTokenSpaceGuid.PcdSpiFlashPageSize - (Size of SPI flash page) - - - gMarvellTokenSpaceGuid.PcdSpiFlashSectorSize - (Size of SPI flash sector, 65536 bytes by default) - - - gMarvellTokenSpaceGuid.PcdSpiFlashId - (Id of SPI flash) - - - gMarvellTokenSpaceGuid.PcdSpiFlashPollCmd - (Spi flash polling flag) - - gMarvellTokenSpaceGuid.PcdSpiFlashMode (Default SCLK mode (see SPI_MODE enum in file edk2-platforms/Platform/Marvell/Drivers/Spi/MvSpi.h)) --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Fri May 3 19:15:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id f21sm107393lja.25.2017.10.30.20.59.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 30 Oct 2017 20:59:56 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::244; helo=mail-lf0-x244.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jtVfw9IYV/aao+pW1a50/7afDylJGz4AlCh5yA7OvMI=; b=XUlxjNPn7GqW5W04lOyG5sYdR1be48M/EWFAooQhsuNFmkgKpIvSLsz4ktkWB17kjA QKb5Pz1M7wIZ+uu8ahh4S3kAVjc9RDXqDIG/JC1NV9hcYjPHyr0UQcR7o/17CxcFPjS/ hgLo36omJq0yh0fLJAW96mUCg40/SnMGvuzDCTzPoysiua95cjobILLP7HclPkH77Ttz 1tQgppBW8H+ZjhTb6Hu5aiXWTLSfink+chCirAuUNPJJexzTQ7MIGD3Bi81XsiB5sH8F tiytNlsgEn2PeB4eQzDxyvh8txEIqKncki9sUaybtRoy8Zw0xqiiEX/GQ6amSKIZV0K/ Hdbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jtVfw9IYV/aao+pW1a50/7afDylJGz4AlCh5yA7OvMI=; b=X/EyW+29welJePubvNi+W4zTODtqWREO9JPmOZGdSUQBJLbaHVdbfQotGHsh0KQlz8 YOag2P0hVpRLXe825vONvJ/oPj7pJ8pVDHqWqmDwhKQ0yJPlJ4xa1JSqf2SXB8+21EFh DTqBgPYjcKSYRnj8/OYH2Etzonuy+E0awUS6iBMBxkOnJ/oFSigkb1UOJc3ejDCSEpLW wLQGED1rEt2XSW7WZ8/A2KyVq4IdMZ/JBq3dzwodPlrTF6v4Czmv4vvmg+SfnjOWx8A4 BeqR0QgpkDhmKa6aKkg+OEF/rzUHHDu0Tmi7XWZyKbJu4BAzF7UksPkI4VTBbu0h5RYu yS7w== X-Gm-Message-State: AMCzsaVOe59c/B/Nk+79ZM245OJfx3ivisjsSaadShYMnEFDUulkCjyB NtuwAjqyTdunR2q9Ktt5qNd/YqCcLEU= X-Google-Smtp-Source: ABhQp+QM6p7O7gfotKoOlpUu4TEZa52yOKHRWxDQ/BHIlmHRCi+MORMHpUKJRGcVx7j4Ke4ZT1r2bA== X-Received: by 10.46.34.66 with SMTP id i63mr222422lji.45.1509422397706; Mon, 30 Oct 2017 20:59:57 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Tue, 31 Oct 2017 04:59:32 +0100 Message-Id: <1509422375-20198-4-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509422375-20198-1-git-send-email-mw@semihalf.com> References: <1509422375-20198-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 3/6] Marvell/Drivers: MvSpiFlash: Remove duplicated macros X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Flash commands macros are already defined locally, so remove them from the protocol header. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Platform/Marvell/Include/Protocol/SpiFlash.h | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/Platform/Marvell/Include/Protocol/SpiFlash.h b/Platform/Marvel= l/Include/Protocol/SpiFlash.h index 4a3053e..4ba29ba 100644 --- a/Platform/Marvell/Include/Protocol/SpiFlash.h +++ b/Platform/Marvell/Include/Protocol/SpiFlash.h @@ -36,17 +36,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAM= AGE. =20 #include =20 -#define CMD_READ_ID 0x9f -#define READ_STATUS_REG_CMD 0x0b -#define CMD_WRITE_ENABLE 0x06 -#define CMD_FLAG_STATUS 0x70 -#define CMD_WRITE_STATUS_REG 0x01 -#define CMD_READ_ARRAY_FAST 0x0b -#define CMD_PAGE_PROGRAM 0x02 -#define CMD_BANK_WRITE 0xc5 -#define CMD_ERASE_64K 0xd8 -#define CMD_4B_ADDR_ENABLE 0xb7 - extern EFI_GUID gMarvellSpiFlashProtocolGuid; =20 typedef struct _MARVELL_SPI_FLASH_PROTOCOL MARVELL_SPI_FLASH_PROTOCOL; --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Fri May 3 19:15:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1509422410556845.703808643851; Mon, 30 Oct 2017 21:00:10 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id B01712034AB38; Mon, 30 Oct 2017 20:56:14 -0700 (PDT) Received: from mail-lf0-x244.google.com (mail-lf0-x244.google.com [IPv6:2a00:1450:4010:c07::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id A862A2034AB33 for ; Mon, 30 Oct 2017 20:56:09 -0700 (PDT) Received: by mail-lf0-x244.google.com with SMTP id a132so17357598lfa.7 for ; Mon, 30 Oct 2017 21:00:01 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id f21sm107393lja.25.2017.10.30.20.59.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 30 Oct 2017 20:59:58 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::244; helo=mail-lf0-x244.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=6l5GSy/1JEXyilT4xEVorKlP3/EuPXxXaZ1m19eF3r4=; b=hU9E/G9wRXc5FzyalsExqmpqef4KW+qFkIzConvAAH9CiP7HKb8glo2VSV1iKIMadU 3ZNf56G2WMiZni9f+uOjkIG+m3kG0lyqQxcoHjukW9rU9yFT3XwD92+MvTYyX3pyZXuC xHO1GaLfaFh4PMtWGE0vtQz0gE2+0jxHB//T91uc3eU92WyNamekw6OVBvfujoSd2CSE WMQxZYiabHCJFLzq6TNK7D1/V32Ub38P/JQy67Qa37lpHRdWB2RTavdc+ByzYtnn36hc sKlHUYvYvCyYVpzOOFW/8Nmxk2K6Ll1+Ryvc/foLdzdniGtURcH0lwPPh9Ywtzt6d/Dm nyNg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=6l5GSy/1JEXyilT4xEVorKlP3/EuPXxXaZ1m19eF3r4=; b=hU4QgKMDVGlggOQF/Nkb4I0eIV0mm145jYBIfhYBlVDJbHZH3EK9eqP0DdM272bYW6 XA7qJWbs1+KIVBJKYK96/qbw+0jqotJ8f2/eL4VvHEqal9rIp9Ur9xZ7w/FxpQmTdqbw nMnvO2wKHxwJJh6lJ4WoG7BBCXFQkslFAN0aNsuB0g/T7kKScHEu7TB+sSQolIaRTHjf QeSr8LZjfv+y/D3JtO0qps5lDI0te15A3wyfPdwg0t6GMK6Gms+S9qcgVBl8g/uNyehD D3i6eLswWaieySD1nZTPKh4Cvop3wDBOxjleliXXA8RLP/0KebjkUI3rw7UPnU7ydUJy dHvQ== X-Gm-Message-State: AMCzsaWWUUZnAiT9FY5ldjTWUlYfnEWdwAyTcJOLj/H+aqt9AwfKN6P2 nlZOEtqaPVckRFshX5/AhUzXe92SizI= X-Google-Smtp-Source: ABhQp+SN62obo5kk0Ngy1rZMzgwevxLB1DoJiZLTRxHNOSwh8wxBG0S8ViqRmtreuOy2vcECyaMhsw== X-Received: by 10.46.2.208 with SMTP id y77mr231275lje.183.1509422398976; Mon, 30 Oct 2017 20:59:58 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Tue, 31 Oct 2017 04:59:33 +0100 Message-Id: <1509422375-20198-5-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509422375-20198-1-git-send-email-mw@semihalf.com> References: <1509422375-20198-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 4/6] Marvell/Applications: SpiTool: Do not override existing slave device X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Current usage of sf command requires running 'sf probe' prior to executing any other option. Because it is done in two separate steps, it turned out that SpiMasterProtocol->SetupDevice could easily overwrite valid Slave pointer when performing second operation. Fix the issue by allocating Slave device only once and keep it as global variable in the SpiTool application. This patch also updates FirmwareUpdate command to follow the modified SetupDevice operation. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Platform/Marvell/Applications/FirmwareUpdate/FUpdate.c | 4 ++-- Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c | 8 ++++---- Platform/Marvell/Drivers/Spi/MvSpiDxe.c | 17 +++++++++-----= --- Platform/Marvell/Drivers/Spi/MvSpiDxe.h | 1 + Platform/Marvell/Include/Protocol/Spi.h | 1 + 5 files changed, 17 insertions(+), 14 deletions(-) diff --git a/Platform/Marvell/Applications/FirmwareUpdate/FUpdate.c b/Platf= orm/Marvell/Applications/FirmwareUpdate/FUpdate.c index 750e52a..9ccb1c7 100644 --- a/Platform/Marvell/Applications/FirmwareUpdate/FUpdate.c +++ b/Platform/Marvell/Applications/FirmwareUpdate/FUpdate.c @@ -240,7 +240,7 @@ ShellCommandRunFUpdate ( ) { IN SHELL_FILE_HANDLE FileHandle; - SPI_DEVICE *Slave; + SPI_DEVICE *Slave =3D NULL; UINT64 FileSize; UINTN *FileBuffer =3D NULL; CHAR16 *ProblemParam; @@ -302,7 +302,7 @@ ShellCommandRunFUpdate ( } =20 // Setup and probe SPI flash - Slave =3D SpiMasterProtocol->SetupDevice (SpiMasterProtocol, 0, 0); + Slave =3D SpiMasterProtocol->SetupDevice (SpiMasterProtocol, Slave, 0, 0= ); if (Slave =3D=3D NULL) { Print(L"%s: Cannot allocate SPI device!\n", CMD_NAME_STRING); goto HeaderError; diff --git a/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c b/Platform= /Marvell/Applications/SpiTool/SpiFlashCmd.c index 68a6cf7..1084f68 100644 --- a/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c +++ b/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c @@ -191,7 +191,7 @@ ShellCommandRunSpiFlash ( ) { EFI_STATUS Status; - SPI_DEVICE *Slave; + STATIC SPI_DEVICE *Slave; LIST_ENTRY *CheckPackage; EFI_PHYSICAL_ADDRESS Address =3D 0, Offset =3D 0; SHELL_FILE_HANDLE FileHandle =3D NULL; @@ -273,7 +273,7 @@ EFI_STATUS Status; Cs =3D PcdGet32 (PcdSpiFlashCs); =20 // Setup new spi device - Slave =3D SpiMasterProtocol->SetupDevice (SpiMasterProtocol, Cs, Mode); + Slave =3D SpiMasterProtocol->SetupDevice (SpiMasterProtocol, Slave, Cs, = Mode); if (Slave =3D=3D NULL) { Print(L"sf: Cannot allocate SPI device!\n"); return SHELL_ABORTED; @@ -285,6 +285,8 @@ EFI_STATUS Status; Status =3D FlashProbe (Slave); if (EFI_ERROR(Status)) { // No supported spi flash detected + SpiMasterProtocol->FreeDevice(Slave); + Slave =3D NULL; return SHELL_ABORTED; } else { return Status; @@ -426,8 +428,6 @@ EFI_STATUS Status; break; } =20 - SpiMasterProtocol->FreeDevice(Slave); - if (EFI_ERROR (Status)) { Print (L"sf: Error while performing spi transfer\n"); return SHELL_ABORTED; diff --git a/Platform/Marvell/Drivers/Spi/MvSpiDxe.c b/Platform/Marvell/Dri= vers/Spi/MvSpiDxe.c index 3b49147..a7db5f2 100755 --- a/Platform/Marvell/Drivers/Spi/MvSpiDxe.c +++ b/Platform/Marvell/Drivers/Spi/MvSpiDxe.c @@ -296,21 +296,22 @@ SPI_DEVICE * EFIAPI MvSpiSetupSlave ( IN MARVELL_SPI_MASTER_PROTOCOL *This, + IN SPI_DEVICE *Slave, IN UINTN Cs, IN SPI_MODE Mode ) { - SPI_DEVICE *Slave; + if (!Slave) { + Slave =3D AllocateZeroPool (sizeof(SPI_DEVICE)); + if (Slave =3D=3D NULL) { + DEBUG((DEBUG_ERROR, "Cannot allocate memory\n")); + return NULL; + } =20 - Slave =3D AllocateZeroPool (sizeof(SPI_DEVICE)); - if (Slave =3D=3D NULL) { - DEBUG((DEBUG_ERROR, "Cannot allocate memory\n")); - return NULL; + Slave->Cs =3D Cs; + Slave->Mode =3D Mode; } =20 - Slave->Cs =3D Cs; - Slave->Mode =3D Mode; - SpiSetupTransfer (This, Slave); =20 return Slave; diff --git a/Platform/Marvell/Drivers/Spi/MvSpiDxe.h b/Platform/Marvell/Dri= vers/Spi/MvSpiDxe.h index 1401f62..e7e280a 100644 --- a/Platform/Marvell/Drivers/Spi/MvSpiDxe.h +++ b/Platform/Marvell/Drivers/Spi/MvSpiDxe.h @@ -125,6 +125,7 @@ SPI_DEVICE * EFIAPI MvSpiSetupSlave ( IN MARVELL_SPI_MASTER_PROTOCOL * This, + IN SPI_DEVICE *Slave, IN UINTN Cs, IN SPI_MODE Mode ); diff --git a/Platform/Marvell/Include/Protocol/Spi.h b/Platform/Marvell/Inc= lude/Protocol/Spi.h index 93a8ec0..0cf7914 100644 --- a/Platform/Marvell/Include/Protocol/Spi.h +++ b/Platform/Marvell/Include/Protocol/Spi.h @@ -87,6 +87,7 @@ typedef SPI_DEVICE * (EFIAPI *MV_SPI_SETUP_DEVICE) ( IN MARVELL_SPI_MASTER_PROTOCOL *This, + IN SPI_DEVICE *Slave, IN UINTN Cs, IN SPI_MODE Mode ); --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Fri May 3 19:15:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1509422414611117.28578096079355; Mon, 30 Oct 2017 21:00:14 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id F0F4F2034AB3E; Mon, 30 Oct 2017 20:56:14 -0700 (PDT) Received: from mail-lf0-x241.google.com (mail-lf0-x241.google.com [IPv6:2a00:1450:4010:c07::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 7C0A721CEB130 for ; Mon, 30 Oct 2017 20:56:11 -0700 (PDT) Received: by mail-lf0-x241.google.com with SMTP id a16so17420432lfk.0 for ; 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id f21sm107393lja.25.2017.10.30.20.59.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 30 Oct 2017 21:00:00 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::241; helo=mail-lf0-x241.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=YZRVkq0NbS33JIyXXwDcOEzxIcpZ4mCgqXpmT3EH+ig=; b=w3+yEmM0a0CPzX/jL0fbGbX2k8hC1Ex0PQ0w6CAA2IxbZnXiCAdBSHotahDGN7H0Z6 4PPo8WISiIqTuS5QmURh4jGV/atIiR3N3ct5xh6fZ81718SGgVpVyYqt+DhTDNEspu4/ nIyM0FB6dvgM+GuYllc/DA5kZiqw/DMnNCvD1G6fXg7xDLMM2qpe7lKMV/M0guHOrNTS uWsc5HXj5KTQ4UKNLEWLpezKzTzYpiACsY0IZ8Q3N5/7jf3ZGPyZmUiUXXL/hP8Hgu2/ I1tg37n3gVeVpRcOUgVF6X3LT5nBtG/TrC1hoN3jTTHP+VTeuqm27HT52kncaNjuW1LJ LTMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=YZRVkq0NbS33JIyXXwDcOEzxIcpZ4mCgqXpmT3EH+ig=; b=ARYlZ4STwBBfEqe194NrtCo0LScCzvo5F12txrUaHvHBNGTQsj1f71ahwaSwV53OCp ATzZZihpFBOZ5XA+0m+RF8lU8Cp4DvlCswOHHXB/9ImkewAB33R6Y33Y0NwNZZq/oU+u sMESbVBV0NBRzFz5YeMZlSkhHejStvCy0dDdNCu3P6+dlL3lWB+r98jn8l8jiJimLvOE lwBQiMOcrMGJ4eh4wS6iMiiP7yQZeias2G1tIj416AQzD0GEYat6Y6crnnsmLJCVJl31 D8OHI6rUw/XGz4fBdI0U5US6VopO9NnsnrChIXTu+DlWApbjaF0FkNh90P0EfEOluVC2 9xmA== X-Gm-Message-State: AMCzsaV4iEULzKOsR+ONWofRMEcjaqf1X9/3pa4yDHfGsEeP/HGeAxtw EcRErx6/Y17eqfPMlYtEwDiwNIpMIOg= X-Google-Smtp-Source: ABhQp+Rj2aaxb4REb9nX3fnz5heBwhbEhG84rrnmovQwFy6ttjeM9yCcxXVoUrQbETJKvjTJ8INBGg== X-Received: by 10.46.80.88 with SMTP id v24mr236142ljd.93.1509422400852; Mon, 30 Oct 2017 21:00:00 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Tue, 31 Oct 2017 04:59:34 +0100 Message-Id: <1509422375-20198-6-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509422375-20198-1-git-send-email-mw@semihalf.com> References: <1509422375-20198-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 5/6] Marvell/Drivers: MvSpiFlash: Fix bank selection for Spansion X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Spansion SPI flash devices use different command for bank selection. Update it, basing on the first byte of flash ID. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.c | 5 +++++ Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.h | 4 ++++ 2 files changed, 9 insertions(+) diff --git a/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.c b/Platform/M= arvell/Drivers/Spi/Devices/MvSpiFlash.c index 703994c..a00fc305 100755 --- a/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.c +++ b/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.c @@ -150,6 +150,11 @@ SpiFlashCmdBankaddrWrite ( { UINT8 Cmd =3D CMD_BANK_WRITE; =20 + /* Update bank selection command for Spansion */ + if (Slave->Info->Id[0] =3D=3D SPI_FLASH_MFR_SPANSION) { + Cmd =3D CMD_BANKADDR_BRWR; + } + MvSpiFlashWriteCommon (Slave, &Cmd, 1, &BankSel, 1); } =20 diff --git a/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.h b/Platform/M= arvell/Drivers/Spi/Devices/MvSpiFlash.h index 2583484..00af188 100755 --- a/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.h +++ b/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.h @@ -57,6 +57,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. #define CMD_READ_ARRAY_FAST 0x0b #define CMD_PAGE_PROGRAM 0x02 #define CMD_BANK_WRITE 0xc5 +#define CMD_BANKADDR_BRWR 0x17 #define CMD_ERASE_4K 0x20 #define CMD_ERASE_32K 0x52 #define CMD_ERASE_64K 0xd8 @@ -72,6 +73,9 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. =20 #define SPI_FLASH_16MB_BOUN 0x1000000 =20 +/* Manufacturer ID's */ +#define SPI_FLASH_MFR_SPANSION 0x01 + typedef enum { SPI_FLASH_READ_ID, SPI_FLASH_READ, // Read from SPI flash with address --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Fri May 3 19:15:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1509422418677571.0169084823037; Mon, 30 Oct 2017 21:00:18 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 38A8A21CEB136; Mon, 30 Oct 2017 20:56:15 -0700 (PDT) Received: from mail-lf0-x244.google.com (mail-lf0-x244.google.com [IPv6:2a00:1450:4010:c07::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id BDF1F21CEB130 for ; Mon, 30 Oct 2017 20:56:12 -0700 (PDT) Received: by mail-lf0-x244.google.com with SMTP id 75so17406190lfx.1 for ; Mon, 30 Oct 2017 21:00:04 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id f21sm107393lja.25.2017.10.30.21.00.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 30 Oct 2017 21:00:01 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::244; helo=mail-lf0-x244.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=gld9rqO5kswB2d11OcJqiNSai8oGSnKuOiKdMb6pREU=; b=YQWnM7MaSU3dJF7JVEq+6oQ7AttCadcm6qKtfNfnpQcDIy5sfEpUokd3ZtRp0XC1VP vZXTQl1BVKeb6E8wLq01KuqWet+LEipYYPgkRxnZkw2V4hsE1frOyWZgNi+lrgXM4U8R L6gp/NmK2aQ9hLnDjOBKvnQgmWPJxg42kZUcZFuhUMRsZkE21MUso0695c+QdsQX/kjq 22sPAYDX6dr5fcUvyrw4QiASRqFIphrN5WiaUlfwJxmxd5w90CCaNsid94qPb5zH4nsa oO5pGLtJkPRKzDBD5tarf+8sJTN8r/jhmXFGQVLqdw9GeZvP9tqf7P7NlTEfkQWaq1TR Nofg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=gld9rqO5kswB2d11OcJqiNSai8oGSnKuOiKdMb6pREU=; b=I+U7riccdJQM5jJMzzgRwSfWRpSQ24g2AE63UckPqtNStHd5j4XF6q6QMfWdP+yLrd A8fOHA/ePo5YxETs4FbGXfb+BDEBGj3XSZiV49nXBr80ek+Q/yp1ZSxnSMIc1wfZflSk dYowYjWNZ+enocu3veLeD//wsV+yvYImGXOv0YLtgxs/4CQSHO9xF9Grne+i4rLdaVR4 ppD0AR0WQJR07139f/9Z+QZQPf368tKGtzHW/zg8lltU3bacAhujW7jFykABLMvl7VwY YoRBT/xy5ePJ5jnmlR5TinkcHByQImwtPHJAycWEqek6bS99kN47nYmun0DagKzBYv8d 2QEw== X-Gm-Message-State: AMCzsaUylvAa69nmcD8Vqr9aF4B315/tztioqjm90hWKPASGsVTJy1gS uVkagt2yFqqFlipnOSKKApMfrULPMBQ= X-Google-Smtp-Source: ABhQp+TW9MEqsp2/QPG3GX2r8ENoxPxHiT/OM6dLVBppsKkOazSArImDg5+hJn2qpJtnuPdX5wpiIQ== X-Received: by 10.46.25.87 with SMTP id p84mr262515lje.67.1509422402165; Mon, 30 Oct 2017 21:00:02 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Tue, 31 Oct 2017 04:59:35 +0100 Message-Id: <1509422375-20198-7-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509422375-20198-1-git-send-email-mw@semihalf.com> References: <1509422375-20198-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 6/6] Marvell/Drivers: MvSpiDxe: Keep data in SPI_DEVICE structure X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" In the MvSpiDxe driver obtaining host register base address, controller clock and device maximum frequency directly from PCDs was done all over the code. This patch cleans up the parameters' handling and enables accessing them from SPI_DEVICE structure fields. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Drivers/Spi/MvSpiDxe.c | 48 ++++++++++++-------- Platform/Marvell/Include/Protocol/Spi.h | 2 + 2 files changed, 31 insertions(+), 19 deletions(-) diff --git a/Platform/Marvell/Drivers/Spi/MvSpiDxe.c b/Platform/Marvell/Dri= vers/Spi/MvSpiDxe.c index a7db5f2..c60a520 100755 --- a/Platform/Marvell/Drivers/Spi/MvSpiDxe.c +++ b/Platform/Marvell/Drivers/Spi/MvSpiDxe.c @@ -38,12 +38,13 @@ SPI_MASTER *mSpiMasterInstance; STATIC EFI_STATUS SpiSetBaudRate ( + IN SPI_DEVICE *Slave, IN UINT32 CpuClock, IN UINT32 MaxFreq ) { UINT32 Spr, BestSpr, Sppr, BestSppr, ClockDivider, Match, Reg, MinBaudDi= ff; - UINTN SpiRegBase =3D PcdGet32 (PcdSpiRegBase); + UINTN SpiRegBase =3D Slave->HostRegisterBaseAddress; =20 MinBaudDiff =3D 0xFFFFFFFF; BestSppr =3D 0; @@ -93,26 +94,28 @@ SpiSetBaudRate ( STATIC VOID SpiSetCs ( - UINT8 CsId + IN SPI_DEVICE *Slave ) { - UINT32 Reg, SpiRegBase =3D PcdGet32 (PcdSpiRegBase); + UINT32 Reg; + UINTN SpiRegBase =3D Slave->HostRegisterBaseAddress; =20 Reg =3D MmioRead32 (SpiRegBase + SPI_CTRL_REG); Reg &=3D ~SPI_CS_NUM_MASK; - Reg |=3D (CsId << SPI_CS_NUM_OFFSET); + Reg |=3D (Slave->Cs << SPI_CS_NUM_OFFSET); MmioWrite32 (SpiRegBase + SPI_CTRL_REG, Reg); } =20 STATIC VOID SpiActivateCs ( - UINT8 IN CsId + IN SPI_DEVICE *Slave ) { - UINT32 Reg, SpiRegBase =3D PcdGet32 (PcdSpiRegBase); + UINT32 Reg; + UINTN SpiRegBase =3D Slave->HostRegisterBaseAddress; =20 - SpiSetCs(CsId); + SpiSetCs(Slave); Reg =3D MmioRead32 (SpiRegBase + SPI_CTRL_REG); Reg |=3D SPI_CS_EN_MASK; MmioWrite32(SpiRegBase + SPI_CTRL_REG, Reg); @@ -121,10 +124,11 @@ SpiActivateCs ( STATIC VOID SpiDeactivateCs ( - VOID + IN SPI_DEVICE *Slave ) { - UINT32 Reg, SpiRegBase =3D PcdGet32 (PcdSpiRegBase); + UINT32 Reg; + UINTN SpiRegBase =3D Slave->HostRegisterBaseAddress; =20 Reg =3D MmioRead32 (SpiRegBase + SPI_CTRL_REG); Reg &=3D ~SPI_CS_EN_MASK; @@ -139,14 +143,15 @@ SpiSetupTransfer ( ) { SPI_MASTER *SpiMaster; - UINT32 Reg, SpiRegBase, CoreClock, SpiMaxFreq; + UINT32 Reg, CoreClock, SpiMaxFreq; + UINTN SpiRegBase; =20 SpiMaster =3D SPI_MASTER_FROM_SPI_MASTER_PROTOCOL (This); =20 // Initialize values from PCDs - SpiRegBase =3D PcdGet32 (PcdSpiRegBase); - CoreClock =3D PcdGet32 (PcdSpiClockFrequency); - SpiMaxFreq =3D PcdGet32 (PcdSpiMaxFrequency); + SpiRegBase =3D Slave->HostRegisterBaseAddress; + CoreClock =3D Slave->CoreClock; + SpiMaxFreq =3D Slave->MaxFreq; =20 EfiAcquireLock (&SpiMaster->Lock); =20 @@ -154,9 +159,9 @@ SpiSetupTransfer ( Reg |=3D SPI_BYTE_LENGTH; MmioWrite32 (SpiRegBase + SPI_CONF_REG, Reg); =20 - SpiSetCs(Slave->Cs); + SpiSetCs(Slave); =20 - SpiSetBaudRate (CoreClock, SpiMaxFreq); + SpiSetBaudRate (Slave, CoreClock, SpiMaxFreq); =20 Reg =3D MmioRead32 (SpiRegBase + SPI_CONF_REG); Reg &=3D ~(SPI_CPOL_MASK | SPI_CPHA_MASK | SPI_TXLSBF_MASK | SPI_RXLSBF_= MASK); @@ -194,21 +199,22 @@ MvSpiTransfer ( { SPI_MASTER *SpiMaster; UINT64 Length; - UINT32 Iterator, Reg, SpiRegBase; + UINT32 Iterator, Reg; UINT8 *DataOutPtr =3D (UINT8 *)DataOut; UINT8 *DataInPtr =3D (UINT8 *)DataIn; UINT8 DataToSend =3D 0; + UINTN SpiRegBase; =20 SpiMaster =3D SPI_MASTER_FROM_SPI_MASTER_PROTOCOL (This); =20 - SpiRegBase =3D PcdGet32 (PcdSpiRegBase); + SpiRegBase =3D Slave->HostRegisterBaseAddress; =20 Length =3D 8 * DataByteCount; =20 EfiAcquireLock (&SpiMaster->Lock); =20 if (Flag & SPI_TRANSFER_BEGIN) { - SpiActivateCs (Slave->Cs); + SpiActivateCs (Slave); } =20 // Set 8-bit mode @@ -245,7 +251,7 @@ MvSpiTransfer ( } =20 if (Flag & SPI_TRANSFER_END) { - SpiDeactivateCs (); + SpiDeactivateCs (Slave); } =20 EfiReleaseLock (&SpiMaster->Lock); @@ -312,6 +318,10 @@ MvSpiSetupSlave ( Slave->Mode =3D Mode; } =20 + Slave->HostRegisterBaseAddress =3D PcdGet32 (PcdSpiRegBase); + Slave->CoreClock =3D PcdGet32 (PcdSpiClockFrequency); + Slave->MaxFreq =3D PcdGet32 (PcdSpiMaxFrequency); + SpiSetupTransfer (This, Slave); =20 return Slave; diff --git a/Platform/Marvell/Include/Protocol/Spi.h b/Platform/Marvell/Inc= lude/Protocol/Spi.h index 0cf7914..b8981f3 100644 --- a/Platform/Marvell/Include/Protocol/Spi.h +++ b/Platform/Marvell/Include/Protocol/Spi.h @@ -52,6 +52,8 @@ typedef struct { INTN MaxFreq; SPI_MODE Mode; NOR_FLASH_INFO *Info; + UINTN HostRegisterBaseAddress; + UINTN CoreClock; } SPI_DEVICE; =20 typedef --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel