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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id r22sm513129ljr.16.2017.10.24.23.46.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 24 Oct 2017 23:46:43 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::241; helo=mail-lf0-x241.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=qZ+h2MPyUS32AeRZekIxNmJznIldLjpejjkh+JDaO3Q=; b=gvGTybLxrxJy54mx1z1DB9af18hLaJUqohIFKPJWoB7ktirpCP/lVo3IiU4pFxBkuv NeKDHZCXZDDA5QCC1uvNsmblf+2qOQlwr6I0ICiegOE049jNAd6IWoTKGZ8W3Cq8yZGv Y17I6sDnA6F6z0JCJryDH2oThSYJG+DPR52qxMFbTSqhfFHBp1bHcMCcWE7vbeqatOOP AuafcEPghAvLqlrj5r+KZMuWR8iHlM9XPQ1x1gOL28N7moW0tXDlJsKaSJMqeCFhfchA 9de8ybcuW9YsB6GU9lLX0HuV8HbzMXliOEZ0WrWFqhfrmMg0fWwDGDz2B7k4MNfbYFvT U3vg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=qZ+h2MPyUS32AeRZekIxNmJznIldLjpejjkh+JDaO3Q=; b=mHbH01qDEOGTaiI2coQw++WAQ4QvUh82Y9lqZEHvcnq8vm7SeTmiwD0xikMr7yry8w XlR933mxlnZCXynlQ+Ubp/mhmF8Lp67H/mXFGfIUsQJIAwJZEOXAIxKHAQs39rN9qKhc 1B64SR39LZtXpSv1d90ntg0pSKSwIF3sWHZVibMfgIPk6R7uRid/k5ny3vn75QTH7x2+ p47LqRdOgRQEJUQ7ZtVmHj3m8dfRhUoYm9lZqA9jaWD/bX2JMwVcjtJg9fwp3K4UvRJY VLlkN/0r04D6dm7oxyPbtPOtDVbbKTuttKYGqMlD/XyVDkUKMbu7fhp3m7lrsWRcf+GE NXaQ== X-Gm-Message-State: AMCzsaUvT9Me6LoWVCAXlKB6phx1EyEjGP6agnm891GpoCxQuKnnwpzs tFNqp8jJjmhbQfH/LhxDS8m/dp+Hc6U= X-Google-Smtp-Source: ABhQp+Q036IWGnFSPdk78UoM/GkpWbqMeTBVQlgbxYF7GEF+w68ZM9pERy8d+k98PKaGvL+70Tedyg== X-Received: by 10.46.9.197 with SMTP id 188mr7600424ljj.134.1508914004326; Tue, 24 Oct 2017 23:46:44 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Wed, 25 Oct 2017 08:45:23 +0200 Message-Id: <1508913930-30886-2-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1508913930-30886-1-git-send-email-mw@semihalf.com> References: <1508913930-30886-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 1/8] Marvell/Armada: Implement EFI_RNG_PROTOCOL driver for EIP76 TRNG X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Ard Biesheuvel Add an implementation of EFI_RNG_PROTOCOL so that the OS loader has access to entropy for KASLR and other purposes (i.e., seeding the OS's entropy pool very early on). Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Armada/Armada.dsc.inc | = 4 + Platform/Marvell/Armada/Armada70x0.fdf | = 1 + Platform/Marvell/Armada/Drivers/Armada70x0RngDxe/Armada70x0RngDxe.c | 25= 5 ++++++++++++++++++++ Platform/Marvell/Armada/Drivers/Armada70x0RngDxe/Armada70x0RngDxe.inf | 4= 7 ++++ Platform/Marvell/Marvell.dec | = 3 + 5 files changed, 310 insertions(+) diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Arma= da/Armada.dsc.inc index 1aa485c..ec24d76 100644 --- a/Platform/Marvell/Armada/Armada.dsc.inc +++ b/Platform/Marvell/Armada/Armada.dsc.inc @@ -364,6 +364,9 @@ gArmTokenSpaceGuid.PcdSystemMemorySize|0x40000000 gArmTokenSpaceGuid.PcdArmScr|0x531 =20 + # TRNG + gMarvellTokenSpaceGuid.PcdEip76TrngBaseAddress|0xF2760000 + ##########################################################################= ###### # # Components Section - list of all EDK II Modules needed by this Platform @@ -400,6 +403,7 @@ Platform/Marvell/Drivers/I2c/Devices/MvEeprom/MvEeprom.inf Platform/Marvell/Drivers/Spi/MvSpiDxe.inf Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.inf + Platform/Marvell/Armada/Drivers/Armada70x0RngDxe/Armada70x0RngDxe.inf =20 # Network support MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf diff --git a/Platform/Marvell/Armada/Armada70x0.fdf b/Platform/Marvell/Arma= da/Armada70x0.fdf index 933c3ed..a94a9ff 100644 --- a/Platform/Marvell/Armada/Armada70x0.fdf +++ b/Platform/Marvell/Armada/Armada70x0.fdf @@ -113,6 +113,7 @@ FvNameGuid =3D 5eda4200-2c5f-43cb-9da3-0baf74b1= b30c INF Platform/Marvell/Drivers/I2c/Devices/MvEeprom/MvEeprom.inf INF Platform/Marvell/Drivers/Spi/MvSpiDxe.inf INF Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.inf + INF Platform/Marvell/Armada/Drivers/Armada70x0RngDxe/Armada70x0RngDxe.inf =20 # Network support INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf diff --git a/Platform/Marvell/Armada/Drivers/Armada70x0RngDxe/Armada70x0Rng= Dxe.c b/Platform/Marvell/Armada/Drivers/Armada70x0RngDxe/Armada70x0RngDxe.c new file mode 100644 index 0000000..014443d --- /dev/null +++ b/Platform/Marvell/Armada/Drivers/Armada70x0RngDxe/Armada70x0RngDxe.c @@ -0,0 +1,255 @@ +/** @file + + This driver produces an EFI_RNG_PROTOCOL instance for the Armada 70x0 TR= NG + + Copyright (C) 2017, Linaro Ltd. All rights reserved.
+ + This program and the accompanying materials are licensed and made availa= ble + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WI= THOUT + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include +#include +#include +#include + +#include + +#define TRNG_OUTPUT_REG mTrngBaseAddress +#define TRNG_OUTPUT_SIZE 0x10 + +#define TRNG_STATUS_REG (mTrngBaseAddress + 0x10) +#define TRNG_STATUS_READY BIT0 + +#define TRNG_INTACK_REG (mTrngBaseAddress + 0x10) +#define TRNG_INTACK_READY BIT0 + +#define TRNG_CONTROL_REG (mTrngBaseAddress + 0x14) +#define TRNG_CONTROL_REG_ENABLE BIT10 + +#define TRNG_CONFIG_REG (mTrngBaseAddress + 0x18) +#define __MIN_REFILL_SHIFT 0 +#define __MAX_REFILL_SHIFT 16 +#define TRNG_CONFIG_MIN_REFILL_CYCLES (0x05 << __MIN_REFILL_SHIF= T) +#define TRNG_CONFIG_MAX_REFILL_CYCLES (0x22 << __MAX_REFILL_SHIF= T) + +#define TRNG_FRODETUNE_REG (mTrngBaseAddress + 0x24) +#define TRNG_FRODETUNE_MASK 0x0 + +#define TRNG_FROENABLE_REG (mTrngBaseAddress + 0x20) +#define TRNG_FROENABLE_MASK 0xffffff + +#define TRNG_MAX_RETRIES 20 + +STATIC EFI_PHYSICAL_ADDRESS mTrngBaseAddress; + +/** + Returns information about the random number generation implementation. + + @param[in] This A pointer to the EFI_RNG_PROTOCOL + instance. + @param[in,out] RNGAlgorithmListSize On input, the size in bytes of + RNGAlgorithmList. + On output with a return code of + EFI_SUCCESS, the size in bytes of the + data returned in RNGAlgorithmList. On + output with a return code of + EFI_BUFFER_TOO_SMALL, the size of + RNGAlgorithmList required to obtain = the + list. + @param[out] RNGAlgorithmList A caller-allocated memory buffer fil= led + by the driver with one EFI_RNG_ALGOR= ITHM + element for each supported RNG algor= ithm. + The list must not change across mult= iple + calls to the same driver. The first + algorithm in the list is the default + algorithm for the driver. + + @retval EFI_SUCCESS The RNG algorithm list was returned + successfully. + @retval EFI_UNSUPPORTED The services is not supported by this + driver. + @retval EFI_DEVICE_ERROR The list of algorithms could not be + retrieved due to a hardware or firmw= are + error. + @retval EFI_INVALID_PARAMETER One or more of the parameters are + incorrect. + @retval EFI_BUFFER_TOO_SMALL The buffer RNGAlgorithmList is too s= mall + to hold the result. + +**/ +STATIC +EFI_STATUS +EFIAPI +Armada70x0RngGetInfo ( + IN EFI_RNG_PROTOCOL *This, + IN OUT UINTN *RNGAlgorithmListSize, + OUT EFI_RNG_ALGORITHM *RNGAlgorithmList + ) +{ + if (This =3D=3D NULL || RNGAlgorithmListSize =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + if (*RNGAlgorithmListSize < sizeof (EFI_RNG_ALGORITHM)) { + *RNGAlgorithmListSize =3D sizeof (EFI_RNG_ALGORITHM); + return EFI_BUFFER_TOO_SMALL; + } + + if (RNGAlgorithmList =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + *RNGAlgorithmListSize =3D sizeof (EFI_RNG_ALGORITHM); + CopyGuid (RNGAlgorithmList, &gEfiRngAlgorithmRaw); + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +GetTrngData ( + IN UINTN Length, + OUT UINT8 *Bits + ) +{ + UINTN Tries; + UINT32 Buf[TRNG_OUTPUT_SIZE / sizeof (UINT32)]; + UINTN Index; + + for (Tries =3D 0; Tries < TRNG_MAX_RETRIES; Tries++) { + if (MmioRead32 (TRNG_STATUS_REG) & TRNG_STATUS_READY) { + for (Index =3D 0; Index < ARRAY_SIZE (Buf); Index++) { + Buf[Index] =3D MmioRead32 (TRNG_OUTPUT_REG + Index * sizeof (UINT3= 2)); + } + CopyMem (Bits, Buf, Length); + MmioWrite32 (TRNG_INTACK_REG, TRNG_INTACK_READY); + + return EFI_SUCCESS; + } + // Wait for more TRNG data to arrive + gBS->Stall (10); + } + return EFI_DEVICE_ERROR; +} + +/** + Produces and returns an RNG value using either the default or specified = RNG + algorithm. + + @param[in] This A pointer to the EFI_RNG_PROTOCOL + instance. + @param[in] RNGAlgorithm A pointer to the EFI_RNG_ALGORITHM t= hat + identifies the RNG algorithm to use.= May + be NULL in which case the function w= ill + use its default RNG algorithm. + @param[in] RNGValueLength The length in bytes of the memory bu= ffer + pointed to by RNGValue. The driver s= hall + return exactly this numbers of bytes. + @param[out] RNGValue A caller-allocated memory buffer fil= led + by the driver with the resulting RNG + value. + + @retval EFI_SUCCESS The RNG value was returned successfu= lly. + @retval EFI_UNSUPPORTED The algorithm specified by RNGAlgori= thm + is not supported by this driver. + @retval EFI_DEVICE_ERROR An RNG value could not be retrieved = due + to a hardware or firmware error. + @retval EFI_NOT_READY There is not enough random data avai= lable + to satisfy the length requested by + RNGValueLength. + @retval EFI_INVALID_PARAMETER RNGValue is NULL or RNGValueLength is + zero. + +**/ +STATIC +EFI_STATUS +EFIAPI +Armada70x0RngGetRNG ( + IN EFI_RNG_PROTOCOL *This, + IN EFI_RNG_ALGORITHM *RNGAlgorithm, OPTIONAL + IN UINTN RNGValueLength, + OUT UINT8 *RNGValue + ) +{ + UINTN Length; + EFI_STATUS Status; + + if (This =3D=3D NULL || RNGValueLength =3D=3D 0 || RNGValue =3D=3D NULL)= { + return EFI_INVALID_PARAMETER; + } + + // + // We only support the raw algorithm, so reject requests for anything el= se + // + if (RNGAlgorithm !=3D NULL && + !CompareGuid (RNGAlgorithm, &gEfiRngAlgorithmRaw)) { + return EFI_UNSUPPORTED; + } + + do { + Length =3D MIN (RNGValueLength, TRNG_OUTPUT_SIZE); + Status =3D GetTrngData (Length, RNGValue); + if (EFI_ERROR (Status)) { + return Status; + } + + RNGValue +=3D Length; + RNGValueLength -=3D Length; + } while (RNGValueLength > 0); + + return EFI_SUCCESS; +} + +STATIC EFI_RNG_PROTOCOL mArmada70x0RngProtocol =3D { + Armada70x0RngGetInfo, + Armada70x0RngGetRNG +}; + +// +// Entry point of this driver. +// +EFI_STATUS +EFIAPI +Armada70x0RngDxeEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + mTrngBaseAddress =3D PcdGet64 (PcdEip76TrngBaseAddress); + + // + // Disable the TRNG before updating its configuration + // + MmioAnd32 (TRNG_CONTROL_REG, ~TRNG_CONTROL_REG_ENABLE); + + // + // Configure the internal conditioning parameters of the TRNG + // + MmioWrite32 (TRNG_CONFIG_REG, TRNG_CONFIG_MIN_REFILL_CYCLES | + TRNG_CONFIG_MAX_REFILL_CYCLES); + + // + // Configure the FROs + // + MmioWrite32 (TRNG_FRODETUNE_REG, TRNG_FRODETUNE_MASK); + MmioWrite32 (TRNG_FROENABLE_REG, TRNG_FROENABLE_MASK); + + // + // Enable the TRNG + // + MmioOr32 (TRNG_CONTROL_REG, TRNG_CONTROL_REG_ENABLE); + + return SystemTable->BootServices->InstallMultipleProtocolInterfaces ( + &ImageHandle, + &gEfiRngProtocolGuid, + &mArmada70x0RngProtocol, + NULL + ); +} diff --git a/Platform/Marvell/Armada/Drivers/Armada70x0RngDxe/Armada70x0Rng= Dxe.inf b/Platform/Marvell/Armada/Drivers/Armada70x0RngDxe/Armada70x0RngDxe= .inf new file mode 100644 index 0000000..189ffc5 --- /dev/null +++ b/Platform/Marvell/Armada/Drivers/Armada70x0RngDxe/Armada70x0RngDxe.inf @@ -0,0 +1,47 @@ +## @file +# This driver produces an EFI_RNG_PROTOCOL instance for the Armada 70x0 TR= NG +# +# Copyright (C) 2017, Linaro Ltd. All rights reserved.
+# +# This program and the accompanying materials are licensed and made availa= ble +# under the terms and conditions of the BSD License which accompanies this +# distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WI= THOUT +# WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +[Defines] + INF_VERSION =3D 0x00010019 + BASE_NAME =3D Armada70x0RngDxe + FILE_GUID =3D dd87096a-cae5-4328-bec1-2ddb755f2e08 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D Armada70x0RngDxeEntryPoint + +[Sources] + Armada70x0RngDxe.c + +[Packages] + MdePkg/MdePkg.dec + Platform/Marvell/Marvell.dec + +[LibraryClasses] + BaseMemoryLib + IoLib + PcdLib + UefiDriverEntryPoint + +[Pcd] + gMarvellTokenSpaceGuid.PcdEip76TrngBaseAddress + +[Protocols] + gEfiRngProtocolGuid ## PRODUCES + +[Guids] + gEfiRngAlgorithmRaw + +[Depex] + TRUE diff --git a/Platform/Marvell/Marvell.dec b/Platform/Marvell/Marvell.dec index e7d7c2c..78f5e53 100644 --- a/Platform/Marvell/Marvell.dec +++ b/Platform/Marvell/Marvell.dec @@ -195,6 +195,9 @@ #RTC gMarvellTokenSpaceGuid.PcdRtcEnabled|{ 0x0 }|VOID*|0x40000052 =20 +#TRNG + gMarvellTokenSpaceGuid.PcdEip76TrngBaseAddress|0x0|UINT64|0x50000053 + [Protocols] gMarvellEepromProtocolGuid =3D { 0x71954bda, 0x60d3, 0x4ef= 8, { 0x8e, 0x3c, 0x0e, 0x33, 0x9f, 0x3b, 0xc2, 0x2b }} gMarvellMdioProtocolGuid =3D { 0x40010b03, 0x5f08, 0x496= a, { 0xa2, 0x64, 0x10, 0x5e, 0x72, 0xd3, 0x71, 0xaa }} --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Tue Apr 30 18:31:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1508914012159791.4794563334837; Tue, 24 Oct 2017 23:46:52 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id EDB3A2034C08E; Tue, 24 Oct 2017 23:43:03 -0700 (PDT) Received: from mail-lf0-x244.google.com (mail-lf0-x244.google.com [IPv6:2a00:1450:4010:c07::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 9D09520347156 for ; Tue, 24 Oct 2017 23:43:02 -0700 (PDT) Received: by mail-lf0-x244.google.com with SMTP id r129so26604911lff.8 for ; Tue, 24 Oct 2017 23:46:47 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id r22sm513129ljr.16.2017.10.24.23.46.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 24 Oct 2017 23:46:44 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::244; helo=mail-lf0-x244.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=bw9zy9yieNoTfW1BPNPxav+fo9hiHlUkZA7MDuePoYo=; b=piFC+lMY6MWJFe3BiS6BL4qjszv5CNh/PztKn4FOU0StkerRbrllKiZ+tNHvY6RQFQ /QlbwcHmlZ6pKDZsccuRrfM/RhTsG3GPyxv7p4EzpdifV0Wdny2oLLMH1UBmzlz8Hofs U65tRb6vUX3QM7wsFmNRYyOodsvnHWDa8ksbP+WAtY+/R72/p26h9aeSBc0hZm92IDUS wfhuPbLaUQqWDth00vjV5qx7sGvK7SRZtvaZa90FJjtxjkBUPYUcqTCKtmfddDyHA6es rGII4+PBMibF/4nd9x2FLhIBSNJYWTBOFxS9jK4q/mL7lKfnN11rxwGc6QOmt6zhensd 6mVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=bw9zy9yieNoTfW1BPNPxav+fo9hiHlUkZA7MDuePoYo=; b=pIcI8osI0CIvA6h1ffLIq6mKtTtQm47dEnwSwzWOU4jZXByf71W8ytaPBpSzUKUIml +4yEQc25C0Qz5KLmtTAzbC5tDF0iVX2c2uitSrxEg/R3hK5dYjpjEKgWFMsx5y5Bpxlf R9vAvSvuYZFjYYO4sJXvdzaYwBqwJDTO94BKteyxI/NMyZV0W1Kp23KyF7MExcN88biw buxSPPhz913Zp9APTHc0cw7uBTSX1SiyXByOs0a/sWVZEkz9HdEYsyCOpNcQSekwUALw wkJrmtU5iBH+HFdbUztXqgrSd0D+vAL+M8vTEhkwo03oXb0BgRgFEwJxu0ws/Qki4I7B FDFg== X-Gm-Message-State: AMCzsaVKUACpmrKmeo1YPHhgImaQH1oZPOznu8dGz+vW/K6HoHNZ7FXV tE5lqeD6KG4jwg1nQY9fv3s414LEEX8= X-Google-Smtp-Source: ABhQp+TxOYxuCTjoWG5PAn1GPGhjADhJN+6juakWCjioofeOTMBTXJUq6l/uV55t26+pMZi5RXiZGg== X-Received: by 10.46.0.222 with SMTP id e91mr7620586lji.64.1508914005524; Tue, 24 Oct 2017 23:46:45 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Wed, 25 Oct 2017 08:45:24 +0200 Message-Id: <1508913930-30886-3-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1508913930-30886-1-git-send-email-mw@semihalf.com> References: <1508913930-30886-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 2/8] Marvell/Armada: Increase preallocated memory region size X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Ard Biesheuvel In order to prevent fragmentation of the UEFI memory map, increase the sizes of the preallocated regions. Note that this does not increase the memory footprint of UEFI, it just modifies it allocation policy to keep similar region types together. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Armada/Armada.dsc.inc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Arma= da/Armada.dsc.inc index ec24d76..56d8941 100644 --- a/Platform/Marvell/Armada/Armada.dsc.inc +++ b/Platform/Marvell/Armada/Armada.dsc.inc @@ -341,10 +341,10 @@ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0 gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0 gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0 - gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|50 - gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|20 - gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|400 - gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|20000 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|1000 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|1000 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|2000 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|35000 gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|20 gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0 =20 --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Tue Apr 30 18:31:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1508914015155774.502957868018; Tue, 24 Oct 2017 23:46:55 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 38A2E2034C0A0; Tue, 24 Oct 2017 23:43:07 -0700 (PDT) Received: from mail-lf0-x243.google.com (mail-lf0-x243.google.com [IPv6:2a00:1450:4010:c07::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 341982034C084 for ; Tue, 24 Oct 2017 23:43:04 -0700 (PDT) Received: by mail-lf0-x243.google.com with SMTP id n69so26594753lfn.2 for ; Tue, 24 Oct 2017 23:46:48 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id r22sm513129ljr.16.2017.10.24.23.46.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 24 Oct 2017 23:46:46 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::243; helo=mail-lf0-x243.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=koqQ86E8EpEqm1v930P0TQ2Hg80RsbC5nIG5QxQCMcc=; b=YaU60E4xbDg25DFPTmyokVlMGOL4Gm94AEz9cxX3FEPwBfXZBhGcYhVQvU5+w3176N Vly6/U8cLgZx54WCtlbbwdFcf5XZxduhWDsifSZvQAUMDGM6kEOwHN87yNYULinSpRaZ suWBQhvtAYPU5wER2FILvORlUoDDjauz0aZLudsu1+NDCeTJT7q2+UhvGLA6+xDR4qd7 FQAPwdrX5T0PaEHTDlcC6zrBB+sZs6JrJrZdpRJv6o6WO1uVerjwgjfk6pKe92eddq2D /LJBb++NGZA8o6LlhjO1GpO2gvSO4Xuzs2/g9Dbj0BrFS7+BgdBIw/BYXM/ZkBpEhP/Q ZnLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=koqQ86E8EpEqm1v930P0TQ2Hg80RsbC5nIG5QxQCMcc=; b=pc7gW9LU5p8YO6uOlbFJuXdpZaqwy9tLWvGtq0nY/jzuoBD8xpSk0Hs4yPbQopsvLf g3Eu57LNChPSr5GHEGiFVvtD8Fyphbp676g7rCTSzXXfzcl7LqEvVAh43DCq0+gziSa1 /Xys7rogsQlnHP4uJBUD9TiXYXcSWMbiccFu3WNXKD5vmt6T2w2O5RW+TED8KrHeua7o rg4mXpLUODm9eodYuAt9paWcvZQg7j1bwkfSQUIyB/8wXIdtMVkHNnazaIwvj2RAkFuU zk4g6/S+/def0SVTcHI/McGx9OfZTfQjtzJSxhXGIrJnquBek5vhjWT183T0qRITMZGk L+Qw== X-Gm-Message-State: AMCzsaWM4H8GqmKnmZoX9GOOf1oRi3tX2BSrM5VrAfGMiGK6cF11bIVe LPMp9v4GcvAsTjf9KTF0DZGq8ItawFY= X-Google-Smtp-Source: ABhQp+R4p3OxtqqJNGQWlgmNFu7agHqx2iz6HYPWGco4d/qq0uLmEtARLwzt9ZamvFGjl0zDVi7Sdg== X-Received: by 10.46.16.155 with SMTP id 27mr6684743ljq.169.1508914006921; Tue, 24 Oct 2017 23:46:46 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Wed, 25 Oct 2017 08:45:25 +0200 Message-Id: <1508913930-30886-4-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1508913930-30886-1-git-send-email-mw@semihalf.com> References: <1508913930-30886-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 3/8] Marvell/Armada: Remove custom reset library residues X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" When switching to generic PSCI reset library, obsolete parts of previous custom reset library (PCDs, documentation) remained. Remove them. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Armada/Armada70x0.dsc | 4 ---- Platform/Marvell/Marvell.dec | 4 ---- Silicon/Marvell/Documentation/PortingGuide.txt | 9 --------- 3 files changed, 17 deletions(-) diff --git a/Platform/Marvell/Armada/Armada70x0.dsc b/Platform/Marvell/Arma= da/Armada70x0.dsc index 430803c..946c93e 100644 --- a/Platform/Marvell/Armada/Armada70x0.dsc +++ b/Platform/Marvell/Armada/Armada70x0.dsc @@ -138,9 +138,5 @@ gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x0 } gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 } =20 - #ResetLib - gMarvellTokenSpaceGuid.PcdResetRegAddress|0xf06f0084 - gMarvellTokenSpaceGuid.PcdResetRegMask|0x1 - #RTC gMarvellTokenSpaceGuid.PcdRtcEnabled|{ 0x1 } diff --git a/Platform/Marvell/Marvell.dec b/Platform/Marvell/Marvell.dec index 78f5e53..434d6cb 100644 --- a/Platform/Marvell/Marvell.dec +++ b/Platform/Marvell/Marvell.dec @@ -188,10 +188,6 @@ gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x0 }|VOID*|0x3000034 gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x0 }|VOID*|0x3000035 =20 -#ResetLib - gMarvellTokenSpaceGuid.PcdResetRegAddress|0|UINT64|0x40000050 - gMarvellTokenSpaceGuid.PcdResetRegMask|0|UINT32|0x4000051 - #RTC gMarvellTokenSpaceGuid.PcdRtcEnabled|{ 0x0 }|VOID*|0x40000052 =20 diff --git a/Silicon/Marvell/Documentation/PortingGuide.txt b/Silicon/Marve= ll/Documentation/PortingGuide.txt index 66ec918..cbe3bed 100644 --- a/Silicon/Marvell/Documentation/PortingGuide.txt +++ b/Silicon/Marvell/Documentation/PortingGuide.txt @@ -383,15 +383,6 @@ Set pin 6 and 7 to 0xa function: gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0xa, 0xa, 0x0, 0x0 } =20 =20 -MarvellResetSystemLib configuration -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D -This simple library allows to mask given bits in given reg at UEFI 'reset' -command call. These variables are configurable through PCDs: - - - gMarvellTokenSpaceGuid.PcdResetRegAddress - - gMarvellTokenSpaceGuid.PcdResetRegMask - - Ramdisk configuration =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D There is one PCD available for Ramdisk configuration --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Tue Apr 30 18:31:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1508914018270805.5308896718327; Tue, 24 Oct 2017 23:46:58 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 6EDE42034CF6B; Tue, 24 Oct 2017 23:43:07 -0700 (PDT) Received: from mail-lf0-x242.google.com (mail-lf0-x242.google.com [IPv6:2a00:1450:4010:c07::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 6DA272034A7D9 for ; Tue, 24 Oct 2017 23:43:05 -0700 (PDT) Received: by mail-lf0-x242.google.com with SMTP id 90so26573333lfs.13 for ; Tue, 24 Oct 2017 23:46:50 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id r22sm513129ljr.16.2017.10.24.23.46.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 24 Oct 2017 23:46:47 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::242; helo=mail-lf0-x242.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=fSiALgDxzjIwSV+SS/N/XkqOKFk0+5z7Evdfyp9yh+A=; b=XyG+xSIBbLfqm7DjOhP2GQlmfRYM/nS0mCGVVGZKGPWshN6JCTXu4kmQ+RZ3bRrk0+ CUHx1ONa3UCr5k9teLmohHwj1k8qt68qBcahMoVwWDcHPdxe5LyE2rKqQIloBbZmd2pC +HEQUT3iwEeT4BJrNmvcT6W4CM+g8fl7sW0uUXA2VzGv1SIAGZFVjibTBJR1kRyW62J7 akxsJSaVlCGjv6PewS/kM+/Os+Oa7sIVdV4BZgi6KyNRLUchYuOokYaFEVnxfSFhCW7W IpJ0dGpTWDX7YE576xcf+POON54SgPzJdMP1TyQvFYHtQ4MRjsZBy3TTiqlVtgCBIMoT HDmg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=fSiALgDxzjIwSV+SS/N/XkqOKFk0+5z7Evdfyp9yh+A=; b=ib3xGUo5bxOtF98BG7/6tB5vLX9ehBo9F31QgbQLuohaB2xL/OcfVXRLjzxZ9IT4kY Pmix0VBcSzTXuRZLz4Bb0WjbX8U/6TeHjZQqz+1Fg8B/JiUjuffHRdFZBX3gWW9fsWSw R82ao9hTw4VtmBjUWau76Vb5re7WNdOgMGC1/+pU1MpFlUq6L1dxmD7eu4AAswTRyiuo j0mYMTInfYETBIulWfR6Ld+T+rFXPyERu3RZ90isvAKmJUs0RTPJQRTC2LNqQ1jQW2EQ OXlU7rvS7IRQiOcVq0a1jLQiRZ8nVtpNFq9vaJxIzIf9E8/DRgaGs29aRtQO8Zp2bYT6 Nc4Q== X-Gm-Message-State: AMCzsaX44v4qI1YKrUGQA54tejdCclt3YjaUD/43+U75qBEp0OoqbkY9 2uiNRqvW3Hoswv/6Ebpv5Fk97iPrKdA= X-Google-Smtp-Source: ABhQp+Ts7c+8HXYcUyl+oPdN610S8EirKV6gXwOF3lLaUq0nK4W4qHqV04+h1a1uZdMZ0k+TNH5MEQ== X-Received: by 10.46.71.77 with SMTP id u74mr8193730lja.79.1508914008206; Tue, 24 Oct 2017 23:46:48 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Wed, 25 Oct 2017 08:45:26 +0200 Message-Id: <1508913930-30886-5-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1508913930-30886-1-git-send-email-mw@semihalf.com> References: <1508913930-30886-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 4/8] Marvell/Armada: Add support from DRAM remapping X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" The Armada 70x0/80x0 DRAM controller allows a single window of DRAM to be remapped to another location in the physical address space. This allows us to free up some memory in the 32-bit addressable region for peripheral MMIO and PCI MMIO32 and CONFIG spaces. This patch adjusts memory blocks to the configuration done in ARM-TF. The remap parameters are otained directly from the registers. Moreover, the configuration space base address is now configurable via PCD, so that to satisfy a case, when remap is not enabled in the early firmware and ensure, that PcdSystemMemorySize is not overlapping it. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Signed-off-by: Ard Biesheuvel --- Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf | 2 + Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c | 90 ++++= +++++++++++----- Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.h | 48 ++++= +++++++ Platform/Marvell/Marvell.dec | 3 + 4 files changed, 124 insertions(+), 19 deletions(-) diff --git a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.in= f b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf index 2e198c3..2236d9f 100644 --- a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf +++ b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf @@ -67,5 +67,7 @@ gArmTokenSpaceGuid.PcdArmPrimaryCoreMask gArmTokenSpaceGuid.PcdArmPrimaryCore =20 + gMarvellTokenSpaceGuid.PcdConfigSpaceBaseAddress + [Ppis] gArmMpCoreInfoPpiGuid diff --git a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem= .c b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c index 74c9956..978e4d3 100644 --- a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c +++ b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c @@ -35,8 +35,12 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAM= AGE. #include #include #include +#include +#include #include =20 +#include "Armada70x0LibMem.h" + // The total number of descriptors, including the final "end-of-table" des= criptor. #define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 16 =20 @@ -44,6 +48,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. #define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_NONSEC= URE_WRITE_BACK #define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACH= ED_UNBUFFERED =20 +STATIC ARM_MEMORY_REGION_DESCRIPTOR mVirtualMemoryTable[MAX_VIRTUAL_MEMORY= _MAP_DESCRIPTORS]; + /** Return the Virtual Memory Map of your platform =20 @@ -59,35 +65,81 @@ ArmPlatformGetVirtualMemoryMap ( IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap ) { - ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; UINTN Index =3D 0; + UINT64 MemSize; + UINT64 MemLowSize; + UINT64 MemHighStart; + UINT64 MemHighSize; + UINT64 ConfigSpaceBaseAddr; + EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes; =20 ASSERT (VirtualMemoryMap !=3D NULL); =20 - VirtualMemoryTable =3D (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_= SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MA= P_DESCRIPTORS)); - if (VirtualMemoryTable =3D=3D NULL) { - return; + ConfigSpaceBaseAddr =3D FixedPcdGet64 (PcdConfigSpaceBaseAddress); + + MemSize =3D FixedPcdGet64 (PcdSystemMemorySize); + + if (DRAM_REMAP_ENABLED) { + MemLowSize =3D MIN (DRAM_REMAP_TARGET, MemSize); + MemHighStart =3D (UINT64)DRAM_REMAP_TARGET + DRAM_REMAP_SIZE; + MemHighSize =3D MemSize - MemLowSize; + } else { + MemLowSize =3D MIN (ConfigSpaceBaseAddr, MemSize); } =20 - // DDR - VirtualMemoryTable[Index].PhysicalBase =3D PcdGet64 (PcdSystemMemoryB= ase); - VirtualMemoryTable[Index].VirtualBase =3D PcdGet64 (PcdSystemMemoryB= ase); - VirtualMemoryTable[Index].Length =3D PcdGet64 (PcdSystemMemoryS= ize); - VirtualMemoryTable[Index].Attributes =3D DDR_ATTRIBUTES_CACHED; + ResourceAttributes =3D ( + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED + ); + + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + ResourceAttributes, + FixedPcdGet64 (PcdSystemMemoryBase), + MemLowSize + ); =20 - // Configuration space 0xF000_0000 - 0xFFFF_FFFF - VirtualMemoryTable[++Index].PhysicalBase =3D 0xF0000000; - VirtualMemoryTable[Index].VirtualBase =3D 0xF0000000; - VirtualMemoryTable[Index].Length =3D 0x10000000; - VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; + // DDR + mVirtualMemoryTable[Index].PhysicalBase =3D FixedPcdGet64 (PcdSystemM= emoryBase); + mVirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdSystemM= emoryBase); + mVirtualMemoryTable[Index].Length =3D MemLowSize; + mVirtualMemoryTable[Index].Attributes =3D DDR_ATTRIBUTES_CACHED; + + // Configuration space + mVirtualMemoryTable[++Index].PhysicalBase =3D ConfigSpaceBaseAddr; + mVirtualMemoryTable[Index].VirtualBase =3D ConfigSpaceBaseAddr; + mVirtualMemoryTable[Index].Length =3D SIZE_4GB - ConfigSpaceBas= eAddr; + mVirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBU= TE_DEVICE; + + if (MemSize > MemLowSize) { + // + // If we have more than MemLowSize worth of DRAM, the remainder will be + // mapped at the top of the remapped window. + // + mVirtualMemoryTable[++Index].PhysicalBase =3D MemHighStart; + mVirtualMemoryTable[Index].VirtualBase =3D MemHighStart; + mVirtualMemoryTable[Index].Length =3D MemHighSize; + mVirtualMemoryTable[Index].Attributes =3D DDR_ATTRIBUTES_CACHED; + + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + ResourceAttributes, + MemHighStart, + MemHighSize + ); + } =20 // End of Table - VirtualMemoryTable[++Index].PhysicalBase =3D 0; - VirtualMemoryTable[Index].VirtualBase =3D 0; - VirtualMemoryTable[Index].Length =3D 0; - VirtualMemoryTable[Index].Attributes =3D 0; + mVirtualMemoryTable[++Index].PhysicalBase =3D 0; + mVirtualMemoryTable[Index].VirtualBase =3D 0; + mVirtualMemoryTable[Index].Length =3D 0; + mVirtualMemoryTable[Index].Attributes =3D 0; =20 ASSERT((Index + 1) <=3D MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS); =20 - *VirtualMemoryMap =3D VirtualMemoryTable; + *VirtualMemoryMap =3D mVirtualMemoryTable; } diff --git a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem= .h b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.h new file mode 100644 index 0000000..8101cf3 --- /dev/null +++ b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.h @@ -0,0 +1,48 @@ +/*************************************************************************= ****** +Copyright (C) 2017 Marvell International Ltd. + +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute a= nd/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modific= ation, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + +* Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +* Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS= " AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPL= IED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABL= E FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAM= AGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICE= S; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AN= D ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF T= HIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +**************************************************************************= *****/ + +#define CCU_MC_RCR_REG 0xf0001700 +#define REMAP_EN_MASK 0x1 +#define REMAP_SIZE_OFFS 20 +#define REMAP_SIZE_MASK (0xfff << REMAP_SIZE_OFFS) +#define CCU_MC_RTBR_REG 0xf0001708 +#define TARGET_BASE_OFFS 10 +#define TARGET_BASE_MASK (0xfffff << TARGET_BASE_OFFS) + +#define DRAM_REMAP_ENABLED \ + (MmioRead32 (CCU_MC_RCR_REG) & REMAP_EN_MASK) +#define DRAM_REMAP_SIZE \ + (MmioRead32 (CCU_MC_RCR_REG) & REMAP_SIZE_MASK) + SIZE_1MB +#define DRAM_REMAP_TARGET \ + (MmioRead32 (CCU_MC_RTBR_REG) << TARGET_BASE_OFFS) diff --git a/Platform/Marvell/Marvell.dec b/Platform/Marvell/Marvell.dec index 434d6cb..36a9d59 100644 --- a/Platform/Marvell/Marvell.dec +++ b/Platform/Marvell/Marvell.dec @@ -194,6 +194,9 @@ #TRNG gMarvellTokenSpaceGuid.PcdEip76TrngBaseAddress|0x0|UINT64|0x50000053 =20 +#Configuration space + gMarvellTokenSpaceGuid.PcdConfigSpaceBaseAddress|0xF0000000|UINT64|0x500= 00054 + [Protocols] gMarvellEepromProtocolGuid =3D { 0x71954bda, 0x60d3, 0x4ef= 8, { 0x8e, 0x3c, 0x0e, 0x33, 0x9f, 0x3b, 0xc2, 0x2b }} gMarvellMdioProtocolGuid =3D { 0x40010b03, 0x5f08, 0x496= a, { 0xa2, 0x64, 0x10, 0x5e, 0x72, 0xd3, 0x71, 0xaa }} --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Tue Apr 30 18:31:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1508914054597850.4587086494355; Tue, 24 Oct 2017 23:47:34 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id A432C2034C0BA; Tue, 24 Oct 2017 23:43:10 -0700 (PDT) Received: from mail-lf0-x241.google.com (mail-lf0-x241.google.com [IPv6:2a00:1450:4010:c07::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 9BA1220347156 for ; Tue, 24 Oct 2017 23:43:06 -0700 (PDT) Received: by mail-lf0-x241.google.com with SMTP id w21so26630948lfc.6 for ; Tue, 24 Oct 2017 23:46:51 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id r22sm513129ljr.16.2017.10.24.23.46.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 24 Oct 2017 23:46:48 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::241; helo=mail-lf0-x241.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=juKWkJIVanRS/g4o+Gi84Idx9mg/Z2jNNRTXkpRqEA0=; b=qkiG/9dZpQSui0HTOseRV8w5sdf4oahVlpPjjiEoMkMnigEThaQEMlGea/xMgulDPN SyBJ56zf6SFk3Pz6ZOaVFtOopgUxgn3y2NIFbEvBzZyx9ClIbhzKYOwN6e26zx3PKjNC Q/oKb8iiWTq+zGoJOr8TM6//Q2fBXZo+674skR9AMkrHFhsKGVfvPmZIUhVwwmqYN/DW PDZigzaBiPKnmqlfVeQ+5dYqFluHScIoAj4tdGrMew2MnoI8if5sC2WcyeRVTjdn1H6G TRbgUInvtqlFtnWg14uAg32tX7QEPNd6wl+7NyJlOYUoswNTWthhESvvNlnnldKjVsV3 EGfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=juKWkJIVanRS/g4o+Gi84Idx9mg/Z2jNNRTXkpRqEA0=; b=O1Nm94k9dQjL9YzNIb+bGP9u2UGU90YK22vL/w+nnLBL9EiLQ9XQoleWGLsVYU+LG0 ZuUAnmUVsyX+BEBITq/64TZCH4dFym4+zUIJ7feXeNoLfbvIKSayVsNgByIOEC9ZzAjS Xlnzm/nxo/2s9623bKNRNr+/XDpfeJuxGIKcRvf1OG1IvkKjJ5udZdPAJ0PwtOLkO2ry NqDhqvog9rQv7eboiCkHYT7Af+VQ2YQmMY3xZAtXeUchAwwf0TiM3sn+Nwu+yoWRxrRM nzOcEmTAbxf0mx18N+c2rtGQswOTlZq2Ck7yi/8HzrfI+I6C9ciEFgpyftz+xMkTscGW 9AkQ== X-Gm-Message-State: AMCzsaVxS736DYbBlPpN7yr5FRfvgAiwY3+Qhss5Qms+6r3dbDJD0w8q 4VBhSxFw6FI97odnaR8zW+YS7rZNtFg= X-Google-Smtp-Source: ABhQp+Qj/K4ttnXisuaO8m1kOnfRmaWFGC5BWga8g21xddRJHRq2SO9SEQ2nOId1fVZFTRQCMqz1qQ== X-Received: by 10.46.43.205 with SMTP id r74mr7701547ljr.159.1508914009438; Tue, 24 Oct 2017 23:46:49 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Wed, 25 Oct 2017 08:45:27 +0200 Message-Id: <1508913930-30886-6-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1508913930-30886-1-git-send-email-mw@semihalf.com> References: <1508913930-30886-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 5/8] Marvell/Armada: Add MemoryInitPeiLib that reserves secure region X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Ard Biesheuvel The default MemoryInitPeiLib implementation insists on reserving the region occupied by our own FV, while this is not necessary at all (the compressed payload is uncompressed elsewhere, so the moment we enter DXE core, we don't care about the FV contents in memory) So clone MemoryInitPeiLib and modify it to suit our needs. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Armada/Armada.dsc.inc = | 6 +- Platform/Marvell/Armada/Library/Armada70x0MemoryInitPeiLib/Armada70x0Memor= yInitPeiLib.c | 158 ++++++++++++++++++++ Platform/Marvell/Armada/Library/Armada70x0MemoryInitPeiLib/Armada70x0Memor= yInitPeiLib.inf | 46 ++++++ Platform/Marvell/Marvell.dec = | 8 + 4 files changed, 217 insertions(+), 1 deletion(-) diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Arma= da/Armada.dsc.inc index 56d8941..b0a8240 100644 --- a/Platform/Marvell/Armada/Armada.dsc.inc +++ b/Platform/Marvell/Armada/Armada.dsc.inc @@ -153,7 +153,7 @@ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf =20 [LibraryClasses.common.SEC, LibraryClasses.common.PEIM] - MemoryInitPeiLib|ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.inf + MemoryInitPeiLib|Platform/Marvell/Armada/Library/Armada70x0MemoryInitPei= Lib/Armada70x0MemoryInitPeiLib.inf BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf =20 [LibraryClasses.common.DXE_CORE] @@ -364,6 +364,10 @@ gArmTokenSpaceGuid.PcdSystemMemorySize|0x40000000 gArmTokenSpaceGuid.PcdArmScr|0x531 =20 + # Secure region reservation + gMarvellTokenSpaceGuid.PcdSecureRegionBase|0x4000000 + gMarvellTokenSpaceGuid.PcdSecureRegionSize|0x0200000 + # TRNG gMarvellTokenSpaceGuid.PcdEip76TrngBaseAddress|0xF2760000 =20 diff --git a/Platform/Marvell/Armada/Library/Armada70x0MemoryInitPeiLib/Arm= ada70x0MemoryInitPeiLib.c b/Platform/Marvell/Armada/Library/Armada70x0Memor= yInitPeiLib/Armada70x0MemoryInitPeiLib.c new file mode 100644 index 0000000..53119f4 --- /dev/null +++ b/Platform/Marvell/Armada/Library/Armada70x0MemoryInitPeiLib/Armada70x0= MemoryInitPeiLib.c @@ -0,0 +1,158 @@ +/** @file +* +* Copyright (c) 2011-2015, ARM Limited. All rights reserved. +* Copyright (c) 2017, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the B= SD License +* which accompanies this distribution. The full text of the license may = be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#include + +#include +#include +#include +#include +#include + +VOID +BuildMemoryTypeInformationHob ( + VOID + ); + +STATIC +VOID +InitMmu ( + IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable + ) +{ + + VOID *TranslationTableBase; + UINTN TranslationTableSize; + RETURN_STATUS Status; + + Status =3D ArmConfigureMmu (MemoryTable, + &TranslationTableBase, + &TranslationTableSize); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Error: Failed to enable MMU\n")); + } +} + +/*++ + +Routine Description: + + + +Arguments: + + FileHandle - Handle of the file being invoked. + PeiServices - Describes the list of possible PEI Services. + +Returns: + + Status - EFI_SUCCESS if the boot mode could be set + +--*/ +EFI_STATUS +EFIAPI +MemoryPeim ( + IN EFI_PHYSICAL_ADDRESS UefiMemoryBase, + IN UINT64 UefiMemorySize + ) +{ + ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable; + EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes; + UINT64 ResourceLength; + EFI_PEI_HOB_POINTERS NextHob; + EFI_PHYSICAL_ADDRESS SecureTop; + EFI_PHYSICAL_ADDRESS ResourceTop; + + // Get Virtual Memory Map from the Platform Library + ArmPlatformGetVirtualMemoryMap (&MemoryTable); + + SecureTop =3D (EFI_PHYSICAL_ADDRESS)FixedPcdGet64 (PcdSecureRegionBase) + + FixedPcdGet32 (PcdSecureRegionSize); + + // + // Search for System Memory Hob that covers the secure firmware, + // and punch a hole in it + // + for (NextHob.Raw =3D GetHobList (); + NextHob.Raw !=3D NULL; + NextHob.Raw =3D GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, + NextHob.Raw)) { + + if ((NextHob.ResourceDescriptor->ResourceType =3D=3D EFI_RESOURCE_SYST= EM_MEMORY) && + (FixedPcdGet64 (PcdSecureRegionBase) >=3D NextHob.ResourceDescript= or->PhysicalStart) && + (SecureTop <=3D NextHob.ResourceDescriptor->PhysicalStart + + NextHob.ResourceDescriptor->ResourceLength)) + { + ResourceAttributes =3D NextHob.ResourceDescriptor->ResourceAttribute; + ResourceLength =3D NextHob.ResourceDescriptor->ResourceLength; + ResourceTop =3D NextHob.ResourceDescriptor->PhysicalStart + Resource= Length; + + if (FixedPcdGet64 (PcdSecureRegionBase) =3D=3D NextHob.ResourceDescr= iptor->PhysicalStart) { + // + // This region starts right at the start of the reserved region, s= o we + // can simply move its start pointer and reduce its length by the = same + // value + // + NextHob.ResourceDescriptor->PhysicalStart +=3D FixedPcdGet32 (PcdS= ecureRegionSize); + NextHob.ResourceDescriptor->ResourceLength -=3D FixedPcdGet32 (Pcd= SecureRegionSize); + + } else if ((NextHob.ResourceDescriptor->PhysicalStart + + NextHob.ResourceDescriptor->ResourceLength) =3D=3D Secur= eTop) { + + // + // This region ends right at the end of the reserved region, so we + // can simply reduce its length by the size of the region. + // + NextHob.ResourceDescriptor->ResourceLength -=3D FixedPcdGet32 (Pcd= SecureRegionSize); + + } else { + // + // This region covers the reserved region. So split it into two re= gions, + // each one touching the reserved region at either end, but not co= vering + // it. + // + NextHob.ResourceDescriptor->ResourceLength =3D FixedPcdGet64 (PcdS= ecureRegionBase) - + NextHob.ResourceDescr= iptor->PhysicalStart; + + // Create the System Memory HOB for the remaining region (top of t= he FD) + BuildResourceDescriptorHob (EFI_RESOURCE_SYSTEM_MEMORY, + ResourceAttributes, + SecureTop, + ResourceTop - SecureTop); + } + + // + // Reserve the memory space occupied by the secure firmware + // + BuildResourceDescriptorHob (EFI_RESOURCE_MEMORY_RESERVED, + 0, + FixedPcdGet64 (PcdSecureRegionBase), + FixedPcdGet32 (PcdSecureRegionSize)); + + break; + } + NextHob.Raw =3D GET_NEXT_HOB (NextHob); + } + + // Build Memory Allocation Hob + InitMmu (MemoryTable); + + if (FeaturePcdGet (PcdPrePiProduceMemoryTypeInformationHob)) { + // Optional feature that helps prevent EFI memory map fragmentation. + BuildMemoryTypeInformationHob (); + } + + return EFI_SUCCESS; +} diff --git a/Platform/Marvell/Armada/Library/Armada70x0MemoryInitPeiLib/Arm= ada70x0MemoryInitPeiLib.inf b/Platform/Marvell/Armada/Library/Armada70x0Mem= oryInitPeiLib/Armada70x0MemoryInitPeiLib.inf new file mode 100644 index 0000000..ebaed01 --- /dev/null +++ b/Platform/Marvell/Armada/Library/Armada70x0MemoryInitPeiLib/Armada70x0= MemoryInitPeiLib.inf @@ -0,0 +1,46 @@ +#/** @file +# +# Copyright (c) 2011-2014, ARM Ltd. All rights reserved.
+# Copyright (c) 2017, Linaro Ltd. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +#**/ + +[Defines] + INF_VERSION =3D 0x00010019 + BASE_NAME =3D Armada70x0MemoryInitPeiLib + FILE_GUID =3D abc4e8a7-89a7-4aea-92bc-0e9421c4a473 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D MemoryInitPeiLib|SEC PEIM + +[Sources] + Armada70x0MemoryInitPeiLib.c + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Platform/Marvell/Marvell.dec + +[LibraryClasses] + ArmPlatformLib + DebugLib + HobLib + ArmMmuLib + +[FeaturePcd] + gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob + +[FixedPcd] + gMarvellTokenSpaceGuid.PcdSecureRegionBase + gMarvellTokenSpaceGuid.PcdSecureRegionSize diff --git a/Platform/Marvell/Marvell.dec b/Platform/Marvell/Marvell.dec index 36a9d59..cd800c8 100644 --- a/Platform/Marvell/Marvell.dec +++ b/Platform/Marvell/Marvell.dec @@ -197,6 +197,14 @@ #Configuration space gMarvellTokenSpaceGuid.PcdConfigSpaceBaseAddress|0xF0000000|UINT64|0x500= 00054 =20 + # + # The secure firmware may occupy a DRAM region that is accessible by the + # normal world. These PCDs describe such a region, which will be convert= ed + # to 'reserved' memory before DXE is entered. + # + gMarvellTokenSpaceGuid.PcdSecureRegionBase|0x0|UINT64|0x50000000 + gMarvellTokenSpaceGuid.PcdSecureRegionSize|0x0|UINT32|0x50000001 + [Protocols] gMarvellEepromProtocolGuid =3D { 0x71954bda, 0x60d3, 0x4ef= 8, { 0x8e, 0x3c, 0x0e, 0x33, 0x9f, 0x3b, 0xc2, 0x2b }} gMarvellMdioProtocolGuid =3D { 0x40010b03, 0x5f08, 0x496= a, { 0xa2, 0x64, 0x10, 0x5e, 0x72, 0xd3, 0x71, 0xaa }} --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Tue Apr 30 18:31:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1508914025284622.6668108719778; Tue, 24 Oct 2017 23:47:05 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id D4F572034CF75; Tue, 24 Oct 2017 23:43:10 -0700 (PDT) Received: from mail-lf0-x243.google.com (mail-lf0-x243.google.com [IPv6:2a00:1450:4010:c07::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id F233F2034C084 for ; Tue, 24 Oct 2017 23:43:07 -0700 (PDT) Received: by mail-lf0-x243.google.com with SMTP id 75so26580862lfx.1 for ; Tue, 24 Oct 2017 23:46:52 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id r22sm513129ljr.16.2017.10.24.23.46.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 24 Oct 2017 23:46:50 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::243; helo=mail-lf0-x243.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=LCLvu6jJfaLlMbFHtMxK9V9F+VtE+0HlgrjYt5tfUbI=; b=zNfyaBiF+KPL5CLpW2A3IHPF2NXW0IN5b2O6DPvJvdupUWVR0cvlTtXpG+mk1OLEeJ x0MW01Y7Ww0cqvYIqy9vO8sBJQX7vdk/Vh0Om98+1O6nqsDStj0ow8Al6yx+p0dxu1Ey 7t6WFNKRiXBPJ2/V8AMB7hPY8farNsH8mTOXsAYZFg/zpXGLmAbnnQPZdvrAc+DOakYV tWS22bzW5/I/I7O4uCIwaho5PUIlP5B8B1VbvA/MMqih0uxLwb7Me7/09N3EzE9HUzVC FQNKj3e2T7VlftCnETc+3ygewnTLYp+1etX6g1fErPzUyD3qFzivgk4SdIOuoYcGMtZk 2lVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=LCLvu6jJfaLlMbFHtMxK9V9F+VtE+0HlgrjYt5tfUbI=; b=c5h5JbeihWGcD3nUS0YR6iyJ4bMZ6a/yFbjMt8APoM/SsQFEo8q9FA/OG58/5rruFb E+v8tSS3TVnEoQrGDgFmrCOsNO5Ghv8tYqbkPEBlQ+1AEHDKIoXQteNuQLsPQGK+Orde JzIn+YnZVKzTHO1AsQ81mWQG7tsXob7jKebXsYdVwuKQv2bXxYdt0R6ArwvoVqi3nOUe FbzQbdU88AIVXd/+WqKPeF9UKWKu3VhjGbwffLf0uVWuO0EGe0fzgqKGFQRnBOVGPLuO ZtwmUyc6SlrV2DwiSVXRqlMKKgkpZfkGr+WneOFs4CHX8ejXHP2J6jurIqYpvKgF/z3y nX8g== X-Gm-Message-State: AMCzsaWMvSd0Ma665Lu7AcRB7DFzbTUpz2rn6bfkOGofAmrlGAkDwatA TblRw115MBWrhV1/dH8gkGGNCH1fKoU= X-Google-Smtp-Source: ABhQp+Q9eC3U64C8DDGytEhWh14b0pz5aN8E6Pd1P+hFLx/lCHBvtlKGo/euC9yCwYTpwNan79HDDQ== X-Received: by 10.46.43.145 with SMTP id r17mr7710972ljr.56.1508914010873; Tue, 24 Oct 2017 23:46:50 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Wed, 25 Oct 2017 08:45:28 +0200 Message-Id: <1508913930-30886-7-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1508913930-30886-1-git-send-email-mw@semihalf.com> References: <1508913930-30886-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 6/8] Marvell/Armada: Enable dynamic DRAM size detection X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Instead of using hardcoded value in PcdSystemMemorySize PCD, obtain DRAM size directly from SoC registers, which are filled by firmware during early initialization stage. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c | 62 ++++= +++++++++++++++- Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.h | 25 ++++= ++++ 2 files changed, 86 insertions(+), 1 deletion(-) diff --git a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem= .c b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c index 978e4d3..bf0ebcf 100644 --- a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c +++ b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c @@ -50,6 +50,60 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAM= AGE. =20 STATIC ARM_MEMORY_REGION_DESCRIPTOR mVirtualMemoryTable[MAX_VIRTUAL_MEMORY= _MAP_DESCRIPTORS]; =20 +// Obtain DRAM size basing on register values filled by early firmware. +STATIC +UINT64 +GetDramSize ( + IN OUT UINT64 *MemSize + ) +{ + UINT64 BaseAddr; + UINT8 RegionCode; + UINT8 Cs; + + *MemSize =3D 0; + + for (Cs =3D 0; Cs < DRAM_MAX_CS_NUM; Cs++) { + + /* Exit loop on first disabled DRAM CS */ + if (!DRAM_CS_ENABLED (Cs)) { + break; + } + + /* + * Sanity check for base address of next DRAM block. + * Only continuous space will be used. + */ + BaseAddr =3D GET_DRAM_REGION_BASE (Cs); + if (BaseAddr !=3D *MemSize) { + DEBUG ((DEBUG_ERROR, + "%a: DRAM blocks are not contiguous, limit size to 0x%llx\n", + __FUNCTION__, + *MemSize)); + return EFI_SUCCESS; + } + + /* Decode area length for current CS from register value */ + RegionCode =3D GET_DRAM_REGION_SIZE_CODE (Cs); + if (DRAM_REGION_SIZE_CODE_INVALID (RegionCode)) { + DEBUG ((DEBUG_ERROR, + "%a: Invalid memory region code (0x%x) for CS#%d\n", + __FUNCTION__, + RegionCode, + Cs)); + return EFI_INVALID_PARAMETER; + } + + if (RegionCode <=3D 0x4) { + *MemSize +=3D GET_DRAM_REGION_SIZE_ODD (RegionCode); + } else { + *MemSize +=3D GET_DRAM_REGION_SIZE_EVEN (RegionCode); + } + } + + return EFI_SUCCESS; +} + /** Return the Virtual Memory Map of your platform =20 @@ -72,12 +126,18 @@ ArmPlatformGetVirtualMemoryMap ( UINT64 MemHighSize; UINT64 ConfigSpaceBaseAddr; EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes; + EFI_STATUS Status; =20 ASSERT (VirtualMemoryMap !=3D NULL); =20 ConfigSpaceBaseAddr =3D FixedPcdGet64 (PcdConfigSpaceBaseAddress); =20 - MemSize =3D FixedPcdGet64 (PcdSystemMemorySize); + // Obtain total memory size from the hardware. + Status =3D GetDramSize (&MemSize); + if (EFI_ERROR (Status)) { + MemSize =3D FixedPcdGet64 (PcdSystemMemorySize); + DEBUG ((DEBUG_ERROR, "Limit total memory size to %d MB\n", MemSize / 1= 024 / 1024)); + } =20 if (DRAM_REMAP_ENABLED) { MemLowSize =3D MIN (DRAM_REMAP_TARGET, MemSize); diff --git a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem= .h b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.h index 8101cf3..dd218d9 100644 --- a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.h +++ b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.h @@ -46,3 +46,28 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAM= AGE. (MmioRead32 (CCU_MC_RCR_REG) & REMAP_SIZE_MASK) + SIZE_1MB #define DRAM_REMAP_TARGET \ (MmioRead32 (CCU_MC_RTBR_REG) << TARGET_BASE_OFFS) + +#define DRAM_CH0_MMAP_LOW_REG(cs) (0xf0020200 + (cs) * 0x8) +#define DRAM_CS_VALID_ENABLED_MASK 0x1 +#define DRAM_AREA_LENGTH_OFFS 16 +#define DRAM_AREA_LENGTH_MASK (0x1f << DRAM_AREA_LENGTH_OFFS) +#define DRAM_START_ADDRESS_L_OFFS 23 +#define DRAM_START_ADDRESS_L_MASK (0x1ff << DRAM_START_ADDRESS_L_OFF= S) +#define DRAM_CH0_MMAP_HIGH_REG(cs) (0xf0020204 + (cs) * 0x8) +#define DRAM_START_ADDR_HTOL_OFFS 32 + +#define DRAM_MAX_CS_NUM 8 + +#define DRAM_CS_ENABLED(Cs) \ + (MmioRead32 (DRAM_CH0_MMAP_LOW_REG (Cs)) & DRAM_CS_VALID_ENABLED= _MASK) +#define GET_DRAM_REGION_BASE(Cs) \ + ((UINT64)MmioRead32 (DRAM_CH0_MMAP_HIGH_REG ((Cs))) << \ + DRAM_START_ADDR_HTOL_OFFS) | \ + (MmioRead32 (DRAM_CH0_MMAP_LOW_REG (Cs)) & DRAM_START_ADDRESS_L_= MASK); +#define GET_DRAM_REGION_SIZE_CODE(Cs) \ + (MmioRead32 (DRAM_CH0_MMAP_LOW_REG ((Cs))) & \ + DRAM_AREA_LENGTH_MASK) >> DRAM_AREA_LENGTH_OFFS +#define DRAM_REGION_SIZE_CODE_INVALID(C) \ + (((C) > 0x4 && (C) < 0x7) || (C) > 0x1b) +#define GET_DRAM_REGION_SIZE_ODD(C) ((UINT64)0x18000000 << (C)) +#define GET_DRAM_REGION_SIZE_EVEN(C) ((UINT64)1 << ((C) + 16)) --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Tue Apr 30 18:31:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 15089140292851020.8845390481923; Tue, 24 Oct 2017 23:47:09 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 23AC52034CF7A; Tue, 24 Oct 2017 23:43:12 -0700 (PDT) Received: from mail-lf0-x241.google.com (mail-lf0-x241.google.com [IPv6:2a00:1450:4010:c07::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 5B3532034C084 for ; Tue, 24 Oct 2017 23:43:09 -0700 (PDT) Received: by mail-lf0-x241.google.com with SMTP id p184so26533181lfe.12 for ; Tue, 24 Oct 2017 23:46:54 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id r22sm513129ljr.16.2017.10.24.23.46.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 24 Oct 2017 23:46:51 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::241; helo=mail-lf0-x241.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=JUsg1sArW1Mn6hCTG3lQLUR7gCzjdaMFTWxOng+EYeg=; b=PmT0RlipjdpJpp6Yh9x6Ny+iWDH3CWW9tGmFNhK4omvzmxLeIxaLV4N9vWHdBla43V V/gTikgFn9EqcNuzbeUa5ZYMcyjxWyzs69XCqqCl4GNYi7fla4ioy50rxJVqEmpCEDZz pfYifrzyueMVqhW+g7aDV/bYC6sx2hSKSyGG3qH1GX3o+8bMhpD/5+L3mSkR04KZN2oI 9eKBcTiPKtnNG9HS6X1VQePJB+vPDLjT0KRlFESpop4Xa+3GMJuZGvd80D/zo/lrjtSN yZDTuJgoN1Zzx1i2NY++7XDgRrVkeOrPntBcDQcrPHWA1VTpNeCXyjpBXH2ka5UXznbt lZmQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=JUsg1sArW1Mn6hCTG3lQLUR7gCzjdaMFTWxOng+EYeg=; b=t+axSSXkHr/xPnVuVtQRt8mBj9EuGbB+80xWDCSSqCnmRXaWxUcr5eSOQ7lyKUeOSA 4qF14Av4/7SY3vlH0CUB/vNZSxqA2dUHeEe/cizRzLSjktrvWrVTF908R9oLGsLURhNg scWpOJEnHwW/kEjlxLxIdW17Mic0vAdxPkRLtekJI7iXasFBewXevQdx/+j64hF84iaX CSqd/ZBMqfVHrLsecwNbEN2OXFMGBFokyTvyNhxWPN6eqtRjjnM9MRXEv0IItwyNqOEc +7/xoULZYwy5bbt/dGxunw9q4cR+hMWrcyHtcmbfH4EH6PtK/W+ubHoreNP+lqRRss3d x4eA== X-Gm-Message-State: AMCzsaW3sYiN0zX+AEgscyMZmlLtHGVPREI1pbWQ8Mon5PCf7FpstvO/ Uw4d44pZPYCTnroiR99GkuNmEUCUV0I= X-Google-Smtp-Source: ABhQp+TsOlu4RcbCbcRPsBNt+p/7EegUOtXXWGJ2wp6B6Z/Cki6m4HTbO4R5F1Q/U5CvVVNFhScrRw== X-Received: by 10.25.169.4 with SMTP id s4mr6619808lfe.61.1508914012236; Tue, 24 Oct 2017 23:46:52 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Wed, 25 Oct 2017 08:45:29 +0200 Message-Id: <1508913930-30886-8-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1508913930-30886-1-git-send-email-mw@semihalf.com> References: <1508913930-30886-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 7/8] Marvell/Armada: Armada70x0Lib: Add support for 32-bit ARM X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Ard Biesheuvel Add an ARM implementation of ArmPlatformHelper.S. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Armada/Library/Armada70x0Lib/ARM/ArmPlatformHelper.S | 77= ++++++++++++++++++++ Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf | 3= + 2 files changed, 80 insertions(+) diff --git a/Platform/Marvell/Armada/Library/Armada70x0Lib/ARM/ArmPlatformH= elper.S b/Platform/Marvell/Armada/Library/Armada70x0Lib/ARM/ArmPlatformHelp= er.S new file mode 100644 index 0000000..21459e5 --- /dev/null +++ b/Platform/Marvell/Armada/Library/Armada70x0Lib/ARM/ArmPlatformHelper.S @@ -0,0 +1,77 @@ +//Based on ArmPlatformPkg/Library/ArmPlatformLibNull/AArch64/ArmPlatformHe= lper.S +// +// Copyright (c) 2012-2013, ARM Limited. All rights reserved. +// Copyright (c) 2016, Marvell. All rights reserved. +// Copyright (c) 2017, Linaro Limited. All rights reserved. +// +// This program and the accompanying materials are licensed and made avai= lable +// under the terms and conditions of the BSD License which accompanies th= is +// distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR I= MPLIED +// + +#include +#include + +#define CCU_MC_BASE 0xF0001700 +#define CCU_MC_RCR_OFFSET 0x0 +#define CCU_MC_RCR_REMAP_EN BIT0 +#define CCU_MC_RCR_REMAP_SIZE(Size) (((Size) - 1) ^ (SIZE_1MB - 1)) + +#define CCU_MC_RSBR_OFFSET 0x4 +#define CCU_MC_RSBR_SOURCE_BASE(Base) (((Base) >> 20) << 10) +#define CCU_MC_RTBR_OFFSET 0x8 +#define CCU_MC_RTBR_TARGET_BASE(Base) (((Base) >> 20) << 10) + +ASM_FUNC(ArmPlatformPeiBootAction) + .if FixedPcdGet64 (PcdSystemMemoryBase) !=3D 0 + .err PcdSystemMemoryBase should be 0x0 on this platform! + .endif + + .if FixedPcdGet64 (PcdSystemMemorySize) > FixedPcdGet32 (PcdDramRemapT= arget) + // + // Use the low range for UEFI itself. The remaining memory will be map= ped + // and added to the GCD map later. + // + ADRL (r0, mSystemMemoryEnd) + MOV32 (r2, FixedPcdGet32 (PcdDramRemapTarget) - 1) + mov r3, #0 + strd r2, r3, [r0] + .endif + + bx lr + +//UINTN +//ArmPlatformGetCorePosition ( +// IN UINTN MpId +// ); +// With this function: CorePos =3D (ClusterId * 2) + CoreId +ASM_FUNC(ArmPlatformGetCorePosition) + and r1, r0, #ARM_CORE_MASK + and r0, r0, #ARM_CLUSTER_MASK + add r0, r1, r0, LSR #7 + bx lr + +//UINTN +//ArmPlatformGetPrimaryCoreMpId ( +// VOID +// ); +ASM_FUNC(ArmPlatformGetPrimaryCoreMpId) + MOV32 (r0, FixedPcdGet32(PcdArmPrimaryCore)) + bx lr + +//UINTN +//ArmPlatformIsPrimaryCore ( +// IN UINTN MpId +// ); +ASM_FUNC(ArmPlatformIsPrimaryCore) + MOV32 (r1, FixedPcdGet32(PcdArmPrimaryCoreMask)) + and r0, r0, r1 + MOV32 (r1, FixedPcdGet32(PcdArmPrimaryCore)) + cmp r0, r1 + moveq r0, #1 + movne r0, #0 + bx lr diff --git a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.in= f b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf index 2236d9f..71abdd4 100644 --- a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf +++ b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf @@ -60,6 +60,9 @@ [Sources.AArch64] AArch64/ArmPlatformHelper.S =20 +[Sources.ARM] + ARM/ArmPlatformHelper.S + [FixedPcd] gArmTokenSpaceGuid.PcdSystemMemoryBase gArmTokenSpaceGuid.PcdSystemMemorySize --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Tue Apr 30 18:31:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1508914033328838.6630519744069; Tue, 24 Oct 2017 23:47:13 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 5D3DA2034CF7E; Tue, 24 Oct 2017 23:43:12 -0700 (PDT) Received: from mail-lf0-x243.google.com (mail-lf0-x243.google.com [IPv6:2a00:1450:4010:c07::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 8B56E2034A7D9 for ; Tue, 24 Oct 2017 23:43:10 -0700 (PDT) Received: by mail-lf0-x243.google.com with SMTP id k40so26581517lfi.4 for ; Tue, 24 Oct 2017 23:46:55 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id r22sm513129ljr.16.2017.10.24.23.46.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 24 Oct 2017 23:46:52 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::243; helo=mail-lf0-x243.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=skPeaC9nSwzOSMNALKrWczFKCOe99YjR7FYyQ4Kz6x4=; b=lg+y/AukU2+IJw+gZpc35jYKeUwsFGWZA8J7GrvCxORWaPnK/bCZSk4QoFsb1nFjjQ 06f6cC78WY2E98h5KgUEACdJrvXKYwijkJ8fx3Ac7VkTCGfUdKU8b0H77u5alS7yyMhk HfIv36gsW5cWK9wPIdxwfXZicaHIQ+ua6AQHeM9ZI1eo/GKN4U6bHEufZ56WXbYAjEIX 8IGkx74UBkEVH0WwOynYH0S8CJSyT9W9oOed9iraPFSM1O474EoCVPXOZjGjyGB74z6J BbyUpgBdoax8yd1UAQEZjQO2fSddB1e/FAXb9AJULIAHf/UVcjY17nXK92UGsAE/o0EO KCGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=skPeaC9nSwzOSMNALKrWczFKCOe99YjR7FYyQ4Kz6x4=; b=HjvBOKTOGsbHlVCKrPLtEzmM+lTi7fD1AewLYiv9qN4ZxeGDhHmMjM5xFn0qZ/mA2N IyqTFSJkedh0le2wRJNhh3BdpYwA3dfnEeGKL3x02dhaLAZ2lupHJjch9+4fE8q5SFUK ciJ2Ki3TrGA4QfTd/cxIo6T940nV6/KixZMYYtM0nZp3GhumzyL3E1PECBmhaCTZJI/H mJT9BlGKU41zXbQCMLWfDufqWkn3OIIEq3z2eKn7ZpiEf5ReaX3y3l2QPDbSAE+Ptjzc 1t6tJ34QVAjtc1zFwdW30LnqWKibPYG+amM2ZZ82hD6B3owzZVvohXxKK2S2zr5f9pjb ZKHg== X-Gm-Message-State: AMCzsaXF3jDD3z8mXE5pXCHGwhYOIBXqunD9Xiyr7c+pFFTtB/k1yoRI dgQJreYmlVhJNyJvYK0TaSApCFVNCWs= X-Google-Smtp-Source: ABhQp+SX37Fg2JX6Iv7rHPj3Mv4KgC5OKzdwUDyriFZZDi7wCg0jZ1Yk4/3LTJduksUuj7g20x7D0Q== X-Received: by 10.25.168.78 with SMTP id r75mr6294156lfe.65.1508914013448; Tue, 24 Oct 2017 23:46:53 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Wed, 25 Oct 2017 08:45:30 +0200 Message-Id: <1508913930-30886-9-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1508913930-30886-1-git-send-email-mw@semihalf.com> References: <1508913930-30886-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 8/8] Marvell/Armada: Add 32-bit ARM support X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Ard Biesheuvel Update the included components and library classes to make this platform build for 32-bit ARM. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Armada/Armada.dsc.inc | 3 +-- Platform/Marvell/Armada/Armada70x0.dsc | 4 ++-- Platform/Marvell/Armada/Armada70x0.fdf | 2 +- 3 files changed, 4 insertions(+), 5 deletions(-) diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Arma= da/Armada.dsc.inc index b0a8240..b9fc384 100644 --- a/Platform/Marvell/Armada/Armada.dsc.inc +++ b/Platform/Marvell/Armada/Armada.dsc.inc @@ -132,7 +132,6 @@ CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/Customize= dDisplayLib.inf FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf =20 -[LibraryClasses.AARCH64] ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/Ar= mGenericTimerPhyCounterLib.inf @@ -362,7 +361,7 @@ # ARM Pcds gArmTokenSpaceGuid.PcdSystemMemoryBase|0 gArmTokenSpaceGuid.PcdSystemMemorySize|0x40000000 - gArmTokenSpaceGuid.PcdArmScr|0x531 + gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|36 =20 # Secure region reservation gMarvellTokenSpaceGuid.PcdSecureRegionBase|0x4000000 diff --git a/Platform/Marvell/Armada/Armada70x0.dsc b/Platform/Marvell/Arma= da/Armada70x0.dsc index 946c93e..0396e8e 100644 --- a/Platform/Marvell/Armada/Armada70x0.dsc +++ b/Platform/Marvell/Armada/Armada70x0.dsc @@ -39,8 +39,8 @@ PLATFORM_GUID =3D f837e231-cfc7-4f56-9a0f-5b218d746ae3 PLATFORM_VERSION =3D 0.1 DSC_SPECIFICATION =3D 0x00010005 - OUTPUT_DIRECTORY =3D Build/$(PLATFORM_NAME) - SUPPORTED_ARCHITECTURES =3D AARCH64 + OUTPUT_DIRECTORY =3D Build/$(PLATFORM_NAME)-$(ARCH) + SUPPORTED_ARCHITECTURES =3D AARCH64|ARM BUILD_TARGETS =3D DEBUG|RELEASE SKUID_IDENTIFIER =3D DEFAULT FLASH_DEFINITION =3D Platform/Marvell/Armada/Armada70x0.fdf diff --git a/Platform/Marvell/Armada/Armada70x0.fdf b/Platform/Marvell/Arma= da/Armada70x0.fdf index a94a9ff..ec2c368 100644 --- a/Platform/Marvell/Armada/Armada70x0.fdf +++ b/Platform/Marvell/Armada/Armada70x0.fdf @@ -237,7 +237,7 @@ READ_LOCK_STATUS =3D TRUE # ##########################################################################= ## =20 -[Rule.AARCH64.SEC] +[Rule.Common.SEC] FILE SEC =3D $(NAMED_GUID) RELOCS_STRIPPED FIXED { TE TE Align =3D Auto $(INF_OUTPUT)/$(MODULE_NAME).efi } --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel