From nobody Fri May 3 15:56:47 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1501826353240466.4896280200438; Thu, 3 Aug 2017 22:59:13 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id E51A321D19947; Thu, 3 Aug 2017 22:56:57 -0700 (PDT) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 4D74021CE7490 for ; Thu, 3 Aug 2017 22:56:56 -0700 (PDT) Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 03 Aug 2017 22:59:08 -0700 Received: from ydong10-win10.ccr.corp.intel.com ([10.239.158.51]) by orsmga005.jf.intel.com with ESMTP; 03 Aug 2017 22:59:07 -0700 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.41,319,1498546800"; d="scan'208";a="133436856" From: Eric Dong To: edk2-devel@lists.01.org Date: Fri, 4 Aug 2017 13:59:04 +0800 Message-Id: <1501826344-13868-1-git-send-email-eric.dong@intel.com> X-Mailer: git-send-email 2.7.0.windows.1 Subject: [edk2] [Patch v2] Vlv2TbltDevicePkg: Remove reference deprecated macro. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ruiyu Ni , Jeff Fan , David Wei MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" v2 changes include: 1. Use MSR data structure instead of redefin local macro. Cc: Jeff Fan Cc: Ruiyu Ni Cc: David Wei Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eric Dong Reviewed-by: Ruiyu Ni --- Vlv2TbltDevicePkg/PlatformInitPei/MemoryPeim.c | 29 ++++++++++++++++++----= ---- 1 file changed, 20 insertions(+), 9 deletions(-) diff --git a/Vlv2TbltDevicePkg/PlatformInitPei/MemoryPeim.c b/Vlv2TbltDevic= ePkg/PlatformInitPei/MemoryPeim.c index 5a18a3f..6f37e3b 100644 --- a/Vlv2TbltDevicePkg/PlatformInitPei/MemoryPeim.c +++ b/Vlv2TbltDevicePkg/PlatformInitPei/MemoryPeim.c @@ -196,16 +196,22 @@ SetPeiCacheMode ( // Cache the flash area to improve the boot performance in PEI phase // Index =3D 0; - MtrrSetting.Variables.Mtrr[0].Base =3D (FixedPcdGet32 (PcdFlashAreaBaseA= ddress) | CacheWriteProtected); - MtrrSetting.Variables.Mtrr[0].Mask =3D ((~((UINT64)(FixedPcdGet32 (PcdFl= ashAreaSize) - 1))) & ValidMtrrAddressMask) | MTRR_LIB_CACHE_MTRR_ENABLED; + ((MSR_IA32_MTRR_PHYSBASE_REGISTER *) &MtrrSetting.Variables.Mtrr[0].Base= )->Uint64 =3D FixedPcdGet32 (PcdFlashAreaBaseAddress); + ((MSR_IA32_MTRR_PHYSBASE_REGISTER *) &MtrrSetting.Variables.Mtrr[0].Base= )->Bits.Type =3D CacheWriteProtected; + ((MSR_IA32_MTRR_PHYSMASK_REGISTER *) &MtrrSetting.Variables.Mtrr[0].Mask= )->Uint64 =3D (~((UINT64)(FixedPcdGet32 (PcdFlashAreaSize) - 1))) & ValidMt= rrAddressMask; + ((MSR_IA32_MTRR_PHYSMASK_REGISTER *) &MtrrSetting.Variables.Mtrr[0].Mask= )->Bits.V =3D 1; + Index ++; =20 MemOverflow =3D0; while (MaxMemoryLength > MemOverflow){ - MtrrSetting.Variables.Mtrr[Index].Base =3D (MemOverflow & ValidMtrrAdd= ressMask) | CacheWriteBack; MemoryLength =3D MaxMemoryLength - MemOverflow; MemoryLength =3D GetPowerOfTwo64 (MemoryLength); - MtrrSetting.Variables.Mtrr[Index].Mask =3D ((~(MemoryLength - 1)) & Va= lidMtrrAddressMask) | MTRR_LIB_CACHE_MTRR_ENABLED; + + ((MSR_IA32_MTRR_PHYSBASE_REGISTER *) &MtrrSetting.Variables.Mtrr[Index= ].Base)->Uint64 =3D MemOverflow & ValidMtrrAddressMask; + ((MSR_IA32_MTRR_PHYSBASE_REGISTER *) &MtrrSetting.Variables.Mtrr[Index= ].Base)->Bits.Type =3D CacheWriteBack; + ((MSR_IA32_MTRR_PHYSMASK_REGISTER *) &MtrrSetting.Variables.Mtrr[Index= ].Mask)->Uint64 =3D (~(MemoryLength - 1)) & ValidMtrrAddressMask; + ((MSR_IA32_MTRR_PHYSMASK_REGISTER *) &MtrrSetting.Variables.Mtrr[Index= ].Mask)->Bits.V =3D 1; =20 MemOverflow +=3D MemoryLength; Index++; @@ -216,23 +222,28 @@ SetPeiCacheMode ( while (MaxMemoryLength !=3D MemoryLength) { MemoryLengthUc =3D GetPowerOfTwo64 (MaxMemoryLength - MemoryLength); =20 - MtrrSetting.Variables.Mtrr[Index].Base =3D ((MaxMemoryLength - MemoryL= engthUc) & ValidMtrrAddressMask) | CacheUncacheable; - MtrrSetting.Variables.Mtrr[Index].Mask=3D ((~(MemoryLengthUc - 1)) &= ValidMtrrAddressMask) | MTRR_LIB_CACHE_MTRR_ENABLED; + ((MSR_IA32_MTRR_PHYSBASE_REGISTER *) &MtrrSetting.Variables.Mtrr[Index= ].Base)->Uint64 =3D (MaxMemoryLength - MemoryLengthUc) & ValidMtrrAddressMa= sk; + ((MSR_IA32_MTRR_PHYSBASE_REGISTER *) &MtrrSetting.Variables.Mtrr[Index= ].Base)->Bits.Type =3D CacheUncacheable; + ((MSR_IA32_MTRR_PHYSMASK_REGISTER *) &MtrrSetting.Variables.Mtrr[Index= ].Mask)->Uint64 =3D (~(MemoryLengthUc - 1)) & ValidMtrrAddressMask; + ((MSR_IA32_MTRR_PHYSMASK_REGISTER *) &MtrrSetting.Variables.Mtrr[Index= ].Mask)->Bits.V =3D 1; + MaxMemoryLength -=3D MemoryLengthUc; Index++; } =20 MemOverflow =3D0x100000000; while (HighMemoryLength > 0) { - MtrrSetting.Variables.Mtrr[Index].Base =3D (MemOverflow & ValidMtrrAdd= ressMask) | CacheWriteBack; + MemoryLength =3D HighMemoryLength; MemoryLength =3D GetPowerOfTwo64 (MemoryLength); - if (MemoryLength > MemOverflow){ MemoryLength =3D MemOverflow; } =20 - MtrrSetting.Variables.Mtrr[Index].Mask =3D ((~(MemoryLength - 1)) & Va= lidMtrrAddressMask) | MTRR_LIB_CACHE_MTRR_ENABLED; + ((MSR_IA32_MTRR_PHYSBASE_REGISTER *) &MtrrSetting.Variables.Mtrr[Index= ].Base)->Uint64 =3D MemOverflow & ValidMtrrAddressMask; + ((MSR_IA32_MTRR_PHYSBASE_REGISTER *) &MtrrSetting.Variables.Mtrr[Index= ].Base)->Bits.Type =3D CacheWriteBack; + ((MSR_IA32_MTRR_PHYSMASK_REGISTER *) &MtrrSetting.Variables.Mtrr[Index= ].Mask)->Uint64 =3D (~(MemoryLength - 1)) & ValidMtrrAddressMask; + ((MSR_IA32_MTRR_PHYSMASK_REGISTER *) &MtrrSetting.Variables.Mtrr[Index= ].Mask)->Bits.V =3D 1; =20 MemOverflow +=3D MemoryLength; HighMemoryLength -=3D MemoryLength; --=20 2.7.0.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel