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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id q200sm1706348lfe.49.2017.07.04.15.02.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 04 Jul 2017 15:02:48 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=gbc81ihIDC0f1/QtqLQ8ZoiD5fjFbDSo/W6jIsqKGZ0=; b=wkO3TPp5TEDqAgN+AdR57yqJFKlUpokKdgS1zjlgyoMpPo9v4eE7iljJBHTR98j4Px xaF+qMV2zJsoBDS3dAeNdj4RzTJapKhUctF5FsZ/oMod145bnAYA79fGkqroLVlg0+Zf 1/gGq2dYTM1S+x9Hj7cGjbnIsmo7hMWU/FiB4dPeeM3iNxOmjcZSfOFcadx93gjz0C8e Nd77E3Oh6J6QOsSWr2TPbSrURqgZiiyUVTUh9hDLF6lwBDCPILCbZWbrVcZKc3C3qzBz uz5ePMoqDVkeSbpGbqzYws1HWoTwwUL4sdo8hqkotb1Tr0enN2WBI5rGZf5zESnzk7ww xeJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=gbc81ihIDC0f1/QtqLQ8ZoiD5fjFbDSo/W6jIsqKGZ0=; b=XclvFWQyHQszeGMVyp/+PWpu7eebu1fG9JvMdTHueQLa+XOyB6Mt9Acc29ZEJ3thZ2 /VMsJfzSsWh0mhm4SNJVmCS198sTMcNSqpliqdzoPsgcP9WDun5TX/9gdZLgM2LdB75Z wd5lMMpfbkbK79Q08lTtkbTdZcGt01Qswd+N+e0btKEQ6DMNtIy0VmpnCwLtsy92mrN/ rBoZAkQ2BWqJeg/dyUph5TO6WLB4Xd+ofqHs0UNAHTVpduTntnOBDAlgaRJvFGkJvmji ADDLTMdSFD4ZgUkCd/9HJFLBIUNOPvQV4dwXXKuDJgXGZbdr5v+obr1ALID22P6bxBFZ 3Ngw== X-Gm-Message-State: AKS2vOyldRJGXwM4jJz8EB48ZHGeuxjXbDnO46QvIdj9tt8Bmzf0P1Tz VFCWhBV7bkIjToF5QWPATA== X-Received: by 10.25.149.74 with SMTP id x71mr14905652lfd.94.1499205769116; Tue, 04 Jul 2017 15:02:49 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Wed, 5 Jul 2017 00:02:11 +0200 Message-Id: <1499205732-12445-2-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1499205732-12445-1-git-send-email-mw@semihalf.com> References: <1499205732-12445-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 09/10] Platform/Marvell: ComPhyLib: Use COMPHY_ prefix in macros X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, leif.lindholm@linaro.org, ard.biesheuvel@linaro.org MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This patch renames macros for speed, type and polarity from 'PHY_' to 'COMPHY_' (Common PHY), so that to avoid confusion with network PHY's definitions (NETPHY_). Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c | 102 ++++++++++++-------= ---- Platform/Marvell/Library/ComPhyLib/ComPhyLib.c | 22 ++--- Platform/Marvell/Library/ComPhyLib/ComPhyLib.h | 90 ++++++++++---------- Platform/Marvell/Library/ComPhyLib/ComPhyMux.c | 4 +- 4 files changed, 111 insertions(+), 107 deletions(-) diff --git a/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c b/Platform/Ma= rvell/Library/ComPhyLib/ComPhyCp110.c index 329bbe8..6ef63a8 100755 --- a/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c +++ b/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c @@ -54,40 +54,44 @@ DECLARE_A7K8K_NONDISCOVERABLE_TEMPLATE; */ COMPHY_MUX_DATA Cp110ComPhyMuxData[] =3D { /* Lane 0 */ - {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII1, 0x1}, {PHY_TYPE_SATA= 1, 0x4}}}, + {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII1, 0x1}, + {COMPHY_TYPE_SATA1, 0x4}}}, /* Lane 1 */ - {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, {PHY_TYPE_SATA= 0, 0x4}}}, + {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII2, 0x1}, + {COMPHY_TYPE_SATA0, 0x4}}}, /* Lane 2 */ - {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x1}, {PHY_TYPE_RXAU= I0, 0x1}, - {PHY_TYPE_SFI, 0x1}, {PHY_TYPE_SATA0, 0x4}}}, + {6, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII0, 0x1}, + {COMPHY_TYPE_RXAUI0, 0x1}, {COMPHY_TYPE_SFI, 0x1}, + {COMPHY_TYPE_SATA0, 0x4}}}, /* Lane 3 */ - {8, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_RXAUI1, 0x1}, {PHY_TYPE_SGMI= I1, 0x2}, - {PHY_TYPE_SATA1, 0x4}}}, + {8, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_RXAUI1, 0x1}, + {COMPHY_TYPE_SGMII1, 0x2}, {COMPHY_TYPE_SATA1, 0x4}}}, /* Lane 4 */ - {7, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x2}, {PHY_TYPE_RXAU= I0, 0x2}, - {PHY_TYPE_SFI, 0x2}, {PHY_TYPE_SGMII1, 0x1}}}, + {7, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII0, 0x2}, + {COMPHY_TYPE_RXAUI0, 0x2}, {COMPHY_TYPE_SFI, 0x2}, + {COMPHY_TYPE_SGMII1, 0x1}}}, /* Lane 5 */ - {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, {PHY_TYPE_RXAU= I1, 0x2}, - {PHY_TYPE_SATA1, 0x4}}}, + {6, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII2, 0x1}, + {COMPHY_TYPE_RXAUI1, 0x2}, {COMPHY_TYPE_SATA1, 0x4}}}, }; =20 COMPHY_MUX_DATA Cp110ComPhyPipeMuxData[] =3D { /* Lane 0 */ - {2, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_PCIE0, 0x4} } }, + {2, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_PCIE0, 0x4}}}, /* Lane 1 */ - {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_USB3_HOST0, 0x1}, - {PHY_TYPE_USB3_DEVICE, 0x2}, {PHY_TYPE_PCIE0, 0x4} } }, + {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_USB3_HOST0, 0x1}, + {COMPHY_TYPE_USB3_DEVICE, 0x2}, {COMPHY_TYPE_PCIE0, 0x4}}}, /* Lane 2 */ - {3, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_USB3_HOST0, 0x1}, - {PHY_TYPE_PCIE0, 0x4} } }, + {3, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_USB3_HOST0, 0x1}, + {COMPHY_TYPE_PCIE0, 0x4}}}, /* Lane 3 */ - {3, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_USB3_HOST1, 0x1}, - {PHY_TYPE_PCIE0, 0x4} } }, + {3, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_USB3_HOST1, 0x1}, + {COMPHY_TYPE_PCIE0, 0x4}}}, /* Lane 4 */ - {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_USB3_HOST1, 0x1}, - {PHY_TYPE_USB3_DEVICE, 0x2}, {PHY_TYPE_PCIE1, 0x4} } }, + {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_USB3_HOST1, 0x1}, + {COMPHY_TYPE_USB3_DEVICE, 0x2}, {COMPHY_TYPE_PCIE1, 0x4}}}, /* Lane 5 */ - {2, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_PCIE2, 0x4} } }, + {2, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_PCIE2, 0x4}}}, }; =20 STATIC @@ -1102,7 +1106,7 @@ ComPhySgmiiRFUConfiguration ( Data =3D 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; Mask |=3D SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK; Mask |=3D SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK; - if (SgmiiSpeed =3D=3D PHY_SPEED_1_25G) { + if (SgmiiSpeed =3D=3D COMPHY_SPEED_1_25G) { Data |=3D 0x6 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET; Data |=3D 0x6 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET; } else { @@ -1320,7 +1324,7 @@ ComPhySfiPhyConfiguration ( =20 /* Set reference clock */ Mask =3D HPIPE_MISC_ICP_FORCE_MASK | HPIPE_MISC_REFCLK_SEL_MASK; - Data =3D (SfiSpeed =3D=3D PHY_SPEED_5_15625G) ? + Data =3D (SfiSpeed =3D=3D COMPHY_SPEED_5_15625G) ? (0x0 << HPIPE_MISC_ICP_FORCE_OFFSET) : (0x1 << HPIPE_MISC_ICP_FORCE_OF= FSET); MmioAndThenOr32 (HpipeAddr + HPIPE_MISC_REG, ~Mask, Data); =20 @@ -1348,7 +1352,7 @@ ComPhySfiPhyConfiguration ( MmioOr32 (HpipeAddr + HPIPE_PWR_CTR_DTL_REG, HPIPE_PWR_CTR_DTL_FLOOP_EN_= MASK); =20 /* Transmitter/Receiver Speed Divider Force */ - if (SfiSpeed =3D=3D PHY_SPEED_5_15625G) { + if (SfiSpeed =3D=3D COMPHY_SPEED_5_15625G) { Mask =3D HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_MASK | HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_MASK | HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_MASK | @@ -1380,7 +1384,7 @@ ComPhySfiSetAnalogParameters ( MmioOr32 (HpipeAddr + HPIPE_DFE_REG0, HPIPE_DFE_RES_FORCE_MASK); =20 /* Generation 1 setting_0 */ - if (SfiSpeed =3D=3D PHY_SPEED_5_15625G) { + if (SfiSpeed =3D=3D COMPHY_SPEED_5_15625G) { Mask =3D HPIPE_GX_SET0_TX_EMPH1_MASK; Data =3D 0x6 << HPIPE_GX_SET0_TX_EMPH1_OFFSET; } else { @@ -1414,7 +1418,7 @@ ComPhySfiSetAnalogParameters ( MmioAnd32 (HpipeAddr + HPIPE_G1_SET5_REG, ~HPIPE_GX_SET5_ICP_MASK); =20 /* Generation 1 setting 1 */ - if (SfiSpeed =3D=3D PHY_SPEED_5_15625G) { + if (SfiSpeed =3D=3D COMPHY_SPEED_5_15625G) { Mask =3D HPIPE_GX_SET1_RX_SELMUPI_MASK | HPIPE_GX_SET1_RX_SELMUPP_MASK; Data =3D 0x1 | (0x1 << HPIPE_GX_SET1_RX_SELMUPP_OFFSET); } else { @@ -1447,7 +1451,7 @@ ComPhySfiSetAnalogParameters ( /* Generation 1 setting 3 */ MmioOr32 (HpipeAddr + HPIPE_G1_SET3_REG, HPIPE_GX_SET3_FBCK_SEL_MASK); =20 - if (SfiSpeed =3D=3D PHY_SPEED_5_15625G) { + if (SfiSpeed =3D=3D COMPHY_SPEED_5_15625G) { /* Force FFE (Feed Forward Equalization) to 5G */ Mask =3D HPIPE_GX_SET3_FFE_CAP_SEL_MASK | HPIPE_GX_SET3_FFE_RES_SEL_MASK | @@ -1760,9 +1764,9 @@ ComPhyMuxCp110 ( =20 /* Fix the Type after check the PHY and PIPE configuration */ for (Lane =3D 0; Lane < ComPhyMaxCount; Lane++) - if ((ComPhyMapPipeData[Lane].Type =3D=3D PHY_TYPE_UNCONNECTED) && - (ComPhyMapPhyData[Lane].Type =3D=3D PHY_TYPE_UNCONNECTED)) - SerdesMap[Lane].Type =3D PHY_TYPE_UNCONNECTED; + if ((ComPhyMapPipeData[Lane].Type =3D=3D COMPHY_TYPE_UNCONNECTED) && + (ComPhyMapPhyData[Lane].Type =3D=3D COMPHY_TYPE_UNCONNECTED)) + SerdesMap[Lane].Type =3D COMPHY_TYPE_UNCONNECTED; } =20 VOID @@ -1786,7 +1790,7 @@ ComPhyCp110Init ( =20 /* Check if the first 4 Lanes configured as By-4 */ for (Lane =3D 0, PtrComPhyMap =3D SerdesMap; Lane < 4; Lane++, PtrComPhy= Map++) { - if (PtrComPhyMap->Type !=3D PHY_TYPE_PCIE0) { + if (PtrComPhyMap->Type !=3D COMPHY_TYPE_PCIE0) { PcieBy4 =3D 0; break; } @@ -1797,39 +1801,39 @@ ComPhyCp110Init ( DEBUG((DEBUG_INFO, "ComPhy: Initialize serdes number %d\n", Lane)); DEBUG((DEBUG_INFO, "ComPhy: Serdes Type =3D 0x%x\n", PtrComPhyMap->Typ= e)); switch (PtrComPhyMap->Type) { - case PHY_TYPE_UNCONNECTED: + case COMPHY_TYPE_UNCONNECTED: continue; break; - case PHY_TYPE_PCIE0: - case PHY_TYPE_PCIE1: - case PHY_TYPE_PCIE2: - case PHY_TYPE_PCIE3: + case COMPHY_TYPE_PCIE0: + case COMPHY_TYPE_PCIE1: + case COMPHY_TYPE_PCIE2: + case COMPHY_TYPE_PCIE3: Status =3D ComPhyPciePowerUp(Lane, PcieBy4, HpipeBaseAddr, ComPhyBas= eAddr); break; - case PHY_TYPE_SATA0: - case PHY_TYPE_SATA1: + case COMPHY_TYPE_SATA0: + case COMPHY_TYPE_SATA1: Status =3D ComPhySataPowerUp (Lane, HpipeBaseAddr, ComPhyBaseAddr, M= VHW_CP0_AHCI0_ID); break; - case PHY_TYPE_SATA2: - case PHY_TYPE_SATA3: + case COMPHY_TYPE_SATA2: + case COMPHY_TYPE_SATA3: Status =3D ComPhySataPowerUp (Lane, HpipeBaseAddr, ComPhyBaseAddr, M= VHW_CP1_AHCI0_ID); break; - case PHY_TYPE_USB3_HOST0: - case PHY_TYPE_USB3_HOST1: + case COMPHY_TYPE_USB3_HOST0: + case COMPHY_TYPE_USB3_HOST1: Status =3D ComphyUsb3PowerUp(Lane, HpipeBaseAddr, ComPhyBaseAddr); break; - case PHY_TYPE_SGMII0: - case PHY_TYPE_SGMII1: - case PHY_TYPE_SGMII2: - case PHY_TYPE_SGMII3: + case COMPHY_TYPE_SGMII0: + case COMPHY_TYPE_SGMII1: + case COMPHY_TYPE_SGMII2: + case COMPHY_TYPE_SGMII3: Status =3D ComPhySgmiiPowerUp(Lane, PtrComPhyMap->Speed, HpipeBaseAd= dr, ComPhyBaseAddr); break; - case PHY_TYPE_SFI: + case COMPHY_TYPE_SFI: Status =3D ComPhySfiPowerUp(Lane, HpipeBaseAddr, ComPhyBaseAddr, Ptr= ComPhyMap->Speed); break; - case PHY_TYPE_RXAUI0: - case PHY_TYPE_RXAUI1: + case COMPHY_TYPE_RXAUI0: + case COMPHY_TYPE_RXAUI1: Status =3D ComPhyRxauiPowerUp(Lane, HpipeBaseAddr, ComPhyBaseAddr); break; default: @@ -1841,7 +1845,7 @@ ComPhyCp110Init ( } if (EFI_ERROR(Status)) { DEBUG ((DEBUG_ERROR, "Failed to initialize Lane %d\n with Status =3D= 0x%x", Lane, Status)); - PtrComPhyMap->Type =3D PHY_TYPE_UNCONNECTED; + PtrComPhyMap->Type =3D COMPHY_TYPE_UNCONNECTED; } } } diff --git a/Platform/Marvell/Library/ComPhyLib/ComPhyLib.c b/Platform/Marv= ell/Library/ComPhyLib/ComPhyLib.c index b61ccb6..3eb5d9f 100644 --- a/Platform/Marvell/Library/ComPhyLib/ComPhyLib.c +++ b/Platform/Marvell/Library/ComPhyLib/ComPhyLib.c @@ -122,16 +122,16 @@ ParseSerdesTypeString ( UINT32 i; =20 if (String =3D=3D NULL) - return PHY_TYPE_INVALID; + return COMPHY_TYPE_INVALID; =20 - for (i =3D 0; i < PHY_TYPE_MAX; i++) { + for (i =3D 0; i < COMPHY_TYPE_MAX; i++) { if (StrCmp (String, TypeStringTable[i]) =3D=3D 0) { return i; } } =20 /* PCD string doesn't match any supported SerDes Type */ - return PHY_TYPE_INVALID; + return COMPHY_TYPE_INVALID; } =20 /* This function converts SerDes speed in MHz to enum with SerDesSpeed */ @@ -144,14 +144,14 @@ ParseSerdesSpeed ( UINT32 ValueTable [] =3D {0, 1250, 1500, 2500, 3000, 3125, 5000, 5156, 6000, 6250, 10310}; =20 - for (i =3D 0; i < PHY_SPEED_MAX; i++) { + for (i =3D 0; i < COMPHY_SPEED_MAX; i++) { if (Value =3D=3D ValueTable[i]) { return i; } } =20 /* PCD SerDes speed value doesn't match any supported SerDes speed */ - return PHY_SPEED_INVALID; + return COMPHY_SPEED_INVALID; } =20 CHAR16 * @@ -160,7 +160,7 @@ GetTypeString ( ) { =20 - if (Type < 0 || Type > PHY_TYPE_MAX) { + if (Type < 0 || Type > COMPHY_TYPE_MAX) { return L"invalid"; } =20 @@ -295,13 +295,13 @@ MvComPhyInit ( ParseSerdesSpeed (LaneData[Index].SpeedValue[Lane]); PtrChipCfg->MapData[Lane].Invert =3D (UINT32)LaneData[Index].InvFlag= [Lane]; =20 - if ((PtrChipCfg->MapData[Lane].Speed =3D=3D PHY_SPEED_INVALID) || - (PtrChipCfg->MapData[Lane].Speed =3D=3D PHY_SPEED_ERROR) || - (PtrChipCfg->MapData[Lane].Type =3D=3D PHY_TYPE_INVALID)) { + if ((PtrChipCfg->MapData[Lane].Speed =3D=3D COMPHY_SPEED_INVALID) || + (PtrChipCfg->MapData[Lane].Speed =3D=3D COMPHY_SPEED_ERROR) || + (PtrChipCfg->MapData[Lane].Type =3D=3D COMPHY_TYPE_INVALID)) { DEBUG((DEBUG_ERROR, "ComPhy: No valid phy speed or type for lane %= d, " "setting lane as unconnected\n", Lane + 1)); - PtrChipCfg->MapData[Lane].Type =3D PHY_TYPE_UNCONNECTED; - PtrChipCfg->MapData[Lane].Speed =3D PHY_SPEED_INVALID; + PtrChipCfg->MapData[Lane].Type =3D COMPHY_TYPE_UNCONNECTED; + PtrChipCfg->MapData[Lane].Speed =3D COMPHY_SPEED_INVALID; } }; =20 diff --git a/Platform/Marvell/Library/ComPhyLib/ComPhyLib.h b/Platform/Marv= ell/Library/ComPhyLib/ComPhyLib.h index 3c589f2..3898978 100644 --- a/Platform/Marvell/Library/ComPhyLib/ComPhyLib.h +++ b/Platform/Marvell/Library/ComPhyLib/ComPhyLib.h @@ -63,51 +63,51 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DA= MAGE. } =20 /***** ComPhy *****/ -#define PHY_SPEED_ERROR 0 -#define PHY_SPEED_1_25G 1 -#define PHY_SPEED_1_5G 2 -#define PHY_SPEED_2_5G 3 -#define PHY_SPEED_3G 4 -#define PHY_SPEED_3_125G 5 -#define PHY_SPEED_5G 6 -#define PHY_SPEED_5_15625G 7 -#define PHY_SPEED_6G 8 -#define PHY_SPEED_6_25G 9 -#define PHY_SPEED_10_3125G 10 -#define PHY_SPEED_MAX 11 -#define PHY_SPEED_INVALID 0xff - -#define PHY_TYPE_UNCONNECTED 0 -#define PHY_TYPE_PCIE0 1 -#define PHY_TYPE_PCIE1 2 -#define PHY_TYPE_PCIE2 3 -#define PHY_TYPE_PCIE3 4 -#define PHY_TYPE_SATA0 5 -#define PHY_TYPE_SATA1 6 -#define PHY_TYPE_SATA2 7 -#define PHY_TYPE_SATA3 8 -#define PHY_TYPE_SGMII0 9 -#define PHY_TYPE_SGMII1 10 -#define PHY_TYPE_SGMII2 11 -#define PHY_TYPE_SGMII3 12 -#define PHY_TYPE_QSGMII 13 -#define PHY_TYPE_USB3_HOST0 14 -#define PHY_TYPE_USB3_HOST1 15 -#define PHY_TYPE_USB3_DEVICE 16 -#define PHY_TYPE_XAUI0 17 -#define PHY_TYPE_XAUI1 18 -#define PHY_TYPE_XAUI2 19 -#define PHY_TYPE_XAUI3 20 -#define PHY_TYPE_RXAUI0 21 -#define PHY_TYPE_RXAUI1 22 -#define PHY_TYPE_SFI 23 -#define PHY_TYPE_MAX 24 -#define PHY_TYPE_INVALID 0xff - -#define PHY_POLARITY_NO_INVERT 0 -#define PHY_POLARITY_TXD_INVERT 1 -#define PHY_POLARITY_RXD_INVERT 2 -#define PHY_POLARITY_ALL_INVERT (PHY_POLARITY_TXD_INVERT= | PHY_POLARITY_RXD_INVERT) +#define COMPHY_SPEED_ERROR 0 +#define COMPHY_SPEED_1_25G 1 +#define COMPHY_SPEED_1_5G 2 +#define COMPHY_SPEED_2_5G 3 +#define COMPHY_SPEED_3G 4 +#define COMPHY_SPEED_3_125G 5 +#define COMPHY_SPEED_5G 6 +#define COMPHY_SPEED_5_15625G 7 +#define COMPHY_SPEED_6G 8 +#define COMPHY_SPEED_6_25G 9 +#define COMPHY_SPEED_10_3125G 10 +#define COMPHY_SPEED_MAX 11 +#define COMPHY_SPEED_INVALID 0xff + +#define COMPHY_TYPE_UNCONNECTED 0 +#define COMPHY_TYPE_PCIE0 1 +#define COMPHY_TYPE_PCIE1 2 +#define COMPHY_TYPE_PCIE2 3 +#define COMPHY_TYPE_PCIE3 4 +#define COMPHY_TYPE_SATA0 5 +#define COMPHY_TYPE_SATA1 6 +#define COMPHY_TYPE_SATA2 7 +#define COMPHY_TYPE_SATA3 8 +#define COMPHY_TYPE_SGMII0 9 +#define COMPHY_TYPE_SGMII1 10 +#define COMPHY_TYPE_SGMII2 11 +#define COMPHY_TYPE_SGMII3 12 +#define COMPHY_TYPE_QSGMII 13 +#define COMPHY_TYPE_USB3_HOST0 14 +#define COMPHY_TYPE_USB3_HOST1 15 +#define COMPHY_TYPE_USB3_DEVICE 16 +#define COMPHY_TYPE_XAUI0 17 +#define COMPHY_TYPE_XAUI1 18 +#define COMPHY_TYPE_XAUI2 19 +#define COMPHY_TYPE_XAUI3 20 +#define COMPHY_TYPE_RXAUI0 21 +#define COMPHY_TYPE_RXAUI1 22 +#define COMPHY_TYPE_SFI 23 +#define COMPHY_TYPE_MAX 24 +#define COMPHY_TYPE_INVALID 0xff + +#define COMPHY_POLARITY_NO_INVERT 0 +#define COMPHY_POLARITY_TXD_INVERT 1 +#define COMPHY_POLARITY_RXD_INVERT 2 +#define COMPHY_POLARITY_ALL_INVERT (COMPHY_POLARITY_TXD_= INVERT | COMPHY_POLARITY_RXD_INVERT) =20 /***** SerDes IP registers *****/ #define SD_EXTERNAL_CONFIG0_REG 0 diff --git a/Platform/Marvell/Library/ComPhyLib/ComPhyMux.c b/Platform/Marv= ell/Library/ComPhyLib/ComPhyMux.c index 595745b..6589fec 100644 --- a/Platform/Marvell/Library/ComPhyLib/ComPhyMux.c +++ b/Platform/Marvell/Library/ComPhyLib/ComPhyMux.c @@ -57,8 +57,8 @@ ComPhyMuxCheckConfig ( DEBUG((DEBUG_INFO, "Lane number %d, had invalid Type %d\n", Lane, ComPhyMapData->Type)); DEBUG((DEBUG_INFO, "Set Lane %d as Type %d\n", Lane, - PHY_TYPE_UNCONNECTED)); - ComPhyMapData->Type =3D PHY_TYPE_UNCONNECTED; + COMPHY_TYPE_UNCONNECTED)); + ComPhyMapData->Type =3D COMPHY_TYPE_UNCONNECTED; } else { DEBUG((DEBUG_INFO, "Lane number %d, has Type %d\n", Lane, ComPhyMapData->Type)); --=20 1.8.3.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel