From nobody Sun Apr 28 20:57:55 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1499174675914232.54570078347024; Tue, 4 Jul 2017 06:24:35 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id AD97C20945603; Tue, 4 Jul 2017 06:22:52 -0700 (PDT) Received: from mail-lf0-x229.google.com (mail-lf0-x229.google.com [IPv6:2a00:1450:4010:c07::229]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 9946420945600 for ; Tue, 4 Jul 2017 06:22:50 -0700 (PDT) Received: by mail-lf0-x229.google.com with SMTP id z78so77470280lff.0 for ; Tue, 04 Jul 2017 06:24:28 -0700 (PDT) Received: from mw-mint.semihalf.local (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id c185sm4980970lfc.43.2017.07.04.06.24.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 04 Jul 2017 06:24:25 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=E3JPLUrU5nb2c61DK6Ki6xB4MrtRpe9Y6xmDSdN1tuw=; b=sTJmW1aMZyalCYwR4VdlShlMfZp5FqwA9ZScmX2RUIz3NYtd187A1CPuUQkTl9Ltq6 a88sDgyLu5iKRRC4ACbzprr80jcfwNPi80GKcEMlF7XsnCIq9HclK7Cvw1SJYvX+B7h1 ku1N1Qh9fSw/taWQakuFEc1z+k3wYCHXl8NEihycFq1aXKAfG+e2X8IEfZcHdF6um7Sl Sv5k8s4mIIC+FpJdMGn+vXqQwxQmowxvlnngTepDL9D8gNMULh2L9arEJBSJmBzdbbLw nh5SnCRPz5yMU+ckaJntjP77LdkT/HBEtMQVlPKowrLNTq8vTTv0E2TiGcNikyDYWWss j3pQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=E3JPLUrU5nb2c61DK6Ki6xB4MrtRpe9Y6xmDSdN1tuw=; b=I7JbJLAQhO7r5m+cMwmZtSrOhA9yEVVWn6KOyQ053Dv3p7O3sP9WHi0sr4rruLWYbP qbCFdBSt6sa1qy62leAAZ6mNzK33lpdVfERURLpW5OWX0bPrCVmEpgPXJP8bQx4J0mHo kc1o4Z0TEVIe/b7rI0LCnYNPEgAZojKBngZy/j4tb0dsStB+dix+Nk60FxHe+c21guxH k4RnsMSZ8Sw+SGnpRNuKH1dRHrIWVis9yycSZo7plFqDz2uklQXKN6pKizx56P/5XJ39 FkokWYzZBjb0dqWpYXQPK3UWFGU2UrVhZFPF9cp3n0MMkjBT/xQp2RGVUVh0Wrf0Y1cA 8dQg== X-Gm-Message-State: AKS2vOzXCs3Od6h9CQUWTD3F6hUQERLsPi+C4h51/yHyJJkqoBn733JX PwDshI1wi+WSSHjOS+Rjsw== X-Received: by 10.25.74.88 with SMTP id x85mr11360159lfa.31.1499174666443; Tue, 04 Jul 2017 06:24:26 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Tue, 4 Jul 2017 15:24:04 +0200 Message-Id: <1499174653-330-2-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1499174653-330-1-git-send-email-mw@semihalf.com> References: <1499174653-330-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 01/10] Platform/Marvell: ComPhyLib: Cleanup and fix SerDes lanes assignment X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, leif.lindholm@linaro.org, ard.biesheuvel@linaro.org MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Hitherto settings of ComPhy lanes' options were not on par with real hardware capabilities. This patch introduces following fixes to the lanes options: * Remove XAUI, because it's not supported; * Correct opiton for Lane1 is SATA0; * Remove KR from Lane3; * KR on Lane4 mux selector should be 0x2; * Align SGMII numbering according to the specification. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Marcin Wojtas Reviewed-by: Ard Biesheuvel --- Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c | 30 ++++++++++----------= ---- 1 file changed, 12 insertions(+), 18 deletions(-) diff --git a/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c b/Platform/Ma= rvell/Library/ComPhyLib/ComPhyCp110.c index c71ddb6..6214bed 100755 --- a/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c +++ b/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c @@ -49,32 +49,26 @@ DECLARE_A7K8K_NONDISCOVERABLE_TEMPLATE; * and " PIPE Selectors". * PIPE selector include USB and PCIe options. * PHY selector include the Ethernet and SATA options, every Ethernet opti= on - * has different options, for example: serdes Lane2 had option Eth_port_0 - * that include (SGMII0, XAUI0, RXAUI0, KR) + * has different options, for example: serdes Lane2 have option Eth_port_0 + * that include (SGMII0, RXAUI0, KR) */ COMPHY_MUX_DATA Cp110ComPhyMuxData[] =3D { /* Lane 0 */ - {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, - {PHY_TYPE_XAUI2, 0x1}, {PHY_TYPE_SATA1, 0x4} } }, + {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII1, 0x1}, {PHY_TYPE_SATA= 1, 0x4}}}, /* Lane 1 */ - {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII3, 0x1}, - {PHY_TYPE_XAUI3, 0x1}, {PHY_TYPE_SATA1, 0x4} } }, + {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, {PHY_TYPE_SATA= 0, 0x4}}}, /* Lane 2 */ - {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x1}, - {PHY_TYPE_XAUI0, 0x1}, {PHY_TYPE_RXAUI0, 0x1}, {PHY_TYPE_KR, 0x1}, - {PHY_TYPE_SATA0, 0x4} } }, + {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x1}, {PHY_TYPE_RXAU= I0, 0x1}, + {PHY_TYPE_KR, 0x1}, {PHY_TYPE_SATA0, 0x4}}}, /* Lane 3 */ - {8, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x1}, - {PHY_TYPE_XAUI0, 0x1}, {PHY_TYPE_RXAUI0, 0x1}, {PHY_TYPE_KR, 0x1}, - {PHY_TYPE_XAUI1, 0x1}, {PHY_TYPE_RXAUI1, 0x1}, {PHY_TYPE_SATA1, 0x4} }= }, + {8, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_RXAUI1, 0x1}, {PHY_TYPE_SGMI= I1, 0x2}, + {PHY_TYPE_SATA1, 0x4}}}, /* Lane 4 */ - {7, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x2}, - {PHY_TYPE_XAUI0, 0x1}, {PHY_TYPE_RXAUI0, 0x1}, {PHY_TYPE_KR, 0x1}, - {PHY_TYPE_SGMII2, 0x1}, {PHY_TYPE_XAUI2, 0x1} } }, + {7, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x2}, {PHY_TYPE_RXAU= I0, 0x2}, + {PHY_TYPE_KR, 0x2}, {PHY_TYPE_SGMII1, 0x1}}}, /* Lane 5 */ - {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_XAUI1, 0x1}, - {PHY_TYPE_RXAUI1, 0x1}, {PHY_TYPE_SGMII3, 0x1}, {PHY_TYPE_XAUI3, 0x1}, - {PHY_TYPE_SATA1, 0x4} } }, + {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, {PHY_TYPE_RXAU= I1, 0x2}, + {PHY_TYPE_SATA1, 0x4}}}, }; =20 COMPHY_MUX_DATA Cp110ComPhyPipeMuxData[] =3D { --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun Apr 28 20:57:55 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1499174680075144.60740567874336; Tue, 4 Jul 2017 06:24:40 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 2B0AB20945609; Tue, 4 Jul 2017 06:22:54 -0700 (PDT) Received: from mail-lf0-x22f.google.com (mail-lf0-x22f.google.com [IPv6:2a00:1450:4010:c07::22f]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 856FC20945601 for ; Tue, 4 Jul 2017 06:22:52 -0700 (PDT) Received: by mail-lf0-x22f.google.com with SMTP id z78so77470821lff.0 for ; Tue, 04 Jul 2017 06:24:30 -0700 (PDT) Received: from mw-mint.semihalf.local (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id c185sm4980970lfc.43.2017.07.04.06.24.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 04 Jul 2017 06:24:26 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=N8XZ2nyVgJ6sXWY4WLvBQb+5tKmhWSQOVv0EohuSgpU=; b=ctCc1EDPkwRclTb+V2kjVOMOyW4mVMDyZT/E0bfPdCYCD/E9AonrFxboRfGKPDX2DU ll3wq/i4/5rHWjRBlrz68mq1UfxUXilq21cmMfAIG6GJ6+adSOIwEC/z3HZrv/n5DX3R 9E3lA6p+i8kfkoeHE8Lsra/AsxY48fQSeZaA9yC0lMxHV57i9hRX0H3hoBEBcZn53RJ5 U3vy1WgsuitQLMZg67pbwj2C7vv+XzN25xAesoEb2DCIadH/rRR1HvGD94xeyrjOhHjn EvYRD5DK/15mbRC5ghSi13CUjFG7C2YSinxpQnv/B7MUqxBLxKLCG4gF8t3OaGrQwf9o sSjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=N8XZ2nyVgJ6sXWY4WLvBQb+5tKmhWSQOVv0EohuSgpU=; b=RV8U4DqA4RqL5wx4wj9JvcZpoJ9WZoktrZuuOhwsABZv4RfGKtnRgyDPK0bno0V/tk BelVN2o29GsERRtsR3tcuuQnIX4CDgbItDsKEn5lLzSIvS65QpolZZGp+hXGcWZr0c10 7MwcSr9H0WnjVW2KobfIJTOmk8TG7P0xsgEWewOD7mavnPnFW6NIqk+tEQtcINR7cUmK r8xeViLAnzz+oybDWi52/Ho5sUjhIs5B+/I/RDkTmA82/S97tO2qQyxYhyrpVGUfN96e /Uhgdi5CRVvtIRXMmbHAU/SjeRml/vwrAh2hEFhMJjShHzPWfRLJH5/s18qGWfDdMtnT ccOQ== X-Gm-Message-State: AKS2vOxKrWfPKF2f4MKG9EKP8X6LC+rhwuj5PLSxSCeDlgKzMtS6K7ME V70VYPW8B+DycjgsqmBavA== X-Received: by 10.25.92.18 with SMTP id q18mr11277651lfb.13.1499174668067; Tue, 04 Jul 2017 06:24:28 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Tue, 4 Jul 2017 15:24:05 +0200 Message-Id: <1499174653-330-3-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1499174653-330-1-git-send-email-mw@semihalf.com> References: <1499174653-330-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 02/10] Platform/Marvell: ComPhyLib: Rename KR to SFI X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, leif.lindholm@linaro.org, ard.biesheuvel@linaro.org MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" The actual SerDes type present by the HW is SFI, whose suppport is added in the following patches. KR mode is its subset of the SFI and it will be enabled in future. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Marcin Wojtas Reviewed-by: Ard Biesheuvel --- Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c | 6 +++--- Platform/Marvell/Library/ComPhyLib/ComPhyLib.c | 2 +- Platform/Marvell/Library/ComPhyLib/ComPhyLib.h | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c b/Platform/Ma= rvell/Library/ComPhyLib/ComPhyCp110.c index 6214bed..cee7519 100755 --- a/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c +++ b/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c @@ -50,7 +50,7 @@ DECLARE_A7K8K_NONDISCOVERABLE_TEMPLATE; * PIPE selector include USB and PCIe options. * PHY selector include the Ethernet and SATA options, every Ethernet opti= on * has different options, for example: serdes Lane2 have option Eth_port_0 - * that include (SGMII0, RXAUI0, KR) + * that include (SGMII0, RXAUI0, SFI) */ COMPHY_MUX_DATA Cp110ComPhyMuxData[] =3D { /* Lane 0 */ @@ -59,13 +59,13 @@ COMPHY_MUX_DATA Cp110ComPhyMuxData[] =3D { {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, {PHY_TYPE_SATA= 0, 0x4}}}, /* Lane 2 */ {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x1}, {PHY_TYPE_RXAU= I0, 0x1}, - {PHY_TYPE_KR, 0x1}, {PHY_TYPE_SATA0, 0x4}}}, + {PHY_TYPE_SFI, 0x1}, {PHY_TYPE_SATA0, 0x4}}}, /* Lane 3 */ {8, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_RXAUI1, 0x1}, {PHY_TYPE_SGMI= I1, 0x2}, {PHY_TYPE_SATA1, 0x4}}}, /* Lane 4 */ {7, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x2}, {PHY_TYPE_RXAU= I0, 0x2}, - {PHY_TYPE_KR, 0x2}, {PHY_TYPE_SGMII1, 0x1}}}, + {PHY_TYPE_SFI, 0x2}, {PHY_TYPE_SGMII1, 0x1}}}, /* Lane 5 */ {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, {PHY_TYPE_RXAU= I1, 0x2}, {PHY_TYPE_SATA1, 0x4}}}, diff --git a/Platform/Marvell/Library/ComPhyLib/ComPhyLib.c b/Platform/Marv= ell/Library/ComPhyLib/ComPhyLib.c index 9efefb2..88680fc 100644 --- a/Platform/Marvell/Library/ComPhyLib/ComPhyLib.c +++ b/Platform/Marvell/Library/ComPhyLib/ComPhyLib.c @@ -39,7 +39,7 @@ CHAR16 * TypeStringTable [] =3D {L"unconnected", L"PCIE0"= , L"PCIE1", L"PCIE2", L"SGMII0", L"SGMII1", L"SGMII2", L"SGMII3", L"QSGMII", L"USB3_HOST0", L"USB3_HOST1", L"USB3_DEVICE", L"XAUI0", L"XAUI1", L"XAUI2", - L"XAUI3", L"RXAUI0", L"RXAUI1", L"KR"}; + L"XAUI3", L"RXAUI0", L"RXAUI1", L"SFI"}; =20 CHAR16 * SpeedStringTable [] =3D {L"-", L"1.25 Gbps", L"1.5 Gbps", L"2.5 G= bps", L"3.0 Gbps", L"3.125 Gbps", L"5 Gbps", diff --git a/Platform/Marvell/Library/ComPhyLib/ComPhyLib.h b/Platform/Marv= ell/Library/ComPhyLib/ComPhyLib.h index 945f266..24839b2 100644 --- a/Platform/Marvell/Library/ComPhyLib/ComPhyLib.h +++ b/Platform/Marvell/Library/ComPhyLib/ComPhyLib.h @@ -109,7 +109,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DA= MAGE. #define PHY_TYPE_XAUI3 20 #define PHY_TYPE_RXAUI0 21 #define PHY_TYPE_RXAUI1 22 -#define PHY_TYPE_KR 23 +#define PHY_TYPE_SFI 23 #define PHY_TYPE_MAX 24 #define PHY_TYPE_INVALID 0xff =20 --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun Apr 28 20:57:55 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1499174681088852.547737456313; Tue, 4 Jul 2017 06:24:41 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 667FB2094560D; Tue, 4 Jul 2017 06:22:54 -0700 (PDT) Received: from mail-lf0-x22e.google.com (mail-lf0-x22e.google.com [IPv6:2a00:1450:4010:c07::22e]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 030B721CAD9BD for ; Tue, 4 Jul 2017 06:22:53 -0700 (PDT) Received: by mail-lf0-x22e.google.com with SMTP id t72so9318561lff.1 for ; Tue, 04 Jul 2017 06:24:31 -0700 (PDT) Received: from mw-mint.semihalf.local (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id c185sm4980970lfc.43.2017.07.04.06.24.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 04 Jul 2017 06:24:28 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=N/mSqE+Wb2uayvTtA9SY33AzcoOV5U1CiyB8GvdkOnQ=; b=HacDUIegYANLxWo5MZh8P+gCEZB2Pe9T1DxZSBbZC2TQFKiRxE/+NntM6DpWm9kLgD pMsnMmwS2uCqiUJsgS26Z8IHwinQIFiUiksAM6dPyb3HWvz19qGMdFrqeC+wXOLjMMCF zK2JE1Ppc6ixQ4qKzKmqkeAcXL0tUFkiuQ3eW4f3eqQaFvShu05H+eeUbTL87AWPvOnQ jeViAtcNUWQEJW3U42Bxq8MfVOfeEDX9SIH75orRPpVPDgmV/tNb3+HfeFwMnRZc3HcP eLw5WV5/P7/+J9Xk+NXHtSe/1M0pj3YFG1/iNbT+JS20+/hpY6L1nopnzhtU6pW6zTaW RJCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=N/mSqE+Wb2uayvTtA9SY33AzcoOV5U1CiyB8GvdkOnQ=; b=QrHJqE+L54Bh8Fqtw8F8SC0pxI9uMCOux6Q+dkGgJ9rBK1Bnv7HqLP/G7eWPUM8YdE CTZ1kTk8Yl61qHglPUAynxchtKp00vsikU8NrfljuVkHii9V8MzdDVApgHhIUY/1tJce e7kSyy8TxKXD7OaVnsc4AaVxmMVAXuK+JL0JXsbh9ihZqbZ2zUzfmTCSJodHhVK+deZe x3fWONhYVSiclngg3KlWT6S4vlnInkf1KMtDJcuf8mZhd7szelfdO0VpoIaWfUK2LfWS oe75Gvn8MQVjq49p/hVrYgQhfmyDYSFfYGHHllo0rOODiEAgHGT7yhm23XdeT1iQnkIL cZ+A== X-Gm-Message-State: AIVw110/nRhc70OrFs9kI9K8aAGJm8VuzTfAlmRyaB+xIGdStQ+jI9W4 5ss3yrwSQHcbMuLKxxNFDQ== X-Received: by 10.25.210.69 with SMTP id j66mr153465lfg.21.1499174669355; Tue, 04 Jul 2017 06:24:29 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Tue, 4 Jul 2017 15:24:06 +0200 Message-Id: <1499174653-330-4-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1499174653-330-1-git-send-email-mw@semihalf.com> References: <1499174653-330-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 03/10] Platform/Marvell: Update SerDes types on A70x0 development board X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, leif.lindholm@linaro.org, ard.biesheuvel@linaro.org MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Recent changes in ComPhy library updated SerDes naming for SGMII. Reflect them in Armada70x0-DB lanes' description. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Marcin Wojtas Reviewed-by: Ard Biesheuvel --- Platform/Marvell/Armada/Armada70x0.dsc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Platform/Marvell/Armada/Armada70x0.dsc b/Platform/Marvell/Arma= da/Armada70x0.dsc index 0a5ef00..af602d5 100644 --- a/Platform/Marvell/Armada/Armada70x0.dsc +++ b/Platform/Marvell/Armada/Armada70x0.dsc @@ -112,7 +112,7 @@ gMarvellTokenSpaceGuid.PcdUtmiPhyRegUtmiUnit|L"0xF2580000;0xF2581000" gMarvellTokenSpaceGuid.PcdUtmiPhyUtmiPort|L"0x0;0x1" =20 - gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|L"SGMII2;USB3_HOST0;SGMII0;SA= TA1;USB3_HOST1;PCIE2" + gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|L"SGMII1;USB3_HOST0;SGMII0;SA= TA1;USB3_HOST1;PCIE2" gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|L"3125;5000;1250;5000;5000;5= 000" =20 #MDIO --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun Apr 28 20:57:55 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 149917468511250.3147621134932; Tue, 4 Jul 2017 06:24:45 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 9F0B220945602; Tue, 4 Jul 2017 06:22:56 -0700 (PDT) Received: from mail-lf0-x236.google.com (mail-lf0-x236.google.com [IPv6:2a00:1450:4010:c07::236]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 4015E2094560B for ; Tue, 4 Jul 2017 06:22:54 -0700 (PDT) Received: by mail-lf0-x236.google.com with SMTP id b207so118828759lfg.2 for ; Tue, 04 Jul 2017 06:24:32 -0700 (PDT) Received: from mw-mint.semihalf.local (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id c185sm4980970lfc.43.2017.07.04.06.24.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 04 Jul 2017 06:24:29 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=9A/+5/3LDZZAH81WJo0BfJR3X7BAWHqeoweCXUnWII8=; b=x1S2JrfCQ/2nIdF0EX6cF/l5YkOsYHtRj6CIsSBCzz9eMAedsKUkSDqCHjOS3v3nxu I7BxjBggEasNO+pchcws6DJmIqdGtMbDbA1vk2fJ3rebxVeJI5Qp0WfL6XSqBh2AkbvU mXEjkuZawvYN/TKpaUJFCpsfupD4HjP+f3Jy0BRErO8m6M+CUgMr9ZSzPMtPdoLjmwYB 2q99dOfi9LTGXd/AveEYBTUhY5ZKdCV7ubJl+tKkI8KRnRR35+zcBDC5hFuDPX3Bd+4O DaQp5gWgLDDnrAT38rfWSFnL0R+8N9g+ELSBoL+VVtolv51GxQPceIzUwPyrXgvia0v2 xVDA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=9A/+5/3LDZZAH81WJo0BfJR3X7BAWHqeoweCXUnWII8=; b=o6XdWQarT/M0J6d0Gjml5Ck8oehMZd3hGNgdacuvTAs6Zq8vlNIk055RUTjupdL5k7 jTQYAnGNs7rumO/s1fEu9KEoDB39mGHsZiHZ5H1ofGtZpTr2AB8tTmRySWFkAhuOg9YQ GGZ9l2RQEDOkiDp/OwSPTlQIvqfOvp7TibXVzTv8Wlg7DD+4ugJ3OKQvy/78oKHGD1/V 4MSbAy37zBYQs/guBtxeOono1HIaHerqW9/ZvwJlyKFzk1t/WlN4ZA+zwqd9EgR22b4+ VtZW7RTkapv9IrWymfTPr/XQhqt05WYzAEGVipKmOJHQc/u3E81BJFQbWMKEgSMtfcxr Ok/Q== X-Gm-Message-State: AKS2vOz+06K3Rs33Nz4hxpoa7maRPLHKncooREcKHckg/2s74MmS1KkI VbM4X8A4xsUuLIx+sYzsOg== X-Received: by 10.25.165.83 with SMTP id o80mr10493342lfe.115.1499174670618; Tue, 04 Jul 2017 06:24:30 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Tue, 4 Jul 2017 15:24:07 +0200 Message-Id: <1499174653-330-5-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1499174653-330-1-git-send-email-mw@semihalf.com> References: <1499174653-330-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 04/10] Platform/Marvell: ComPhyLib: Mark failing lane as unconnected X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, leif.lindholm@linaro.org, ard.biesheuvel@linaro.org MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" In case of an error during initialization, setting PHY_TYPE_UNCONNECTED will allow to present proper information of the lane status. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm Reviewed-by: Ard Biesheuvel --- Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c | 1 + 1 file changed, 1 insertion(+) diff --git a/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c b/Platform/Ma= rvell/Library/ComPhyLib/ComPhyCp110.c index cee7519..ee3ce99 100755 --- a/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c +++ b/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c @@ -1051,6 +1051,7 @@ ComPhyCp110Init ( } if (EFI_ERROR(Status)) { DEBUG ((DEBUG_ERROR, "Failed to initialize Lane %d\n with Status =3D= 0x%x", Lane, Status)); + PtrComPhyMap->Type =3D PHY_TYPE_UNCONNECTED; } } } --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun Apr 28 20:57:55 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1499174688308367.72024019282026; Tue, 4 Jul 2017 06:24:48 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id DBA8920945615; Tue, 4 Jul 2017 06:22:58 -0700 (PDT) Received: from mail-lf0-x235.google.com (mail-lf0-x235.google.com [IPv6:2a00:1450:4010:c07::235]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3EC7120945610 for ; Tue, 4 Jul 2017 06:22:56 -0700 (PDT) Received: by mail-lf0-x235.google.com with SMTP id t72so9319459lff.1 for ; Tue, 04 Jul 2017 06:24:34 -0700 (PDT) Received: from mw-mint.semihalf.local (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id c185sm4980970lfc.43.2017.07.04.06.24.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 04 Jul 2017 06:24:31 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Cslcrao36bTg265AcXQRtPUpstwBFiBZLBnPO4t+spQ=; b=0BNVclGevGgHdwn1Yrn3ie2fJEhZwXVkcAU5MTd2tG9CtBdVAAaKLd9u6n3Ctp8buH wDa4ZkC+Il4bYIxmkhb+v+LafqrlPrDO8nUpm3FJiq7Nv5LQWCd6KJeaOsFO/2i4BDqI l/7bHwoiqnSfgfLSHFNN4RP5QL2ct92y07TSniV2NBUtQdQx+wjt2x8HMRYCsNAE7ZSe mQQrw64YmkAF+zXsm9J80D/U6WMgIEYnrbTLKpJHteQluvL8Z6CNbv4CtTHhgMzgzLxr w+muSC0CBhG3dySGGHE+JlNwdGIRvFhtzmDn+vnygPU+WenOJk2uINtcn+pwRhCmVTv2 ZWqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Cslcrao36bTg265AcXQRtPUpstwBFiBZLBnPO4t+spQ=; b=Gnw3ldC6UvKinPzGfHXzEAPcEiV2WGPJa3Sqk9Yge5uBmYfT7fB4cqg8ngFYtEGs22 mcgt30E/flYPHR1yXGeKGH9Bw2MVteuQBTPoCFG9tFpxMSEm9wFYY/1t9MUzKiedF0G2 7IAfEIzjqPnkIOzJ6lxn6tAW8erlrIG9w4cWoaDKatxBYHBoO/FB6LIT+ejGGwuVsaxZ whEHn9hj3UEknmL03FRTE85i6S+IN0GB8+9p0yYJgm55z4z7dEJIbDR6k432RFiYGaT5 TweF5H4vTIo5BEbMQfNHvymBkDunR7DLH2/D5XEMrYhvafPMfKXUcNzl1SorGec6v6g2 pFhQ== X-Gm-Message-State: AKS2vOyG7MZM4QOL3QHXb8yIo66s0F+gTXgYv2/HEvNW93ypbfh1nrgn 0Z5SBSGydArj3UKYmhlPTQ== X-Received: by 10.46.77.197 with SMTP id c66mr11719126ljd.71.1499174672009; Tue, 04 Jul 2017 06:24:32 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Tue, 4 Jul 2017 15:24:08 +0200 Message-Id: <1499174653-330-6-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1499174653-330-1-git-send-email-mw@semihalf.com> References: <1499174653-330-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 05/10] Platform/Marvell: ComPhyLib: Configure analog parameters for SATA X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, leif.lindholm@linaro.org, ard.biesheuvel@linaro.org MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This patch adds analog parameters configuration for SATA with the values defined during electrical tests of the interface. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Marcin Wojtas Reviewed-by: Ard Biesheuvel --- Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c | 207 +++++++++++++++++++= ++-- Platform/Marvell/Library/ComPhyLib/ComPhyLib.h | 148 +++++++++++++--- 2 files changed, 321 insertions(+), 34 deletions(-) diff --git a/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c b/Platform/Ma= rvell/Library/ComPhyLib/ComPhyCp110.c index ee3ce99..ea9525a 100755 --- a/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c +++ b/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c @@ -608,20 +608,203 @@ ComPhySataPhyConfiguration ( STATIC VOID ComPhySataSetAnalogParameters ( - IN EFI_PHYSICAL_ADDRESS HpipeAddr + IN EFI_PHYSICAL_ADDRESS HpipeAddr, + IN EFI_PHYSICAL_ADDRESS SdIpAddr ) { + UINT32 Mask, Data; + + /* Hpipe Generation 1 settings 1 */ + Mask =3D HPIPE_GX_SET1_RX_SELMUPI_MASK | + HPIPE_GX_SET1_RX_SELMUPP_MASK | + HPIPE_GX_SET1_RX_SELMUFI_MASK | + HPIPE_GX_SET1_RX_SELMUFF_MASK | + HPIPE_GX_SET1_RX_DIGCK_DIV_MASK; + Data =3D (0x1 << HPIPE_GX_SET1_RX_SELMUPP_OFFSET) | + (0x3 << HPIPE_GX_SET1_RX_SELMUFF_OFFSET) | + (0x1 << HPIPE_GX_SET1_RX_DIGCK_DIV_OFFSET); + MmioAndThenOr32 (HpipeAddr + HPIPE_G1_SET1_REG, ~Mask, Data); + + /* Hpipe Generation 1 settings 3 */ + Mask =3D HPIPE_GX_SET3_FFE_CAP_SEL_MASK | + HPIPE_GX_SET3_FFE_RES_SEL_MASK | + HPIPE_GX_SET3_FFE_SETTING_FORCE_MASK | + HPIPE_GX_SET3_FFE_DEG_RES_LEVEL_MASK | + HPIPE_GX_SET3_FFE_LOAD_RES_LEVEL_MASK; + Data =3D 0xf | + (0x2 << HPIPE_GX_SET3_FFE_RES_SEL_OFFSET) | + (0x1 << HPIPE_GX_SET3_FFE_SETTING_FORCE_OFFSET) | + (0x1 << HPIPE_GX_SET3_FFE_DEG_RES_LEVEL_OFFSET) | + (0x1 << HPIPE_GX_SET3_FFE_LOAD_RES_LEVEL_OFFSET); + MmioAndThenOr32 (HpipeAddr + HPIPE_G1_SET3_REG, ~Mask, Data); + + /* Hpipe Generation 2 settings 1 */ + Mask =3D HPIPE_GX_SET1_RX_SELMUPI_MASK | + HPIPE_GX_SET1_RX_SELMUPP_MASK | + HPIPE_GX_SET1_RX_SELMUFI_MASK | + HPIPE_GX_SET1_RX_SELMUFF_MASK | + HPIPE_GX_SET1_RX_DIGCK_DIV_MASK; + Data =3D (0x1 << HPIPE_GX_SET1_RX_SELMUPP_OFFSET) | + (0x3 << HPIPE_GX_SET1_RX_SELMUFF_OFFSET) | + (0x1 << HPIPE_GX_SET1_RX_DIGCK_DIV_OFFSET); + MmioAndThenOr32 (HpipeAddr + HPIPE_G2_SET1_REG, ~Mask, Data); + + /* Hpipe Generation 3 settings 1 */ + Mask =3D HPIPE_GX_SET1_RX_SELMUPI_MASK | + HPIPE_GX_SET1_RX_SELMUPP_MASK | + HPIPE_GX_SET1_RX_SELMUFI_MASK | + HPIPE_GX_SET1_RX_SELMUFF_MASK | + HPIPE_GX_SET1_RX_DFE_EN_MASK | + HPIPE_GX_SET1_RX_DIGCK_DIV_MASK | + HPIPE_GX_SET1_SAMPLER_INPAIRX2_EN_MASK; + Data =3D 0x2 | + (0x2 << HPIPE_GX_SET1_RX_SELMUPP_OFFSET) | + (0x3 << HPIPE_GX_SET1_RX_SELMUFI_OFFSET) | + (0x3 << HPIPE_GX_SET1_RX_SELMUFF_OFFSET) | + (0x1 << HPIPE_GX_SET1_RX_DFE_EN_OFFSET) | + (0x2 << HPIPE_GX_SET1_RX_DIGCK_DIV_OFFSET); + MmioAndThenOr32 (HpipeAddr + HPIPE_G3_SET1_REG, ~Mask, Data); + + /* DTL Control */ + Mask =3D HPIPE_PWR_CTR_DTL_SQ_DET_EN_MASK | + HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_MASK | + HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK | + HPIPE_PWR_CTR_DTL_CLAMPING_SEL_MASK | + HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_MASK | + HPIPE_PWR_CTR_DTL_CLK_MODE_MASK | + HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_MASK; + Data =3D 0x1 | + (0x1 << HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET) | + (0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET) | + (0x1 << HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET) | + (0x1 << HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET) | + (0x1 << HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET) | + (0x1 << HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET); + MmioAndThenOr32 (HpipeAddr + HPIPE_PWR_CTR_DTL_REG, ~Mask, Data); + + /* Trigger sampler enable pulse (by toggling the bit) */ + MmioAndThenOr32 ( + HpipeAddr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, + ~HPIPE_SAMPLER_MASK, + 0x1 << HPIPE_SAMPLER_OFFSET + ); + MmioAnd32 ( + HpipeAddr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, + ~HPIPE_SAMPLER_MASK + ); + + /* VDD Calibration Control 3 */ + MmioAndThenOr32 ( + HpipeAddr + HPIPE_VDD_CAL_CTRL_REG, + ~HPIPE_EXT_SELLV_RXSAMPL_MASK, + 0x10 << HPIPE_EXT_SELLV_RXSAMPL_OFFSET + ); + + /* DFE Resolution Control */ + MmioOr32 (HpipeAddr + HPIPE_DFE_REG0, HPIPE_DFE_RES_FORCE_MASK); + + /* DFE F3-F5 Coefficient Control */ + MmioAnd32 ( + HpipeAddr + HPIPE_DFE_F3_F5_REG, + ~(HPIPE_DFE_F3_F5_DFE_EN_MASK | HPIPE_DFE_F3_F5_DFE_CTRL_MASK) + ); + + /* Hpipe Generation 3 settings 3 */ + Mask =3D HPIPE_GX_SET3_FFE_CAP_SEL_MASK | + HPIPE_GX_SET3_FFE_RES_SEL_MASK | + HPIPE_GX_SET3_FFE_SETTING_FORCE_MASK | + HPIPE_GX_SET3_FFE_DEG_RES_LEVEL_MASK | + HPIPE_GX_SET3_FFE_LOAD_RES_LEVEL_MASK; + Data =3D 0xf | + (0x4 << HPIPE_GX_SET3_FFE_RES_SEL_OFFSET) | + (0x1 << HPIPE_GX_SET3_FFE_SETTING_FORCE_OFFSET) | + (0x1 << HPIPE_GX_SET3_FFE_DEG_RES_LEVEL_OFFSET) | + (0x3 << HPIPE_GX_SET3_FFE_LOAD_RES_LEVEL_OFFSET); + MmioAndThenOr32 (HpipeAddr + HPIPE_G3_SET3_REG, ~Mask, Data); + + /* Hpipe Generation 3 settings 4 */ + MmioAndThenOr32 ( + HpipeAddr + HPIPE_G3_SET4_REG, + ~HPIPE_GX_SET4_DFE_RES_MASK, + 0x2 << HPIPE_GX_SET4_DFE_RES_OFFSET + ); + + /* Offset Phase Control - force offset and toggle 'valid' bit */ + MmioAndThenOr32 ( + HpipeAddr + HPIPE_PHASE_CONTROL_REG, + ~(HPIPE_OS_PH_OFFSET_MASK | HPIPE_OS_PH_OFFSET_FORCE_MASK), + 0x5c | (0x1 << HPIPE_OS_PH_OFFSET_FORCE_OFFSET) + ); + MmioAndThenOr32 ( + HpipeAddr + HPIPE_PHASE_CONTROL_REG, + ~HPIPE_OS_PH_VALID_MASK, + 0x1 << HPIPE_OS_PH_VALID_OFFSET + ); + MmioAnd32 ( + HpipeAddr + HPIPE_PHASE_CONTROL_REG, + ~HPIPE_OS_PH_VALID_MASK + ); + + /* Set G1 TX amplitude and TX post emphasis value */ + Mask =3D HPIPE_GX_SET0_TX_AMP_MASK | + HPIPE_GX_SET0_TX_AMP_ADJ_MASK | + HPIPE_GX_SET0_TX_EMPH1_MASK | + HPIPE_GX_SET0_TX_EMPH1_EN_MASK; + Data =3D (0x8 << HPIPE_GX_SET0_TX_AMP_OFFSET) | + (0x1 << HPIPE_GX_SET0_TX_AMP_ADJ_OFFSET) | + (0x1 << HPIPE_GX_SET0_TX_EMPH1_OFFSET) | + (0x1 << HPIPE_GX_SET0_TX_EMPH1_EN_OFFSET); + MmioAndThenOr32 (HpipeAddr + HPIPE_G1_SET0_REG, ~Mask, Data); + + /* Set G2 TX amplitude and TX post emphasis value */ + Mask =3D HPIPE_GX_SET0_TX_AMP_MASK | + HPIPE_GX_SET0_TX_AMP_ADJ_MASK | + HPIPE_GX_SET0_TX_EMPH1_MASK | + HPIPE_GX_SET0_TX_EMPH1_EN_MASK; + Data =3D (0xa << HPIPE_GX_SET0_TX_AMP_OFFSET) | + (0x1 << HPIPE_GX_SET0_TX_AMP_ADJ_OFFSET) | + (0x2 << HPIPE_GX_SET0_TX_EMPH1_OFFSET) | + (0x1 << HPIPE_GX_SET0_TX_EMPH1_EN_OFFSET); + MmioAndThenOr32 (HpipeAddr + HPIPE_G2_SET0_REG, ~Mask, Data); + + /* Set G3 TX amplitude and TX post emphasis value */ + Mask =3D HPIPE_GX_SET0_TX_AMP_MASK | + HPIPE_GX_SET0_TX_AMP_ADJ_MASK | + HPIPE_GX_SET0_TX_EMPH1_MASK | + HPIPE_GX_SET0_TX_EMPH1_EN_MASK | + HPIPE_GX_SET0_TX_SLEW_RATE_SEL_MASK | + HPIPE_GX_SET0_TX_SLEW_CTRL_EN_MASK; + Data =3D (0xe << HPIPE_GX_SET0_TX_AMP_OFFSET) | + (0x1 << HPIPE_GX_SET0_TX_AMP_ADJ_OFFSET) | + (0x6 << HPIPE_GX_SET0_TX_EMPH1_OFFSET) | + (0x1 << HPIPE_GX_SET0_TX_EMPH1_EN_OFFSET) | + (0x4 << HPIPE_GX_SET0_TX_SLEW_RATE_SEL_OFFSET); + MmioAndThenOr32 (HpipeAddr + HPIPE_G3_SET0_REG, ~Mask, Data); + + /* SERDES External Configuration 2 register - enable spread spectrum clo= ck */ + MmioOr32 (SdIpAddr + SD_EXTERNAL_CONFIG2_REG, SD_EXTERNAL_CONFIG2_SSC_EN= ABLE_MASK); + /* DFE reset sequence */ - RegSet (HpipeAddr + HPIPE_PWR_CTR_REG, - 0x1 << HPIPE_PWR_CTR_RST_DFE_OFFSET, HPIPE_PWR_CTR_RST_DFE_MASK); - RegSet (HpipeAddr + HPIPE_PWR_CTR_REG, - 0x0 << HPIPE_PWR_CTR_RST_DFE_OFFSET, HPIPE_PWR_CTR_RST_DFE_MASK); + MmioAndThenOr32 ( + HpipeAddr + HPIPE_PWR_CTR_REG, + ~HPIPE_PWR_CTR_RST_DFE_MASK, + 0x1 + ); + MmioAnd32 ( + HpipeAddr + HPIPE_PWR_CTR_REG, + ~HPIPE_PWR_CTR_RST_DFE_MASK + ); =20 /* SW reset for interupt logic */ - RegSet (HpipeAddr + HPIPE_PWR_CTR_REG, - 0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET, HPIPE_PWR_CTR_SFT_RST_MASK); - RegSet (HpipeAddr + HPIPE_PWR_CTR_REG, - 0x0 << HPIPE_PWR_CTR_SFT_RST_OFFSET, HPIPE_PWR_CTR_SFT_RST_MASK); + MmioAndThenOr32 ( + HpipeAddr + HPIPE_PWR_CTR_REG, + ~HPIPE_PWR_CTR_SFT_RST_MASK, + 0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET + ); + MmioAnd32 ( + HpipeAddr + HPIPE_PWR_CTR_REG, + ~HPIPE_PWR_CTR_SFT_RST_MASK + ); } =20 STATIC @@ -738,7 +921,7 @@ ComPhySataPowerUp ( =20 DEBUG((DEBUG_INFO, "ComPhy: stage: Analog paramters from ETP(HW)\n")); =20 - ComPhySataSetAnalogParameters (HpipeAddr); + ComPhySataSetAnalogParameters (HpipeAddr, SdIpAddr); =20 DEBUG((DEBUG_INFO, "ComPhy: stage: ComPhy power up\n")); =20 @@ -930,8 +1113,8 @@ ComPhySgmiiPowerUp ( /* Set analog paramters from ETP(HW) - for now use the default data */ DEBUG((DEBUG_INFO, "ComPhy: stage: Analog paramters from ETP(HW)\n")); =20 - RegSet (HpipeAddr + HPIPE_G1_SET_0_REG, - 0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET, HPIPE_G1_SET_0_G1_TX_EMPH1_M= ASK); + RegSet (HpipeAddr + HPIPE_G1_SET0_REG, + 0x1 << HPIPE_GX_SET0_TX_EMPH1_OFFSET, HPIPE_GX_SET0_TX_EMPH1_MASK); =20 DEBUG((DEBUG_INFO, "ComPhy: stage: RFU configurations - Power Up PLL,Tx,= Rx\n")); =20 diff --git a/Platform/Marvell/Library/ComPhyLib/ComPhyLib.h b/Platform/Marv= ell/Library/ComPhyLib/ComPhyLib.h index 24839b2..8418315 100644 --- a/Platform/Marvell/Library/ComPhyLib/ComPhyLib.h +++ b/Platform/Marvell/Library/ComPhyLib/ComPhyLib.h @@ -143,6 +143,11 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH D= AMAGE. #define SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET 6 #define SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK (0x1 << SD_EXTERNAL_CONF= IG1_RF_RESET_IN_OFFSET) =20 +#define SD_EXTERNAL_CONFIG2_REG 0x8 +#define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET 4 +#define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK (0x1 << SD_EXTERNAL_CONF= IG2_PIN_DFE_EN_OFFSET) +#define SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET 7 +#define SD_EXTERNAL_CONFIG2_SSC_ENABLE_MASK (0x1 << SD_EXTERNAL_CONF= IG2_SSC_ENABLE_OFFSET) =20 #define SD_EXTERNAL_STATUS0_REG 0x18 #define SD_EXTERNAL_STATUS0_PLL_TX_OFFSET 2 @@ -176,19 +181,39 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE. #define HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET 15 #define HPIPE_DFE_F3_F5_DFE_CTRL_MASK (0x1 << HPIPE_DFE_F3_F5_= DFE_CTRL_OFFSET) =20 -#define HPIPE_G1_SET_0_REG 0x034 -#define HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET 7 -#define HPIPE_G1_SET_0_G1_TX_EMPH1_MASK (0xf << HPIPE_G1_SET_0_G= 1_TX_EMPH1_OFFSET) - -#define HPIPE_G1_SET_1_REG 0x038 -#define HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET 0 -#define HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK (0x7 << HPIPE_G1_SET_1_G= 1_RX_SELMUPI_OFFSET) -#define HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET 3 -#define HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK (0x7 << HPIPE_G1_SET_1_G= 1_RX_SELMUPP_OFFSET) -#define HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET 10 -#define HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK (0x1 << HPIPE_G1_SET_1_G= 1_RX_DFE_EN_OFFSET) - -#define HPIPE_G2_SETTINGS_1_REG 0x040 +#define HPIPE_G1_SET0_REG 0x034 +#define HPIPE_G2_SET0_REG 0x03c +#define HPIPE_G3_SET0_REG 0x044 +#define HPIPE_GX_SET0_TX_AMP_OFFSET 1 +#define HPIPE_GX_SET0_TX_AMP_MASK (0x1f << HPIPE_GX_SET0_T= X_AMP_OFFSET) +#define HPIPE_GX_SET0_TX_AMP_ADJ_OFFSET 6 +#define HPIPE_GX_SET0_TX_AMP_ADJ_MASK (0x1 << HPIPE_GX_SET0_TX= _AMP_ADJ_OFFSET) +#define HPIPE_GX_SET0_TX_EMPH1_OFFSET 7 +#define HPIPE_GX_SET0_TX_EMPH1_MASK (0xf << HPIPE_GX_SET0_TX= _EMPH1_OFFSET) +#define HPIPE_GX_SET0_TX_EMPH1_EN_OFFSET 11 +#define HPIPE_GX_SET0_TX_EMPH1_EN_MASK (0x1 << HPIPE_GX_SET0_TX= _EMPH1_EN_OFFSET) +#define HPIPE_GX_SET0_TX_SLEW_RATE_SEL_OFFSET 12 +#define HPIPE_GX_SET0_TX_SLEW_RATE_SEL_MASK (0x7 << HPIPE_GX_SET0_TX= _SLEW_RATE_SEL_OFFSET) +#define HPIPE_GX_SET0_TX_SLEW_CTRL_EN_OFFSET 15 +#define HPIPE_GX_SET0_TX_SLEW_CTRL_EN_MASK (0x1 << HPIPE_GX_SET0_TX= _SLEW_CTRL_EN_OFFSET) + +#define HPIPE_G1_SET1_REG 0x038 +#define HPIPE_G2_SET1_REG 0x040 +#define HPIPE_G3_SET1_REG 0x048 +#define HPIPE_GX_SET1_RX_SELMUPI_OFFSET 0 +#define HPIPE_GX_SET1_RX_SELMUPI_MASK (0x7 << HPIPE_GX_SET1_RX= _SELMUPI_OFFSET) +#define HPIPE_GX_SET1_RX_SELMUPP_OFFSET 3 +#define HPIPE_GX_SET1_RX_SELMUPP_MASK (0x7 << HPIPE_GX_SET1_RX= _SELMUPP_OFFSET) +#define HPIPE_GX_SET1_RX_SELMUFI_OFFSET 6 +#define HPIPE_GX_SET1_RX_SELMUFI_MASK (0x3 << HPIPE_GX_SET1_RX= _SELMUFI_OFFSET) +#define HPIPE_GX_SET1_RX_SELMUFF_OFFSET 8 +#define HPIPE_GX_SET1_RX_SELMUFF_MASK (0x3 << HPIPE_GX_SET1_RX= _SELMUFF_OFFSET) +#define HPIPE_GX_SET1_RX_DFE_EN_OFFSET 10 +#define HPIPE_GX_SET1_RX_DFE_EN_MASK (0x1 << HPIPE_GX_SET1_RX= _DFE_EN_OFFSET) +#define HPIPE_GX_SET1_RX_DIGCK_DIV_OFFSET 11 +#define HPIPE_GX_SET1_RX_DIGCK_DIV_MASK (0x3 << HPIPE_GX_SET1_RX= _DIGCK_DIV_OFFSET) +#define HPIPE_GX_SET1_SAMPLER_INPAIRX2_EN_OFFSET 13 +#define HPIPE_GX_SET1_SAMPLER_INPAIRX2_EN_MASK (0x1 << HPIPE_GX_SET1_SA= MPLER_INPAIRX2_EN_OFFSET) =20 #define HPIPE_LOOPBACK_REG 0x08c #define HPIPE_LOOPBACK_SEL_OFFSET 1 @@ -210,6 +235,14 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH D= AMAGE. =20 #define HPIPE_VTHIMPCAL_CTRL_REG 0x104 =20 +#define HPIPE_VDD_CAL_CTRL_REG 0x114 +#define HPIPE_EXT_SELLV_RXSAMPL_OFFSET 5 +#define HPIPE_EXT_SELLV_RXSAMPL_MASK (0x1f << HPIPE_EXT_SELLV= _RXSAMPL_OFFSET) + +#define HPIPE_VDD_CAL_0_REG 0x108 +#define HPIPE_CAL_VDD_CONT_MODE_OFFSET 15 +#define HPIPE_CAL_VDD_CONT_MODE_MASK (0x1 << HPIPE_CAL_VDD_CO= NT_MODE_OFFSET) + #define HPIPE_PCIE_REG0 0x120 #define HPIPE_PCIE_IDLE_SYNC_OFFSET 12 #define HPIPE_PCIE_IDLE_SYNC_MASK (0x1 << HPIPE_PCIE_IDLE_= SYNC_OFFSET) @@ -244,11 +277,57 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE. =20 #define HPIPE_PLLINTP_REG1 0x150 =20 -#define HPIPE_PWR_CTR_DTL_REG 0x184 -#define HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET 0x2 -#define HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK (0x1 << HPIPE_PWR_CTR_DT= L_FLOOP_EN_OFFSET) - -#define HPIPE_RX_REG3 0x188 +#define HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG 0x16C +#define HPIPE_RX_SAMPLER_OS_GAIN_OFFSET 6 +#define HPIPE_RX_SAMPLER_OS_GAIN_MASK (0x3 << HPIPE_RX_SAMPLER= _OS_GAIN_OFFSET) +#define HPIPE_SAMPLER_OFFSET 12 +#define HPIPE_SAMPLER_MASK (0x1 << HPIPE_SAMPLER_OF= FSET) + +#define HPIPE_TX_REG1_REG 0x174 +#define HPIPE_TX_REG1_TX_EMPH_RES_OFFSET 5 +#define HPIPE_TX_REG1_TX_EMPH_RES_MASK (0x3 << HPIPE_TX_REG1_TX= _EMPH_RES_OFFSET) +#define HPIPE_TX_REG1_SLC_EN_OFFSET 10 +#define HPIPE_TX_REG1_SLC_EN_MASK (0x3f << HPIPE_TX_REG1_S= LC_EN_OFFSET) + +#define HPIPE_PWR_CTR_DTL_REG 0x184 +#define HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET 0 +#define HPIPE_PWR_CTR_DTL_SQ_DET_EN_MASK (0x1 << HPIPE_PWR_CT= R_DTL_SQ_DET_EN_OFFSET) +#define HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET 1 +#define HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_MASK (0x1 << HPIPE_PWR_CT= R_DTL_SQ_PLOOP_EN_OFFSET) +#define HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET 2 +#define HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK (0x1 << HPIPE_PWR_CT= R_DTL_FLOOP_EN_OFFSET) +#define HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET 4 +#define HPIPE_PWR_CTR_DTL_CLAMPING_SEL_MASK (0x7 << HPIPE_PWR_CT= R_DTL_CLAMPING_SEL_OFFSET) +#define HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET 10 +#define HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_MASK (0x1 << HPIPE_PWR_CT= R_DTL_INTPCLK_DIV_FORCE_OFFSET) +#define HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET 12 +#define HPIPE_PWR_CTR_DTL_CLK_MODE_MASK (0x3 << HPIPE_PWR_CT= R_DTL_CLK_MODE_OFFSET) +#define HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET 14 +#define HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_MASK (1 << HPIPE_PWR_CTR_= DTL_CLK_MODE_FORCE_OFFSET) + +#define HPIPE_PHASE_CONTROL_REG 0x188 +#define HPIPE_OS_PH_OFFSET_OFFSET 0 +#define HPIPE_OS_PH_OFFSET_MASK (0x7f << HPIPE_OS_PH_OFF= SET_OFFSET) +#define HPIPE_OS_PH_OFFSET_FORCE_OFFSET 7 +#define HPIPE_OS_PH_OFFSET_FORCE_MASK (0x1 << HPIPE_OS_PH_OFFS= ET_FORCE_OFFSET) +#define HPIPE_OS_PH_VALID_OFFSET 8 +#define HPIPE_OS_PH_VALID_MASK (0x1 << HPIPE_OS_PH_VALI= D_OFFSET) + +#define HPIPE_FRAME_DETECT_CTRL_0_REG 0x214 +#define HPIPE_TRAIN_PAT_NUM_OFFSET 0x7 +#define HPIPE_TRAIN_PAT_NUM_MASK (0x1FF << HPIPE_TRAIN_PA= T_NUM_OFFSET) + +#define HPIPE_FRAME_DETECT_CTRL_3_REG 0x220 +#define HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET 12 +#define HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_MASK (0x1 << HPIPE_PATTERN_LO= CK_LOST_TIMEOUT_EN_OFFSET) + +#define HPIPE_DME_REG 0x228 +#define HPIPE_DME_ETHERNET_MODE_OFFSET 7 +#define HPIPE_DME_ETHERNET_MODE_MASK (0x1 << HPIPE_DME_ETHERN= ET_MODE_OFFSET) + +#define HPIPE_TX_TRAIN_CTRL_0_REG 0x268 +#define HPIPE_TX_TRAIN_P2P_HOLD_OFFSET 15 +#define HPIPE_TX_TRAIN_P2P_HOLD_MASK (0x1 << HPIPE_TX_TRAIN_P= 2P_HOLD_OFFSET) =20 #define HPIPE_TX_TRAIN_CTRL_REG 0x26C #define HPIPE_TX_TRAIN_CTRL_G1_OFFSET 0 @@ -267,10 +346,35 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE. #define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET 7 #define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK (0x1 << HPIPE_TX_TRAIN_C= OE_FM_PIN_PCIE3_OFFSET) =20 -#define HPIPE_G1_SETTINGS_3_REG 0x440 -#define HPIPE_G1_SETTINGS_4_REG 0x444 -#define HPIPE_G2_SETTINGS_3_REG 0x448 -#define HPIPE_G2_SETTINGS_4_REG 0x44C +#define HPIPE_G1_SET3_REG 0x440 +#define HPIPE_G2_SET3_REG 0x448 +#define HPIPE_G3_SET3_REG 0x450 +#define HPIPE_GX_SET3_FFE_CAP_SEL_OFFSET 0 +#define HPIPE_GX_SET3_FFE_CAP_SEL_MASK (0xf << HPIPE_GX_SET3_FF= E_CAP_SEL_OFFSET) +#define HPIPE_GX_SET3_FFE_RES_SEL_OFFSET 4 +#define HPIPE_GX_SET3_FFE_RES_SEL_MASK (0x7 << HPIPE_GX_SET3_FF= E_RES_SEL_OFFSET) +#define HPIPE_GX_SET3_FFE_SETTING_FORCE_OFFSET 7 +#define HPIPE_GX_SET3_FFE_SETTING_FORCE_MASK (0x1 << HPIPE_GX_SET3_FF= E_SETTING_FORCE_OFFSET) +#define HPIPE_GX_SET3_FBCK_SEL_OFFSET 9 +#define HPIPE_GX_SET3_FBCK_SEL_MASK (0x1 << HPIPE_GX_SET3_FB= CK_SEL_OFFSET) +#define HPIPE_GX_SET3_FFE_DEG_RES_LEVEL_OFFSET 12 +#define HPIPE_GX_SET3_FFE_DEG_RES_LEVEL_MASK (0x3 << HPIPE_GX_SET3_FF= E_DEG_RES_LEVEL_OFFSET) +#define HPIPE_GX_SET3_FFE_LOAD_RES_LEVEL_OFFSET 14 +#define HPIPE_GX_SET3_FFE_LOAD_RES_LEVEL_MASK (0x3 << HPIPE_GX_SET3_FF= E_LOAD_RES_LEVEL_OFFSET) + +#define HPIPE_G1_SET4_REG 0x444 +#define HPIPE_G2_SET4_REG 0x44C +#define HPIPE_G3_SET4_REG 0x454 +#define HPIPE_GX_SET4_DFE_RES_OFFSET 8 +#define HPIPE_GX_SET4_DFE_RES_MASK (0x3 << HPIPE_GX_SET4_DF= E_RES_OFFSET) + +#define HPIPE_TX_PRESET_INDEX_REG 0x468 +#define HPIPE_TX_PRESET_INDEX_OFFSET 0 +#define HPIPE_TX_PRESET_INDEX_MASK (0xf << HPIPE_TX_PRESET_= INDEX_OFFSET) + +#define HPIPE_DFE_CONTROL_REG 0x470 +#define HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET 14 +#define HPIPE_DFE_TX_MAX_DFE_ADAPT_MASK (0x3 << HPIPE_DFE_TX_MAX= _DFE_ADAPT_OFFSET) =20 #define HPIPE_DFE_CTRL_28_REG 0x49C #define HPIPE_DFE_CTRL_28_PIPE4_OFFSET 7 --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun Apr 28 20:57:55 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1499174692534977.0245451137365; Tue, 4 Jul 2017 06:24:52 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id c185sm4980970lfc.43.2017.07.04.06.24.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 04 Jul 2017 06:24:32 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=3mKqGKmvPcFhcWW9zOmaiYUzuLS6Ib4vc/7uIOoSyX8=; b=F2wFv/Sl0PnA4UDi5aCtshH5f8HBNxNszz2vYkYDPpynO8QXwPAigN4kDeRSm/dku1 JeoJOGJVWRE7yuXpbPzM8wQjVOCSX/0DEnEEDdIWzkORcKkkyCh6JkKscECYeb3xeIcR eI7114UrVKC+ZfYa9gpiT4hTpk+u983plJYwx4haLFUWVKtCav26tRUCb88zWWbDkZyU z5JosE94ynl46QiuoFrwPcJzSXoDzstzGuqdChxXOZ04iYlXErVfqSuMRdP532taXWmp 0KL3jE5u0F8wZsp7GE2vPbh0j2pV03TDZKEq+RANmxgjM1LWXP3iLIv3GUpnzy2ibXoN gsXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=3mKqGKmvPcFhcWW9zOmaiYUzuLS6Ib4vc/7uIOoSyX8=; b=sOKdD67q1Sl49/zJ3EGQovoraw+o8JRtKGz0Q8hSQn0/AtfCam+D38TEhuIY8TgxFU 9SmpCd1OSqa+UMdPOI8aWdktcgurMQEjsqmRsOsFZf0eCuP+GsCDwciLtZWs10dShnVW 3peVHRjWsGFarguuJWM7C5/40CREhY9sq8fSXvtKD/sgG7q3CeqT6v1Nh0uB5PdglHsD fxE5rRkMeZs8M0dRkTTly5dZ264CYSph4CyPWC+eY0j4CR2B4nkcBkVwbtARHBqsV2k4 OsIHUvIkxE8qnKaVtHh3iTng1H825dhOq1A2VIhPufuIQ6wUEd1Tqt5cX0QUOxxhEZ+y Emmg== X-Gm-Message-State: AKS2vOzZCmL8PZud1DaBLxP4EBz3g0nZmOF+GQiGOxQCKkFxtCXi7UH9 iHE0+QLaav3mdpV7sOHa6Q== X-Received: by 10.46.22.28 with SMTP id w28mr12526722ljd.62.1499174673155; Tue, 04 Jul 2017 06:24:33 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Tue, 4 Jul 2017 15:24:09 +0200 Message-Id: <1499174653-330-7-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1499174653-330-1-git-send-email-mw@semihalf.com> References: <1499174653-330-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 06/10] Platform/Marvell: ComPhyLib: Configure analog parameters for PCIE X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, leif.lindholm@linaro.org, ard.biesheuvel@linaro.org MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This patch adds analog parameters configuration for PCIE with the values defined during electrical tests of the interface. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Marcin Wojtas Reviewed-by: Ard Biesheuvel --- Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c | 149 +++++++++++++++++++= +++- Platform/Marvell/Library/ComPhyLib/ComPhyLib.h | 53 +++++++- 2 files changed, 200 insertions(+), 2 deletions(-) diff --git a/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c b/Platform/Ma= rvell/Library/ComPhyLib/ComPhyCp110.c index ea9525a..6f26bc4 100755 --- a/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c +++ b/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c @@ -187,6 +187,10 @@ ComPhyPciePhyConfiguration ( Mask |=3D HPIPE_MISC_REFCLK_SEL_MASK; Data |=3D 0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET; } + + /* Force ICP */ + Mask |=3D HPIPE_MISC_ICP_FORCE_MASK; + Data |=3D 0x1 << HPIPE_MISC_ICP_FORCE_OFFSET; RegSet (HpipeAddr + HPIPE_MISC_REG, Data, Mask); =20 if (PcieClk) { @@ -216,7 +220,9 @@ ComPhyPciePhyConfiguration ( /* Set Maximal PHY Generation Setting (8Gbps) */ Mask =3D HPIPE_INTERFACE_GEN_MAX_MASK; Data =3D 0x2 << HPIPE_INTERFACE_GEN_MAX_OFFSET; - + /* Bypass frame detection and sync detection for RX DATA */ + Mask |=3D HPIPE_INTERFACE_DET_BYPASS_MASK; + Data |=3D 0x1 << HPIPE_INTERFACE_DET_BYPASS_OFFSET; /* Set Link Train Mode (Tx training control pins are used) */ Mask |=3D HPIPE_INTERFACE_LINK_TRAIN_MASK; Data |=3D 0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET; @@ -256,6 +262,143 @@ ComPhyPciePhyConfiguration ( =20 STATIC VOID +ComPhyPcieSetAnalogParameters ( + IN EFI_PHYSICAL_ADDRESS HpipeAddr +) +{ + UINT32 Data, Mask; + + /* Set preset sweep configurations */ + Mask =3D HPIPE_TX_TX_STATUS_CHECK_MODE_MASK | + HPIPE_TX_NUM_OF_PRESET_MASK | + HPIPE_TX_SWEEP_PRESET_EN_MASK; + Data =3D (0x1 << HPIPE_TX_STATUS_CHECK_MODE_OFFSET) | + (0x7 << HPIPE_TX_NUM_OF_PRESET_OFFSET) | + (0x1 << HPIPE_TX_SWEEP_PRESET_EN_OFFSET); + MmioAndThenOr32 (HpipeAddr + HPIPE_TX_TRAIN_CTRL_11_REG, ~Mask, Data); + + /* Tx train start configuration */ + Mask =3D HPIPE_TX_TRAIN_START_SQ_EN_MASK | + HPIPE_TX_TRAIN_START_FRM_DET_EN_MASK | + HPIPE_TX_TRAIN_START_FRM_LOCK_EN_MASK | + HPIPE_TX_TRAIN_WAIT_TIME_EN_MASK; + Data =3D (0x1 << HPIPE_TX_TRAIN_START_SQ_EN_OFFSET) | + (0x1 << HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET); + MmioAndThenOr32 (HpipeAddr + HPIPE_TX_TRAIN_CTRL_5_REG, ~Mask, Data); + + /* Enable Tx train P2P */ + MmioOr32 (HpipeAddr + HPIPE_TX_TRAIN_CTRL_0_REG, HPIPE_TX_TRAIN_P2P_HOLD= _MASK); + + /* Configure Tx train timeout */ + MmioAndThenOr32 ( + HpipeAddr + HPIPE_TX_TRAIN_CTRL_4_REG, + ~HPIPE_TRX_TRAIN_TIMER_MASK, + 0x17 << HPIPE_TRX_TRAIN_TIMER_OFFSET + ); + + /* Disable G0/G1/GN1 adaptation */ + MmioAnd32 ( + HpipeAddr + HPIPE_TX_TRAIN_CTRL_REG, + ~(HPIPE_TX_TRAIN_CTRL_G1_MASK | HPIPE_TX_TRAIN_CTRL_GN1_MASK | H= PIPE_TX_TRAIN_CTRL_G0_OFFSET) + ); + + /* Disable DTL frequency loop */ + MmioAnd32 (HpipeAddr + HPIPE_PWR_CTR_DTL_REG, ~HPIPE_PWR_CTR_DTL_FLOOP_E= N_MASK); + + /* Configure Generation 3 DFE */ + MmioAndThenOr32 ( + HpipeAddr + HPIPE_G3_SET4_REG, + ~HPIPE_GX_SET4_DFE_RES_MASK, + 0x3 << HPIPE_GX_SET4_DFE_RES_OFFSET + ); + + /* Use TX/RX training result for DFE */ + MmioAnd32 (HpipeAddr + HPIPE_DFE_REG0, ~HPIPE_DFE_RES_FORCE_MASK); + + /* Configure initial and final coefficient value for receiver */ + MmioAndThenOr32 (HpipeAddr + HPIPE_G3_SET1_REG, ~Mask, Data); + Mask =3D HPIPE_GX_SET1_RX_SELMUPI_MASK | + HPIPE_GX_SET1_RX_SELMUPP_MASK | + HPIPE_GX_SET1_SAMPLER_INPAIRX2_EN_MASK; + Data =3D 0x1 | (0x1 << HPIPE_GX_SET1_RX_SELMUPP_OFFSET); + MmioAndThenOr32 (HpipeAddr + HPIPE_G3_SET1_REG, ~Mask, Data); + + /* Trigger sampler 5us enable pulse */ + MmioAndThenOr32 ( + HpipeAddr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, + ~HPIPE_SAMPLER_MASK, + 0x1 << HPIPE_SAMPLER_OFFSET + ); + MicroSecondDelay (5); + MmioAnd32 ( + HpipeAddr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, + ~HPIPE_SAMPLER_MASK + ); + + /* FFE resistor tuning for different bandwidth */ + Mask =3D HPIPE_GX_SET3_FFE_DEG_RES_LEVEL_MASK | + HPIPE_GX_SET3_FFE_LOAD_RES_LEVEL_MASK; + Data =3D (0x1 << HPIPE_GX_SET3_FFE_DEG_RES_LEVEL_OFFSET) | + (0x3 << HPIPE_GX_SET3_FFE_LOAD_RES_LEVEL_OFFSET); + MmioAndThenOr32 (HpipeAddr + HPIPE_G3_SET3_REG, ~Mask, Data); + + /* Pattern lock lost timeout disable */ + MmioAnd32 (HpipeAddr + HPIPE_FRAME_DETECT_CTRL_3_REG, ~HPIPE_PATTERN_LOC= K_LOST_TIMEOUT_EN_MASK); + + /* Configure DFE adaptations */ + MmioAndThenOr32 ( + HpipeAddr + HPIPE_CDR_CONTROL_REG, + ~(HPIPE_CDR_MAX_DFE_ADAPT_1_MASK | HPIPE_CDR_MAX_DFE_ADAPT_0_MAS= K | HPIPE_CDR_RX_MAX_DFE_ADAPT_1_MASK), + 0x1 << HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET + ); + MmioAnd32 (HpipeAddr + HPIPE_DFE_CONTROL_REG, ~HPIPE_DFE_TX_MAX_DFE_ADAP= T_MASK); + + /* Hpipe Generation 2 setting 1*/ + MmioAndThenOr32 ( + HpipeAddr + HPIPE_G2_SET1_REG, + ~(HPIPE_GX_SET1_RX_SELMUPI_MASK | HPIPE_GX_SET1_RX_SELMUPP_MASK = | HPIPE_GX_SET1_RX_SELMUFI_MASK), + 0x1 << HPIPE_GX_SET1_RX_SELMUPP_OFFSET + ); + + /* DFE enable */ + MmioAndThenOr32 ( + HpipeAddr + HPIPE_G2_SET4_REG, + ~HPIPE_GX_SET4_DFE_RES_MASK, + 0x3 << HPIPE_GX_SET4_DFE_RES_OFFSET + ); + + /* Configure DFE Resolution */ + MmioAndThenOr32 ( + HpipeAddr + HPIPE_LANE_CFG4_REG, + ~HPIPE_LANE_CFG4_DFE_EN_SEL_MASK, + 0x1 << HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET + ); + + /* VDD calibration control */ + MmioAndThenOr32 ( + HpipeAddr + HPIPE_VDD_CAL_CTRL_REG, + ~HPIPE_EXT_SELLV_RXSAMPL_MASK, + 0x16 << HPIPE_EXT_SELLV_RXSAMPL_OFFSET + ); + + /* Set PLL Charge-pump Current Control */ + MmioAndThenOr32 (HpipeAddr + HPIPE_G3_SET5_REG, ~HPIPE_GX_SET5_ICP_MASK,= 0x4); + + /* Set lane rqualization remote setting */ + Mask =3D HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_MASK | + HPIPE_LANE_CFG_FOM_ONLY_MODE_MASK | + HPIPE_LANE_CFG_FOM_PRESET_VECTOR_MASK; + Data =3D (0x1 << HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET) | + (0x1 << HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET) | + (0x2 << HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET); + MmioAndThenOr32 (HpipeAddr + HPIPE_LANE_EQ_REMOTE_SETTING_REG, ~Mask, Da= ta); + + /* Set phy in root complex mode */ + MmioOr32 (HpipeAddr + HPIPE_LANE_EQU_CONFIG_0_REG, HPIPE_CFG_PHY_RC_EP_M= ASK); +} + +STATIC +VOID ComPhyPciePhyPowerUp ( IN EFI_PHYSICAL_ADDRESS HpipeAddr ) @@ -312,6 +455,10 @@ ComPhyPciePowerUp ( =20 ComPhyPciePhyConfiguration (ComPhyAddr, HpipeAddr); =20 + DEBUG((DEBUG_INFO, "ComPhy: stage: Set analog paramters\n")); + + ComPhyPcieSetAnalogParameters (HpipeAddr); + DEBUG((DEBUG_INFO, "ComPhy: stage: ComPhy power up\n")); =20 ComPhyPciePhyPowerUp (HpipeAddr); diff --git a/Platform/Marvell/Library/ComPhyLib/ComPhyLib.h b/Platform/Marv= ell/Library/ComPhyLib/ComPhyLib.h index 8418315..58f1d81 100644 --- a/Platform/Marvell/Library/ComPhyLib/ComPhyLib.h +++ b/Platform/Marvell/Library/ComPhyLib/ComPhyLib.h @@ -174,7 +174,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DA= MAGE. #define HPIPE_DFE_RES_FORCE_OFFSET 15 #define HPIPE_DFE_RES_FORCE_MASK (0x1 << HPIPE_DFE_RES_FO= RCE_OFFSET) =20 - #define HPIPE_DFE_F3_F5_REG 0x028 #define HPIPE_DFE_F3_F5_DFE_EN_OFFSET 14 #define HPIPE_DFE_F3_F5_DFE_EN_MASK (0x1 << HPIPE_DFE_F3_F5_= DFE_EN_OFFSET) @@ -224,6 +223,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DA= MAGE. #define HPIPE_INTERFACE_REG 0x94 #define HPIPE_INTERFACE_GEN_MAX_OFFSET 10 #define HPIPE_INTERFACE_GEN_MAX_MASK (0x3 << HPIPE_INTERFACE_= GEN_MAX_OFFSET) +#define HPIPE_INTERFACE_DET_BYPASS_OFFSET 12 +#define HPIPE_INTERFACE_DET_BYPASS_MASK (0x1 << HPIPE_INTERFACE_= DET_BYPASS_OFFSET) #define HPIPE_INTERFACE_LINK_TRAIN_OFFSET 14 #define HPIPE_INTERFACE_LINK_TRAIN_MASK (0x1 << HPIPE_INTERFACE_= LINK_TRAIN_OFFSET) =20 @@ -256,6 +257,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DA= MAGE. #define HPIPE_MISC_REG 0x13C #define HPIPE_MISC_CLK100M_125M_OFFSET 4 #define HPIPE_MISC_CLK100M_125M_MASK (0x1 << HPIPE_MISC_CLK10= 0M_125M_OFFSET) +#define HPIPE_MISC_ICP_FORCE_OFFSET 5 +#define HPIPE_MISC_ICP_FORCE_MASK (0x1 << HPIPE_MISC_ICP_F= ORCE_OFFSET) #define HPIPE_MISC_TXDCLK_2X_OFFSET 6 #define HPIPE_MISC_TXDCLK_2X_MASK (0x1 << HPIPE_MISC_TXDCL= K_2X_OFFSET) #define HPIPE_MISC_CLK500_EN_OFFSET 7 @@ -337,15 +340,45 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE. #define HPIPE_TX_TRAIN_CTRL_G0_OFFSET 2 #define HPIPE_TX_TRAIN_CTRL_G0_MASK (0x1 << HPIPE_TX_TRAIN_C= TRL_G0_OFFSET) =20 +#define HPIPE_TX_TRAIN_CTRL_4_REG 0x278 +#define HPIPE_TRX_TRAIN_TIMER_OFFSET 0 +#define HPIPE_TRX_TRAIN_TIMER_MASK (0x3FF << HPIPE_TRX_TRAI= N_TIMER_OFFSET) + #define HPIPE_PCIE_REG1 0x288 #define HPIPE_PCIE_REG3 0x290 =20 +#define HPIPE_TX_TRAIN_CTRL_5_REG 0x2A4 +#define HPIPE_TX_TRAIN_START_SQ_EN_OFFSET 11 +#define HPIPE_TX_TRAIN_START_SQ_EN_MASK (0x1 << HPIPE_TX_TRAIN_S= TART_SQ_EN_OFFSET) +#define HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET 12 +#define HPIPE_TX_TRAIN_START_FRM_DET_EN_MASK (0x1 << HPIPE_TX_TRAIN_S= TART_FRM_DET_EN_OFFSET) +#define HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET 13 +#define HPIPE_TX_TRAIN_START_FRM_LOCK_EN_MASK (0x1 << HPIPE_TX_TRAIN_S= TART_FRM_LOCK_EN_OFFSET) +#define HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET 14 +#define HPIPE_TX_TRAIN_WAIT_TIME_EN_MASK (0x1 << HPIPE_TX_TRAIN_W= AIT_TIME_EN_OFFSET) + #define HPIPE_TX_TRAIN_REG 0x31C #define HPIPE_TX_TRAIN_CHK_INIT_OFFSET 4 #define HPIPE_TX_TRAIN_CHK_INIT_MASK (0x1 << HPIPE_TX_TRAIN_C= HK_INIT_OFFSET) #define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET 7 #define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK (0x1 << HPIPE_TX_TRAIN_C= OE_FM_PIN_PCIE3_OFFSET) =20 +#define HPIPE_CDR_CONTROL_REG 0x418 +#define HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET 6 +#define HPIPE_CDR_MAX_DFE_ADAPT_1_MASK (0x7 << HPIPE_CDR_MAX_DF= E_ADAPT_1_OFFSET) +#define HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET 9 +#define HPIPE_CDR_MAX_DFE_ADAPT_0_MASK (0x7 << HPIPE_CDR_MAX_DF= E_ADAPT_0_OFFSET) +#define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET 12 +#define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_MASK (0x3 << HPIPE_CDR_RX_MAX= _DFE_ADAPT_1_OFFSET) + +#define HPIPE_TX_TRAIN_CTRL_11_REG 0x438 +#define HPIPE_TX_STATUS_CHECK_MODE_OFFSET 6 +#define HPIPE_TX_TX_STATUS_CHECK_MODE_MASK (0x1 << HPIPE_TX_STATUS_= CHECK_MODE_OFFSET) +#define HPIPE_TX_NUM_OF_PRESET_OFFSET 10 +#define HPIPE_TX_NUM_OF_PRESET_MASK (0x7 << HPIPE_TX_NUM_OF_= PRESET_OFFSET) +#define HPIPE_TX_SWEEP_PRESET_EN_OFFSET 15 +#define HPIPE_TX_SWEEP_PRESET_EN_MASK (0x1 << HPIPE_TX_SWEEP_P= RESET_EN_OFFSET) + #define HPIPE_G1_SET3_REG 0x440 #define HPIPE_G2_SET3_REG 0x448 #define HPIPE_G3_SET3_REG 0x450 @@ -380,6 +413,10 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH D= AMAGE. #define HPIPE_DFE_CTRL_28_PIPE4_OFFSET 7 #define HPIPE_DFE_CTRL_28_PIPE4_MASK (0x1 << HPIPE_DFE_CTRL_2= 8_PIPE4_OFFSET) =20 +#define HPIPE_G3_SET5_REG 0x548 +#define HPIPE_GX_SET5_ICP_OFFSET 0 +#define HPIPE_GX_SET5_ICP_MASK (0xf << HPIPE_GX_SET5_IC= P_OFFSET) + #define HPIPE_LANE_CONFIG0_REG 0x604 #define HPIPE_LANE_CONFIG0_MAX_PLL_OFFSET 9 #define HPIPE_LANE_CONFIG0_MAX_PLL_MASK (0x1 << HPIPE_LANE_CONFI= G0_MAX_PLL_OFFSET) @@ -393,15 +430,29 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE. #define HPIPE_LANE_CFG4_REG 0x620 #define HPIPE_LANE_CFG4_DFE_CTRL_OFFSET 0 #define HPIPE_LANE_CFG4_DFE_CTRL_MASK (0x7 << HPIPE_LANE_CFG4_= DFE_CTRL_OFFSET) +#define HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET 3 +#define HPIPE_LANE_CFG4_DFE_EN_SEL_MASK (0x1 << HPIPE_LANE_CFG4_= DFE_EN_SEL_OFFSET) #define HPIPE_LANE_CFG4_DFE_OVER_OFFSET 6 #define HPIPE_LANE_CFG4_DFE_OVER_MASK (0x1 << HPIPE_LANE_CFG4_= DFE_OVER_OFFSET) #define HPIPE_LANE_CFG4_SSC_CTRL_OFFSET 7 #define HPIPE_LANE_CFG4_SSC_CTRL_MASK (0x1 << HPIPE_LANE_CFG4_= SSC_CTRL_OFFSET) =20 +#define HPIPE_LANE_EQU_CONFIG_0_REG 0x69C +#define HPIPE_CFG_PHY_RC_EP_OFFSET 12 +#define HPIPE_CFG_PHY_RC_EP_MASK (0x1 << HPIPE_CFG_PHY_RC= _EP_OFFSET) + #define HPIPE_LANE_EQ_CFG1_REG 0x6a0 #define HPIPE_CFG_UPDATE_POLARITY_OFFSET 12 #define HPIPE_CFG_UPDATE_POLARITY_MASK (0x1 << HPIPE_CFG_UPDATE= _POLARITY_OFFSET) =20 +#define HPIPE_LANE_EQ_REMOTE_SETTING_REG 0x6f8 +#define HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET 0 +#define HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_MASK (0x1 << HPIPE_LANE_CFG_F= OM_DIRN_OVERRIDE_OFFSET) +#define HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET 1 +#define HPIPE_LANE_CFG_FOM_ONLY_MODE_MASK (0x1 << HPIPE_LANE_CFG_F= OM_ONLY_MODE_OFFFSET) +#define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET 2 +#define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_MASK (0xf << HPIPE_LANE_CFG_F= OM_PRESET_VECTOR_OFFSET) + #define HPIPE_RST_CLK_CTRL_REG 0x704 #define HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET 0 #define HPIPE_RST_CLK_CTRL_PIPE_RST_MASK (0x1 << HPIPE_RST_CLK_CT= RL_PIPE_RST_OFFSET) --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun Apr 28 20:57:55 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id c185sm4980970lfc.43.2017.07.04.06.24.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 04 Jul 2017 06:24:33 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=3ybErsVok4YIVXZW/3JS8lzyQhrV2WVr16smsBeVQWA=; b=vPZhPibtoL6S58BDlXqwL200Y2Z/q/Nf3twOe1YNgKDEEbnHSfkKCG7HZCuW1evQ59 kxhgsYCqFSlOLD4AiBy0Z2Z7dhVMTQP0AR9Q5+0+jGG+wAHSx9a5PnFdpjRWE5HL+ZMW 1i0id1EZV367zEhkL8Q5IiLNhdFHOpFqY0XrTHDfY8elF2nwz0uNWtA312GM7JVEalKt OUyKzbuYuafwbhdWnvBdVNEegh2ecqi9lq2U+sDzRzGqP3x97OA2LbUtlQnuSZGKaeYS b19Uiw6znAkKxcP2FyxWQq6Rz/WSRXJuZftnS50eBRN7o7+2adKo1T+94B+OZR6I8K+I zquw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=3ybErsVok4YIVXZW/3JS8lzyQhrV2WVr16smsBeVQWA=; b=G76WvTYch7kcZh4igGVQXE+n3qeBCwZAYt42RHfn4kcj1dpUquAAxGNVESBcEo1DDH 1ZNPo8qDkfSWSnl1hJ19n1MwrU63us9fwZ37oCmxw/dRz9rjxSQJnAJo/kZFoR/0kvRR YykepqYNFvw0esDUjW4/lN5D2vFL4zHrSocsoE0Z/S4pQicNoTVyYygcDiflq0v9HpkQ PMJUlqVg0ZoC+sl8rvz+mkznY0FHL/0ZojZ3Becf7traA9WxJTlYzZfO/lnukBgVW94s 3aqP9f5rVG9FwbrqlKRgh1/wRqK53LjN9uWOmdSZ1nCholliUWoj+BzwLZtvfHEUeMcf nBLw== X-Gm-Message-State: AKS2vOyhpGOCNKLxx8GWFaUv1P30BXZfxfhZTU76H1qST1F6bGgtGlL1 ef6dzLa+J6zyWvqyDt2AIA== X-Received: by 10.46.82.208 with SMTP id n77mr12876019lje.93.1499174674372; Tue, 04 Jul 2017 06:24:34 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Tue, 4 Jul 2017 15:24:10 +0200 Message-Id: <1499174653-330-8-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1499174653-330-1-git-send-email-mw@semihalf.com> References: <1499174653-330-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 07/10] Platform/Marvell: ComPhyLib: Add missing SFI and RXAUI configuration X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, leif.lindholm@linaro.org, ard.biesheuvel@linaro.org MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Despite the fact, that SFI and RXAUI modes are present on supported feature list, their configuration was non existent and could not be executed. This patch adds the missing initialization sequences. Because ComPhySgmiiRFUPowerUp routine is common for SGMII, SFI and RXAUI, rename it and reuse for those modes. Also add an option to use XFI mode (SFI @ 5156 MHz). Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Marcin Wojtas Reviewed-by: Ard Biesheuvel --- Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c | 464 +++++++++++++++++++= +++- Platform/Marvell/Library/ComPhyLib/ComPhyLib.c | 6 +- Platform/Marvell/Library/ComPhyLib/ComPhyLib.h | 54 ++- 3 files changed, 515 insertions(+), 9 deletions(-) diff --git a/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c b/Platform/Ma= rvell/Library/ComPhyLib/ComPhyCp110.c index 6f26bc4..329bbe8 100755 --- a/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c +++ b/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c @@ -1179,7 +1179,7 @@ ComPhySgmiiPhyConfiguration ( =20 STATIC EFI_STATUS -ComPhySgmiiRFUPowerUp ( +ComPhyEthCommonRFUPowerUp ( IN EFI_PHYSICAL_ADDRESS SdIpAddr ) { @@ -1265,7 +1265,460 @@ ComPhySgmiiPowerUp ( =20 DEBUG((DEBUG_INFO, "ComPhy: stage: RFU configurations - Power Up PLL,Tx,= Rx\n")); =20 - Status =3D ComPhySgmiiRFUPowerUp (SdIpAddr); + Status =3D ComPhyEthCommonRFUPowerUp (SdIpAddr); + + return Status; +} + +STATIC +VOID +ComPhySfiRFUConfiguration ( + IN EFI_PHYSICAL_ADDRESS ComPhyAddr, + IN EFI_PHYSICAL_ADDRESS SdIpAddr +) +{ + UINT32 Mask, Data; + + MmioAndThenOr32 ( + ComPhyAddr + COMMON_PHY_CFG1_REG, + ~(COMMON_PHY_CFG1_PWR_UP_MASK | COMMON_PHY_CFG1_PIPE_SELECT_MASK= ), + COMMON_PHY_CFG1_PWR_UP_MASK + ); + + /* Select Baud Rate of Comphy And PD_PLL/Tx/Rx */ + Mask =3D SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK | + SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK | + SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK | + SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK | + SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK | + SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK; + Data =3D (0xe << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET) | + (0xe << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET); + MmioAndThenOr32 (SdIpAddr + SD_EXTERNAL_CONFIG0_REG, ~Mask, Data); + + /* Release from hard reset */ + Mask =3D SD_EXTERNAL_CONFIG1_RESET_IN_MASK | + SD_EXTERNAL_CONFIG1_RESET_CORE_MASK | + SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; + Data =3D SD_EXTERNAL_CONFIG1_RESET_IN_MASK | + SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; + MmioAndThenOr32 (SdIpAddr + SD_EXTERNAL_CONFIG1_REG, ~Mask, Data); + + /* Wait 1ms - until band gap and ref clock are ready */ + MicroSecondDelay (1000); + MemoryFence (); +} + +STATIC +VOID +ComPhySfiPhyConfiguration ( + IN EFI_PHYSICAL_ADDRESS HpipeAddr, + IN UINT32 SfiSpeed +) +{ + UINT32 Mask, Data; + + /* Set reference clock */ + Mask =3D HPIPE_MISC_ICP_FORCE_MASK | HPIPE_MISC_REFCLK_SEL_MASK; + Data =3D (SfiSpeed =3D=3D PHY_SPEED_5_15625G) ? + (0x0 << HPIPE_MISC_ICP_FORCE_OFFSET) : (0x1 << HPIPE_MISC_ICP_FORCE_OF= FSET); + MmioAndThenOr32 (HpipeAddr + HPIPE_MISC_REG, ~Mask, Data); + + /* Power and PLL Control */ + MmioAndThenOr32 ( + HpipeAddr + HPIPE_PWR_PLL_REG, + ~(HPIPE_PWR_PLL_REF_FREQ_MASK | HPIPE_PWR_PLL_PHY_MODE_MASK), + 0x1 | (0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET) + ); + + /* Loopback register */ + MmioAndThenOr32 ( + HpipeAddr + HPIPE_LOOPBACK_REG, + ~HPIPE_LOOPBACK_SEL_MASK, + 0x1 << HPIPE_LOOPBACK_SEL_OFFSET + ); + + /* Rx control 1 */ + MmioOr32 ( + HpipeAddr + HPIPE_RX_CONTROL_1_REG, + HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK | HPIPE_RX_CONTROL_1_CLK8T_E= N_MASK + ); + + /* DTL Control */ + MmioOr32 (HpipeAddr + HPIPE_PWR_CTR_DTL_REG, HPIPE_PWR_CTR_DTL_FLOOP_EN_= MASK); + + /* Transmitter/Receiver Speed Divider Force */ + if (SfiSpeed =3D=3D PHY_SPEED_5_15625G) { + Mask =3D HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_MASK | + HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_MASK | + HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_MASK | + HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_MASK; + Data =3D (1 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET) | + (1 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_OFFSET) | + (1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET) | + (1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET); + MmioAndThenOr32 (HpipeAddr + HPIPE_SPD_DIV_FORCE_REG, ~Mask, Data); + } else { + MmioOr32 (HpipeAddr + HPIPE_SPD_DIV_FORCE_REG, HPIPE_TXDIGCK_DIV_FORCE= _MASK); + } +} + +STATIC +VOID +ComPhySfiSetAnalogParameters ( + IN EFI_PHYSICAL_ADDRESS HpipeAddr, + IN EFI_PHYSICAL_ADDRESS SdIpAddr, + IN UINT32 SfiSpeed +) +{ + UINT32 Mask, Data; + + /* SERDES External Configuration 2 */ + MmioOr32 (SdIpAddr + SD_EXTERNAL_CONFIG2_REG, SD_EXTERNAL_CONFIG2_PIN_DF= E_EN_MASK); + + /* DFE Resolution control */ + MmioOr32 (HpipeAddr + HPIPE_DFE_REG0, HPIPE_DFE_RES_FORCE_MASK); + + /* Generation 1 setting_0 */ + if (SfiSpeed =3D=3D PHY_SPEED_5_15625G) { + Mask =3D HPIPE_GX_SET0_TX_EMPH1_MASK; + Data =3D 0x6 << HPIPE_GX_SET0_TX_EMPH1_OFFSET; + } else { + Mask =3D HPIPE_GX_SET0_TX_AMP_MASK | HPIPE_GX_SET0_TX_EMPH1_MASK; + Data =3D (0x1c << HPIPE_GX_SET0_TX_AMP_OFFSET) | (0xe << HPIPE_GX_SET0= _TX_EMPH1_OFFSET); + } + MmioAndThenOr32 (HpipeAddr + HPIPE_G1_SET0_REG, ~Mask, Data); + + /* Generation 1 setting 2 */ + MmioAndThenOr32 ( + HpipeAddr + HPIPE_GX_SET2_REG, + ~HPIPE_GX_SET2_TX_EMPH0_MASK, + HPIPE_GX_SET2_TX_EMPH0_EN_MASK + ); + + /* Transmitter Slew Rate Control register */ + MmioAndThenOr32 ( + HpipeAddr + HPIPE_TX_REG1_REG, + ~(HPIPE_TX_REG1_TX_EMPH_RES_MASK | HPIPE_TX_REG1_SLC_EN_MASK), + (0x3 << HPIPE_TX_REG1_TX_EMPH_RES_OFFSET) | (0x3f << HPIPE_TX_RE= G1_SLC_EN_OFFSET) + ); + + /* Impedance Calibration Control register */ + MmioAndThenOr32 ( + HpipeAddr + HPIPE_CAL_REG1_REG, + ~(HPIPE_CAL_REG_1_EXT_TXIMP_MASK | HPIPE_CAL_REG_1_EXT_TXIMP_EN_= MASK), + (0xe << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET) | HPIPE_CAL_REG_1_EXT_= TXIMP_EN_MASK + ); + + /* Generation 1 setting 5 */ + MmioAnd32 (HpipeAddr + HPIPE_G1_SET5_REG, ~HPIPE_GX_SET5_ICP_MASK); + + /* Generation 1 setting 1 */ + if (SfiSpeed =3D=3D PHY_SPEED_5_15625G) { + Mask =3D HPIPE_GX_SET1_RX_SELMUPI_MASK | HPIPE_GX_SET1_RX_SELMUPP_MASK; + Data =3D 0x1 | (0x1 << HPIPE_GX_SET1_RX_SELMUPP_OFFSET); + } else { + Mask =3D HPIPE_GX_SET1_RX_SELMUPI_MASK | + HPIPE_GX_SET1_RX_SELMUPP_MASK | + HPIPE_GX_SET1_RX_SELMUFI_MASK | + HPIPE_GX_SET1_RX_SELMUFF_MASK | + HPIPE_GX_SET1_RX_DIGCK_DIV_MASK; + Data =3D 0x2 | + (0x2 << HPIPE_GX_SET1_RX_SELMUPP_OFFSET) | + (0x1 << HPIPE_GX_SET1_RX_SELMUFF_OFFSET) | + (0x3 << HPIPE_GX_SET1_RX_DIGCK_DIV_OFFSET); + } + MmioAndThenOr32 (HpipeAddr + HPIPE_G1_SET1_REG, ~Mask, Data); + MmioOr32 (HpipeAddr + HPIPE_G1_SET1_REG, HPIPE_GX_SET1_RX_DFE_EN_MASK); + + /* DFE F3-F5 Coefficient Control */ + MmioAnd32 ( + HpipeAddr + HPIPE_DFE_F3_F5_REG, + ~(HPIPE_DFE_F3_F5_DFE_EN_MASK | HPIPE_DFE_F3_F5_DFE_CTRL_MASK) + ); + + /* Configure Generation 1 setting 4 (DFE) */ + MmioAndThenOr32 ( + HpipeAddr + HPIPE_G1_SET4_REG, + ~HPIPE_GX_SET4_DFE_RES_MASK, + 0x1 << HPIPE_GX_SET4_DFE_RES_OFFSET + ); + + /* Generation 1 setting 3 */ + MmioOr32 (HpipeAddr + HPIPE_G1_SET3_REG, HPIPE_GX_SET3_FBCK_SEL_MASK); + + if (SfiSpeed =3D=3D PHY_SPEED_5_15625G) { + /* Force FFE (Feed Forward Equalization) to 5G */ + Mask =3D HPIPE_GX_SET3_FFE_CAP_SEL_MASK | + HPIPE_GX_SET3_FFE_RES_SEL_MASK | + HPIPE_GX_SET3_FFE_SETTING_FORCE_MASK; + Data =3D 0xf | (0x4 << HPIPE_GX_SET3_FFE_RES_SEL_OFFSET) | HPIPE_GX_SE= T3_FFE_SETTING_FORCE_MASK; + MmioAndThenOr32 (HpipeAddr + HPIPE_G1_SET3_REG, ~Mask, Data); + } + + /* Configure RX training timer */ + MmioAndThenOr32 (HpipeAddr + HPIPE_TX_TRAIN_CTRL_5_REG, ~HPIPE_RX_TRAIN_= TIMER_MASK, 0x13); + + /* Enable TX train peak to peak hold */ + MmioOr32 (HpipeAddr + HPIPE_TX_TRAIN_CTRL_0_REG, HPIPE_TX_TRAIN_P2P_HOLD= _MASK); + + /* Configure TX preset index */ + MmioAndThenOr32 ( + HpipeAddr + HPIPE_TX_PRESET_INDEX_REG, + ~HPIPE_TX_PRESET_INDEX_MASK, + 0x2 << HPIPE_TX_PRESET_INDEX_OFFSET + ); + + /* Disable pattern lock lost timeout */ + MmioAnd32 (HpipeAddr + HPIPE_FRAME_DETECT_CTRL_3_REG, ~HPIPE_PATTERN_LOC= K_LOST_TIMEOUT_EN_MASK); + + /* Configure TX training pattern and TX training 16bit auto */ + MmioOr32 ( + HpipeAddr + HPIPE_TX_TRAIN_REG, + HPIPE_TX_TRAIN_16BIT_AUTO_EN_MASK | HPIPE_TX_TRAIN_PAT_SEL_MASK + ); + + /* Configure training pattern number */ + MmioAndThenOr32 ( + HpipeAddr + HPIPE_FRAME_DETECT_CTRL_0_REG, + ~HPIPE_TRAIN_PAT_NUM_MASK, + 0x88 << HPIPE_TRAIN_PAT_NUM_OFFSET + ); + + /* Configure differential manchester encoder to ethernet mode */ + MmioOr32 (HpipeAddr + HPIPE_DME_REG, HPIPE_DME_ETHERNET_MODE_MASK); + + /* Configure VDD Continuous Calibration */ + MmioOr32 (HpipeAddr + HPIPE_VDD_CAL_0_REG, HPIPE_CAL_VDD_CONT_MODE_MASK); + + /* Configure sampler gain */ + MmioAndThenOr32 ( + HpipeAddr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, + ~HPIPE_RX_SAMPLER_OS_GAIN_MASK, + 0x3 << HPIPE_RX_SAMPLER_OS_GAIN_OFFSET + ); + + /* Trigger sampler enable pulse (by toggling the bit) */ + MmioAndThenOr32 ( + HpipeAddr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, + ~HPIPE_SAMPLER_MASK, + 0x1 << HPIPE_SAMPLER_OFFSET + ); + MmioAnd32 ( + HpipeAddr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, + ~HPIPE_SAMPLER_MASK + ); + + /* VDD calibration control */ + MmioAndThenOr32 ( + HpipeAddr + HPIPE_VDD_CAL_CTRL_REG, + ~HPIPE_EXT_SELLV_RXSAMPL_MASK, + 0x1a << HPIPE_EXT_SELLV_RXSAMPL_OFFSET + ); +} + +STATIC +EFI_STATUS +ComPhySfiPowerUp ( + IN UINT32 Lane, + IN EFI_PHYSICAL_ADDRESS HpipeBase, + IN EFI_PHYSICAL_ADDRESS ComPhyBase, + IN UINT32 SfiSpeed + ) +{ + EFI_STATUS Status; + EFI_PHYSICAL_ADDRESS HpipeAddr =3D HPIPE_ADDR(HpipeBase, Lane); + EFI_PHYSICAL_ADDRESS SdIpAddr =3D SD_ADDR(HpipeBase, Lane); + EFI_PHYSICAL_ADDRESS ComPhyAddr =3D COMPHY_ADDR(ComPhyBase, Lane); + + DEBUG ((DEBUG_INFO, "ComPhy: stage: RFU configurations - hard reset ComP= hy\n")); + + ComPhySfiRFUConfiguration (ComPhyAddr, SdIpAddr); + + DEBUG ((DEBUG_INFO, "ComPhy: stage: ComPhy configuration\n")); + + ComPhySfiPhyConfiguration (HpipeAddr, SfiSpeed); + + DEBUG ((DEBUG_INFO, "ComPhy: stage: Set analog paramters\n")); + + ComPhySfiSetAnalogParameters (HpipeAddr, SdIpAddr, SfiSpeed); + + DEBUG ((DEBUG_INFO, "ComPhy: stage: RFU configurations - Power Up PLL,Tx= ,Rx\n")); + + Status =3D ComPhyEthCommonRFUPowerUp (SdIpAddr); + + return Status; +} + +STATIC +EFI_STATUS +ComPhyRxauiRFUConfiguration ( + IN UINT32 Lane, + IN EFI_PHYSICAL_ADDRESS ComPhyAddr, + IN EFI_PHYSICAL_ADDRESS SdIpAddr +) +{ + UINT32 Mask, Data; + + MmioAndThenOr32 ( + ComPhyAddr + COMMON_PHY_CFG1_REG, + ~(COMMON_PHY_CFG1_PWR_UP_MASK | COMMON_PHY_CFG1_PIPE_SELECT_MASK= ), + COMMON_PHY_CFG1_PWR_UP_MASK + ); + + switch (Lane) { + case 2: + case 4: + MmioOr32 (ComPhyAddr + COMMON_PHY_SD_CTRL1, COMMON_PHY_SD_CTRL1_RXAUI0= _MASK); + case 3: + case 5: + MmioOr32 (ComPhyAddr + COMMON_PHY_SD_CTRL1, COMMON_PHY_SD_CTRL1_RXAUI1= _MASK); + break; + default: + DEBUG ((DEBUG_ERROR, "RXAUI used on invalid lane %d\n", Lane)); + return EFI_INVALID_PARAMETER; + } + + /* Select Baud Rate of Comphy And PD_PLL/Tx/Rx */ + Mask =3D SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK | + SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK | + SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK | + SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK | + SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK | + SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK | + SD_EXTERNAL_CONFIG0_MEDIA_MODE_MASK; + Data =3D (0xb << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET) | + (0xb << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET) | + (0x1 << SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET); + MmioAndThenOr32 (SdIpAddr + SD_EXTERNAL_CONFIG0_REG, ~Mask, Data); + + /* Release from hard reset */ + Mask =3D SD_EXTERNAL_CONFIG1_RESET_IN_MASK | + SD_EXTERNAL_CONFIG1_RESET_CORE_MASK | + SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; + Data =3D SD_EXTERNAL_CONFIG1_RESET_IN_MASK | + SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; + MmioAndThenOr32 (SdIpAddr + SD_EXTERNAL_CONFIG1_REG, ~Mask, Data); + + /* Wait 1ms - until band gap and ref clock are ready */ + MicroSecondDelay (1000); + MemoryFence (); + + return EFI_SUCCESS; +} + +STATIC +VOID +ComPhyRxauiPhyConfiguration ( + IN EFI_PHYSICAL_ADDRESS HpipeAddr +) +{ + /* Set reference clock */ + MmioAnd32 (HpipeAddr + HPIPE_MISC_REG, ~HPIPE_MISC_REFCLK_SEL_MASK); + + /* Power and PLL Control */ + MmioAndThenOr32 ( + HpipeAddr + HPIPE_PWR_PLL_REG, + ~(HPIPE_PWR_PLL_REF_FREQ_MASK | HPIPE_PWR_PLL_PHY_MODE_MASK), + 0x1 | (0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET) + ); + + /* Loopback register */ + MmioAndThenOr32 ( + HpipeAddr + HPIPE_LOOPBACK_REG, + ~HPIPE_LOOPBACK_SEL_MASK, + 0x1 << HPIPE_LOOPBACK_SEL_OFFSET + ); + + /* Rx control 1 */ + MmioOr32 ( + HpipeAddr + HPIPE_RX_CONTROL_1_REG, + HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK | HPIPE_RX_CONTROL_1_CLK8T_E= N_MASK + ); + + /* DTL Control */ + MmioAnd32 (HpipeAddr + HPIPE_PWR_CTR_DTL_REG, ~HPIPE_PWR_CTR_DTL_FLOOP_E= N_MASK); +} + +STATIC +VOID +ComPhyRxauiSetAnalogParameters ( + IN EFI_PHYSICAL_ADDRESS HpipeAddr, + IN EFI_PHYSICAL_ADDRESS SdIpAddr +) +{ + UINT32 Mask, Data; + + /* SERDES External Configuration 2 */ + MmioOr32 (SdIpAddr + SD_EXTERNAL_CONFIG2_REG, SD_EXTERNAL_CONFIG2_PIN_DF= E_EN_MASK); + + /* DFE Resolution control */ + MmioOr32 (HpipeAddr + HPIPE_DFE_REG0, HPIPE_DFE_RES_FORCE_MASK); + + /* Generation 1 setting_0 */ + MmioAndThenOr32 ( + HpipeAddr + HPIPE_G1_SET0_REG, + ~HPIPE_GX_SET0_TX_EMPH1_MASK, + 0xe << HPIPE_GX_SET0_TX_EMPH1_OFFSET + ); + + /* Generation 1 setting 1 */ + Mask =3D HPIPE_GX_SET1_RX_SELMUPI_MASK | + HPIPE_GX_SET1_RX_SELMUPP_MASK | + HPIPE_GX_SET1_RX_DFE_EN_MASK; + Data =3D 0x1 | + (0x1 << HPIPE_GX_SET1_RX_SELMUPP_OFFSET) | + (0x1 << HPIPE_GX_SET1_RX_DFE_EN_OFFSET); + MmioAndThenOr32 (HpipeAddr + HPIPE_G1_SET1_REG, ~Mask, Data); + + /* DFE F3-F5 Coefficient Control */ + MmioAnd32 ( + HpipeAddr + HPIPE_DFE_F3_F5_REG, + ~(HPIPE_DFE_F3_F5_DFE_EN_MASK | HPIPE_DFE_F3_F5_DFE_CTRL_MASK) + ); + + /* Configure Generation 1 setting 4 (DFE) */ + MmioAndThenOr32 ( + HpipeAddr + HPIPE_G1_SET4_REG, + ~HPIPE_GX_SET4_DFE_RES_MASK, + 0x1 << HPIPE_GX_SET4_DFE_RES_OFFSET + ); + + /* Generation 1 setting 3 */ + MmioOr32 (HpipeAddr + HPIPE_G1_SET3_REG, HPIPE_GX_SET3_FBCK_SEL_MASK); +} + +STATIC +EFI_STATUS +ComPhyRxauiPowerUp ( + IN UINT32 Lane, + IN EFI_PHYSICAL_ADDRESS HpipeBase, + IN EFI_PHYSICAL_ADDRESS ComPhyBase + ) +{ + EFI_STATUS Status; + EFI_PHYSICAL_ADDRESS HpipeAddr =3D HPIPE_ADDR(HpipeBase, Lane); + EFI_PHYSICAL_ADDRESS SdIpAddr =3D SD_ADDR(HpipeBase, Lane); + EFI_PHYSICAL_ADDRESS ComPhyAddr =3D COMPHY_ADDR(ComPhyBase, Lane); + + DEBUG ((DEBUG_INFO, "ComPhy: stage: RFU configurations - hard reset ComP= hy\n")); + + Status =3D ComPhyRxauiRFUConfiguration (Lane, ComPhyAddr, SdIpAddr); + if (EFI_ERROR(Status)) { + return Status; + } + + DEBUG ((DEBUG_INFO, "ComPhy: stage: ComPhy configuration\n")); + + ComPhyRxauiPhyConfiguration (HpipeAddr); + + DEBUG ((DEBUG_INFO, "ComPhy: stage: Set analog paramters\n")); + + ComPhyRxauiSetAnalogParameters (HpipeAddr, SdIpAddr); + + DEBUG ((DEBUG_INFO, "ComPhy: stage: RFU configurations - Power Up PLL,Tx= ,Rx\n")); + + Status =3D ComPhyEthCommonRFUPowerUp (SdIpAddr); =20 return Status; } @@ -1372,6 +1825,13 @@ ComPhyCp110Init ( Status =3D ComPhySgmiiPowerUp(Lane, PtrComPhyMap->Speed, HpipeBaseAd= dr, ComPhyBaseAddr); break; + case PHY_TYPE_SFI: + Status =3D ComPhySfiPowerUp(Lane, HpipeBaseAddr, ComPhyBaseAddr, Ptr= ComPhyMap->Speed); + break; + case PHY_TYPE_RXAUI0: + case PHY_TYPE_RXAUI1: + Status =3D ComPhyRxauiPowerUp(Lane, HpipeBaseAddr, ComPhyBaseAddr); + break; default: DEBUG((DEBUG_ERROR, "Unknown SerDes Type, skip initialize SerDes %d\= n", Lane)); diff --git a/Platform/Marvell/Library/ComPhyLib/ComPhyLib.c b/Platform/Marv= ell/Library/ComPhyLib/ComPhyLib.c index 88680fc..174f10d 100644 --- a/Platform/Marvell/Library/ComPhyLib/ComPhyLib.c +++ b/Platform/Marvell/Library/ComPhyLib/ComPhyLib.c @@ -42,7 +42,7 @@ CHAR16 * TypeStringTable [] =3D {L"unconnected", L"PCIE0"= , L"PCIE1", L"PCIE2", L"XAUI3", L"RXAUI0", L"RXAUI1", L"SFI"}; =20 CHAR16 * SpeedStringTable [] =3D {L"-", L"1.25 Gbps", L"1.5 Gbps", L"2.5 G= bps", - L"3.0 Gbps", L"3.125 Gbps", L"5 Gbps", + L"3.0 Gbps", L"3.125 Gbps", L"5 Gbps", L"5= .156 Gbps", L"6 Gbps", L"6.25 Gbps", L"10.31 Gbps"}; =20 CHIP_COMPHY_CONFIG ChipCfgTbl[] =3D { @@ -142,9 +142,9 @@ ParseSerdesSpeed ( { UINT32 i; UINT32 ValueTable [] =3D {0, 1250, 1500, 2500, 3000, 3125, - 5000, 6000, 6250, 10310}; + 5000, 5156, 6000, 6250, 10310}; =20 - for (i =3D 0; i < 10; i++) { + for (i =3D 0; i < PHY_SPEED_MAX; i++) { if (Value =3D=3D ValueTable[i]) { return i; } diff --git a/Platform/Marvell/Library/ComPhyLib/ComPhyLib.h b/Platform/Marv= ell/Library/ComPhyLib/ComPhyLib.h index 58f1d81..56bb991 100644 --- a/Platform/Marvell/Library/ComPhyLib/ComPhyLib.h +++ b/Platform/Marvell/Library/ComPhyLib/ComPhyLib.h @@ -80,10 +80,11 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DA= MAGE. #define PHY_SPEED_3G 4 #define PHY_SPEED_3_125G 5 #define PHY_SPEED_5G 6 -#define PHY_SPEED_6G 7 -#define PHY_SPEED_6_25G 8 -#define PHY_SPEED_10_3125G 9 -#define PHY_SPEED_MAX 10 +#define PHY_SPEED_5_15625G 7 +#define PHY_SPEED_6G 8 +#define PHY_SPEED_6_25G 9 +#define PHY_SPEED_10_3125G 10 +#define PHY_SPEED_MAX 11 #define PHY_SPEED_INVALID 0xff =20 #define PHY_TYPE_UNCONNECTED 0 @@ -132,6 +133,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DA= MAGE. #define SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK (1 << SD_EXTERNAL_CONFIG= 0_SD_PU_TX_OFFSET) #define SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET 14 #define SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK (1 << SD_EXTERNAL_CONFIG= 0_HALF_BUS_MODE_OFFSET) +#define SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET 15 +#define SD_EXTERNAL_CONFIG0_MEDIA_MODE_MASK (0x1 << SD_EXTERNAL_CONF= IG0_MEDIA_MODE_OFFSET) =20 #define SD_EXTERNAL_CONFIG1_REG 0x4 #define SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET 3 @@ -168,6 +171,12 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH D= AMAGE. #define HPIPE_KVCO_CALIB_CTRL_MAX_PLL_OFFSET 12 #define HPIPE_KVCO_CALIB_CTRL_MAX_PLL_MASK (0x1 << HPIPE_KVCO_CALIB= _CTRL_MAX_PLL_OFFSET) =20 +#define HPIPE_CAL_REG1_REG 0xc +#define HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET 10 +#define HPIPE_CAL_REG_1_EXT_TXIMP_MASK (0x1f << HPIPE_CAL_REG_1= _EXT_TXIMP_OFFSET) +#define HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET 15 +#define HPIPE_CAL_REG_1_EXT_TXIMP_EN_MASK (0x1 << HPIPE_CAL_REG_1_= EXT_TXIMP_EN_OFFSET) + #define HPIPE_SQUELCH_FFE_SETTING_REG 0x018 =20 #define HPIPE_DFE_REG0 0x01C @@ -234,6 +243,12 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH D= AMAGE. #define HPIPE_ISOLATE_MODE_GEN_TX_OFFSET 4 #define HPIPE_ISOLATE_MODE_GEN_TX_MASK (0xf << HPIPE_ISOLATE_MO= DE_GEN_TX_OFFSET) =20 +#define HPIPE_GX_SET2_REG 0xf4 +#define HPIPE_GX_SET2_TX_EMPH0_OFFSET 0 +#define HPIPE_GX_SET2_TX_EMPH0_MASK (0xf << HPIPE_GX_SET2_TX= _EMPH0_OFFSET) +#define HPIPE_GX_SET2_TX_EMPH0_EN_OFFSET 4 +#define HPIPE_GX_SET2_TX_EMPH0_EN_MASK (0x1 << HPIPE_GX_SET2_TX= _EMPH0_MASK) + #define HPIPE_VTHIMPCAL_CTRL_REG 0x104 =20 #define HPIPE_VDD_CAL_CTRL_REG 0x114 @@ -280,6 +295,18 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH D= AMAGE. =20 #define HPIPE_PLLINTP_REG1 0x150 =20 +#define HPIPE_SPD_DIV_FORCE_REG 0x154 +#define HPIPE_TXDIGCK_DIV_FORCE_OFFSET 7 +#define HPIPE_TXDIGCK_DIV_FORCE_MASK (0x1 << HPIPE_TXDIGC= K_DIV_FORCE_OFFSET) +#define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET 8 +#define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_MASK (0x3 << HPIPE_SPD_DI= V_FORCE_RX_SPD_DIV_OFFSET) +#define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_OFFSET 10 +#define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_MASK (0x1 << HPIPE_SPD_DI= V_FORCE_RX_SPD_DIV_FORCE_OFFSET) +#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET 13 +#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_MASK (0x3 << HPIPE_SPD_DI= V_FORCE_TX_SPD_DIV_OFFSET) +#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET 15 +#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_MASK (0x1 << HPIPE_SPD_DI= V_FORCE_TX_SPD_DIV_FORCE_OFFSET) + #define HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG 0x16C #define HPIPE_RX_SAMPLER_OS_GAIN_OFFSET 6 #define HPIPE_RX_SAMPLER_OS_GAIN_MASK (0x3 << HPIPE_RX_SAMPLER= _OS_GAIN_OFFSET) @@ -292,6 +319,12 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH D= AMAGE. #define HPIPE_TX_REG1_SLC_EN_OFFSET 10 #define HPIPE_TX_REG1_SLC_EN_MASK (0x3f << HPIPE_TX_REG1_S= LC_EN_OFFSET) =20 +#define HPIPE_TX_REG1_REG 0x174 +#define HPIPE_TX_REG1_TX_EMPH_RES_OFFSET 5 +#define HPIPE_TX_REG1_TX_EMPH_RES_MASK (0x3 << HPIPE_TX_REG1_TX= _EMPH_RES_OFFSET) +#define HPIPE_TX_REG1_SLC_EN_OFFSET 10 +#define HPIPE_TX_REG1_SLC_EN_MASK (0x3f << HPIPE_TX_REG1_S= LC_EN_OFFSET) + #define HPIPE_PWR_CTR_DTL_REG 0x184 #define HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET 0 #define HPIPE_PWR_CTR_DTL_SQ_DET_EN_MASK (0x1 << HPIPE_PWR_CT= R_DTL_SQ_DET_EN_OFFSET) @@ -348,6 +381,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DA= MAGE. #define HPIPE_PCIE_REG3 0x290 =20 #define HPIPE_TX_TRAIN_CTRL_5_REG 0x2A4 +#define HPIPE_RX_TRAIN_TIMER_OFFSET 0 +#define HPIPE_RX_TRAIN_TIMER_MASK (0x3ff << HPIPE_RX_TRAIN= _TIMER_OFFSET) #define HPIPE_TX_TRAIN_START_SQ_EN_OFFSET 11 #define HPIPE_TX_TRAIN_START_SQ_EN_MASK (0x1 << HPIPE_TX_TRAIN_S= TART_SQ_EN_OFFSET) #define HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET 12 @@ -362,6 +397,10 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH D= AMAGE. #define HPIPE_TX_TRAIN_CHK_INIT_MASK (0x1 << HPIPE_TX_TRAIN_C= HK_INIT_OFFSET) #define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET 7 #define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK (0x1 << HPIPE_TX_TRAIN_C= OE_FM_PIN_PCIE3_OFFSET) +#define HPIPE_TX_TRAIN_16BIT_AUTO_EN_OFFSET 8 +#define HPIPE_TX_TRAIN_16BIT_AUTO_EN_MASK (0x1 << HPIPE_TX_TRAIN_1= 6BIT_AUTO_EN_OFFSET) +#define HPIPE_TX_TRAIN_PAT_SEL_OFFSET 9 +#define HPIPE_TX_TRAIN_PAT_SEL_MASK (0x1 << HPIPE_TX_TRAIN_P= AT_SEL_OFFSET) =20 #define HPIPE_CDR_CONTROL_REG 0x418 #define HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET 6 @@ -413,6 +452,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DA= MAGE. #define HPIPE_DFE_CTRL_28_PIPE4_OFFSET 7 #define HPIPE_DFE_CTRL_28_PIPE4_MASK (0x1 << HPIPE_DFE_CTRL_2= 8_PIPE4_OFFSET) =20 +#define HPIPE_G1_SET5_REG 0x538 #define HPIPE_G3_SET5_REG 0x548 #define HPIPE_GX_SET5_ICP_OFFSET 0 #define HPIPE_GX_SET5_ICP_MASK (0xf << HPIPE_GX_SET5_IC= P_OFFSET) @@ -502,6 +542,12 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH D= AMAGE. #define COMMON_SELECTOR_PHY_OFFSET 0x140 #define COMMON_SELECTOR_PIPE_OFFSET 0x144 =20 +#define COMMON_PHY_SD_CTRL1 0x148 +#define COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET 26 +#define COMMON_PHY_SD_CTRL1_RXAUI1_MASK (0x1 << COMMON_PHY_SD_CT= RL1_RXAUI1_OFFSET) +#define COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET 27 +#define COMMON_PHY_SD_CTRL1_RXAUI0_MASK (0x1 << COMMON_PHY_SD_CT= RL1_RXAUI0_OFFSET) + /***** SATA registers *****/ #define SATA3_VENDOR_ADDRESS 0xA0 #define SATA3_VENDOR_ADDR_OFSSET 0 --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun Apr 28 20:57:55 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id c185sm4980970lfc.43.2017.07.04.06.24.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 04 Jul 2017 06:24:34 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=0nB+SGF5sC9IK48WVdVczTCMaK5LJyMlz+eApJSCGjM=; b=htFhwPGnWEJb4sN6BiKAsYdSsnqmlRUmkwRhA2aWi9Zb5dItOIseC7j0IdMaG6PJH3 NqX6I52MBNLhIu/vzeSRB1HGVydY421tVqDODu5n2GqqeLLfdjBrcm2DZVtbqrnbfEjs lRj9cyx3xPczBQJTwgqFfTV8JcUHtAfm1WBuaCz+i4jNuK/6hBEsXdmsvFxwWDqHikZS bjb7gQXb1XILD4xLJ41Kzv50VLYas7b2Ol8a6FCHkuRWgjctzpMLVG9DehPTM4zebqIY UHx720hyOYR5abywiiFzcY/m1F6g/TylDZMHZ6xIV3ii+a/NDGkmAQ9nz2d4xz6qE4l3 PqOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=0nB+SGF5sC9IK48WVdVczTCMaK5LJyMlz+eApJSCGjM=; b=IqzprX8+hWerACnNwogXhL7JMNM6mgxArJJF3UJ7HU9SEa4zFNh6vvFKJQfOrWSe2O aJjIVT/E+QdZtBhuy3Vp1zq9X06XgleQf0QwSQzTVMxzennNwNVpvBxSm5Qhqg9JkIaN uriUcHIYCGarK5dlxwKU5jtpRgPH0YP+iYpIthrAcVAhDUqJCNiYsVdUtkMhP0JaQshg aKmDSsy+yxa42g4B0SXmysS9ZqwV8iNWraxZ0OQ1CPHFfMEqYdFvL+fEdVRmolRQfDm8 RHnXOZfRIh+fWOhf/wOOL7TQGpBGCkXVqsVNiL8wro+p/kLltMfCtN5DkqtuMk1SGnUU WHXg== X-Gm-Message-State: AKS2vOx4Q0dHZTaBmxilSDJU++G7V+gXhfUJPv/OTQYAAfT6LNIH5PMW 2lh7ine5K4qCqBRZj/gbIg== X-Received: by 10.25.145.82 with SMTP id y18mr13078301lfj.158.1499174675742; Tue, 04 Jul 2017 06:24:35 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Tue, 4 Jul 2017 15:24:11 +0200 Message-Id: <1499174653-330-9-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1499174653-330-1-git-send-email-mw@semihalf.com> References: <1499174653-330-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 08/10] Platform/Marvell: ComPhyLib: Move devices description to MvHwDescLib X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, leif.lindholm@linaro.org, ard.biesheuvel@linaro.org MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This patch introduces ComPhy description, using the new structures and template in MvHwDescLib. This change enables more flexible addition of multiple ComPhy chips and also significantly reduces amount of used PCD's for that purpose. Update PortingGuide documentation accordingly. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Marcin Wojtas Reviewed-by: Ard Biesheuvel --- Documentation/Marvell/PortingGuide/ComPhy.txt | 64 ++++------------- Platform/Marvell/Armada/Armada70x0.dsc | 13 +--- Platform/Marvell/Include/Library/MvComPhyLib.h | 5 ++ Platform/Marvell/Include/Library/MvHwDescLib.h | 38 ++++++++++ Platform/Marvell/Library/ComPhyLib/ComPhyLib.c | 89 ++++++++++++++++----= ---- Platform/Marvell/Library/ComPhyLib/ComPhyLib.h | 14 +--- Platform/Marvell/Library/ComPhyLib/ComPhyLib.inf | 26 +------ Platform/Marvell/Marvell.dec | 28 +------- 8 files changed, 122 insertions(+), 155 deletions(-) diff --git a/Documentation/Marvell/PortingGuide/ComPhy.txt b/Documentation/= Marvell/PortingGuide/ComPhy.txt index b5c4727..a96015e 100644 --- a/Documentation/Marvell/PortingGuide/ComPhy.txt +++ b/Documentation/Marvell/PortingGuide/ComPhy.txt @@ -2,44 +2,18 @@ COMPHY configuration --------------------------- In order to configure ComPhy library, following PCDs are available: =20 - gMarvellTokenSpaceGuid.PcdComPhyChipCount + gMarvellTokenSpaceGuid.PcdComPhyDevices =20 -Indicates how many different chips are placed on board. So far, up to 4 ch= ips -are supported. +This array indicates, which ones of the ComPhy chips defined in +MVHW_COMPHY_DESC template will be configured. =20 Every ComPhy PCD has part where stands for chip ID (order is n= ot important, but configuration will be set for first PcdComPhyChipCount chip= s). =20 -Every chip has 8 ComPhy PCDs and three of them concern lanes settings for = this -chip. Below is example for the first chip (Chip0). - -General PCDs: - - gMarvellTokenSpaceGuid.PcdChip0Compatible - -Unicode string indicating type of chip - currently supported is -{ L"Cp110" } - - gMarvellTokenSpaceGuid.PcdChip0ComPhyBaseAddress - -Indicates COMPHY unit base address. - - gMarvellTokenSpaceGuid.PcdChip0Hpipe3BaseAddress - -Indicates Hpipe3 unit base address. - - gMarvellTokenSpaceGuid.PcdChip0ComPhyMuxBitCount - -Indicates number of bits that are allocated for every MUX in the -COMPHY-selector register. - - gMarvellTokenSpaceGuid.PcdChip0ComPhyMaxLanes - -Indicates maximum ComPhy lanes number. - -Next three PCDs are in unicode string format containing settings for up to= 10 -lanes. Setting for each one is separated with semicolon. These PCDs form -structure describing outputs of PHY integrated in simple cihp. +Every chip has 3 ComPhy PCDs and three of them comprise per-board lanes +settings for this chip. Their format is unicode string, containing settings +for up to 10 lanes. Setting for each one is separated with semicolon. +These PCDs together describe outputs of PHY integrated in simple cihp. Below is example for the first chip (Chip0). =20 gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes @@ -48,16 +22,9 @@ Unicode string indicating PHY types. Currently supported= are: =20 { L"unconnected", L"PCIE0", L"PCIE1", L"PCIE2", L"PCIE3", L"SATA0", L"SATA1", L"SATA2", L"SATA3", L"SGMII0", -L"SGMII1", L"SGMII2", L"SGMII3", L"QSGMII", +L"SGMII1", L"SGMII2", L"SGMII3", L"USB3_HOST0", L"USB3_HOST1", L"USB3_DEVICE", -L"XAUI0", L"XAUI1", L"XAUI2", L"XAUI3", L"RXAUI0", -L"RXAUI1", L"KR" } - -Below documents describes some of above interfaces' types: - -SGMII, QSGMII, XAUI - IEEE 802.3 -KR - IEEE 802.3a -RXAUI - RXAUI Interface and RXAUI Adapter Specification, Marvell +L"RXAUI0", L"RXAUI1", L"SFI" } =20 gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds =20 @@ -72,14 +39,7 @@ Indicates lane polarity invert. Example ------- #ComPhy - gMarvellTokenSpaceGuid.PcdComPhyChipCount|1 - - gMarvellTokenSpaceGuid.PcdChip0ComPhyMaxLanes|6 - gMarvellTokenSpaceGuid.PcdChip0ComPhyBaseAddress|0xF2441000 - gMarvellTokenSpaceGuid.PcdChip0Hpipe3BaseAddress|0xF2120000 - gMarvellTokenSpaceGuid.PcdChip0ComPhyMuxBitCount|4 - gMarvellTokenSpaceGuid.PcdChip0Compatible|L"Cp110" - - gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|L"SGMII2;USB3_HOST0;SGMII0;SA= TA1;USB3_HOST1;PCIE2" - gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|L"1250;5000;1250;5000;5000;5= 000" + gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1 } + gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|L"SGMII1;USB3_HOST0;SFI;SATA1= ;USB3_HOST1;PCIE2" + gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|L"1250;5000;10310;5000;5000;= 5000" =20 diff --git a/Platform/Marvell/Armada/Armada70x0.dsc b/Platform/Marvell/Arma= da/Armada70x0.dsc index af602d5..3440038 100644 --- a/Platform/Marvell/Armada/Armada70x0.dsc +++ b/Platform/Marvell/Armada/Armada70x0.dsc @@ -97,13 +97,9 @@ gMarvellTokenSpaceGuid.PcdSpiFlashId|0x20BA18 =20 #ComPhy - gMarvellTokenSpaceGuid.PcdComPhyChipCount|1 - - gMarvellTokenSpaceGuid.PcdChip0ComPhyMaxLanes|6 - gMarvellTokenSpaceGuid.PcdChip0ComPhyBaseAddress|0xF2441000 - gMarvellTokenSpaceGuid.PcdChip0Hpipe3BaseAddress|0xF2120000 - gMarvellTokenSpaceGuid.PcdChip0ComPhyMuxBitCount|4 - gMarvellTokenSpaceGuid.PcdChip0Compatible|L"Cp110m" + gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1 } + gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|L"SGMII1;USB3_HOST0;SGMII0;SA= TA1;USB3_HOST1;PCIE2" + gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|L"3125;5000;1250;5000;5000;5= 000" =20 #UtmiPhy gMarvellTokenSpaceGuid.PcdUtmiPhyCount|2 @@ -112,9 +108,6 @@ gMarvellTokenSpaceGuid.PcdUtmiPhyRegUtmiUnit|L"0xF2580000;0xF2581000" gMarvellTokenSpaceGuid.PcdUtmiPhyUtmiPort|L"0x0;0x1" =20 - gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|L"SGMII1;USB3_HOST0;SGMII0;SA= TA1;USB3_HOST1;PCIE2" - gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|L"3125;5000;1250;5000;5000;5= 000" - #MDIO gMarvellTokenSpaceGuid.PcdMdioBaseAddress|0xF212A200 =20 diff --git a/Platform/Marvell/Include/Library/MvComPhyLib.h b/Platform/Marv= ell/Include/Library/MvComPhyLib.h index 6bd6243..6076ede 100644 --- a/Platform/Marvell/Include/Library/MvComPhyLib.h +++ b/Platform/Marvell/Include/Library/MvComPhyLib.h @@ -35,6 +35,11 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAM= AGE. #ifndef __MVCOMPHYLIB_H__ #define __MVCOMPHYLIB_H__ =20 +typedef enum { + MvComPhyTypeCp110, + MvComPhyTypeMax, +} MV_COMPHY_CHIP_TYPE; + EFI_STATUS MvComPhyInit ( VOID diff --git a/Platform/Marvell/Include/Library/MvHwDescLib.h b/Platform/Marv= ell/Include/Library/MvHwDescLib.h index 32284a0..ac8dc37 100644 --- a/Platform/Marvell/Include/Library/MvHwDescLib.h +++ b/Platform/Marvell/Include/Library/MvHwDescLib.h @@ -35,6 +35,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. #ifndef __MVHWDESCLIB_H__ #define __MVHWDESCLIB_H__ =20 +#include #include =20 // @@ -45,6 +46,20 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAM= AGE. #define MVHW_DEV_ENABLED(type, index) (type ## DeviceTable[index]) =20 // +// CommonPhy devices description template definition +// +#define MVHW_MAX_COMPHY_DEVS 4 + +typedef struct { + UINT8 ComPhyDevCount; + UINTN ComPhyBaseAddresses[MVHW_MAX_COMPHY_DEVS]; + UINTN ComPhyHpipe3BaseAddresses[MVHW_MAX_COMPHY_DEVS]; + UINTN ComPhyLaneCount[MVHW_MAX_COMPHY_DEVS]; + UINTN ComPhyMuxBitCount[MVHW_MAX_COMPHY_DEVS]; + MV_COMPHY_CHIP_TYPE ComPhyChipType[MVHW_MAX_COMPHY_DEVS]; +} MVHW_COMPHY_DESC; + +// // NonDiscoverable devices description template definition // #define MVHW_MAX_XHCI_DEVS 4 @@ -81,6 +96,29 @@ typedef struct { } MVHW_RTC_DESC; =20 // +// Platform description of CommonPhy devices +// +#define MVHW_CP0_COMPHY_BASE 0xF2441000 +#define MVHW_CP0_HPIPE3_BASE 0xF2120000 +#define MVHW_CP0_COMPHY_LANES 6 +#define MVHW_CP0_COMPHY_MUX_BITS 4 +#define MVHW_CP1_COMPHY_BASE 0xF4441000 +#define MVHW_CP1_HPIPE3_BASE 0xF4120000 +#define MVHW_CP1_COMPHY_LANES 6 +#define MVHW_CP1_COMPHY_MUX_BITS 4 + +#define DECLARE_A7K8K_COMPHY_TEMPLATE \ +STATIC \ +MVHW_COMPHY_DESC mA7k8kComPhyDescTemplate =3D {\ + 2,\ + { MVHW_CP0_COMPHY_BASE, MVHW_CP1_COMPHY_BASE },\ + { MVHW_CP0_HPIPE3_BASE, MVHW_CP1_HPIPE3_BASE },\ + { MVHW_CP0_COMPHY_LANES, MVHW_CP1_COMPHY_LANES },\ + { MVHW_CP0_COMPHY_MUX_BITS, MVHW_CP1_COMPHY_MUX_BITS },\ + { MvComPhyTypeCp110, MvComPhyTypeCp110 }\ +} + +// // Platform description of NonDiscoverable devices // #define MVHW_CP0_XHCI0_BASE 0xF2500000 diff --git a/Platform/Marvell/Library/ComPhyLib/ComPhyLib.c b/Platform/Marv= ell/Library/ComPhyLib/ComPhyLib.c index 174f10d..b61ccb6 100644 --- a/Platform/Marvell/Library/ComPhyLib/ComPhyLib.c +++ b/Platform/Marvell/Library/ComPhyLib/ComPhyLib.c @@ -33,6 +33,10 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAM= AGE. **************************************************************************= *****/ =20 #include "ComPhyLib.h" +#include +#include + +DECLARE_A7K8K_COMPHY_TEMPLATE; =20 CHAR16 * TypeStringTable [] =3D {L"unconnected", L"PCIE0", L"PCIE1", L"PCI= E2", L"PCIE3", L"SATA0", L"SATA1", L"SATA2", L"SATA3= ", @@ -46,14 +50,10 @@ CHAR16 * SpeedStringTable [] =3D {L"-", L"1.25 Gbps", L= "1.5 Gbps", L"2.5 Gbps", L"6 Gbps", L"6.25 Gbps", L"10.31 Gbps"}; =20 CHIP_COMPHY_CONFIG ChipCfgTbl[] =3D { - { /* CP master */ - .ChipType =3D L"Cp110m", + { + .ChipType =3D MvComPhyTypeCp110, .Init =3D ComPhyCp110Init }, - { /* CP slave */ - .ChipType =3D L"Cp110s", - .Init =3D ComPhyCp110Init - } }; =20 VOID @@ -208,13 +208,12 @@ GetChipComPhyInit ( TblSize =3D sizeof(ChipCfgTbl) / sizeof(ChipCfgTbl[0]); =20 for (i =3D 0; i < TblSize ; i++) { - if (StrCmp (PtrChipCfg->ChipType, ChipCfgTbl[i].ChipType) =3D=3D 0) { + if (PtrChipCfg->ChipType =3D=3D ChipCfgTbl[i].ChipType) { PtrChipCfg->Init =3D ChipCfgTbl[i].Init; return EFI_SUCCESS; } } =20 - DEBUG((DEBUG_ERROR, "ComPhy: Empty ChipType string\n")); return EFI_D_ERROR; } =20 @@ -222,18 +221,35 @@ STATIC VOID InitComPhyConfig ( IN OUT CHIP_COMPHY_CONFIG *ChipConfig, - IN OUT PCD_LANE_MAP *LaneData + IN OUT PCD_LANE_MAP *LaneData, + IN UINT8 Id ) { + MVHW_COMPHY_DESC *Desc =3D &mA7k8kComPhyDescTemplate; + + ChipConfig->ChipType =3D Desc->ComPhyChipType[Id]; + ChipConfig->ComPhyBaseAddr =3D Desc->ComPhyBaseAddresses[Id]; + ChipConfig->Hpipe3BaseAddr =3D Desc->ComPhyHpipe3BaseAddresses[Id]; + ChipConfig->LanesCount =3D Desc->ComPhyLaneCount[Id]; + ChipConfig->MuxBitCount =3D Desc->ComPhyMuxBitCount[Id]; + /* - * Below macro contains variable name concatenation (used to form PCD's = name) - * and that's why invoking it cannot be automated, e.g. using for loop. - * Currently up to 4 ComPhys might be configured. + * Below macro contains variable name concatenation (used to form PCD's = name). */ - GetComPhyPcd(ChipConfig, LaneData, 0); - GetComPhyPcd(ChipConfig, LaneData, 1); - GetComPhyPcd(ChipConfig, LaneData, 2); - GetComPhyPcd(ChipConfig, LaneData, 3); + switch (Id) { + case 0: + GetComPhyPcd (ChipConfig, LaneData, 0); + break; + case 1: + GetComPhyPcd (ChipConfig, LaneData, 1); + break; + case 2: + GetComPhyPcd (ChipConfig, LaneData, 2); + break; + case 3: + GetComPhyPcd (ChipConfig, LaneData, 3); + break; + } } =20 EFI_STATUS @@ -242,29 +258,42 @@ MvComPhyInit ( ) { EFI_STATUS Status; - CHIP_COMPHY_CONFIG ChipConfig[MAX_CHIPS], *PtrChipCfg; - PCD_LANE_MAP LaneData[MAX_CHIPS]; - UINT32 Lane, ChipCount, i, MaxComphyCount; - - ChipCount =3D PcdGet32 (PcdComPhyChipCount); - - InitComPhyConfig(ChipConfig, LaneData); + CHIP_COMPHY_CONFIG ChipConfig[MVHW_MAX_COMPHY_DEVS], *PtrChipCfg; + PCD_LANE_MAP LaneData[MVHW_MAX_COMPHY_DEVS]; + UINT32 Lane, MaxComphyCount; + UINT8 *ComPhyDeviceTable, Index; + + /* Obtain table with enabled ComPhy devices */ + ComPhyDeviceTable =3D (UINT8 *)PcdGetPtr (PcdComPhyDevices); + if (ComPhyDeviceTable =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "Missing PcdComPhyDevices\n")); + return EFI_INVALID_PARAMETER; + } =20 - if (ChipCount <=3D 0 || ChipCount > MAX_CHIPS) + if (PcdGetSize (PcdComPhyDevices) > MVHW_MAX_COMPHY_DEVS) { + DEBUG ((DEBUG_ERROR, "Wrong PcdComPhyDevices format\n")); return EFI_INVALID_PARAMETER; + } + + /* Initialize enabled chips */ + for (Index =3D 0; Index < PcdGetSize (PcdComPhyDevices); Index++) { + if (!MVHW_DEV_ENABLED (ComPhy, Index)) { + DEBUG ((DEBUG_ERROR, "Skip ComPhy chip %d\n", Index)); + continue; + } =20 - for (i =3D 0; i < ChipCount ; i++) { - PtrChipCfg =3D &ChipConfig[i]; + PtrChipCfg =3D &ChipConfig[Index]; + InitComPhyConfig(PtrChipCfg, LaneData, Index); =20 /* Get the count of the SerDes of the specific chip */ MaxComphyCount =3D PtrChipCfg->LanesCount; for (Lane =3D 0; Lane < MaxComphyCount; Lane++) { /* Parse PCD with string indicating SerDes Type */ PtrChipCfg->MapData[Lane].Type =3D - ParseSerdesTypeString (LaneData[i].TypeStr[Lane]); + ParseSerdesTypeString (LaneData[Index].TypeStr[Lane]); PtrChipCfg->MapData[Lane].Speed =3D - ParseSerdesSpeed (LaneData[i].SpeedValue[Lane]); - PtrChipCfg->MapData[Lane].Invert =3D (UINT32) LaneData[i].InvFlag[La= ne]; + ParseSerdesSpeed (LaneData[Index].SpeedValue[Lane]); + PtrChipCfg->MapData[Lane].Invert =3D (UINT32)LaneData[Index].InvFlag= [Lane]; =20 if ((PtrChipCfg->MapData[Lane].Speed =3D=3D PHY_SPEED_INVALID) || (PtrChipCfg->MapData[Lane].Speed =3D=3D PHY_SPEED_ERROR) || @@ -278,7 +307,7 @@ MvComPhyInit ( =20 Status =3D GetChipComPhyInit (PtrChipCfg); if (EFI_ERROR(Status)) { - DEBUG((DEBUG_ERROR, "ComPhy: Invalid Chip%dType name\n", i)); + DEBUG ((DEBUG_ERROR, "ComPhy: Invalid Chip%d type\n", Index)); return Status; } =20 diff --git a/Platform/Marvell/Library/ComPhyLib/ComPhyLib.h b/Platform/Marv= ell/Library/ComPhyLib/ComPhyLib.h index 56bb991..3c589f2 100644 --- a/Platform/Marvell/Library/ComPhyLib/ComPhyLib.h +++ b/Platform/Marvell/Library/ComPhyLib/ComPhyLib.h @@ -40,22 +40,17 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DA= MAGE. #include #include #include +#include #include #include #include =20 #define MAX_LANE_OPTIONS 10 -#define MAX_CHIPS 4 =20 /***** Parsing PCD *****/ -#define GET_TYPE_STRING(id) PcdGetPtr(PcdChip##id##Compatible) #define GET_LANE_TYPE(id) PcdGetPtr(PcdChip##id##ComPhyTypes) #define GET_LANE_SPEED(id) PcdGetPtr(PcdChip##id##ComPhySpeeds) #define GET_LANE_INV(id) PcdGetPtr(PcdChip##id##ComPhyInvFlags) -#define GET_COMPHY_BASE_ADDR(id) PcdGet64(PcdChip##id##ComPhyBaseAddress) -#define GET_HPIPE3_BASE_ADDR(id) PcdGet64(PcdChip##id##Hpipe3BaseAddress) -#define GET_MUX_BIT_COUNT(id) PcdGet32(PcdChip##id##ComPhyMuxBitCount) -#define GET_MAX_LANES(id) PcdGet32(PcdChip##id##ComPhyMaxLanes) =20 #define FillLaneMap(chip_struct, lane_struct, id) { \ ParsePcdString((CHAR16 *) GET_LANE_TYPE(id), chip_struct[id].LanesCount,= NULL, lane_struct[id].TypeStr); \ @@ -64,11 +59,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAM= AGE. } =20 #define GetComPhyPcd(chip_struct, lane_struct, id) { \ - chip_struct[id].ChipType =3D (CHAR16 *) GET_TYPE_STRING(id); \ - chip_struct[id].ComPhyBaseAddr =3D GET_COMPHY_BASE_ADDR(id); \ - chip_struct[id].Hpipe3BaseAddr =3D GET_HPIPE3_BASE_ADDR(id); \ - chip_struct[id].MuxBitCount =3D GET_MUX_BIT_COUNT(id); \ - chip_struct[id].LanesCount =3D GET_MAX_LANES(id); \ FillLaneMap(chip_struct, lane_struct, id); \ } =20 @@ -601,7 +591,7 @@ VOID ); =20 struct _CHIP_COMPHY_CONFIG { - CHAR16* ChipType; + MV_COMPHY_CHIP_TYPE ChipType; COMPHY_MAP MapData[MAX_LANE_OPTIONS]; COMPHY_MUX_DATA *MuxData; EFI_PHYSICAL_ADDRESS ComPhyBaseAddr; diff --git a/Platform/Marvell/Library/ComPhyLib/ComPhyLib.inf b/Platform/Ma= rvell/Library/ComPhyLib/ComPhyLib.inf index 45bfef2..e0f4634 100644 --- a/Platform/Marvell/Library/ComPhyLib/ComPhyLib.inf +++ b/Platform/Marvell/Library/ComPhyLib/ComPhyLib.inf @@ -59,48 +59,24 @@ ComPhyMux.c =20 [FixedPcd] - gMarvellTokenSpaceGuid.PcdComPhyChipCount + gMarvellTokenSpaceGuid.PcdComPhyDevices =20 #Chip0 - gMarvellTokenSpaceGuid.PcdChip0Compatible - gMarvellTokenSpaceGuid.PcdChip0ComPhyBaseAddress - gMarvellTokenSpaceGuid.PcdChip0Hpipe3BaseAddress - gMarvellTokenSpaceGuid.PcdChip0ComPhyMuxBitCount - gMarvellTokenSpaceGuid.PcdChip0ComPhyMaxLanes - gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds gMarvellTokenSpaceGuid.PcdChip0ComPhyInvFlags =20 #Chip1 - gMarvellTokenSpaceGuid.PcdChip1Compatible - gMarvellTokenSpaceGuid.PcdChip1ComPhyBaseAddress - gMarvellTokenSpaceGuid.PcdChip1Hpipe3BaseAddress - gMarvellTokenSpaceGuid.PcdChip1ComPhyMuxBitCount - gMarvellTokenSpaceGuid.PcdChip1ComPhyMaxLanes - gMarvellTokenSpaceGuid.PcdChip1ComPhyTypes gMarvellTokenSpaceGuid.PcdChip1ComPhySpeeds gMarvellTokenSpaceGuid.PcdChip1ComPhyInvFlags =20 #Chip2 - gMarvellTokenSpaceGuid.PcdChip2Compatible - gMarvellTokenSpaceGuid.PcdChip2ComPhyBaseAddress - gMarvellTokenSpaceGuid.PcdChip2Hpipe3BaseAddress - gMarvellTokenSpaceGuid.PcdChip2ComPhyMuxBitCount - gMarvellTokenSpaceGuid.PcdChip2ComPhyMaxLanes - gMarvellTokenSpaceGuid.PcdChip2ComPhyTypes gMarvellTokenSpaceGuid.PcdChip2ComPhySpeeds gMarvellTokenSpaceGuid.PcdChip2ComPhyInvFlags =20 #Chip3 - gMarvellTokenSpaceGuid.PcdChip3Compatible - gMarvellTokenSpaceGuid.PcdChip3ComPhyBaseAddress - gMarvellTokenSpaceGuid.PcdChip3Hpipe3BaseAddress - gMarvellTokenSpaceGuid.PcdChip3ComPhyMuxBitCount - gMarvellTokenSpaceGuid.PcdChip3ComPhyMaxLanes - gMarvellTokenSpaceGuid.PcdChip3ComPhyTypes gMarvellTokenSpaceGuid.PcdChip3ComPhySpeeds gMarvellTokenSpaceGuid.PcdChip3ComPhyInvFlags diff --git a/Platform/Marvell/Marvell.dec b/Platform/Marvell/Marvell.dec index 735a71f..5cbf0c3 100644 --- a/Platform/Marvell/Marvell.dec +++ b/Platform/Marvell/Marvell.dec @@ -130,48 +130,24 @@ gMarvellTokenSpaceGuid.PcdSpiFlashId|0|UINT32|0x3000056 =20 #ComPhy - #Chip0 - gMarvellTokenSpaceGuid.PcdComPhyChipCount|0|UINT32|0x30000098 - - gMarvellTokenSpaceGuid.PcdChip0Compatible|{ 0x0 }|VOID*|0x30000064 - gMarvellTokenSpaceGuid.PcdChip0ComPhyBaseAddress|0|UINT64|0x30000065 - gMarvellTokenSpaceGuid.PcdChip0Hpipe3BaseAddress|0|UINT64|0x30000066 - gMarvellTokenSpaceGuid.PcdChip0ComPhyMuxBitCount|0|UINT32|0x30000067 - gMarvellTokenSpaceGuid.PcdChip0ComPhyMaxLanes|0|UINT32|0x30001267 + gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x0 }|VOID*|0x30000098 =20 + #Chip0 gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ 0x0 }|VOID*|0x30000068 gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ 0x0 }|VOID*|0x30000069 gMarvellTokenSpaceGuid.PcdChip0ComPhyInvFlags|{ 0x0 }|VOID*|0x30000070 =20 #Chip1 - gMarvellTokenSpaceGuid.PcdChip1Compatible|{ 0x0 }|VOID*|0x30000100 - gMarvellTokenSpaceGuid.PcdChip1ComPhyBaseAddress|0|UINT64|0x30000101 - gMarvellTokenSpaceGuid.PcdChip1Hpipe3BaseAddress|0|UINT64|0x30000102 - gMarvellTokenSpaceGuid.PcdChip1ComPhyMuxBitCount|0|UINT32|0x30000103 - gMarvellTokenSpaceGuid.PcdChip1ComPhyMaxLanes|0|UINT32|0x30001304 - gMarvellTokenSpaceGuid.PcdChip1ComPhyTypes|{ 0x0 }|VOID*|0x30000105 gMarvellTokenSpaceGuid.PcdChip1ComPhySpeeds|{ 0x0 }|VOID*|0x30000106 gMarvellTokenSpaceGuid.PcdChip1ComPhyInvFlags|{ 0x0 }|VOID*|0x30000107 =20 #Chip2 - gMarvellTokenSpaceGuid.PcdChip2Compatible|{ 0x0 }|VOID*|0x30000135 - gMarvellTokenSpaceGuid.PcdChip2ComPhyBaseAddress|0|UINT64|0x30000136 - gMarvellTokenSpaceGuid.PcdChip2Hpipe3BaseAddress|0|UINT64|0x30000137 - gMarvellTokenSpaceGuid.PcdChip2ComPhyMuxBitCount|0|UINT32|0x30000138 - gMarvellTokenSpaceGuid.PcdChip2ComPhyMaxLanes|0|UINT32|0x30000139 - gMarvellTokenSpaceGuid.PcdChip2ComPhyTypes|{ 0x0 }|VOID*|0x30000140 gMarvellTokenSpaceGuid.PcdChip2ComPhySpeeds|{ 0x0 }|VOID*|0x30000141 gMarvellTokenSpaceGuid.PcdChip2ComPhyInvFlags|{ 0x0 }|VOID*|0x30000142 =20 #Chip3 - gMarvellTokenSpaceGuid.PcdChip3Compatible|{ 0x0 }|VOID*|0x30000170 - gMarvellTokenSpaceGuid.PcdChip3ComPhyBaseAddress|0|UINT64|0x30000171 - gMarvellTokenSpaceGuid.PcdChip3Hpipe3BaseAddress|0|UINT64|0x30000172 - gMarvellTokenSpaceGuid.PcdChip3ComPhyMuxBitCount|0|UINT32|0x30000173 - gMarvellTokenSpaceGuid.PcdChip3ComPhyMaxLanes|0|UINT32|0x30000174 - gMarvellTokenSpaceGuid.PcdChip3ComPhyTypes|{ 0x0 }|VOID*|0x30000175 gMarvellTokenSpaceGuid.PcdChip3ComPhySpeeds|{ 0x0 }|VOID*|0x30000176 gMarvellTokenSpaceGuid.PcdChip3ComPhyInvFlags|{ 0x0 }|VOID*|0x30000177 --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun Apr 28 20:57:55 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1499174705305569.8587700589156; Tue, 4 Jul 2017 06:25:05 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id EA71321CB74D2; Tue, 4 Jul 2017 06:23:02 -0700 (PDT) Received: from mail-lf0-x22b.google.com (mail-lf0-x22b.google.com [IPv6:2a00:1450:4010:c07::22b]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id D399420945610 for ; Tue, 4 Jul 2017 06:23:00 -0700 (PDT) Received: by mail-lf0-x22b.google.com with SMTP id z78so77472988lff.0 for ; Tue, 04 Jul 2017 06:24:39 -0700 (PDT) Received: from mw-mint.semihalf.local (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id c185sm4980970lfc.43.2017.07.04.06.24.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 04 Jul 2017 06:24:36 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=WU0Q3kuDOiNXC+5MU2i8wcoWPlov7X5ln0gd81YSXBc=; b=j+lnuUHH7qKw+VqeJptFi4NEgz49UwA3YSI7xK9xAaaUYa6TIwtGZqPeoGQMdeLNHX Cr4X7El1f3QXt4LwJaVFdkkYPbl/CWBS6/fQvdaH+Zm/ZH1+kcLqMOLrbI9KeTquaZzH vbi2So2nCc5C5EHw9x9hmOhLwFZ/x2zP1GTGjMPcX8VXfa6rj2L6BwNSop/KWhCPGdoP D5OavsThlFSLcjB1lF3gDItShpLO9WBz+4NEO54AVPW1MMrVUrIvO/5XtmdWHU/n1w4J XvFZrljK7b+LFJZswK9DLqjt0DUY1aMdOQqMwDOdCMkzm2RGNS4kPs7dXfZZGgkisblc PLKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=WU0Q3kuDOiNXC+5MU2i8wcoWPlov7X5ln0gd81YSXBc=; b=jl3NQaS5VjNlWiO6D9A2WwTP18bn8zCkoWbxha9vtOKjiuCwIidHblQ81ZsAfdquJK NwFbKY4bjOTrBFp24Wl3iVl7QjM49D5p3u1ZFHGpgZsHrdtGoI5/GzcWLK60HqZTnvpo nw7QmI6IqKr2GZRHT6VpBR3MBZY8D3VYU/Gp/ZPxobWOzj48MZQPmhXiL5I0WKy8GcPs 6xCc7FjiOd2Z4RXcChb9r+Q1GmKsMHgNUUKz574BhjOZZ4zU+fjRqtKRe9dAEw9CZnWg qvY34eoP2oR/TJCQX1s3n2h+Da3UXW3plqICeLZ9cJF+HIalro7B6f0EIHItN98h8i4d XnUA== X-Gm-Message-State: AKS2vOyByVL36g9Q8DWjC+KUZix86+S2ilP55NuP4j7XAssibWADTD93 vU+DRp/nHmVgbULe/Yensg== X-Received: by 10.25.67.81 with SMTP id m17mr10682969lfj.147.1499174677018; Tue, 04 Jul 2017 06:24:37 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Tue, 4 Jul 2017 15:24:12 +0200 Message-Id: <1499174653-330-10-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1499174653-330-1-git-send-email-mw@semihalf.com> References: <1499174653-330-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 09/10] Platform/Marvell: ComPhyLib: Use COMPHY_ prefix in macros X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, leif.lindholm@linaro.org, ard.biesheuvel@linaro.org MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This patch renames macros for speed, type and polarity from 'PHY_' to 'COMPHY_', so that to avoid confusion with network PHY's definitions. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Marcin Wojtas --- Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c | 98 ++++++++++++--------= ---- Platform/Marvell/Library/ComPhyLib/ComPhyLib.c | 22 +++--- Platform/Marvell/Library/ComPhyLib/ComPhyLib.h | 90 +++++++++++---------= -- Platform/Marvell/Library/ComPhyLib/ComPhyMux.c | 4 +- 4 files changed, 107 insertions(+), 107 deletions(-) diff --git a/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c b/Platform/Ma= rvell/Library/ComPhyLib/ComPhyCp110.c index 329bbe8..de35265 100755 --- a/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c +++ b/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c @@ -54,40 +54,40 @@ DECLARE_A7K8K_NONDISCOVERABLE_TEMPLATE; */ COMPHY_MUX_DATA Cp110ComPhyMuxData[] =3D { /* Lane 0 */ - {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII1, 0x1}, {PHY_TYPE_SATA= 1, 0x4}}}, + {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII1, 0x1}, {COMPHY_= TYPE_SATA1, 0x4}}}, /* Lane 1 */ - {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, {PHY_TYPE_SATA= 0, 0x4}}}, + {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII2, 0x1}, {COMPHY_= TYPE_SATA0, 0x4}}}, /* Lane 2 */ - {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x1}, {PHY_TYPE_RXAU= I0, 0x1}, - {PHY_TYPE_SFI, 0x1}, {PHY_TYPE_SATA0, 0x4}}}, + {6, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII0, 0x1}, {COMPHY_= TYPE_RXAUI0, 0x1}, + {COMPHY_TYPE_SFI, 0x1}, {COMPHY_TYPE_SATA0, 0x4}}}, /* Lane 3 */ - {8, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_RXAUI1, 0x1}, {PHY_TYPE_SGMI= I1, 0x2}, - {PHY_TYPE_SATA1, 0x4}}}, + {8, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_RXAUI1, 0x1}, {COMPHY_= TYPE_SGMII1, 0x2}, + {COMPHY_TYPE_SATA1, 0x4}}}, /* Lane 4 */ - {7, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x2}, {PHY_TYPE_RXAU= I0, 0x2}, - {PHY_TYPE_SFI, 0x2}, {PHY_TYPE_SGMII1, 0x1}}}, + {7, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII0, 0x2}, {COMPHY_= TYPE_RXAUI0, 0x2}, + {COMPHY_TYPE_SFI, 0x2}, {COMPHY_TYPE_SGMII1, 0x1}}}, /* Lane 5 */ - {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, {PHY_TYPE_RXAU= I1, 0x2}, - {PHY_TYPE_SATA1, 0x4}}}, + {6, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII2, 0x1}, {COMPHY_= TYPE_RXAUI1, 0x2}, + {COMPHY_TYPE_SATA1, 0x4}}}, }; =20 COMPHY_MUX_DATA Cp110ComPhyPipeMuxData[] =3D { /* Lane 0 */ - {2, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_PCIE0, 0x4} } }, + {2, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_PCIE0, 0x4} } }, /* Lane 1 */ - {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_USB3_HOST0, 0x1}, - {PHY_TYPE_USB3_DEVICE, 0x2}, {PHY_TYPE_PCIE0, 0x4} } }, + {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_USB3_HOST0, 0x1}, + {COMPHY_TYPE_USB3_DEVICE, 0x2}, {COMPHY_TYPE_PCIE0, 0x4} } }, /* Lane 2 */ - {3, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_USB3_HOST0, 0x1}, - {PHY_TYPE_PCIE0, 0x4} } }, + {3, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_USB3_HOST0, 0x1}, + {COMPHY_TYPE_PCIE0, 0x4} } }, /* Lane 3 */ - {3, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_USB3_HOST1, 0x1}, - {PHY_TYPE_PCIE0, 0x4} } }, + {3, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_USB3_HOST1, 0x1}, + {COMPHY_TYPE_PCIE0, 0x4} } }, /* Lane 4 */ - {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_USB3_HOST1, 0x1}, - {PHY_TYPE_USB3_DEVICE, 0x2}, {PHY_TYPE_PCIE1, 0x4} } }, + {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_USB3_HOST1, 0x1}, + {COMPHY_TYPE_USB3_DEVICE, 0x2}, {COMPHY_TYPE_PCIE1, 0x4} } }, /* Lane 5 */ - {2, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_PCIE2, 0x4} } }, + {2, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_PCIE2, 0x4} } }, }; =20 STATIC @@ -1102,7 +1102,7 @@ ComPhySgmiiRFUConfiguration ( Data =3D 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; Mask |=3D SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK; Mask |=3D SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK; - if (SgmiiSpeed =3D=3D PHY_SPEED_1_25G) { + if (SgmiiSpeed =3D=3D COMPHY_SPEED_1_25G) { Data |=3D 0x6 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET; Data |=3D 0x6 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET; } else { @@ -1320,7 +1320,7 @@ ComPhySfiPhyConfiguration ( =20 /* Set reference clock */ Mask =3D HPIPE_MISC_ICP_FORCE_MASK | HPIPE_MISC_REFCLK_SEL_MASK; - Data =3D (SfiSpeed =3D=3D PHY_SPEED_5_15625G) ? + Data =3D (SfiSpeed =3D=3D COMPHY_SPEED_5_15625G) ? (0x0 << HPIPE_MISC_ICP_FORCE_OFFSET) : (0x1 << HPIPE_MISC_ICP_FORCE_OF= FSET); MmioAndThenOr32 (HpipeAddr + HPIPE_MISC_REG, ~Mask, Data); =20 @@ -1348,7 +1348,7 @@ ComPhySfiPhyConfiguration ( MmioOr32 (HpipeAddr + HPIPE_PWR_CTR_DTL_REG, HPIPE_PWR_CTR_DTL_FLOOP_EN_= MASK); =20 /* Transmitter/Receiver Speed Divider Force */ - if (SfiSpeed =3D=3D PHY_SPEED_5_15625G) { + if (SfiSpeed =3D=3D COMPHY_SPEED_5_15625G) { Mask =3D HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_MASK | HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_MASK | HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_MASK | @@ -1380,7 +1380,7 @@ ComPhySfiSetAnalogParameters ( MmioOr32 (HpipeAddr + HPIPE_DFE_REG0, HPIPE_DFE_RES_FORCE_MASK); =20 /* Generation 1 setting_0 */ - if (SfiSpeed =3D=3D PHY_SPEED_5_15625G) { + if (SfiSpeed =3D=3D COMPHY_SPEED_5_15625G) { Mask =3D HPIPE_GX_SET0_TX_EMPH1_MASK; Data =3D 0x6 << HPIPE_GX_SET0_TX_EMPH1_OFFSET; } else { @@ -1414,7 +1414,7 @@ ComPhySfiSetAnalogParameters ( MmioAnd32 (HpipeAddr + HPIPE_G1_SET5_REG, ~HPIPE_GX_SET5_ICP_MASK); =20 /* Generation 1 setting 1 */ - if (SfiSpeed =3D=3D PHY_SPEED_5_15625G) { + if (SfiSpeed =3D=3D COMPHY_SPEED_5_15625G) { Mask =3D HPIPE_GX_SET1_RX_SELMUPI_MASK | HPIPE_GX_SET1_RX_SELMUPP_MASK; Data =3D 0x1 | (0x1 << HPIPE_GX_SET1_RX_SELMUPP_OFFSET); } else { @@ -1447,7 +1447,7 @@ ComPhySfiSetAnalogParameters ( /* Generation 1 setting 3 */ MmioOr32 (HpipeAddr + HPIPE_G1_SET3_REG, HPIPE_GX_SET3_FBCK_SEL_MASK); =20 - if (SfiSpeed =3D=3D PHY_SPEED_5_15625G) { + if (SfiSpeed =3D=3D COMPHY_SPEED_5_15625G) { /* Force FFE (Feed Forward Equalization) to 5G */ Mask =3D HPIPE_GX_SET3_FFE_CAP_SEL_MASK | HPIPE_GX_SET3_FFE_RES_SEL_MASK | @@ -1760,9 +1760,9 @@ ComPhyMuxCp110 ( =20 /* Fix the Type after check the PHY and PIPE configuration */ for (Lane =3D 0; Lane < ComPhyMaxCount; Lane++) - if ((ComPhyMapPipeData[Lane].Type =3D=3D PHY_TYPE_UNCONNECTED) && - (ComPhyMapPhyData[Lane].Type =3D=3D PHY_TYPE_UNCONNECTED)) - SerdesMap[Lane].Type =3D PHY_TYPE_UNCONNECTED; + if ((ComPhyMapPipeData[Lane].Type =3D=3D COMPHY_TYPE_UNCONNECTED) && + (ComPhyMapPhyData[Lane].Type =3D=3D COMPHY_TYPE_UNCONNECTED)) + SerdesMap[Lane].Type =3D COMPHY_TYPE_UNCONNECTED; } =20 VOID @@ -1786,7 +1786,7 @@ ComPhyCp110Init ( =20 /* Check if the first 4 Lanes configured as By-4 */ for (Lane =3D 0, PtrComPhyMap =3D SerdesMap; Lane < 4; Lane++, PtrComPhy= Map++) { - if (PtrComPhyMap->Type !=3D PHY_TYPE_PCIE0) { + if (PtrComPhyMap->Type !=3D COMPHY_TYPE_PCIE0) { PcieBy4 =3D 0; break; } @@ -1797,39 +1797,39 @@ ComPhyCp110Init ( DEBUG((DEBUG_INFO, "ComPhy: Initialize serdes number %d\n", Lane)); DEBUG((DEBUG_INFO, "ComPhy: Serdes Type =3D 0x%x\n", PtrComPhyMap->Typ= e)); switch (PtrComPhyMap->Type) { - case PHY_TYPE_UNCONNECTED: + case COMPHY_TYPE_UNCONNECTED: continue; break; - case PHY_TYPE_PCIE0: - case PHY_TYPE_PCIE1: - case PHY_TYPE_PCIE2: - case PHY_TYPE_PCIE3: + case COMPHY_TYPE_PCIE0: + case COMPHY_TYPE_PCIE1: + case COMPHY_TYPE_PCIE2: + case COMPHY_TYPE_PCIE3: Status =3D ComPhyPciePowerUp(Lane, PcieBy4, HpipeBaseAddr, ComPhyBas= eAddr); break; - case PHY_TYPE_SATA0: - case PHY_TYPE_SATA1: + case COMPHY_TYPE_SATA0: + case COMPHY_TYPE_SATA1: Status =3D ComPhySataPowerUp (Lane, HpipeBaseAddr, ComPhyBaseAddr, M= VHW_CP0_AHCI0_ID); break; - case PHY_TYPE_SATA2: - case PHY_TYPE_SATA3: + case COMPHY_TYPE_SATA2: + case COMPHY_TYPE_SATA3: Status =3D ComPhySataPowerUp (Lane, HpipeBaseAddr, ComPhyBaseAddr, M= VHW_CP1_AHCI0_ID); break; - case PHY_TYPE_USB3_HOST0: - case PHY_TYPE_USB3_HOST1: + case COMPHY_TYPE_USB3_HOST0: + case COMPHY_TYPE_USB3_HOST1: Status =3D ComphyUsb3PowerUp(Lane, HpipeBaseAddr, ComPhyBaseAddr); break; - case PHY_TYPE_SGMII0: - case PHY_TYPE_SGMII1: - case PHY_TYPE_SGMII2: - case PHY_TYPE_SGMII3: + case COMPHY_TYPE_SGMII0: + case COMPHY_TYPE_SGMII1: + case COMPHY_TYPE_SGMII2: + case COMPHY_TYPE_SGMII3: Status =3D ComPhySgmiiPowerUp(Lane, PtrComPhyMap->Speed, HpipeBaseAd= dr, ComPhyBaseAddr); break; - case PHY_TYPE_SFI: + case COMPHY_TYPE_SFI: Status =3D ComPhySfiPowerUp(Lane, HpipeBaseAddr, ComPhyBaseAddr, Ptr= ComPhyMap->Speed); break; - case PHY_TYPE_RXAUI0: - case PHY_TYPE_RXAUI1: + case COMPHY_TYPE_RXAUI0: + case COMPHY_TYPE_RXAUI1: Status =3D ComPhyRxauiPowerUp(Lane, HpipeBaseAddr, ComPhyBaseAddr); break; default: @@ -1841,7 +1841,7 @@ ComPhyCp110Init ( } if (EFI_ERROR(Status)) { DEBUG ((DEBUG_ERROR, "Failed to initialize Lane %d\n with Status =3D= 0x%x", Lane, Status)); - PtrComPhyMap->Type =3D PHY_TYPE_UNCONNECTED; + PtrComPhyMap->Type =3D COMPHY_TYPE_UNCONNECTED; } } } diff --git a/Platform/Marvell/Library/ComPhyLib/ComPhyLib.c b/Platform/Marv= ell/Library/ComPhyLib/ComPhyLib.c index b61ccb6..3eb5d9f 100644 --- a/Platform/Marvell/Library/ComPhyLib/ComPhyLib.c +++ b/Platform/Marvell/Library/ComPhyLib/ComPhyLib.c @@ -122,16 +122,16 @@ ParseSerdesTypeString ( UINT32 i; =20 if (String =3D=3D NULL) - return PHY_TYPE_INVALID; + return COMPHY_TYPE_INVALID; =20 - for (i =3D 0; i < PHY_TYPE_MAX; i++) { + for (i =3D 0; i < COMPHY_TYPE_MAX; i++) { if (StrCmp (String, TypeStringTable[i]) =3D=3D 0) { return i; } } =20 /* PCD string doesn't match any supported SerDes Type */ - return PHY_TYPE_INVALID; + return COMPHY_TYPE_INVALID; } =20 /* This function converts SerDes speed in MHz to enum with SerDesSpeed */ @@ -144,14 +144,14 @@ ParseSerdesSpeed ( UINT32 ValueTable [] =3D {0, 1250, 1500, 2500, 3000, 3125, 5000, 5156, 6000, 6250, 10310}; =20 - for (i =3D 0; i < PHY_SPEED_MAX; i++) { + for (i =3D 0; i < COMPHY_SPEED_MAX; i++) { if (Value =3D=3D ValueTable[i]) { return i; } } =20 /* PCD SerDes speed value doesn't match any supported SerDes speed */ - return PHY_SPEED_INVALID; + return COMPHY_SPEED_INVALID; } =20 CHAR16 * @@ -160,7 +160,7 @@ GetTypeString ( ) { =20 - if (Type < 0 || Type > PHY_TYPE_MAX) { + if (Type < 0 || Type > COMPHY_TYPE_MAX) { return L"invalid"; } =20 @@ -295,13 +295,13 @@ MvComPhyInit ( ParseSerdesSpeed (LaneData[Index].SpeedValue[Lane]); PtrChipCfg->MapData[Lane].Invert =3D (UINT32)LaneData[Index].InvFlag= [Lane]; =20 - if ((PtrChipCfg->MapData[Lane].Speed =3D=3D PHY_SPEED_INVALID) || - (PtrChipCfg->MapData[Lane].Speed =3D=3D PHY_SPEED_ERROR) || - (PtrChipCfg->MapData[Lane].Type =3D=3D PHY_TYPE_INVALID)) { + if ((PtrChipCfg->MapData[Lane].Speed =3D=3D COMPHY_SPEED_INVALID) || + (PtrChipCfg->MapData[Lane].Speed =3D=3D COMPHY_SPEED_ERROR) || + (PtrChipCfg->MapData[Lane].Type =3D=3D COMPHY_TYPE_INVALID)) { DEBUG((DEBUG_ERROR, "ComPhy: No valid phy speed or type for lane %= d, " "setting lane as unconnected\n", Lane + 1)); - PtrChipCfg->MapData[Lane].Type =3D PHY_TYPE_UNCONNECTED; - PtrChipCfg->MapData[Lane].Speed =3D PHY_SPEED_INVALID; + PtrChipCfg->MapData[Lane].Type =3D COMPHY_TYPE_UNCONNECTED; + PtrChipCfg->MapData[Lane].Speed =3D COMPHY_SPEED_INVALID; } }; =20 diff --git a/Platform/Marvell/Library/ComPhyLib/ComPhyLib.h b/Platform/Marv= ell/Library/ComPhyLib/ComPhyLib.h index 3c589f2..3898978 100644 --- a/Platform/Marvell/Library/ComPhyLib/ComPhyLib.h +++ b/Platform/Marvell/Library/ComPhyLib/ComPhyLib.h @@ -63,51 +63,51 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DA= MAGE. } =20 /***** ComPhy *****/ -#define PHY_SPEED_ERROR 0 -#define PHY_SPEED_1_25G 1 -#define PHY_SPEED_1_5G 2 -#define PHY_SPEED_2_5G 3 -#define PHY_SPEED_3G 4 -#define PHY_SPEED_3_125G 5 -#define PHY_SPEED_5G 6 -#define PHY_SPEED_5_15625G 7 -#define PHY_SPEED_6G 8 -#define PHY_SPEED_6_25G 9 -#define PHY_SPEED_10_3125G 10 -#define PHY_SPEED_MAX 11 -#define PHY_SPEED_INVALID 0xff - -#define PHY_TYPE_UNCONNECTED 0 -#define PHY_TYPE_PCIE0 1 -#define PHY_TYPE_PCIE1 2 -#define PHY_TYPE_PCIE2 3 -#define PHY_TYPE_PCIE3 4 -#define PHY_TYPE_SATA0 5 -#define PHY_TYPE_SATA1 6 -#define PHY_TYPE_SATA2 7 -#define PHY_TYPE_SATA3 8 -#define PHY_TYPE_SGMII0 9 -#define PHY_TYPE_SGMII1 10 -#define PHY_TYPE_SGMII2 11 -#define PHY_TYPE_SGMII3 12 -#define PHY_TYPE_QSGMII 13 -#define PHY_TYPE_USB3_HOST0 14 -#define PHY_TYPE_USB3_HOST1 15 -#define PHY_TYPE_USB3_DEVICE 16 -#define PHY_TYPE_XAUI0 17 -#define PHY_TYPE_XAUI1 18 -#define PHY_TYPE_XAUI2 19 -#define PHY_TYPE_XAUI3 20 -#define PHY_TYPE_RXAUI0 21 -#define PHY_TYPE_RXAUI1 22 -#define PHY_TYPE_SFI 23 -#define PHY_TYPE_MAX 24 -#define PHY_TYPE_INVALID 0xff - -#define PHY_POLARITY_NO_INVERT 0 -#define PHY_POLARITY_TXD_INVERT 1 -#define PHY_POLARITY_RXD_INVERT 2 -#define PHY_POLARITY_ALL_INVERT (PHY_POLARITY_TXD_INVERT= | PHY_POLARITY_RXD_INVERT) +#define COMPHY_SPEED_ERROR 0 +#define COMPHY_SPEED_1_25G 1 +#define COMPHY_SPEED_1_5G 2 +#define COMPHY_SPEED_2_5G 3 +#define COMPHY_SPEED_3G 4 +#define COMPHY_SPEED_3_125G 5 +#define COMPHY_SPEED_5G 6 +#define COMPHY_SPEED_5_15625G 7 +#define COMPHY_SPEED_6G 8 +#define COMPHY_SPEED_6_25G 9 +#define COMPHY_SPEED_10_3125G 10 +#define COMPHY_SPEED_MAX 11 +#define COMPHY_SPEED_INVALID 0xff + +#define COMPHY_TYPE_UNCONNECTED 0 +#define COMPHY_TYPE_PCIE0 1 +#define COMPHY_TYPE_PCIE1 2 +#define COMPHY_TYPE_PCIE2 3 +#define COMPHY_TYPE_PCIE3 4 +#define COMPHY_TYPE_SATA0 5 +#define COMPHY_TYPE_SATA1 6 +#define COMPHY_TYPE_SATA2 7 +#define COMPHY_TYPE_SATA3 8 +#define COMPHY_TYPE_SGMII0 9 +#define COMPHY_TYPE_SGMII1 10 +#define COMPHY_TYPE_SGMII2 11 +#define COMPHY_TYPE_SGMII3 12 +#define COMPHY_TYPE_QSGMII 13 +#define COMPHY_TYPE_USB3_HOST0 14 +#define COMPHY_TYPE_USB3_HOST1 15 +#define COMPHY_TYPE_USB3_DEVICE 16 +#define COMPHY_TYPE_XAUI0 17 +#define COMPHY_TYPE_XAUI1 18 +#define COMPHY_TYPE_XAUI2 19 +#define COMPHY_TYPE_XAUI3 20 +#define COMPHY_TYPE_RXAUI0 21 +#define COMPHY_TYPE_RXAUI1 22 +#define COMPHY_TYPE_SFI 23 +#define COMPHY_TYPE_MAX 24 +#define COMPHY_TYPE_INVALID 0xff + +#define COMPHY_POLARITY_NO_INVERT 0 +#define COMPHY_POLARITY_TXD_INVERT 1 +#define COMPHY_POLARITY_RXD_INVERT 2 +#define COMPHY_POLARITY_ALL_INVERT (COMPHY_POLARITY_TXD_= INVERT | COMPHY_POLARITY_RXD_INVERT) =20 /***** SerDes IP registers *****/ #define SD_EXTERNAL_CONFIG0_REG 0 diff --git a/Platform/Marvell/Library/ComPhyLib/ComPhyMux.c b/Platform/Marv= ell/Library/ComPhyLib/ComPhyMux.c index 595745b..6589fec 100644 --- a/Platform/Marvell/Library/ComPhyLib/ComPhyMux.c +++ b/Platform/Marvell/Library/ComPhyLib/ComPhyMux.c @@ -57,8 +57,8 @@ ComPhyMuxCheckConfig ( DEBUG((DEBUG_INFO, "Lane number %d, had invalid Type %d\n", Lane, ComPhyMapData->Type)); DEBUG((DEBUG_INFO, "Set Lane %d as Type %d\n", Lane, - PHY_TYPE_UNCONNECTED)); - ComPhyMapData->Type =3D PHY_TYPE_UNCONNECTED; + COMPHY_TYPE_UNCONNECTED)); + ComPhyMapData->Type =3D COMPHY_TYPE_UNCONNECTED; } else { DEBUG((DEBUG_INFO, "Lane number %d, has Type %d\n", Lane, ComPhyMapData->Type)); --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun Apr 28 20:57:55 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1499174710414251.0650485131158; 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id c185sm4980970lfc.43.2017.07.04.06.24.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 04 Jul 2017 06:24:37 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=PEQNcf3btk9MMoMC0qc6msWMMPRNjUFU+hxv90elF3A=; b=y7M/WWRblurePQYV4dy8gVpxUTnq+icEhONa09/6C9hGj2kEG1WEPmg9co9H4xN3pb lb4Jcelzzllb1yrUUkROhdJS7W9J7urX9AKIBtviTTMPEYAdyfg6085VdVIqjtjAbKy+ uYmWyNzRCSNnKlVDGSzySdG7kNAW2itPRxlrveEEKXM2kQTYUg90nkUMLOKdHI3gU7Af 5zrCv2PpR+JwaaaEMosAX2LGlBEDoL55ZA/TidrT/h9zOOivosz4Nbn07pW3spTYFY2Z tISooban8lr05VEQJCYHu5TZ/PG+2KARyP5QEl2hUAV5vBLeYFkTOWZPlA4F5qK0bRCy nQXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=PEQNcf3btk9MMoMC0qc6msWMMPRNjUFU+hxv90elF3A=; b=cb+smyNTone6HojdJ5FSs0CAui381c9Siry6e02FNzIAKmc93ThJuuRd+3hywnbtgG TWxWUtEb4lZwXsA0VmwzaOP5vT9Ofs9Hzbj6MdWk1S8xTH29ztyd0REAq8aoSOBwCLid 2cvry78X0H4QIBxWg60X6PvMbxAdOaQt8qsXK1GVvnvDQvnPvPN6vc1fqeKNNRkYAoLD +oI+DVzA926aSvK5rzfBxsOrHFZQCBz0kK4le1clrNk/Gyw4ETjdkK6XprTPkkuAbg2s TF+BAFYebbMsG79PUiUUjJbJmtmQ8KtGAZ1EV5F8KslbQm4VK8dbBNmAWz2KjBOrf13C zFGw== X-Gm-Message-State: AKS2vOz9G3U8hexZtrUAT+k4fVbNEKn66mdzSso+4plLQt83ogwFYAiz qjcpIo0pHTxknQqQpf5t2w== X-Received: by 10.25.67.22 with SMTP id q22mr11068883lfa.144.1499174678156; Tue, 04 Jul 2017 06:24:38 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Tue, 4 Jul 2017 15:24:13 +0200 Message-Id: <1499174653-330-11-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1499174653-330-1-git-send-email-mw@semihalf.com> References: <1499174653-330-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 10/10] Platform/Marvell: ComPhyLib: Add support for SATA ports on CP110 slave X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, leif.lindholm@linaro.org, ard.biesheuvel@linaro.org MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Ard Biesheuvel Add support for PHY_TYPE_SATA2 and PHY_TYPE_SATA3, which map to the SATA ports on the second CP110's AHCI controller. While at it, add a missing newline in the debug output to make it more legible. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel Signed-off-by: Marcin Wojtas --- Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c b/Platform/Ma= rvell/Library/ComPhyLib/ComPhyCp110.c index de35265..5180060 100755 --- a/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c +++ b/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c @@ -54,21 +54,23 @@ DECLARE_A7K8K_NONDISCOVERABLE_TEMPLATE; */ COMPHY_MUX_DATA Cp110ComPhyMuxData[] =3D { /* Lane 0 */ - {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII1, 0x1}, {COMPHY_= TYPE_SATA1, 0x4}}}, + {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII1, 0x1}, {COMPHY_= TYPE_SATA1, 0x4}, + {COMPHY_TYPE_SATA3, 0x4}}}, /* Lane 1 */ - {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII2, 0x1}, {COMPHY_= TYPE_SATA0, 0x4}}}, + {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII2, 0x1}, {COMPHY_= TYPE_SATA0, 0x4}, + {COMPHY_TYPE_SATA2, 0x4}}}, /* Lane 2 */ {6, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII0, 0x1}, {COMPHY_= TYPE_RXAUI0, 0x1}, - {COMPHY_TYPE_SFI, 0x1}, {COMPHY_TYPE_SATA0, 0x4}}}, + {COMPHY_TYPE_SFI, 0x1}, {COMPHY_TYPE_SATA0, 0x4}, {COMPHY_TYPE_SATA2, = 0x4}}}, /* Lane 3 */ - {8, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_RXAUI1, 0x1}, {COMPHY_= TYPE_SGMII1, 0x2}, - {COMPHY_TYPE_SATA1, 0x4}}}, + {5, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_RXAUI1, 0x1}, {COMPHY_= TYPE_SGMII1, 0x2}, + {COMPHY_TYPE_SATA1, 0x4}, {COMPHY_TYPE_SATA3, 0x4}}}, /* Lane 4 */ - {7, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII0, 0x2}, {COMPHY_= TYPE_RXAUI0, 0x2}, + {5, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII0, 0x2}, {COMPHY_= TYPE_RXAUI0, 0x2}, {COMPHY_TYPE_SFI, 0x2}, {COMPHY_TYPE_SGMII1, 0x1}}}, /* Lane 5 */ - {6, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII2, 0x1}, {COMPHY_= TYPE_RXAUI1, 0x2}, - {COMPHY_TYPE_SATA1, 0x4}}}, + {5, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII2, 0x1}, {COMPHY_= TYPE_RXAUI1, 0x2}, + {COMPHY_TYPE_SATA1, 0x4}, {COMPHY_TYPE_SATA3, 0x4}}}, }; =20 COMPHY_MUX_DATA Cp110ComPhyPipeMuxData[] =3D { @@ -1840,7 +1842,7 @@ ComPhyCp110Init ( break; } if (EFI_ERROR(Status)) { - DEBUG ((DEBUG_ERROR, "Failed to initialize Lane %d\n with Status =3D= 0x%x", Lane, Status)); + DEBUG ((DEBUG_ERROR, "Failed to initialize Lane %d\n with Status =3D= 0x%x\n", Lane, Status)); PtrComPhyMap->Type =3D COMPHY_TYPE_UNCONNECTED; } } --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel