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X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jordan Justen , Leo Duran , Jeff Fan , Liming Gao Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Cc: Jordan Justen Cc: Jeff Fan Cc: Liming Gao Cc: Brijesh Singh Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leo Duran --- UefiCpuPkg/Include/Register/Amd/Cpuid.h | 574 ++++++++++++++++++++++++++++= +++- 1 file changed, 565 insertions(+), 9 deletions(-) diff --git a/UefiCpuPkg/Include/Register/Amd/Cpuid.h b/UefiCpuPkg/Include/R= egister/Amd/Cpuid.h index 74ffb95..d4d777b 100644 --- a/UefiCpuPkg/Include/Register/Amd/Cpuid.h +++ b/UefiCpuPkg/Include/Register/Amd/Cpuid.h @@ -7,6 +7,7 @@ not provided for that register. =20 Copyright (c) 2017, Advanced Micro Devices. All rights reserved.
+ This program and the accompanying materials are licensed and made availa= ble under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at @@ -24,8 +25,562 @@ #define __AMD_CPUID_H__ =20 /** + CPUID Extended Processor Signature and Features =20 - Memory Encryption Information + @param EAX CPUID_EXTENDED_CPU_SIG (0x80000001) + + @retval EAX Extended Family, Model, Stepping Identifiers + described by the type CPUID_AMD_EXTENDED_CPU_SIG_EAX. + @retval EBX Brand Identifier + described by the type CPUID_AMD_EXTENDED_CPU_SIG_EBX. + @retval ECX Extended Feature Identifiers + described by the type CPUID_AMD_EXTENDED_CPU_SIG_ECX. + @retval EDX Extended Feature Identifiers + described by the type CPUID_AMD_EXTENDED_CPU_SIG_EDX. +**/ + +/** + CPUID Extended Processor Signature and Features EAX for CPUID leaf + #CPUID_EXTENDED_CPU_SIG. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 3:0] Stepping. + /// + UINT32 Stepping:4; + /// + /// [Bits 7:4] Base Model. + /// + UINT32 BaseModel:4; + /// + /// [Bits 11:8] Base Family. + /// + UINT32 BaseFamily:4; + /// + /// [Bit 15:12] Reserved. + /// + UINT32 Reserved1:4; + /// + /// [Bits 19:16] Extended Model. + /// + UINT32 ExtModel:4; + /// + /// [Bits 27:20] Extended Family. + /// + UINT32 ExtFamily:8; + /// + /// [Bit 31:28] Reserved. + /// + UINT32 Reserved2:4; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_AMD_EXTENDED_CPU_SIG_EAX; + +/** + CPUID Extended Processor Signature and Features EBX for CPUID leaf + #CPUID_EXTENDED_CPU_SIG. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 27:0] Reserved. + /// + UINT32 Reserved:28; + /// + /// [Bit 31:28] Package Type. + /// + UINT32 PkgType:4; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_AMD_EXTENDED_CPU_SIG_EBX; + +/** + CPUID Extended Processor Signature and Features ECX for CPUID leaf + #CPUID_EXTENDED_CPU_SIG. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] LAHF/SAHF available in 64-bit mode. + /// + UINT32 LAHF_SAHF:1; + /// + /// [Bit 1] Core multi-processing legacy mode. + /// + UINT32 CmpLegacy:1; + /// + /// [Bit 2] Secure Virtual Mode feature. + /// + UINT32 SVM:1; + /// + /// [Bit 3] Extended APIC register space. + /// + UINT32 ExtApicSpace:1; + /// + /// [Bit 4] LOCK MOV CR0 means MOV CR8. + /// + UINT32 AltMovCr8:1; + /// + /// [Bit 5] LZCNT instruction support. + /// + UINT32 LZCNT:1; + /// + /// [Bit 6] SSE4A instruction support. + /// + UINT32 SSE4A:1; + /// + /// [Bit 7] Misaligned SSE Mode. + /// + UINT32 MisAlignSse:1; + /// + /// [Bit 8] ThreeDNow Prefetch instructions. + /// + UINT32 PREFETCHW:1; + /// + /// [Bit 9] OS Visible Work-around support. + /// + UINT32 OSVW:1; + /// + /// [Bit 10] Instruction Based Sampling. + /// + UINT32 IBS:1; + /// + /// [Bit 11] Extended Operation Support. + /// + UINT32 XOP:1; + /// + /// [Bit 12] SKINIT and STGI support. + /// + UINT32 SKINIT:1; + /// + /// [Bit 13] Watchdog Timer support. + /// + UINT32 WDT:1; + /// + /// [Bit 14] Reserved. + /// + UINT32 Reserved1:1; + /// + /// [Bit 15] Lightweight Profiling support. + /// + UINT32 LWP:1; + /// + /// [Bit 16] 4-Operand FMA instruction support. + /// + UINT32 FMA4:1; + /// + /// [Bit 17] Translation Cache Extension. + /// + UINT32 TCE:1; + /// + /// [Bit 21:18] Reserved. + /// + UINT32 Reserved2:4; + /// + /// [Bit 22] Topology Extensions support. + /// + UINT32 TopologyExtensions:1; + /// + /// [Bit 23] Core Performance Counter Extensions. + /// + UINT32 PerfCtrExtCore:1; + /// + /// [Bit 25:24] Reserved. + /// + UINT32 Reserved3:2; + /// + /// [Bit 26] Data Breakpoint Extension. + /// + UINT32 DataBreakpointExtension:1; + /// + /// [Bit 27] Performance Time-Stamp Counter. + /// + UINT32 PerfTsc:1; + /// + /// [Bit 28] L3 Performance Counter Extensions. + /// + UINT32 PerfCtrExtL3:1; + /// + /// [Bit 29] MWAITX and MONITORX capability. + /// + UINT32 MwaitExtended:1; + /// + /// [Bit 31:30] Reserved. + /// + UINT32 Reserved4:2; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_AMD_EXTENDED_CPU_SIG_ECX; + +/** + CPUID Extended Processor Signature and Features EDX for CPUID leaf + #CPUID_EXTENDED_CPU_SIG. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] x87 floating point unit on-chip. + /// + UINT32 FPU:1; + /// + /// [Bit 1] Virtual-mode enhancements. + /// + UINT32 VME:1; + /// + /// [Bit 2] Debugging extensions, IO breakpoints, CR4.DE. + /// + UINT32 DE:1; + /// + /// [Bit 3] Page-size extensions (4 MB pages). + /// + UINT32 PSE:1; + /// + /// [Bit 4] Time stamp counter, RDTSC/RDTSCP instructions, CR4.TSD. + /// + UINT32 TSC:1; + /// + /// [Bit 5] MSRs, with RDMSR and WRMSR instructions. + /// + UINT32 MSR:1; + /// + /// [Bit 6] Physical-address extensions (PAE). + /// + UINT32 PAE:1; + /// + /// [Bit 7] Machine check exception, CR4.MCE. + /// + UINT32 MCE:1; + /// + /// [Bit 8] CMPXCHG8B instruction. + /// + UINT32 CMPXCHG8B:1; + /// + /// [Bit 9] APIC exists and is enabled. + /// + UINT32 APIC:1; + /// + /// [Bit 10] Reserved. + /// + UINT32 Reserved1:1; + /// + /// [Bit 11] SYSCALL and SYSRET instructions. + /// + UINT32 SYSCALL_SYSRET:1; + /// + /// [Bit 12] Memory-type range registers. + /// + UINT32 MTRR:1; + /// + /// [Bit 13] Page global extension, CR4.PGE. + /// + UINT32 PGE:1; + /// + /// [Bit 14] Machine check architecture, MCG_CAP. + /// + UINT32 MCA:1; + /// + /// [Bit 15] Conditional move instructions, CMOV, FCOMI, FCMOV. + /// + UINT32 CMOV:1; + /// + /// [Bit 16] Page attribute table. + /// + UINT32 PAT:1; + /// + /// [Bit 17] Page-size extensions. + /// + UINT32 PSE36 : 1; + /// + /// [Bit 19:18] Reserved. + /// + UINT32 Reserved2:2; + /// + /// [Bit 20] No-execute page protection. + /// + UINT32 NX:1; + /// + /// [Bit 21] Reserved. + /// + UINT32 Reserved3:1; + /// + /// [Bit 22] AMD Extensions to MMX instructions. + /// + UINT32 MmxExt:1; + /// + /// [Bit 23] MMX instructions. + /// + UINT32 MMX:1; + /// + /// [Bit 24] FXSAVE and FXRSTOR instructions. + /// + UINT32 FFSR:1; + /// + /// [Bit 25] FXSAVE and FXRSTOR instruction optimizations. + /// + UINT32 FFXSR:1; + /// + /// [Bit 26] 1-GByte large page support. + /// + UINT32 Page1GB:1; + /// + /// [Bit 27] RDTSCP intructions. + /// + UINT32 RDTSCP:1; + /// + /// [Bit 28] Reserved. + /// + UINT32 Reserved4:1; + /// + /// [Bit 29] Long Mode. + /// + UINT32 LM:1; + /// + /// [Bit 30] 3DNow! instructions. + /// + UINT32 ThreeDNow:1; + /// + /// [Bit 31] AMD Extensions to 3DNow! instructions. + /// + UINT32 ThreeDNowExt:1; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_AMD_EXTENDED_CPU_SIG_EDX; + + +/** +CPUID Linear Physical Address Size + +@param EAX CPUID_VIR_PHY_ADDRESS_SIZE (0x80000008) + +@retval EAX Linear/Physical Address Size described by the type + CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX. +@retval EBX Linear/Physical Address Size described by the type + CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX. +@retval ECX Linear/Physical Address Size described by the type + CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX. +@retval EDX Reserved. +**/ + +/** + CPUID Linear Physical Address Size EAX for CPUID leaf + #CPUID_VIR_PHY_ADDRESS_SIZE. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] Maximum physical byte address size in bits. + /// + UINT32 PhysicalAddressBits:8; + /// + /// [Bits 15:8] Maximum linear byte address size in bits. + /// + UINT32 LinearAddressBits:8; + /// + /// [Bits 23:16] Maximum guest physical byte address size in bits. + /// + UINT32 GuestPhysAddrSize:8; + /// + /// [Bit 31:24] Reserved. + /// + UINT32 Reserved:8; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX; + +/** + CPUID Linear Physical Address Size EBX for CPUID leaf + #CPUID_VIR_PHY_ADDRESS_SIZE. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 0] Clear Zero Instruction. + /// + UINT32 CLZERO:1; + /// + /// [Bits 1] Instructions retired count support. + /// + UINT32 IRPerf:1; + /// + /// [Bits 2] Restore error pointers for XSave instructions. + /// + UINT32 XSaveErPtr:1; + /// + /// [Bit 31:3] Reserved. + /// + UINT32 Reserved:29; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX; + +/** + CPUID Linear Physical Address Size ECX for CPUID leaf + #CPUID_VIR_PHY_ADDRESS_SIZE. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] Number of threads - 1. + /// + UINT32 NC:8; + /// + /// [Bit 11:8] Reserved. + /// + UINT32 Reserved1:4; + /// + /// [Bits 15:12] APIC ID size. + /// + UINT32 ApicIdCoreIdSize:4; + /// + /// [Bits 17:16] Performance time-stamp counter size. + /// + UINT32 PerfTscSize:2; + /// + /// [Bit 31:18] Reserved. + /// + UINT32 Reserved2:14; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX; + + +/** + CPUID AMD Processor Topology + + @param EAX CPUID_AMD_PROCESSOR_TOPOLOGY (0x8000001E) + + @retval EAX Extended APIC ID described by the type + CPUID_AMD_PROCESSOR_TOPOLOGY_EAX. + @retval EBX Core Indentifiers described by the type + CPUID_AMD_PROCESSOR_TOPOLOGY_EBX. + @retval ECX Node Indentifiers described by the type + CPUID_AMD_PROCESSOR_TOPOLOGY_ECX. + @retval EDX Reserved. +**/ +#define CPUID_AMD_PROCESSOR_TOPOLOGY 0x8000001E + +/** + CPUID AMD Processor Topology EAX for CPUID leaf + #CPUID_AMD_PROCESSOR_TOPOLOGY. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 31:0] Extended APIC Id. + /// + UINT32 ExtendedApicId; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_AMD_PROCESSOR_TOPOLOGY_EAX; + +/** + CPUID AMD Processor Topology EBX for CPUID leaf + #CPUID_AMD_PROCESSOR_TOPOLOGY. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] Core Id. + /// + UINT32 CoreId:8; + /// + /// [Bits 15:8] Threads per core. + /// + UINT32 ThreadsPerCore:8; + /// + /// [Bit 31:16] Reserved. + /// + UINT32 Reserved:16; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_AMD_PROCESSOR_TOPOLOGY_EBX; + +/** + CPUID AMD Processor Topology ECX for CPUID leaf + #CPUID_AMD_PROCESSOR_TOPOLOGY. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] Node Id. + /// + UINT32 NodeId:8; + /// + /// [Bits 10:8] Nodes per processor. + /// + UINT32 NodesPerProcessor:3; + /// + /// [Bit 31:11] Reserved. + /// + UINT32 Reserved:21; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_AMD_PROCESSOR_TOPOLOGY_ECX; + + +/** + CPUID Memory Encryption Information =20 @param EAX CPUID_MEMORY_ENCRYPTION_INFO (0x8000001F) =20 @@ -33,8 +588,8 @@ @retval EBX If memory encryption feature is present then return the page table bit number used to enable memory encryption= support and reducing of physical address space in bits. - @retval ECX Returns number of encrypted guest supported simultaneosuly. - @retval EDX Returns minimum SEV enabled and SEV disbled ASID.. + @retval ECX Returns number of encrypted guest supported simultaneously. + @retval EDX Returns minimum SEV enabled and SEV disabled ASID. =20 Example usage @code @@ -79,7 +634,7 @@ typedef union { UINT32 SevEsBit:1; =20 /// - /// [Bit 4:31] Reserved + /// [Bit 31:4] Reserved /// UINT32 ReservedBits:28; } Bits; @@ -99,17 +654,18 @@ typedef union { /// struct { /// - /// [Bit 0:5] Page table bit number used to enable memory encryption + /// [Bit 5:0] Page table bit number used to enable memory encryption /// UINT32 PtePosBits:6; =20 /// - /// [Bit 6:11] Reduction of system physical address space bits when me= mory encryption is enabled + /// [Bit 11:6] Reduction of system physical address space bits when + /// memory encryption is enabled /// UINT32 ReducedPhysBits:5; =20 /// - /// [Bit 12:31] Reserved + /// [Bit 31:12] Reserved /// UINT32 ReservedBits:21; } Bits; @@ -129,7 +685,7 @@ typedef union { /// struct { /// - /// [Bit 0:31] Number of encrypted guest supported simultaneously + /// [Bit 31:0] Number of encrypted guest supported simultaneously /// UINT32 NumGuests; } Bits; @@ -149,7 +705,7 @@ typedef union { /// struct { /// - /// [Bit 0:31] Minimum SEV enabled, SEV-ES disabled ASID + /// [Bit 31:0] Minimum SEV enabled, SEV-ES disabled ASID /// UINT32 MinAsid; } Bits; --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun Apr 28 09:38:24 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; 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X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jordan Justen , Leo Duran , Jeff Fan , Liming Gao Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Cc: Jordan Justen Cc: Jeff Fan Cc: Liming Gao Cc: Brijesh Singh Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leo Duran --- UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c | 130 +++++++++++++++--= ---- .../BaseXApicX2ApicLib/BaseXApicX2ApicLib.c | 130 +++++++++++++++--= ---- 2 files changed, 184 insertions(+), 76 deletions(-) mode change 100644 =3D> 100755 UefiCpuPkg/Library/BaseXApicLib/BaseXApicLi= b.c diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c b/UefiCpuPkg/Li= brary/BaseXApicLib/BaseXApicLib.c old mode 100644 new mode 100755 index f81bbb2..02dfabc --- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c +++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c @@ -4,6 +4,8 @@ This local APIC library instance supports xAPIC mode only. =20 Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2017, AMD Inc. All rights reserved.
+ This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License which accompanies this distribution. The full text of the license may b= e found at @@ -15,6 +17,7 @@ **/ =20 #include +#include #include #include =20 @@ -966,20 +969,29 @@ GetProcessorLocationByApicId ( OUT UINT32 *Thread OPTIONAL ) { - BOOLEAN TopologyLeafSupported; - UINTN ThreadBits; - UINTN CoreBits; - CPUID_VERSION_INFO_EBX VersionInfoEbx; - CPUID_VERSION_INFO_EDX VersionInfoEdx; - CPUID_CACHE_PARAMS_EAX CacheParamsEax; - CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax; - CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx; - CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx; - UINT32 MaxCpuIdIndex; - UINT32 SubIndex; - UINTN LevelType; - UINT32 MaxLogicProcessorsPerPackage; - UINT32 MaxCoresPerPackage; + CPUID_VERSION_INFO_EBX VersionInfoEbx; + CPUID_VERSION_INFO_EDX VersionInfoEdx; + CPUID_CACHE_PARAMS_EAX CacheParamsEax; + CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax; + CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx; + CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx; + CPUID_AMD_EXTENDED_CPU_SIG_ECX AmdExtendedCpuSigEcx; + CPUID_AMD_PROCESSOR_TOPOLOGY_EBX AmdProcessorTopologyEbx; + CPUID_AMD_PROCESSOR_TOPOLOGY_ECX AmdProcessorTopologyEcx; + CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX AmdVirPhyAddressSizeEcx; + UINT32 MaxStandardCpuIdIndex; + UINT32 MaxExtendedCpuIdIndex; + UINT32 SubIndex; + UINTN LevelType; + UINT32 MaxLogicProcessorsPerPackage; + UINT32 MaxCoresPerPackage; + UINT32 MaxThreadPerPackageMask; + UINT32 ActualThreadPerPackageMask; + UINT32 MaxCoresPerNode; + UINT32 CorePerNodeMask; + UINT32 ApicIdShift; + UINTN ThreadBits; + UINTN CoreBits; =20 // // Check if the processor is capable of supporting more than one logical= processor. @@ -987,10 +999,10 @@ GetProcessorLocationByApicId ( AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32); if (VersionInfoEdx.Bits.HTT =3D=3D 0) { if (Thread !=3D NULL) { - *Thread =3D 0; + *Thread =3D 0; } if (Core !=3D NULL) { - *Core =3D 0; + *Core =3D 0; } if (Package !=3D NULL) { *Package =3D 0; @@ -1002,20 +1014,16 @@ GetProcessorLocationByApicId ( CoreBits =3D 0; =20 // - // Assume three-level mapping of APIC ID: Package:Core:SMT. + // Get the max index of CPUID // - TopologyLeafSupported =3D FALSE; - - // - // Get the max index of basic CPUID - // - AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL); + AsmCpuid(CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, NULL); + AsmCpuid(CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, NULL, NULL, NU= LL); =20 // // If the extended topology enumeration leaf is available, it // is the preferred mechanism for enumerating topology. // - if (MaxCpuIdIndex >=3D CPUID_EXTENDED_TOPOLOGY) { + if (MaxStandardCpuIdIndex >=3D CPUID_EXTENDED_TOPOLOGY) { AsmCpuidEx( CPUID_EXTENDED_TOPOLOGY, 0, @@ -1030,8 +1038,6 @@ GetProcessorLocationByApicId ( // supported on that processor. // if (ExtendedTopologyEbx.Uint32 !=3D 0) { - TopologyLeafSupported =3D TRUE; - // // Sub-leaf index 0 (ECX=3D 0 as input) provides enumeration paramet= ers to extract // the SMT sub-field of x2APIC ID. @@ -1061,31 +1067,79 @@ GetProcessorLocationByApicId ( } SubIndex++; } while (LevelType !=3D CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID); + goto GetLocation; } } =20 - if (!TopologyLeafSupported) { - AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL); - MaxLogicProcessorsPerPackage =3D VersionInfoEbx.Bits.MaximumAddressabl= eIdsForLogicalProcessors; - if (MaxCpuIdIndex >=3D CPUID_CACHE_PARAMS) { - AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL= , NULL); + AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL); + MaxLogicProcessorsPerPackage =3D VersionInfoEbx.Bits.MaximumAddressableI= dsForLogicalProcessors; + + if (MaxStandardCpuIdIndex >=3D CPUID_CACHE_PARAMS) { + AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, = NULL); + if (CacheParamsEax.Uint32 !=3D 0) { MaxCoresPerPackage =3D CacheParamsEax.Bits.MaximumAddressableIdsForL= ogicalProcessors + 1; + goto GetBits; } - else { + } + + if (MaxExtendedCpuIdIndex >=3D CPUID_AMD_PROCESSOR_TOPOLOGY) { + AsmCpuid(CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx.Uin= t32, NULL); + if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions !=3D 0) { + AsmCpuid(CPUID_AMD_PROCESSOR_TOPOLOGY, NULL, &AmdProcessorTopologyEb= x.Uint32, + &AmdProcessorTopologyEcx.Uint32, NULL); + + MaxCoresPerPackage =3D MaxLogicProcessorsPerPackage / (AmdProcessorT= opologyEbx.Bits.ThreadsPerCore + 1); + // - // Must be a single-core processor. + // Account for actual thread count (e.g., SMT disabled) // - MaxCoresPerPackage =3D 1; + AsmCpuid(CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL, &AmdVirPhyAddressSi= zeEcx.Uint32, NULL); + MaxThreadPerPackageMask =3D 1 << AmdVirPhyAddressSizeEcx.Bits.ApicId= CoreIdSize; + ActualThreadPerPackageMask =3D 1; + while (ActualThreadPerPackageMask < MaxLogicProcessorsPerPackage) { + ActualThreadPerPackageMask <<=3D 1; + } + + if (ActualThreadPerPackageMask < MaxThreadPerPackageMask) { + MaxCoresPerNode =3D MaxCoresPerPackage / (AmdProcessorTopologyEcx.= Bits.NodesPerProcessor + 1); + + CorePerNodeMask =3D 1; + while (CorePerNodeMask < MaxCoresPerNode) { + CorePerNodeMask <<=3D 1; + } + CorePerNodeMask -=3D 1; + + ApicIdShift =3D 0; + do { + ApicIdShift +=3D 1; + ActualThreadPerPackageMask <<=3D 1; + } while (ActualThreadPerPackageMask < MaxThreadPerPackageMask); + + // + // Adjust APIC Id to report concatenation of Package|Core|Thread. + // + InitialApicId =3D ((InitialApicId & ~CorePerNodeMask) >> ApicIdShi= ft) | (InitialApicId & CorePerNodeMask); + } + + goto GetBits; } + } + + // + // Must be a single-core processor. + // + MaxCoresPerPackage =3D 1; =20 - ThreadBits =3D (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / Max= CoresPerPackage - 1) + 1); - CoreBits =3D (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); } +GetBits: + ThreadBits =3D (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCo= resPerPackage - 1) + 1); + CoreBits =3D (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); =20 +GetLocation: if (Thread !=3D NULL) { - *Thread =3D InitialApicId & ((1 << ThreadBits) - 1); + *Thread =3D InitialApicId & ((1 << ThreadBits) - 1); } if (Core !=3D NULL) { - *Core =3D (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1); + *Core =3D (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1); } if (Package !=3D NULL) { *Package =3D (InitialApicId >> (ThreadBits + CoreBits)); diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c b/U= efiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c index e690d2a..726e1e0 100644 --- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c +++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c @@ -5,6 +5,8 @@ which have xAPIC and x2APIC modes. =20 Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2017, AMD Inc. All rights reserved.
+ This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License which accompanies this distribution. The full text of the license may b= e found at @@ -16,6 +18,7 @@ **/ =20 #include +#include #include #include =20 @@ -1061,20 +1064,29 @@ GetProcessorLocationByApicId ( OUT UINT32 *Thread OPTIONAL ) { - BOOLEAN TopologyLeafSupported; - UINTN ThreadBits; - UINTN CoreBits; - CPUID_VERSION_INFO_EBX VersionInfoEbx; - CPUID_VERSION_INFO_EDX VersionInfoEdx; - CPUID_CACHE_PARAMS_EAX CacheParamsEax; - CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax; - CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx; - CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx; - UINT32 MaxCpuIdIndex; - UINT32 SubIndex; - UINTN LevelType; - UINT32 MaxLogicProcessorsPerPackage; - UINT32 MaxCoresPerPackage; + CPUID_VERSION_INFO_EBX VersionInfoEbx; + CPUID_VERSION_INFO_EDX VersionInfoEdx; + CPUID_CACHE_PARAMS_EAX CacheParamsEax; + CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax; + CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx; + CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx; + CPUID_AMD_EXTENDED_CPU_SIG_ECX AmdExtendedCpuSigEcx; + CPUID_AMD_PROCESSOR_TOPOLOGY_EBX AmdProcessorTopologyEbx; + CPUID_AMD_PROCESSOR_TOPOLOGY_ECX AmdProcessorTopologyEcx; + CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX AmdVirPhyAddressSizeEcx; + UINT32 MaxStandardCpuIdIndex; + UINT32 MaxExtendedCpuIdIndex; + UINT32 SubIndex; + UINTN LevelType; + UINT32 MaxLogicProcessorsPerPackage; + UINT32 MaxCoresPerPackage; + UINT32 MaxThreadPerPackageMask; + UINT32 ActualThreadPerPackageMask; + UINT32 MaxCoresPerNode; + UINT32 CorePerNodeMask; + UINT32 ApicIdShift; + UINTN ThreadBits; + UINTN CoreBits; =20 // // Check if the processor is capable of supporting more than one logical= processor. @@ -1082,10 +1094,10 @@ GetProcessorLocationByApicId ( AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32); if (VersionInfoEdx.Bits.HTT =3D=3D 0) { if (Thread !=3D NULL) { - *Thread =3D 0; + *Thread =3D 0; } if (Core !=3D NULL) { - *Core =3D 0; + *Core =3D 0; } if (Package !=3D NULL) { *Package =3D 0; @@ -1097,20 +1109,16 @@ GetProcessorLocationByApicId ( CoreBits =3D 0; =20 // - // Assume three-level mapping of APIC ID: Package:Core:SMT. + // Get the max index of CPUID // - TopologyLeafSupported =3D FALSE; - - // - // Get the max index of basic CPUID - // - AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL); + AsmCpuid(CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, NULL); + AsmCpuid(CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, NULL, NULL, NU= LL); =20 // // If the extended topology enumeration leaf is available, it // is the preferred mechanism for enumerating topology. // - if (MaxCpuIdIndex >=3D CPUID_EXTENDED_TOPOLOGY) { + if (MaxStandardCpuIdIndex >=3D CPUID_EXTENDED_TOPOLOGY) { AsmCpuidEx( CPUID_EXTENDED_TOPOLOGY, 0, @@ -1125,8 +1133,6 @@ GetProcessorLocationByApicId ( // supported on that processor. // if (ExtendedTopologyEbx.Uint32 !=3D 0) { - TopologyLeafSupported =3D TRUE; - // // Sub-leaf index 0 (ECX=3D 0 as input) provides enumeration paramet= ers to extract // the SMT sub-field of x2APIC ID. @@ -1156,31 +1162,79 @@ GetProcessorLocationByApicId ( } SubIndex++; } while (LevelType !=3D CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID); + goto GetLocation; } } =20 - if (!TopologyLeafSupported) { - AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL); - MaxLogicProcessorsPerPackage =3D VersionInfoEbx.Bits.MaximumAddressabl= eIdsForLogicalProcessors; - if (MaxCpuIdIndex >=3D CPUID_CACHE_PARAMS) { - AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL= , NULL); + AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL); + MaxLogicProcessorsPerPackage =3D VersionInfoEbx.Bits.MaximumAddressableI= dsForLogicalProcessors; + + if (MaxStandardCpuIdIndex >=3D CPUID_CACHE_PARAMS) { + AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, = NULL); + if (CacheParamsEax.Uint32 !=3D 0) { MaxCoresPerPackage =3D CacheParamsEax.Bits.MaximumAddressableIdsForL= ogicalProcessors + 1; + goto GetBits; } - else { + } + + if (MaxExtendedCpuIdIndex >=3D CPUID_AMD_PROCESSOR_TOPOLOGY) { + AsmCpuid(CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx.Uin= t32, NULL); + if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions !=3D 0) { + AsmCpuid(CPUID_AMD_PROCESSOR_TOPOLOGY, NULL, &AmdProcessorTopologyEb= x.Uint32, + &AmdProcessorTopologyEcx.Uint32, NULL); + + MaxCoresPerPackage =3D MaxLogicProcessorsPerPackage / (AmdProcessorT= opologyEbx.Bits.ThreadsPerCore + 1); + // - // Must be a single-core processor. + // Account for actual thread count (e.g., SMT disabled) // - MaxCoresPerPackage =3D 1; + AsmCpuid(CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL, &AmdVirPhyAddressSi= zeEcx.Uint32, NULL); + MaxThreadPerPackageMask =3D 1 << AmdVirPhyAddressSizeEcx.Bits.ApicId= CoreIdSize; + ActualThreadPerPackageMask =3D 1; + while (ActualThreadPerPackageMask < MaxLogicProcessorsPerPackage) { + ActualThreadPerPackageMask <<=3D 1; + } + + if (ActualThreadPerPackageMask < MaxThreadPerPackageMask) { + MaxCoresPerNode =3D MaxCoresPerPackage / (AmdProcessorTopologyEcx.= Bits.NodesPerProcessor + 1); + + CorePerNodeMask =3D 1; + while (CorePerNodeMask < MaxCoresPerNode) { + CorePerNodeMask <<=3D 1; + } + CorePerNodeMask -=3D 1; + + ApicIdShift =3D 0; + do { + ApicIdShift +=3D 1; + ActualThreadPerPackageMask <<=3D 1; + } while (ActualThreadPerPackageMask < MaxThreadPerPackageMask); + + // + // Adjust APIC Id to report concatenation of Package|Core|Thread. + // + InitialApicId =3D ((InitialApicId & ~CorePerNodeMask) >> ApicIdShi= ft) | (InitialApicId & CorePerNodeMask); + } + + goto GetBits; } + } + + // + // Must be a single-core processor. + // + MaxCoresPerPackage =3D 1; =20 - ThreadBits =3D (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / Max= CoresPerPackage - 1) + 1); - CoreBits =3D (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); } +GetBits: + ThreadBits =3D (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCo= resPerPackage - 1) + 1); + CoreBits =3D (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); =20 +GetLocation: if (Thread !=3D NULL) { - *Thread =3D InitialApicId & ((1 << ThreadBits) - 1); + *Thread =3D InitialApicId & ((1 << ThreadBits) - 1); } if (Core !=3D NULL) { - *Core =3D (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1); + *Core =3D (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1); } if (Package !=3D NULL) { *Package =3D (InitialApicId >> (ThreadBits + CoreBits)); --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel