From nobody Sat Apr 27 10:54:59 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zoho.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1496659863356685.8104833007495; Mon, 5 Jun 2017 03:51:03 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 3AEB421C93EED; Mon, 5 Jun 2017 03:49:50 -0700 (PDT) Received: from mx-sanjose5.cadence.com (keymaster.Cadence.COM [158.140.2.26]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3168821AE3CA8 for ; Mon, 5 Jun 2017 03:49:48 -0700 (PDT) Received: from maileu3.global.cadence.com (maileu3.Cadence.COM [10.160.88.99]) by mx-sanjose5.cadence.com (8.13.8+Sun/8.14.4) with ESMTP id v55Aonke028201; Mon, 5 Jun 2017 03:50:50 -0700 (PDT) Received: from maileu3.global.cadence.com (10.160.88.99) by maileu3.global.cadence.com (10.160.88.99) with Microsoft SMTP Server (TLS) id 15.0.1044.25; Mon, 5 Jun 2017 12:50:44 +0200 Received: from lvloginb.cadence.com (10.165.177.11) by maileu3.global.cadence.com (10.160.88.99) with Microsoft SMTP Server (TLS) id 15.0.1044.25 via Frontend Transport; Mon, 5 Jun 2017 12:50:43 +0200 Received: from lvloginb.cadence.com (localhost [127.0.0.1]) by lvloginb.cadence.com (8.14.4/8.14.4) with ESMTP id v55Aoh5l000557; Mon, 5 Jun 2017 11:50:43 +0100 Received: (from stelford@localhost) by lvloginb.cadence.com (8.14.4/8.14.4/Submit) id v55AohaU000556; Mon, 5 Jun 2017 11:50:43 +0100 X-Original-To: edk2-devel@ml01.01.org X-CrossPremisesHeadersFilteredBySendConnector: maileu3.global.cadence.com From: Scott Telford To: , , , , , Date: Mon, 5 Jun 2017 11:50:23 +0100 Message-ID: <1496659828-28702-2-git-send-email-stelford@cadence.com> X-Mailer: git-send-email 2.2.2 In-Reply-To: <1496659828-28702-1-git-send-email-stelford@cadence.com> References: <1496659828-28702-1-git-send-email-stelford@cadence.com> MIME-Version: 1.0 X-OrganizationHeadersPreserved: maileu3.global.cadence.com Subject: [edk2] [staging/cadence-aarch64 PATCH v2 1/6] CadencePkg: Add libraries for Cadence CSP platform. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Add libraries (CadenceCspLib, CadenceCspSecLib, CadenceCspResetSystemLib) to support the Cadence Configurable System Platform (CSP) configured with a single ARM Cortex-A53, GIC-500, Cadence UART and Cadence PCIe Root Complex. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Scott Telford --- CadencePkg/Include/Library/CspSysReg.h | 37 ++++++ .../CadenceCspLib/AArch64/ArmPlatformHelper.S | 62 +++++++++ CadencePkg/Library/CadenceCspLib/CadenceCspLib.c | 135 +++++++++++++++++= ++ CadencePkg/Library/CadenceCspLib/CadenceCspLib.inf | 76 +++++++++++ .../Library/CadenceCspLib/CadenceCspLibMem.c | 145 +++++++++++++++++= ++++ .../Library/CadenceCspLib/CadenceCspLibSec.inf | 52 ++++++++ .../CadenceCspResetSystemLib.c | 83 ++++++++++++ .../CadenceCspResetSystemLib.inf | 40 ++++++ .../Library/CadenceCspSecLib/AArch64/CspBoot.S | 63 +++++++++ .../Library/CadenceCspSecLib/AArch64/GicV3.S | 70 ++++++++++ .../Library/CadenceCspSecLib/CadenceCspSecLib.inf | 44 +++++++ CadencePkg/Library/CadenceCspSecLib/CspSec.c | 79 +++++++++++ 12 files changed, 886 insertions(+) create mode 100644 CadencePkg/Include/Library/CspSysReg.h create mode 100644 CadencePkg/Library/CadenceCspLib/AArch64/ArmPlatformHel= per.S create mode 100644 CadencePkg/Library/CadenceCspLib/CadenceCspLib.c create mode 100644 CadencePkg/Library/CadenceCspLib/CadenceCspLib.inf create mode 100644 CadencePkg/Library/CadenceCspLib/CadenceCspLibMem.c create mode 100644 CadencePkg/Library/CadenceCspLib/CadenceCspLibSec.inf create mode 100644 CadencePkg/Library/CadenceCspResetSystemLib/CadenceCspR= esetSystemLib.c create mode 100644 CadencePkg/Library/CadenceCspResetSystemLib/CadenceCspR= esetSystemLib.inf create mode 100644 CadencePkg/Library/CadenceCspSecLib/AArch64/CspBoot.S create mode 100644 CadencePkg/Library/CadenceCspSecLib/AArch64/GicV3.S create mode 100644 CadencePkg/Library/CadenceCspSecLib/CadenceCspSecLib.inf create mode 100644 CadencePkg/Library/CadenceCspSecLib/CspSec.c diff --git a/CadencePkg/Include/Library/CspSysReg.h b/CadencePkg/Include/Li= brary/CspSysReg.h new file mode 100644 index 0000000..4d3ac925 --- /dev/null +++ b/CadencePkg/Include/Library/CspSysReg.h @@ -0,0 +1,37 @@ +/** @file +* Cadence CSP system register offsets. +* Copyright (c) 2017, Cadence Design Systems. All rights reserved. +* +* This program and the accompanying materials are licensed and made +* available under the terms and conditions of the BSD License which +* accompanies this distribution. The full text of the license may be +* found at http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#ifndef __CSP_SYS_REG_H__ +#define __CSP_SYS_REG_H__ + +// Cadence CSP system register offsets +#define CSP_SYSREG_VERSION 0x00 +#define CSP_SYSREG_CPU_FREQ 0x04 +#define CSP_SYSREG_STATUS 0x08 +#define CSP_SYSREG_RUN_STALL 0x0C +#define CSP_SYSREG_SW_RESET 0x10 +#define CSP_SYSREG_CORE1_RESET 0x14 +#define CSP_SYSREG_SCRATCH_REG_0 0x18 +#define CSP_SYSREG_PROC_INTERRUPT 0x1C +#define CSP_SYSREG_SCRATCH_REG_1 0x20 +#define CSP_SYSREG_SCRATCH_REG_2 0x24 +#define CSP_SYSREG_SCRATCH_REG_3 0x28 +#define CSP_SYSREG_SCRATCH_REG_4 0x2C +#define CSP_SYSREG_SCRATCH_REG_5 0x30 +#define CSP_SYSREG_SCRATCH_REG_6 0x34 +#define CSP_SYSREG_SET_INTERRUPT 0x38 +#define CSP_SYSREG_CLR_INTERRUPT 0x3C +#define CSP_SYSREG_DIP_SWITCHES 0x40 + +#endif diff --git a/CadencePkg/Library/CadenceCspLib/AArch64/ArmPlatformHelper.S b= /CadencePkg/Library/CadenceCspLib/AArch64/ArmPlatformHelper.S new file mode 100644 index 0000000..56af563 --- /dev/null +++ b/CadencePkg/Library/CadenceCspLib/AArch64/ArmPlatformHelper.S @@ -0,0 +1,62 @@ +// +// Copyright (c) 2012-2013, ARM Limited. All rights reserved. +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the = BSD License +// which accompanies this distribution. The full text of the license may= be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR I= MPLIED. +// +// + +#include +#include + +.text +.align 2 + +GCC_ASM_EXPORT(ArmPlatformPeiBootAction) +GCC_ASM_EXPORT(ArmPlatformGetCorePosition) +GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId) +GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore) + +GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCore) +GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask) + +ASM_PFX(ArmPlatformPeiBootAction): + ret + +//UINTN +//ArmPlatformGetCorePosition ( +// IN UINTN MpId +// ); +// With this function: CorePos =3D (ClusterId * 4) + CoreId +ASM_PFX(ArmPlatformGetCorePosition): + and x1, x0, #ARM_CORE_MASK + and x0, x0, #ARM_CLUSTER_MASK + add x0, x1, x0, LSR #6 + ret + +//UINTN +//ArmPlatformGetPrimaryCoreMpId ( +// VOID +// ); +ASM_PFX(ArmPlatformGetPrimaryCoreMpId): + MOV32 (w0, FixedPcdGet32(PcdArmPrimaryCore)) + ret + +//UINTN +//ArmPlatformIsPrimaryCore ( +// IN UINTN MpId +// ); +ASM_PFX(ArmPlatformIsPrimaryCore): + MOV32 (w1, FixedPcdGet32(PcdArmPrimaryCoreMask)) + and x0, x0, x1 + MOV32 (w1, FixedPcdGet32(PcdArmPrimaryCore)) + cmp w0, w1 + mov x0, #1 + mov x1, #0 + csel x0, x0, x1, eq + ret diff --git a/CadencePkg/Library/CadenceCspLib/CadenceCspLib.c b/CadencePkg/= Library/CadenceCspLib/CadenceCspLib.c new file mode 100644 index 0000000..8a985ec --- /dev/null +++ b/CadencePkg/Library/CadenceCspLib/CadenceCspLib.c @@ -0,0 +1,135 @@ +/** @file +* +* Copyright (c) 2011-2012, ARM Limited. All rights reserved. +* Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the B= SD License +* which accompanies this distribution. The full text of the license may = be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#include +#include +#include +#include +#include + +#include + + +ARM_CORE_INFO mArmPlatformNullMpCoreInfoTable[] =3D { + { + // Cluster 0, Core 0 + 0x0, 0x0, + + // MP Core MailBox Set/Get/Clear Addresses and Clear Value + (EFI_PHYSICAL_ADDRESS)0, + (EFI_PHYSICAL_ADDRESS)0, + (EFI_PHYSICAL_ADDRESS)0, + (UINT64)0xFFFFFFFF + } +}; + + + +/** + Return the current Boot Mode + + This function returns the boot reason on the platform + +**/ +EFI_BOOT_MODE +ArmPlatformGetBootMode ( + VOID + ) +{ + return BOOT_WITH_FULL_CONFIGURATION; +} + +/** + Initialize controllers that must setup in the normal world + + This function is called by the ArmPlatformPkg/PrePi or ArmPlatformPkg/Pl= atformPei + in the PEI phase. + +**/ +RETURN_STATUS +ArmPlatformInitialize ( + IN UINTN MpId + ) +{ + UINTN CspScratchReg2; + + if (!ArmPlatformIsPrimaryCore (MpId)) { + return RETURN_SUCCESS; + } + + // CSP System Register initialisation + CspScratchReg2 =3D PcdGet64 (PcdCspSysRegBase) + CSP_SYSREG_SCRATCH_REG_= 2; + MmioWrite32 ((UINTN)CspScratchReg2, 0x1); + MmioWrite32 ((UINTN)CspScratchReg2, 0x3); + + return RETURN_SUCCESS; +} + +/** + Initialize the system (or sometimes called permanent) memory + + This memory is generally represented by the DRAM. + +**/ +VOID +ArmPlatformInitializeSystemMemory ( + VOID + ) +{ + //TODO: Implement me +} + +EFI_STATUS +PrePeiCoreGetMpCoreInfo ( + OUT UINTN *CoreCount, + OUT ARM_CORE_INFO **ArmCoreTable + ) +{ + if (ArmIsMpCore()) { + *CoreCount =3D sizeof(mArmPlatformNullMpCoreInfoTable) / sizeof(ARM= _CORE_INFO); + *ArmCoreTable =3D mArmPlatformNullMpCoreInfoTable; + return EFI_SUCCESS; + } else { + return EFI_UNSUPPORTED; + } +} + +// Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is un= defined in the contect of PrePeiCore +EFI_GUID mArmMpCoreInfoPpiGuid =3D ARM_MP_CORE_INFO_PPI_GUID; +ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi =3D { PrePeiCoreGetMpCoreInfo }; + +EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] =3D { + { + EFI_PEI_PPI_DESCRIPTOR_PPI, + &mArmMpCoreInfoPpiGuid, + &mMpCoreInfoPpi + } +}; + +VOID +ArmPlatformGetPlatformPpiList ( + OUT UINTN *PpiListSize, + OUT EFI_PEI_PPI_DESCRIPTOR **PpiList + ) +{ + if (ArmIsMpCore()) { + *PpiListSize =3D sizeof(gPlatformPpiTable); + *PpiList =3D gPlatformPpiTable; + } else { + *PpiListSize =3D 0; + *PpiList =3D NULL; + } +} + diff --git a/CadencePkg/Library/CadenceCspLib/CadenceCspLib.inf b/CadencePk= g/Library/CadenceCspLib/CadenceCspLib.inf new file mode 100644 index 0000000..b2c6440 --- /dev/null +++ b/CadencePkg/Library/CadenceCspLib/CadenceCspLib.inf @@ -0,0 +1,76 @@ +#/* @file +# Copyright (c) 2011-2012, ARM Limited. All rights reserved. +# Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +#*/ + +[Defines] + INF_VERSION =3D 1.25 + BASE_NAME =3D CadenceCspLib + FILE_GUID =3D 13392a39-0fd2-4ec1-8541-1a7b5f0005d9 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D ArmPlatformLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + CadencePkg/CadenceCspPkg.dec + +[LibraryClasses] + ArmLib + MemoryAllocationLib + SerialPortLib + DebugLib + HobLib + +[Sources.common] + CadenceCspLib.c + CadenceCspLibMem.c + +[Sources.AArch64] + AArch64/ArmPlatformHelper.S + +[FeaturePcd] + gEmbeddedTokenSpaceGuid.PcdCacheEnable + +[FixedPcd] + gArmTokenSpaceGuid.PcdSystemMemoryBase + gArmTokenSpaceGuid.PcdSystemMemorySize + + gArmTokenSpaceGuid.PcdSecureFdBaseAddress + gArmTokenSpaceGuid.PcdSecureFdSize + gArmTokenSpaceGuid.PcdFdBaseAddress + gArmTokenSpaceGuid.PcdFdSize + + gArmTokenSpaceGuid.PcdArmPrimaryCoreMask + gArmTokenSpaceGuid.PcdArmPrimaryCore + + gArmTokenSpaceGuid.PcdGicDistributorBase + gArmTokenSpaceGuid.PcdGicRedistributorsBase + + gCadenceCspTokenSpaceGuid.PcdCspSysRegBase + gCadenceCspTokenSpaceGuid.PcdCspSysRegSize + + gCadenceCspTokenSpaceGuid.PcdCspSerialBase + gCadenceCspTokenSpaceGuid.PcdCspSerialSize + + gCadenceCspTokenSpaceGuid.PcdPcie1RootPortBaseAddress + gCadenceCspTokenSpaceGuid.PcdPcieRootPortBaseAddress + gCadenceCspTokenSpaceGuid.PcdPciConfigurationSpaceBaseAddress + gCadenceCspTokenSpaceGuid.PcdPciConfigurationSpaceSize + gArmTokenSpaceGuid.PcdPciMmio32Base + gArmTokenSpaceGuid.PcdPciMmio32Size + gArmTokenSpaceGuid.PcdPciMmio64Base + gArmTokenSpaceGuid.PcdPciMmio64Size diff --git a/CadencePkg/Library/CadenceCspLib/CadenceCspLibMem.c b/CadenceP= kg/Library/CadenceCspLib/CadenceCspLibMem.c new file mode 100644 index 0000000..12cd6a5 --- /dev/null +++ b/CadencePkg/Library/CadenceCspLib/CadenceCspLibMem.c @@ -0,0 +1,145 @@ +/** @file +* +* Copyright (c) 2011, ARM Limited. All rights reserved. +* Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the B= SD License +* which accompanies this distribution. The full text of the license may = be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#include +#include +#include +#include +#include + +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 14 + +// DDR attributes +#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_= BACK +#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACH= ED_UNBUFFERED + +/** + Return the Virtual Memory Map of your platform + + This Virtual Memory Map is used by MemoryInitPei Module to initialize th= e MMU on your platform. + + @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR = describing a Physical-to- + Virtual Memory mapping. This array mus= t be ended by a zero-filled + entry + +**/ +VOID +ArmPlatformGetVirtualMemoryMap ( + IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap + ) +{ + ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes; + UINTN Index =3D 0; + ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; + + ASSERT(VirtualMemoryMap !=3D NULL); + + VirtualMemoryTable =3D (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_= SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MA= P_DESCRIPTORS)); + if (VirtualMemoryTable =3D=3D NULL) { + return; + } + + CacheAttributes =3D (FeaturePcdGet(PcdCacheEnable)) + ? DDR_ATTRIBUTES_CACHED + : DDR_ATTRIBUTES_UNCACHED; + + // SRAM + VirtualMemoryTable[Index].PhysicalBase =3D PcdGet64(PcdSystemMemoryBase); + VirtualMemoryTable[Index].VirtualBase =3D PcdGet64(PcdSystemMemoryBase); + VirtualMemoryTable[Index].Length =3D PcdGet64(PcdSystemMemorySize); + VirtualMemoryTable[Index].Attributes =3D CacheAttributes; + + // CDNS UART + VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet64(PcdCspSerialBase); + VirtualMemoryTable[Index].VirtualBase =3D PcdGet64(PcdCspSerialBase); + VirtualMemoryTable[Index].Length =3D PcdGet32(PcdCspSerialSize); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + // UEFI ROM (Secure) + VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet64(PcdSecureFdBaseAdd= ress); + VirtualMemoryTable[Index].VirtualBase =3D PcdGet64(PcdSecureFdBaseAddre= ss); + VirtualMemoryTable[Index].Length =3D PcdGet32(PcdSecureFdSize); + VirtualMemoryTable[Index].Attributes =3D CacheAttributes; + + // UEFI ROM (Normal) + VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet64(PcdFdBaseAddress); + VirtualMemoryTable[Index].VirtualBase =3D PcdGet64(PcdFdBaseAddress); + VirtualMemoryTable[Index].Length =3D PcdGet32(PcdFdSize); + VirtualMemoryTable[Index].Attributes =3D CacheAttributes; + + // CSP SysRegs + VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet64(PcdCspSysRegBase); + VirtualMemoryTable[Index].VirtualBase =3D PcdGet64(PcdCspSysRegBase); + VirtualMemoryTable[Index].Length =3D PcdGet32(PcdCspSysRegSize); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + // GIC Distributor + VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet64(PcdGicDistributorB= ase); + VirtualMemoryTable[Index].VirtualBase =3D PcdGet64(PcdGicDistributorBas= e); + VirtualMemoryTable[Index].Length =3D 0x10000; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + // GIC Redistributor + VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet64(PcdGicRedistributo= rsBase); + VirtualMemoryTable[Index].VirtualBase =3D PcdGet64(PcdGicRedistributors= Base); + VirtualMemoryTable[Index].Length =3D 0x20000; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + // PCIe RP + VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet64(PcdPcieRootPortBas= eAddress); + VirtualMemoryTable[Index].VirtualBase =3D PcdGet64(PcdPcieRootPortBaseA= ddress); + VirtualMemoryTable[Index].Length =3D 0x00800000; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + // + // PCI Configuration Space (AXI region) + // + VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet64 (PcdPciConfigurat= ionSpaceBaseAddress); + VirtualMemoryTable[Index].VirtualBase =3D PcdGet64 (PcdPciConfigurat= ionSpaceBaseAddress); + VirtualMemoryTable[Index].Length =3D PcdGet64 (PcdPciConfigurat= ionSpaceSize); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; + + // + // PCI Memory Space + // + VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet32 (PcdPciMmio32Base= ); + VirtualMemoryTable[Index].VirtualBase =3D PcdGet32 (PcdPciMmio32Base= ); + VirtualMemoryTable[Index].Length =3D PcdGet32 (PcdPciMmio32Size= ); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; + + // + // 64-bit PCI Memory Space + // + VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet64 (PcdPciMmio64Base= ); + VirtualMemoryTable[Index].VirtualBase =3D PcdGet64 (PcdPciMmio64Base= ); + VirtualMemoryTable[Index].Length =3D PcdGet64 (PcdPciMmio64Size= ); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; + + // PCIe EP + VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet64(PcdPcie1RootPortBa= seAddress); + VirtualMemoryTable[Index].VirtualBase =3D PcdGet64(PcdPcie1RootPortBase= Address); + VirtualMemoryTable[Index].Length =3D 0x00800000; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + // End of Table + VirtualMemoryTable[++Index].PhysicalBase =3D 0; + VirtualMemoryTable[Index].VirtualBase =3D 0; + VirtualMemoryTable[Index].Length =3D 0; + VirtualMemoryTable[Index].Attributes =3D (ARM_MEMORY_REGION_ATTRIBUTES= )0; + + ASSERT(Index < MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS); + + *VirtualMemoryMap =3D VirtualMemoryTable; +} diff --git a/CadencePkg/Library/CadenceCspLib/CadenceCspLibSec.inf b/Cadenc= ePkg/Library/CadenceCspLib/CadenceCspLibSec.inf new file mode 100644 index 0000000..dd6c5c3 --- /dev/null +++ b/CadencePkg/Library/CadenceCspLib/CadenceCspLibSec.inf @@ -0,0 +1,52 @@ +#/* @file +# Copyright (c) 2011-2012, ARM Limited. All rights reserved. +# Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +#*/ + +[Defines] + INF_VERSION =3D 1.25 + BASE_NAME =3D CadenceCspLibSec + FILE_GUID =3D 3008d873-1400-48d8-abda-6ac9cce97246 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D ArmPlatformLib + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + CadencePkg/CadenceCspPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses] + ArmLib + DebugLib + +[Sources.common] + CadenceCspLib.c + +[Sources.AARCH64] + AArch64/ArmPlatformHelper.S + +[FixedPcd] + gArmTokenSpaceGuid.PcdSystemMemoryBase + gArmTokenSpaceGuid.PcdSystemMemorySize + gArmTokenSpaceGuid.PcdFvBaseAddress + + gArmTokenSpaceGuid.PcdArmPrimaryCoreMask + gArmTokenSpaceGuid.PcdArmPrimaryCore + + gCadenceCspTokenSpaceGuid.PcdCspSysRegBase + gCadenceCspTokenSpaceGuid.PcdCspSysRegSize + +[Ppis] + gArmMpCoreInfoPpiGuid diff --git a/CadencePkg/Library/CadenceCspResetSystemLib/CadenceCspResetSys= temLib.c b/CadencePkg/Library/CadenceCspResetSystemLib/CadenceCspResetSyste= mLib.c new file mode 100644 index 0000000..144fa9f --- /dev/null +++ b/CadencePkg/Library/CadenceCspResetSystemLib/CadenceCspResetSystemLib.c @@ -0,0 +1,83 @@ +/** @file + Library to support ResetSystem Runtime call. + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+ Copyright (c) 2013, ARM Ltd. All rights reserved.
+ Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved. + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include + +#include +#include +#include +#include +#include +#include + +/** + Resets the entire platform. + + @param ResetType The type of reset to perform. + @param ResetStatus The status code for the reset. + @param DataSize The size, in bytes, of WatchdogData. + @param ResetData For a ResetType of EfiResetCold, EfiResetW= arm, or + EfiResetShutdown the data buffer starts wi= th a Null-terminated + Unicode string, optionally followed by add= itional binary data. + +**/ +EFI_STATUS +EFIAPI +LibResetSystem ( + IN EFI_RESET_TYPE ResetType, + IN EFI_STATUS ResetStatus, + IN UINTN DataSize, + IN CHAR16 *ResetData OPTIONAL + ) +{ + switch (ResetType) { + case EfiResetPlatformSpecific: + // Map the platform specific reset as reboot + case EfiResetWarm: + // Map a warm reset into a cold reset + case EfiResetCold: + MmioWrite16((PcdGet64(PcdCspSysRegBase) + CSP_SYSREG_SW_RESET), 0xDEAD= ); + break; + case EfiResetShutdown: + // XXX TODO + break; + default: + return EFI_INVALID_PARAMETER; + } + + ASSERT(FALSE); + return EFI_UNSUPPORTED; +} + +/** + Initialize any infrastructure required for LibResetSystem () to function. + + @param ImageHandle The firmware allocated handle for the EFI image. + @param SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS. + +**/ +EFI_STATUS +EFIAPI +LibInitializeResetSystem ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + return EFI_SUCCESS; +} diff --git a/CadencePkg/Library/CadenceCspResetSystemLib/CadenceCspResetSys= temLib.inf b/CadencePkg/Library/CadenceCspResetSystemLib/CadenceCspResetSys= temLib.inf new file mode 100644 index 0000000..66491ee --- /dev/null +++ b/CadencePkg/Library/CadenceCspResetSystemLib/CadenceCspResetSystemLib.= inf @@ -0,0 +1,40 @@ +#/** @file +# Library to support ResetSystem Runtime call. +# +# Copyright (c) 2006, Intel Corporation. All rights reserved.
+# Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may b= e found at +# http://opensource.org/licenses/bsd-license.php +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +# +#**/ + +[Defines] + INF_VERSION =3D 1.25 + BASE_NAME =3D CadenceCspResetSystemLib + FILE_GUID =3D 4b1bc734-7534-4baa-b33f-7f5caa743996 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D EfiResetSystemLib + + +[Sources.common] + CadenceCspResetSystemLib.c + +[Packages] + CadencePkg/CadenceCspPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses] + IoLib + DebugLib + PcdLib + +[FixedPcd] + gCadenceCspTokenSpaceGuid.PcdCspSysRegBase diff --git a/CadencePkg/Library/CadenceCspSecLib/AArch64/CspBoot.S b/Cadenc= ePkg/Library/CadenceCspSecLib/AArch64/CspBoot.S new file mode 100644 index 0000000..ae0d66b --- /dev/null +++ b/CadencePkg/Library/CadenceCspSecLib/AArch64/CspBoot.S @@ -0,0 +1,63 @@ +// +// Copyright (c) 2011 - 2014, ARM Limited. All rights reserved. +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the = BSD License +// which accompanies this distribution. The full text of the license may= be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR I= MPLIED. +// +// + +#include +#include +#include +#include + +.text +.align 3 + +GCC_ASM_EXPORT(ArmPlatformSecBootAction) +GCC_ASM_EXPORT(ArmPlatformSecBootMemoryInit) +GCC_ASM_EXPORT(ArmSecMpCoreSecondariesWrite) +GCC_ASM_EXPORT(ArmSecMpCoreSecondariesRead) + +/** + Call at the beginning of the platform boot up + + This function allows the firmware platform to do extra actions at the ea= rly + stage of the platform power up. + + Note: This function must be implemented in assembler as there is no stac= k set up yet + +**/ +ASM_PFX(ArmPlatformSecBootAction): + ret + +/** + Initialize the memory where the initial stacks will reside + + This memory can contain the initial stacks (Secure and Secure Monitor st= acks). + In some platform, this region is already initialized and the implementat= ion of this function can + do nothing. This memory can also represent the Secure RAM. + This function is called before the satck has been set up. Its implementa= tion must ensure the stack + pointer is not used (probably required to use assembly language) + +**/ +ASM_PFX(ArmPlatformSecBootMemoryInit): + // The SMC does not need to be initialized for RTSM + ret + +/* Write the flag register used to start Secondary cores */ +ASM_PFX(ArmSecMpCoreSecondariesWrite): + // Write to the CPU Mailbox + ret + +/* Read the flag register used to start Secondary cores */ +ASM_PFX(ArmSecMpCoreSecondariesRead): + // Return the value from the CPU Mailbox + mov x0, #0 + ret + diff --git a/CadencePkg/Library/CadenceCspSecLib/AArch64/GicV3.S b/CadenceP= kg/Library/CadenceCspSecLib/AArch64/GicV3.S new file mode 100644 index 0000000..035e095 --- /dev/null +++ b/CadencePkg/Library/CadenceCspSecLib/AArch64/GicV3.S @@ -0,0 +1,70 @@ +// +// Copyright (c) 2013-2014, ARM Limited. All rights reserved. +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the = BSD License +// which accompanies this distribution. The full text of the license may= be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR I= MPLIED. +// +// + +#include +#include + +#ifndef __clang__ +// Register definitions used by GCC for GICv3 access. +// These are defined by ARMCC, so keep them in the GCC specific code for n= ow. +#define ICC_SRE_EL2 S3_4_C12_C9_5 +#define ICC_SRE_EL3 S3_6_C12_C12_5 +#define ICC_CTLR_EL1 S3_0_C12_C12_4 +#define ICC_CTLR_EL3 S3_6_C12_C12_4 +#define ICC_PMR_EL1 S3_0_C4_C6_0 +#endif + +.text +.align 3 + +GCC_ASM_EXPORT(InitializeGicV3) + +/* Initialize GICv3 to expose it as a GICv2 as UEFI does not support GICv3= yet */ +ASM_PFX(InitializeGicV3): + // We have a GICv3. UEFI still uses the GICv2 mode. We must do enough se= tup + // to allow Linux to use GICv3 if it chooses. + + // In order to setup NS side we need to enable it first. + mrs x0, scr_el3 + orr x0, x0, #1 + msr scr_el3, x0 + + // Enable SRE at EL3 and ICC_SRE_EL2 access + mov x0, #((1 << 3) | (1 << 0)) // Enable | SRE + mrs x1, ICC_SRE_EL3 + orr x1, x1, x0 + msr ICC_SRE_EL3, x1 + isb + + // Enable SRE at EL2 and ICC_SRE_EL1 access.. + mrs x1, ICC_SRE_EL2 + orr x1, x1, x0 + msr ICC_SRE_EL2, x1 + isb + + // Configure CPU interface + msr ICC_CTLR_EL3, xzr + isb + msr ICC_CTLR_EL1, xzr + isb + + // The MemoryMap view and Register view may not be consistent, So Set PM= R again. + mov w1, #1 << 7 // allow NS access to GICC_PMR + msr ICC_PMR_EL1, x1 + isb + + // Remove the SCR.NS bit + mrs x0, scr_el3 + and x0, x0, #~SCR_NS + msr scr_el3, x0 + ret diff --git a/CadencePkg/Library/CadenceCspSecLib/CadenceCspSecLib.inf b/Cad= encePkg/Library/CadenceCspSecLib/CadenceCspSecLib.inf new file mode 100644 index 0000000..1603ed1 --- /dev/null +++ b/CadencePkg/Library/CadenceCspSecLib/CadenceCspSecLib.inf @@ -0,0 +1,44 @@ +#/* @file +# Copyright (c) 2011-2013, ARM Limited. All rights reserved. +# Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +#*/ + +[Defines] + INF_VERSION =3D 1.25 + BASE_NAME =3D CadenceCspSecLib + FILE_GUID =3D 07a2577e-43fb-40d9-9833-415cb7feefab + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D ArmPlatformSecLib + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses] + IoLib + ArmLib + SerialPortLib + +[Sources.common] + CspSec.c + +[Sources.AARCH64] + AArch64/CspBoot.S + AArch64/GicV3.S + +[FixedPcd] + gArmTokenSpaceGuid.PcdFvBaseAddress + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase diff --git a/CadencePkg/Library/CadenceCspSecLib/CspSec.c b/CadencePkg/Libr= ary/CadenceCspSecLib/CspSec.c new file mode 100644 index 0000000..65eedb4 --- /dev/null +++ b/CadencePkg/Library/CadenceCspSecLib/CspSec.c @@ -0,0 +1,79 @@ +/** @file +* +* Copyright (c) 2011-2014, ARM Limited. All rights reserved. +* Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the B= SD License +* which accompanies this distribution. The full text of the license may = be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#include +#include +#include +#include +#include + +// Initialize GICv3 to expose it as a GICv2 as UEFI does not support GICv3= yet +VOID +InitializeGicV3 ( + VOID + ); + +/** + Initialize the Secure peripherals and memory regions + + If Trustzone is supported by your platform then this function makes the = required initialization + of the secure peripherals and memory regions. + +**/ +VOID +ArmPlatformSecTrustzoneInit ( + IN UINTN MpId + ) +{ + // No TZPC or TZASC on RTSM to initialize +} + +/** + Initialize controllers that must setup at the early stage + + Some peripherals must be initialized in Secure World. + For example, some L2x0 requires to be initialized in Secure World + +**/ +RETURN_STATUS +ArmPlatformSecInitialize ( + IN UINTN MpId + ) +{ + // If it is not the primary core then there is nothing to do + if (!ArmPlatformIsPrimaryCore (MpId)) { + return RETURN_SUCCESS; + } + + InitializeGicV3 (); + + return RETURN_SUCCESS; +} + +/** + Call before jumping to Normal World + + This function allows the firmware platform to do extra actions before + jumping to the Normal World + +**/ +VOID +ArmPlatformSecExtraAction ( + IN UINTN MpId, + OUT UINTN* JumpAddress + ) +{ + *JumpAddress =3D PcdGet64 (PcdFvBaseAddress); +} --=20 2.2.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat Apr 27 10:54:59 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zoho.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1496659860162681.0408642441097; Mon, 5 Jun 2017 03:51:00 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 027CA21C8D0C5; Mon, 5 Jun 2017 03:49:50 -0700 (PDT) Received: from mx-sanjose5.cadence.com (keymaster.Cadence.COM [158.140.2.26]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 2D1A12095CC44 for ; Mon, 5 Jun 2017 03:49:48 -0700 (PDT) Received: from maileu3.global.cadence.com (maileu3.Cadence.COM [10.160.88.99]) by mx-sanjose5.cadence.com (8.13.8+Sun/8.14.4) with ESMTP id v55Aonkf028201; Mon, 5 Jun 2017 03:50:51 -0700 (PDT) Received: from maileu3.global.cadence.com (10.160.88.99) by maileu3.global.cadence.com (10.160.88.99) with Microsoft SMTP Server (TLS) id 15.0.1044.25; Mon, 5 Jun 2017 12:50:44 +0200 Received: from lvloginb.cadence.com (10.165.177.11) by maileu3.global.cadence.com (10.160.88.99) with Microsoft SMTP Server (TLS) id 15.0.1044.25 via Frontend Transport; Mon, 5 Jun 2017 12:50:43 +0200 Received: from lvloginb.cadence.com (localhost [127.0.0.1]) by lvloginb.cadence.com (8.14.4/8.14.4) with ESMTP id v55Aoh7Q000562; Mon, 5 Jun 2017 11:50:43 +0100 Received: (from stelford@localhost) by lvloginb.cadence.com (8.14.4/8.14.4/Submit) id v55Aohqo000561; Mon, 5 Jun 2017 11:50:43 +0100 X-Original-To: edk2-devel@ml01.01.org X-CrossPremisesHeadersFilteredBySendConnector: maileu3.global.cadence.com From: Scott Telford To: , , , , , Date: Mon, 5 Jun 2017 11:50:24 +0100 Message-ID: <1496659828-28702-3-git-send-email-stelford@cadence.com> X-Mailer: git-send-email 2.2.2 In-Reply-To: <1496659828-28702-1-git-send-email-stelford@cadence.com> References: <1496659828-28702-1-git-send-email-stelford@cadence.com> MIME-Version: 1.0 X-OrganizationHeadersPreserved: maileu3.global.cadence.com Subject: [edk2] [staging/cadence-aarch64 PATCH v2 2/6] CadencePkg: Add library for Cadence UART. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Add serial port library to support the Cadence IP6528 UART used in the Cadence CSP platform. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Scott Telford --- CadencePkg/Include/Library/CspSerialPortLib.h | 86 ++++ .../CadenceCspSerialPortLib/CspSerialPortLib.c | 525 +++++++++++++++++= ++++ .../CadenceCspSerialPortLib/CspSerialPortLib.inf | 52 ++ .../CadenceCspSerialPortLib/CspSerialPortLib.uni | Bin 0 -> 1622 bytes 4 files changed, 663 insertions(+) create mode 100644 CadencePkg/Include/Library/CspSerialPortLib.h create mode 100644 CadencePkg/Library/CadenceCspSerialPortLib/CspSerialPor= tLib.c create mode 100644 CadencePkg/Library/CadenceCspSerialPortLib/CspSerialPor= tLib.inf create mode 100644 CadencePkg/Library/CadenceCspSerialPortLib/CspSerialPor= tLib.uni diff --git a/CadencePkg/Include/Library/CspSerialPortLib.h b/CadencePkg/Inc= lude/Library/CspSerialPortLib.h new file mode 100644 index 0000000..46fa0d8 --- /dev/null +++ b/CadencePkg/Include/Library/CspSerialPortLib.h @@ -0,0 +1,86 @@ +/** @file +* Serial Port Library for Cadence IP6528 UART. +* Copyright (c) 2017, Cadence Design Systems. All rights reserved. +* +* This program and the accompanying materials are licensed and made +* available under the terms and conditions of the BSD License which +* accompanies this distribution. The full text of the license may be +* found at http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#ifndef __CSP_SERIAL_PORT_LIB_H__ +#define __CSP_SERIAL_PORT_LIB_H__ + +// Cadence UART register offsets +#define CSP_UART_CR 0x00 // Control +#define CSP_UART_MR 0x04 // Mode +#define CSP_UART_IER 0x08 // Interrupt enable +#define CSP_UART_IDR 0x0C // Interrupt disable +#define CSP_UART_IMR 0x10 // Interrupt mask +#define CSP_UART_CISR 0x14 // Channel interrupt status +#define CSP_UART_BRGR 0x18 // Baud rate generator +#define CSP_UART_RTOR 0x1C // Rx Timeout +#define CSP_UART_RTRIG 0x20 // Rx FIFO trigger level +#define CSP_UART_MCR 0x24 // Modem control +#define CSP_UART_MSR 0x28 // Modem status +#define CSP_UART_CSR 0x2C // Channel status +#define CSP_UART_FIFO 0x30 // FIFO (Tx/Rx) +#define CSP_UART_BDIV 0x34 // Baud rate divider +#define CSP_UART_FDEL 0x38 // Flow delay +#define CSP_UART_PMIN 0x3C // IR min received pulse width +#define CSP_UART_PWID 0x40 // IR transmitted pulse Width +#define CSP_UART_TTRIG 0x44 // Tx FIFO trigger level + + +// Control Register Bit Definitions +#define CSP_UART_CR_STPBRK 0x00000100 // Stop Tx break +#define CSP_UART_CR_STTBRK 0x00000080 // Start Tx break +#define CSP_UART_CR_RSTTO 0x00000040 // Restart Rx timeout Counter +#define CSP_UART_CR_TXDIS 0x00000020 // Tx disable +#define CSP_UART_CR_TXEN 0x00000010 // Tx enable +#define CSP_UART_CR_RXDIS 0x00000008 // Rx disable +#define CSP_UART_CR_RXEN 0x00000004 // Rx enable +#define CSP_UART_CR_TXRES 0x00000002 // Tx reset +#define CSP_UART_CR_RXRES 0x00000001 // Rx reset + + +// Mode register bit definitions +#define CSP_UART_MR_CLKS 0x00000001 // Baud rate /8 pre-sc= alar +#define CSP_UART_MR_CHMODE_LLB 0x00000200 // Local loopback mode +#define CSP_UART_MR_CHMODE_NML 0x00000000 // Normal mode + +#define CSP_UART_MR_CHRL_6 0x00000006 // 6 databits +#define CSP_UART_MR_CHRL_7 0x00000004 // 7 databits +#define CSP_UART_MR_CHRL_8 0x00000000 // 8 databits + +#define CSP_UART_MR_PAR_NONE 0x00000020 // No parity mode +#define CSP_UART_MR_PAR_MARK 0x00000018 // Mark parity mode +#define CSP_UART_MR_PAR_SPACE 0x00000010 // Space parity mode +#define CSP_UART_MR_PAR_ODD 0x00000008 // Odd parity mode +#define CSP_UART_MR_PAR_EVEN 0x00000000 // Even parity mode + +#define CSP_UART_MR_NBSTOP_1 0x00000000 // 1 stop bit +#define CSP_UART_MR_NBSTOP_2 0x00000080 // 2 stop bits + +// Modem control register bit definitions +#define CSP_UART_MCR_DTR 0x00000001 // DTR control +#define CSP_UART_MCR_RTS 0x00000002 // RTS control +#define CSP_UART_MCR_FCM 0x00000020 // Auto flow control + +// Modem status register bit definitions +#define CSP_UART_MSR_FCMS 0x00000100 // Auto flow control s= tatus +#define CSP_UART_MSR_DCD 0x00000080 // DCD status +#define CSP_UART_MSR_RI 0x00000040 // RI status +#define CSP_UART_MSR_DSR 0x00000020 // DSR status +#define CSP_UART_MSR_CTS 0x00000010 // CTS status + +// Channel status register bit definitions +#define CSP_UART_CSR_REMPTY 0x00000002 // Rx FIFO empty +#define CSP_UART_CSR_TEMPTY 0x00000008 // Tx FIFO empty +#define CSP_UART_CSR_TFUL 0x00000010 // Tx FIFO full + +#endif diff --git a/CadencePkg/Library/CadenceCspSerialPortLib/CspSerialPortLib.c = b/CadencePkg/Library/CadenceCspSerialPortLib/CspSerialPortLib.c new file mode 100644 index 0000000..ee9823c --- /dev/null +++ b/CadencePkg/Library/CadenceCspSerialPortLib/CspSerialPortLib.c @@ -0,0 +1,525 @@ +/** @file + Serial Port Library for Cadence IP6528 UART. + Copyright (c) 2015-2017, Cadence Design Systems, Inc. All rights reserve= d. + + Based on: + + Null Serial Port library instance with empty functions. + + Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
+ This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + + +RETURN_STATUS +EFIAPI +CspUartInitializePort ( + IN UINTN UartBase, + IN OUT UINT64 *BaudRate, + IN OUT EFI_PARITY_TYPE *Parity, + IN OUT UINT8 *DataBits, + IN OUT EFI_STOP_BITS_TYPE *StopBits +); +VOID CspUartPutChar (IN UINTN UartBase, IN UINT8 Char); +UINT8 CspUartGetChar (IN UINTN UartBase); + +/** + Initialize the serial device hardware. + + If no initialization is required, then return RETURN_SUCCESS. + If the serial device was successfully initialized, then return RETURN_SU= CCESS. + If the serial device could not be initialized, then return RETURN_DEVICE= _ERROR. + + @retval RETURN_SUCCESS The serial device was initialized. + @retval RETURN_DEVICE_ERROR The serial device could not be initialized. + +**/ +RETURN_STATUS +EFIAPI +SerialPortInitialize ( + VOID + ) +{ + UINT64 BaudRate; + EFI_PARITY_TYPE Parity; + UINT8 DataBits; + EFI_STOP_BITS_TYPE StopBits; + + BaudRate =3D FixedPcdGet64 (PcdUartDefaultBaudRate); + Parity =3D (EFI_PARITY_TYPE)FixedPcdGet8 (PcdUartDefaultParity); + DataBits =3D FixedPcdGet8 (PcdUartDefaultDataBits); + StopBits =3D (EFI_STOP_BITS_TYPE) FixedPcdGet8 (PcdUartDefaultStopBits); + + return CspUartInitializePort ( + (UINTN)FixedPcdGet64 (PcdCspSerialBase), + &BaudRate, + &Parity, + &DataBits, + &StopBits + ); +} + +/** + Set new attributes to UART. + + @param BaudRate The baud rate of the serial device. If t= he + baud rate is not supported, the speed wi= ll + be reduced down to the nearest supported= one + and the variable's value will be updated + accordingly. + @param ReceiveFifoDepth The number of characters the device will + buffer on input. If the specified value = is + not supported, the variable's value will + be reduced down to the nearest supported= one. + @param Timeout If applicable, the number of microsecond= s the + device will wait before timing out a Rea= d or + a Write operation. + @param Parity If applicable, this is the EFI_PARITY_TY= PE + that is computed or checked as each char= acter + is transmitted or received. If the device + does not support parity, the value is the + default parity value. + @param DataBits The number of data bits in each character + @param StopBits If applicable, the EFI_STOP_BITS_TYPE nu= mber + of stop bits per character. If the device + does not support stop bits, the value is= the + default stop bit value. + + @retval EFI_SUCCESS All attributes were set correctly. + @retval EFI_INVALID_PARAMETERS One or more attributes has an unsupported + value. + +**/ +RETURN_STATUS +EFIAPI +SerialPortSetAttributes ( + IN OUT UINT64 *BaudRate, + IN OUT UINT32 *ReceiveFifoDepth, + IN OUT UINT32 *Timeout, + IN OUT EFI_PARITY_TYPE *Parity, + IN OUT UINT8 *DataBits, + IN OUT EFI_STOP_BITS_TYPE *StopBits + ) +{ + return CspUartInitializePort ( + (UINTN)FixedPcdGet64 (PcdCspSerialBase), + BaudRate, + Parity, + DataBits, + StopBits + ); +} + +/** + Write data from buffer to serial device. + + Writes NumberOfBytes data bytes from Buffer to the serial device. + The number of bytes actually written to the serial device is returned. + If the return value is less than NumberOfBytes, then the write operation= failed. + If Buffer is NULL, then ASSERT(). + If NumberOfBytes is zero, then return 0. + + @param Buffer The pointer to the data buffer to be written. + @param NumberOfBytes The number of bytes to written to the serial de= vice. + + @retval 0 NumberOfBytes is 0. + @retval >0 The number of bytes written to the serial devic= e. + If this value is less than NumberOfBytes, then = the read operation failed. + +**/ +UINTN +EFIAPI +SerialPortWrite ( + IN UINT8 *Buffer, + IN UINTN NumberOfBytes +) +{ + UINTN i; + for (i =3D 0; i < NumberOfBytes; i++) { + CspUartPutChar((UINTN)PcdGet64(PcdCspSerialBase), Buffer[i]); + } + return i; +} + + +/** + Read data from serial device and save the datas in buffer. + + Reads NumberOfBytes data bytes from a serial device into the buffer + specified by Buffer. The number of bytes actually read is returned. + If the return value is less than NumberOfBytes, then the rest operation = failed. + If Buffer is NULL, then ASSERT(). + If NumberOfBytes is zero, then return 0. + + @param Buffer The pointer to the data buffer to store the dat= a read from the serial device. + @param NumberOfBytes The number of bytes which will be read. + + @retval 0 Read data failed; No data is to be read. + @retval >0 The actual number of bytes read from serial dev= ice. + +**/ +UINTN +EFIAPI +SerialPortRead ( + OUT UINT8 *Buffer, + IN UINTN NumberOfBytes +) +{ + UINTN i; + for (i =3D 0; i < NumberOfBytes; i++) { + Buffer[i] =3D CspUartGetChar((UINTN)PcdGet64(PcdCspSerialBase)); + } + return i; +} + +/** + Polls a serial device to see if there is any data waiting to be read. + + Polls a serial device to see if there is any data waiting to be read. + If there is data waiting to be read from the serial device, then TRUE is= returned. + If there is no data waiting to be read from the serial device, then FALS= E is returned. + + @retval TRUE Data is waiting to be read from the serial devi= ce. + @retval FALSE There is no data waiting to be read from the se= rial device. + +**/ +BOOLEAN +EFIAPI +SerialPortPoll ( + VOID + ) +{ + return (MmioRead32((UINTN)(PcdGet64(PcdCspSerialBase + CSP_UART_CSR))) & + CSP_UART_CSR_REMPTY) ? FALSE : TRUE; +} + +/** + + Assert or deassert the control signals on a serial port. + The following control signals are set according their bit settings : + . Request to Send + . Data Terminal Ready + + @param[in] Control The following bits are taken into account : + . EFI_SERIAL_REQUEST_TO_SEND : assert/deassert the + "Request To Send" control signal if this bit is + equal to one/zero. + . EFI_SERIAL_DATA_TERMINAL_READY : assert/deassert + the "Data Terminal Ready" control signal if this + bit is equal to one/zero. + . EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : enable/disa= ble + the hardware loopback if this bit is equal to + one/zero. + . EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : not support= ed. + . EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : enable/ + disable the hardware flow control based on CTS (C= lear + To Send) and RTS (Ready To Send) control signals. + + @retval RETURN_SUCCESS The new control bits were set on the device. + @retval RETURN_UNSUPPORTED The device does not support this operation. + +**/ +RETURN_STATUS +EFIAPI +SerialPortSetControl ( + IN UINT32 Control + ) +{ + UINT32 Bits; + + if (Control & (EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE | + EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE )) { + return RETURN_UNSUPPORTED; + } + + Bits =3D MmioRead32 (PcdGet64(PcdCspSerialBase) + CSP_UART_MCR); + + if (Control & EFI_SERIAL_REQUEST_TO_SEND) { + Bits |=3D CSP_UART_MCR_RTS; + } else { + Bits &=3D ~CSP_UART_MCR_RTS; + } + + if (Control & EFI_SERIAL_DATA_TERMINAL_READY) { + Bits |=3D CSP_UART_MCR_DTR; + } else { + Bits &=3D ~CSP_UART_MCR_DTR; + } + + if (Control & EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE) { + Bits |=3D CSP_UART_MCR_FCM; + } else { + Bits &=3D CSP_UART_MCR_FCM; + } + + MmioWrite32 ((PcdGet64(PcdCspSerialBase) + CSP_UART_MCR), Bits); + + return RETURN_SUCCESS; +} + +/** + + Retrieve the status of the control bits on a serial device. + + @param[out] Control Status of the control bits on a serial device : + + . EFI_SERIAL_DATA_CLEAR_TO_SEND, + EFI_SERIAL_DATA_SET_READY, + EFI_SERIAL_RING_INDICATE, + EFI_SERIAL_CARRIER_DETECT, + EFI_SERIAL_REQUEST_TO_SEND, + EFI_SERIAL_DATA_TERMINAL_READY + are all related to the DTE (Data Terminal Equipm= ent) + and DCE (Data Communication Equipment) modes of + operation of the serial device. + . EFI_SERIAL_INPUT_BUFFER_EMPTY : equal to one if = the + receive buffer is empty, 0 otherwise. + . EFI_SERIAL_OUTPUT_BUFFER_EMPTY : equal to one if= the + transmit buffer is empty, 0 otherwise. + . EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : equal to o= ne if + the hardware loopback is enabled (the output fee= ds + the receive buffer), 0 otherwise. + . EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : equal to o= ne + if a loopback is accomplished by software, else = 0. + . EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : equal = to + one if the hardware flow control based on CTS (C= lear + To Send) and RTS (Ready To Send) control signals= is + enabled, 0 otherwise. + + @retval RETURN_SUCCESS The control bits were read from the device. + +**/ +RETURN_STATUS +EFIAPI +SerialPortGetControl ( + OUT UINT32 *Control + ) +{ + UINT32 ModemStatusReg; + UINT32 ModemCtrlReg; + UINT32 ChanStatusReg; + + ModemCtrlReg =3D MmioRead32 ((UINTN)(PcdGet64(PcdCspSerialBase) + + CSP_UART_MCR)); + ModemStatusReg =3D MmioRead32 ((UINTN)(PcdGet64(PcdCspSerialBase) + + CSP_UART_MSR)); + ChanStatusReg =3D MmioRead32 ((UINTN)(PcdGet64(PcdCspSerialBase) + + CSP_UART_CSR)); + + *Control =3D 0; + + if ((ModemStatusReg & CSP_UART_MSR_CTS) =3D=3D CSP_UART_MSR_CTS) { + *Control |=3D EFI_SERIAL_CLEAR_TO_SEND; + } + + if ((ModemStatusReg & CSP_UART_MSR_DSR) =3D=3D CSP_UART_MSR_DSR) { + *Control |=3D EFI_SERIAL_DATA_SET_READY; + } + + if ((ModemStatusReg & CSP_UART_MSR_RI) =3D=3D CSP_UART_MSR_RI) { + *Control |=3D EFI_SERIAL_RING_INDICATE; + } + + if ((ModemStatusReg & CSP_UART_MSR_DCD) =3D=3D CSP_UART_MSR_DCD) { + *Control |=3D EFI_SERIAL_CARRIER_DETECT; + } + + if ((ModemCtrlReg & CSP_UART_MCR_RTS) =3D=3D CSP_UART_MCR_RTS) { + *Control |=3D EFI_SERIAL_REQUEST_TO_SEND; + } + + if ((ModemCtrlReg & CSP_UART_MCR_DTR) =3D=3D CSP_UART_MCR_DTR) { + *Control |=3D EFI_SERIAL_DATA_TERMINAL_READY; + } + + if ((ChanStatusReg & CSP_UART_CSR_REMPTY) =3D=3D CSP_UART_CSR_REMPTY) { + *Control |=3D EFI_SERIAL_INPUT_BUFFER_EMPTY; + } + + if ((ChanStatusReg & CSP_UART_CSR_TEMPTY) =3D=3D CSP_UART_CSR_TEMPTY) { + *Control |=3D EFI_SERIAL_OUTPUT_BUFFER_EMPTY; + } + + if ((ModemCtrlReg & CSP_UART_MCR_FCM) =3D=3D CSP_UART_MCR_FCM) { + *Control |=3D EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE; + } + + return RETURN_SUCCESS; +} + + +/** + + Initialise the serial port to the specified settings. + The serial port is re-configured only if the specified settings + are different from the current settings. + All unspecified settings will be set to the default values. + + @param UartBase The base address of the serial device. + @param BaudRate The baud rate of the serial device. If t= he + baud rate is not supported, the speed wi= ll be + reduced to the nearest supported one and= the + variable's value will be updated accordi= ngly. + @param Parity If applicable, this is the EFI_PARITY_TY= PE + that is computed or checked as each char= acter + is transmitted or received. If the device + does not support parity, the value is the + default parity value. + @param DataBits The number of data bits in each characte= r. + @param StopBits If applicable, the EFI_STOP_BITS_TYPE nu= mber + of stop bits per character. + If the device does not support stop bits= , the + value is the default stop bit value. + + @retval RETURN_SUCCESS All attributes were set correctly on t= he + serial device. + @retval RETURN_INVALID_PARAMETER One or more of the attributes has an + unsupported value. + +**/ +RETURN_STATUS +EFIAPI +CspUartInitializePort ( + IN UINTN UartBase, + IN OUT UINT64 *BaudRate, + IN OUT EFI_PARITY_TYPE *Parity, + IN OUT UINT8 *DataBits, + IN OUT EFI_STOP_BITS_TYPE *StopBits + ) +{ + UINT32 RegVal =3D 0; + UINT32 BaudDivisor =3D 0; + + // Wait for Tx FIFO to empty before initializing + if (!(MmioRead32(UartBase + CSP_UART_CR) & + CSP_UART_CR_TXDIS)) { + while (!(MmioRead32(UartBase + CSP_UART_CSR) & + CSP_UART_CSR_TEMPTY)) + ; + } + + // Disable Tx/Rx before setting baud rate + RegVal =3D MmioRead32(UartBase + CSP_UART_CR); + RegVal |=3D CSP_UART_CR_TXDIS | CSP_UART_CR_RXDIS; + MmioWrite32((UartBase + CSP_UART_CR), RegVal); + + // Set baud rate + UINT32 SelClk =3D MmioRead32 ((UINTN)(PcdGet64(PcdCspSysRegBase) + + CSP_SYSREG_CPU_FREQ)); + UINT32 BDiv =3D 0; + + if (SelClk < 0x1800000) { + BaudDivisor =3D 1; + } else { + BaudDivisor =3D 8; + } + MmioWrite32((UartBase + CSP_UART_BRGR), BaudDivisor); + BDiv =3D (SelClk + ((*BaudRate * BaudDivisor) / 2)) / (*BaudRate * BaudD= ivisor); + MmioWrite32((UartBase + CSP_UART_BDIV), (BDiv - 1)); + + // Reset and enable Tx/Rx + RegVal =3D MmioRead32(UartBase + CSP_UART_CR); + RegVal &=3D ~(CSP_UART_CR_TXDIS | CSP_UART_CR_RXDIS); + RegVal |=3D CSP_UART_CR_TXEN | CSP_UART_CR_TXRES | \ + CSP_UART_CR_RXEN | CSP_UART_CR_RXRES;; + MmioWrite32((UartBase + CSP_UART_CR), RegVal); + + RegVal =3D MmioRead32(UartBase + CSP_UART_MR) & 1; + + // + // Data Bits + // + switch (*DataBits) { + case 0: + *DataBits =3D 8; + case 8: + RegVal |=3D CSP_UART_MR_CHRL_8; + break; + case 7: + RegVal |=3D CSP_UART_MR_CHRL_7; + break; + case 6: + RegVal |=3D CSP_UART_MR_CHRL_6; + break; + default: + return RETURN_INVALID_PARAMETER; + } + + // + // Stop Bits + // + switch (*StopBits) { + case DefaultStopBits: + *StopBits =3D OneStopBit; + case OneStopBit: + RegVal |=3D CSP_UART_MR_NBSTOP_1; + break; + case TwoStopBits: + RegVal |=3D CSP_UART_MR_NBSTOP_2; + break; + default: + return RETURN_INVALID_PARAMETER; + } + + // + // Parity + // + switch (*Parity) { + case DefaultParity: + *Parity =3D NoParity; + case NoParity: + RegVal |=3D CSP_UART_MR_PAR_NONE; + break; + case EvenParity: + RegVal |=3D CSP_UART_MR_PAR_EVEN; + break; + case OddParity: + RegVal |=3D CSP_UART_MR_PAR_ODD; + break; + case MarkParity: + RegVal |=3D CSP_UART_MR_PAR_MARK; + break; + case SpaceParity: + RegVal |=3D CSP_UART_MR_PAR_SPACE; + break; + default: + return RETURN_INVALID_PARAMETER; + } + + MmioWrite32((UartBase + CSP_UART_MR), RegVal); + + return RETURN_SUCCESS; +} + +VOID CspUartPutChar (IN UINTN UartBase, IN UINT8 Char) +{ + while ((MmioRead32(UartBase + CSP_UART_CSR) & + CSP_UART_CSR_TFUL) =3D=3D CSP_UART_CSR_TFUL) + ; + MmioWrite8(UartBase + CSP_UART_FIFO, Char); +} + +UINT8 CspUartGetChar (IN UINTN UartBase) +{ + while ((MmioRead32(UartBase + CSP_UART_CSR) & + CSP_UART_CSR_REMPTY) =3D=3D CSP_UART_CSR_REMPTY) + ; + return MmioRead8(UartBase + CSP_UART_FIFO); +} + diff --git a/CadencePkg/Library/CadenceCspSerialPortLib/CspSerialPortLib.in= f b/CadencePkg/Library/CadenceCspSerialPortLib/CspSerialPortLib.inf new file mode 100644 index 0000000..46ea8f9 --- /dev/null +++ b/CadencePkg/Library/CadenceCspSerialPortLib/CspSerialPortLib.inf @@ -0,0 +1,52 @@ +## @file +# Serial Port Library for Cadence IP6528 UART. +# +# Based on: +# +# Null instance of Serial Port Library with empty functions. +# +# Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
+# Copyright (C) 2017 Cadence Design Systems. All rights reserved worldwid= e. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may b= e found at +# http://opensource.org/licenses/bsd-license.php. +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +# +## + +[Defines] + INF_VERSION =3D 1.25 + BASE_NAME =3D CspSerialPortLib + MODULE_UNI_FILE =3D CspSerialPortLib.uni + FILE_GUID =3D C456789-8897-411a-91F8-7D7E45837146 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SerialPortLib + +[Sources] + CspSerialPortLib.c + +[Packages] + ArmPkg/ArmPkg.dec + CadencePkg/CadenceCspPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses] + DebugLib + IoLib + BaseLib + PcdLib + +[FixedPcd] + gCadenceCspTokenSpaceGuid.PcdCspSerialBase + gCadenceCspTokenSpaceGuid.PcdCspSysRegBase + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits + diff --git a/CadencePkg/Library/CadenceCspSerialPortLib/CspSerialPortLib.un= i b/CadencePkg/Library/CadenceCspSerialPortLib/CspSerialPortLib.uni new file mode 100644 index 0000000000000000000000000000000000000000..60434d42366ee99f53da028381d= eff21250cfda8 GIT binary patch literal 1622 zcmc(fL2uJQ5QXQA#D7?&7eK88T#z`CGzKi7juJx>u&mVBL^Vw+=3DW>=3DWzR$TExCEFs$|G2g&b#)Vz^Oiw^~3eHP=3DZZGWB z0mK35m5*3)J0@OCF728%!qS7g*ay_gpA@C)Zh6nKY(3*8`z>hVe28NPuYyPi(~^h< z@0?uD*Djn59#SAji5VW(cuJQ$;#T-OEV*acC|k8!D5~_)OT49|bglUbL->joJNe%7 zsAoCdQ0JW8crVozm`IJ1II(U}#7uYvObWl(?V7%YxIStQIIG)%OX%0uYcb>fd$k2Q zg(x*@y_8FxQPop;HhI+}saj9X&8}PG{2iZ%oPO1%Rznjw-NmnW3W(8WPghOThEBZp zldU*yi%Xh z**RV#&+H6)0;(`lpMAth++|bF3}5*uYwh(GUuFNo`hgoUKV~2AveZ??_PNCg=3Dm}a3 znJ48O?CBO}O8-S&&s{b>NA1+qUr(*y1xP6v6VPJ2fRXf)vOUzw;Pa>75na?*u%Pof rZ_S-%;RGx(?eP9r|9YLavcIcJGcl$f&C9Uu!=3DcLlXH^lJHQo9N7Zm#w literal 0 HcmV?d00001 --=20 2.2.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat Apr 27 10:54:59 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zoho.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 149665986657212.39437454385245; Mon, 5 Jun 2017 03:51:06 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 73C6921C93EFF; Mon, 5 Jun 2017 03:49:50 -0700 (PDT) Received: from mx-sanjose5.cadence.com (keymaster.Cadence.COM [158.140.2.26]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 38DFD2095CC57 for ; Mon, 5 Jun 2017 03:49:48 -0700 (PDT) Received: from maileu3.global.cadence.com (maileu3.Cadence.COM [10.160.88.99]) by mx-sanjose5.cadence.com (8.13.8+Sun/8.14.4) with ESMTP id v55Aonkg028201; Mon, 5 Jun 2017 03:50:51 -0700 (PDT) Received: from maileu3.global.cadence.com (10.160.88.99) by maileu3.global.cadence.com (10.160.88.99) with Microsoft SMTP Server (TLS) id 15.0.1044.25; Mon, 5 Jun 2017 12:50:44 +0200 Received: from lvloginb.cadence.com (10.165.177.11) by maileu3.global.cadence.com (10.160.88.99) with Microsoft SMTP Server (TLS) id 15.0.1044.25 via Frontend Transport; Mon, 5 Jun 2017 12:50:44 +0200 Received: from lvloginb.cadence.com (localhost [127.0.0.1]) by lvloginb.cadence.com (8.14.4/8.14.4) with ESMTP id v55AohC2000580; Mon, 5 Jun 2017 11:50:43 +0100 Received: (from stelford@localhost) by lvloginb.cadence.com (8.14.4/8.14.4/Submit) id v55AohcE000578; Mon, 5 Jun 2017 11:50:43 +0100 X-Original-To: edk2-devel@ml01.01.org X-CrossPremisesHeadersFilteredBySendConnector: maileu3.global.cadence.com From: Scott Telford To: , , , , , Date: Mon, 5 Jun 2017 11:50:25 +0100 Message-ID: <1496659828-28702-4-git-send-email-stelford@cadence.com> X-Mailer: git-send-email 2.2.2 In-Reply-To: <1496659828-28702-1-git-send-email-stelford@cadence.com> References: <1496659828-28702-1-git-send-email-stelford@cadence.com> MIME-Version: 1.0 X-OrganizationHeadersPreserved: maileu3.global.cadence.com Subject: [edk2] [staging/cadence-aarch64 PATCH v2 3/6] CadencePkg: Add PCI host bridge library for Cadence PCIe Root Complex. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Add PciHostBridgeLib implementation for the Cadence PCIe Root Complex. This library is derived from Platforms/ARM/Juno/Library/JunoPciHostBridgeLib in OpenPlatformPkg. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Scott Telford --- .../Library/CadencePciHostBridgeLib/CdnsPci.c | 103 +++++++++++ .../Library/CadencePciHostBridgeLib/CdnsPci.h | 85 +++++++++ .../CadencePciHostBridgeLib/CdnsPciHostBridgeLib.c | 189 +++++++++++++++++= ++++ .../CdnsPciHostBridgeLib.inf | 77 +++++++++ 4 files changed, 454 insertions(+) create mode 100644 CadencePkg/Library/CadencePciHostBridgeLib/CdnsPci.c create mode 100644 CadencePkg/Library/CadencePciHostBridgeLib/CdnsPci.h create mode 100644 CadencePkg/Library/CadencePciHostBridgeLib/CdnsPciHostB= ridgeLib.c create mode 100644 CadencePkg/Library/CadencePciHostBridgeLib/CdnsPciHostB= ridgeLib.inf diff --git a/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPci.c b/Cadence= Pkg/Library/CadencePciHostBridgeLib/CdnsPci.c new file mode 100644 index 0000000..afab354 --- /dev/null +++ b/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPci.c @@ -0,0 +1,103 @@ +/** @file +* Initialize the Cadence PCIe Root complex +* +* Copyright (c) 2017, Cadence Design Systems. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the B= SD License +* which accompanies this distribution. The full text of the license may = be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#include +#include +#include +#include +#include + +#include + +#include "CdnsPci.h" + +STATIC +VOID +CdnsPciRegInit( + EFI_CPU_IO2_PROTOCOL *CpuIo +) +{ + UINT32 Value; + + // Setup the class code as PCIe Host Bridge. + PCIE_ROOTPORT_WRITE32 (PCIE_RP + PCIE_PCI_CLASSCODE, PCIE_BRIDGE_CLASSCO= DE); + + // Set up the BARs via the Root Port registers + PCIE_ROOTPORT_READ32 (PCIE_LM + PCIE_RP_BAR_CONFIG, Value); + PCIE_ROOTPORT_WRITE32 (PCIE_LM + PCIE_RP_BAR_CONFIG, Value | (1 << PCIE_= RCBARPIE)); + + // Allow incoming writes + PCIE_ROOTPORT_WRITE32 (PCIE_AXI + PCIE_AXI_BAR0_IB, 0x1f); + PCIE_ROOTPORT_WRITE32 (PCIE_AXI + PCIE_AXI_BAR1_IB, 0x1f); + PCIE_ROOTPORT_WRITE32 (PCIE_AXI + PCIE_AXI_NO_BAR_IB, 0x1f); + + // Set up an area for Type 0 write + PCIE_ROOTPORT_WRITE32 (PCIE_AXI + PCIE_AXI_REG0_ADDR0, 0x18); + PCIE_ROOTPORT_WRITE32 (PCIE_AXI + PCIE_AXI_REG0_DESC0, PCIE_AXI_TYPE0); + PCIE_ROOTPORT_WRITE32 (PCIE_AXI + PCIE_AXI_REG0_AXI_ADDR0, 0x14); + + // Set up an area for Type 1 write + PCIE_ROOTPORT_WRITE32 (PCIE_AXI + PCIE_AXI_REG1_ADDR0, PCI_ECAM_BASE + (= 2*PCI_BUS_SIZE) + 0x18); + PCIE_ROOTPORT_WRITE32 (PCIE_AXI + PCIE_AXI_REG1_DESC0, PCIE_AXI_TYPE1); + PCIE_ROOTPORT_WRITE32 (PCIE_AXI + PCIE_AXI_REG1_AXI_ADDR0, (2*PCI_BUS_SI= ZE) + 0x18); + + // Set up an area for memory write + PCIE_ROOTPORT_WRITE32 (PCIE_AXI + PCIE_AXI_REG2_ADDR0, PCI_MEM32_BASE + = 0x18); + PCIE_ROOTPORT_WRITE32 (PCIE_AXI + PCIE_AXI_REG2_DESC0, PCIE_AXI_MEM); + PCIE_ROOTPORT_WRITE32 (PCIE_AXI + PCIE_AXI_REG2_AXI_ADDR0, PCI_ECAM_SIZE= + 0x17); + + // Set up an area for IO write + PCIE_ROOTPORT_WRITE32 (PCIE_AXI + PCIE_AXI_REG3_ADDR0, PCI_IO_BASE + 0x1= 8); + PCIE_ROOTPORT_WRITE32 (PCIE_AXI + PCIE_AXI_REG3_DESC0, PCIE_AXI_IO); + PCIE_ROOTPORT_WRITE32 (PCIE_AXI + PCIE_AXI_REG3_AXI_ADDR0, (PCI_ECAM_SIZ= E + PCI_MEM32_SIZE) + 0x17 ); +} + +EFI_STATUS +HWPciRbInit ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + UINT32 Count; + EFI_CPU_IO2_PROTOCOL *CpuIo; + EFI_STATUS Status; + UINT32 Value; + + PCI_TRACE ("HWPciRbInit()"); + + PCI_TRACE ("PCIe Setting up Address Translation"); + + Status =3D gBS->LocateProtocol (&gEfiCpuIo2ProtocolGuid, NULL, + (VOID **)&CpuIo); + ASSERT_EFI_ERROR (Status); + + // Check for link up + for (Count =3D 0; Count < PCI_LINK_TIMEOUT_COUNT; Count++) { + gBS->Stall (PCI_LINK_TIMEOUT_WAIT_US); + PCIE_ROOTPORT_READ32 (PCIE_LM + PCIE_LINK_CTRL_STATUS, Value); + if (Value & PCIE_LINK_UP) { + break; + } + } + if (!(Value & PCIE_LINK_UP)) { + DEBUG ((DEBUG_ERROR, "PCIe link not up: %x.\n", Value)); + return EFI_NOT_READY; + } + + // Initialise configuration registers + CdnsPciRegInit(CpuIo); + + return EFI_SUCCESS; +} diff --git a/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPci.h b/Cadence= Pkg/Library/CadencePciHostBridgeLib/CdnsPci.h new file mode 100644 index 0000000..7d47ed6 --- /dev/null +++ b/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPci.h @@ -0,0 +1,85 @@ +/** @file +* Header for Cadence PCIe Root Complex +* +* Copyright (c) 2011-2015, ARM Ltd. All rights reserved. +* Copyright (c) 2017, Cadence Design Systems. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the B= SD License +* which accompanies this distribution. The full text of the license may = be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#ifndef __CDNS_PCI_H__ +#define __CDNS_PCI_H__ + +#include + +#define PCI_ECAM_BASE FixedPcdGet64 (PcdPciConfigurationSpaceBaseAdd= ress) +#define PCI_ECAM_SIZE FixedPcdGet64 (PcdPciConfigurationSpaceSize) +#define PCI_IO_BASE FixedPcdGet64 (PcdPciIoBase) +#define PCI_IO_SIZE FixedPcdGet64 (PcdPciIoSize) +#define PCI_MEM32_BASE FixedPcdGet64 (PcdPciMmio32Base) +#define PCI_MEM32_SIZE FixedPcdGet64 (PcdPciMmio32Size) +#define PCI_MEM64_BASE FixedPcdGet64 (PcdPciMmio64Base) +#define PCI_MEM64_SIZE FixedPcdGet64 (PcdPciMmio64Size) + +#define PCI_BUS_SIZE 0x00100000 + +#define PCI_LINK_TIMEOUT_WAIT_US 1000 // microseconds +#define PCI_LINK_TIMEOUT_COUNT 1000 + +#define PCI_TRACE(txt) DEBUG((DEBUG_VERBOSE, "CDNS_PCI: " txt "\n")) + +#define PCIE_ROOTPORT_WRITE32(Add, Val) { UINT32 Value =3D (UINT32)(Val); = CpuIo->Mem.Write (CpuIo,EfiCpuIoWidthUint32,(UINT64)(PcdGet64 (PcdPcieRootP= ortBaseAddress)+(Add)),1,&Value); } +#define PCIE_ROOTPORT_READ32(Add, Val) { CpuIo->Mem.Read (CpuIo,EfiCpuIoWi= dthUint32,(UINT64)(PcdGet64 (PcdPcieRootPortBaseAddress)+(Add)),1,&Val); } +#ifdef CDNS_B2B +#define PCIE1_ROOTPORT_WRITE32(Add, Val) { UINT32 Value =3D (UINT32)(Val);= CpuIo->Mem.Write (CpuIo,EfiCpuIoWidthUint32,(UINT64)(PcdGet64 (PcdPcie1Roo= tPortBaseAddress)+(Add)),1,&Value); } +#define PCIE1_ROOTPORT_READ32(Add, Val) { CpuIo->Mem.Read (CpuIo,EfiCpuIoW= idthUint32,(UINT64)(PcdGet64 (PcdPcie1RootPortBaseAddress)+(Add)),1,&Val); } +#endif + +/* + * Bridge Internal Registers + */ + +// Root Port Configuration +#define PCIE_RP 0x00200000 +#define PCIE_PCI_CLASSCODE 0x8 + +// Local Management +#define PCIE_LM 0x00100000 +#define PCIE_LINK_CTRL_STATUS 0x00 +#define PCIE_RP_BAR_CONFIG 0x300 + +// AXI Configuration +#define PCIE_AXI 0x00400000 +#define PCIE_AXI_REG0_ADDR0 0x000 +#define PCIE_AXI_REG0_DESC0 0x008 +#define PCIE_AXI_REG0_AXI_ADDR0 0x018 +#define PCIE_AXI_REG1_ADDR0 0x020 +#define PCIE_AXI_REG1_DESC0 0x028 +#define PCIE_AXI_REG1_AXI_ADDR0 0x038 +#define PCIE_AXI_REG2_ADDR0 0x040 +#define PCIE_AXI_REG2_DESC0 0x048 +#define PCIE_AXI_REG2_AXI_ADDR0 0x058 +#define PCIE_AXI_REG3_ADDR0 0x060 +#define PCIE_AXI_REG3_DESC0 0x068 +#define PCIE_AXI_REG3_AXI_ADDR0 0x078 +#define PCIE_AXI_BAR0_IB 0x800 +#define PCIE_AXI_BAR1_IB 0x808 +#define PCIE_AXI_NO_BAR_IB 0x810 + +// Register values +#define PCIE_BRIDGE_CLASSCODE 0x06040000 +#define PCIE_LINK_UP 0x01 +#define PCIE_RCBARPIE 0x19 +#define PCIE_AXI_TYPE0 0x80000A +#define PCIE_AXI_TYPE1 0x80000B +#define PCIE_AXI_MEM 0x800002 +#define PCIE_AXI_IO 0x800006 + +#endif diff --git a/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPciHostBridgeLi= b.c b/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPciHostBridgeLib.c new file mode 100644 index 0000000..7e37948 --- /dev/null +++ b/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPciHostBridgeLib.c @@ -0,0 +1,189 @@ +/** @file + PCI Host Bridge support for the Cadence PCIe Root Complex + + Copyright (c) 2017, Linaro Ltd. All rights reserved.
+ Copyright (c) 2017, Cadence Design Systems. All rights reserved. + + This program and the accompanying materials are licensed and made availa= ble + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WI= THOUT + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#include +#include +#include +#include +#include +#include + +#include + +#include +#include + +#pragma pack(1) +typedef struct { + ACPI_HID_DEVICE_PATH AcpiDevicePath; + EFI_DEVICE_PATH_PROTOCOL EndDevicePath; +} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH; +#pragma pack () + +STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath =3D { + { + { + ACPI_DEVICE_PATH, + ACPI_DP, + { + (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)), + (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8) + } + }, + EISA_PNP_ID(0x0A03), // PCI + 0 + }, { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { + END_DEVICE_PATH_LENGTH, + 0 + } + } +}; + +STATIC PCI_ROOT_BRIDGE mRootBridge =3D { + 0, // Segment + 0, // Supports + 0, // Attributes + TRUE, // DmaAbove4G + FALSE, // NoExtendedConfigSpace + FALSE, // ResourceAssigned + EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | // AllocationAttributes + EFI_PCI_HOST_BRIDGE_MEM64_DECODE, + { + // Bus + FixedPcdGet32 (PcdPciBusMin), + FixedPcdGet32 (PcdPciBusMax) + }, { + // Io + FixedPcdGet64 (PcdPciIoBase), + FixedPcdGet64 (PcdPciIoBase) + FixedPcdGet64 (PcdPciIoSize) - 1 + }, { + // Mem + FixedPcdGet32 (PcdPciMmio32Base), + FixedPcdGet32 (PcdPciMmio32Base) + FixedPcdGet32 (PcdPciMmio32Size) - 1 + }, { + // MemAbove4G + FixedPcdGet64 (PcdPciMmio64Base), + FixedPcdGet64 (PcdPciMmio64Base) + FixedPcdGet64 (PcdPciMmio64Size) - 1 + }, { + // PMem + MAX_UINT64, + 0 + }, { + // PMemAbove4G + MAX_UINT64, + 0 + }, + (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath +}; + +/** + Return all the root bridge instances in an array. + + @param Count Return the count of root bridge instances. + + @return All the root bridge instances in an array. + The array should be passed into PciHostBridgeFreeRootBridges() + when it's not used. +**/ +PCI_ROOT_BRIDGE * +EFIAPI +PciHostBridgeGetRootBridges ( + UINTN *Count + ) +{ + *Count =3D 1; + + return &mRootBridge; +} + +/** + Free the root bridge instances array returned from PciHostBridgeGetRootB= ridges(). + + @param Bridges The root bridge instances array. + @param Count The count of the array. +**/ +VOID +EFIAPI +PciHostBridgeFreeRootBridges ( + PCI_ROOT_BRIDGE *Bridges, + UINTN Count + ) +{ +} + +#ifndef MDEPKG_NDEBUG +STATIC CONST CHAR16 mPciHostBridgeLibAcpiAddressSpaceTypeStr[][4] =3D { + L"Mem", L"I/O", L"Bus" +}; +#endif + +/** + Inform the platform that the resource conflict happens. + + @param HostBridgeHandle Handle of the Host Bridge. + @param Configuration Pointer to PCI I/O and PCI memory resource + descriptors. The Configuration contains the reso= urces + for all the root bridges. The resource for each = root + bridge is terminated with END descriptor and an + additional END is appended indicating the end of= the + entire resources. The resource descriptor field + values follow the description in + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL + .SubmitResources(). +**/ +VOID +EFIAPI +PciHostBridgeResourceConflict ( + EFI_HANDLE HostBridgeHandle, + VOID *Configuration + ) +{ + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor; + UINTN RootBridgeIndex; + DEBUG ((DEBUG_ERROR, "PciHostBridge: Resource conflict happens!\n")); + + RootBridgeIndex =3D 0; + Descriptor =3D (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration; + while (Descriptor->Desc =3D=3D ACPI_ADDRESS_SPACE_DESCRIPTOR) { + DEBUG ((DEBUG_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++)); + for (; Descriptor->Desc =3D=3D ACPI_ADDRESS_SPACE_DESCRIPTOR; Descript= or++) { + ASSERT (Descriptor->ResType < + ARRAY_SIZE (mPciHostBridgeLibAcpiAddressSpaceTypeStr) + ); + DEBUG ((DEBUG_ERROR, " %s: Length/Alignment =3D 0x%lx / 0x%lx\n", + mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType= ], + Descriptor->AddrLen, Descriptor->AddrRangeMax + )); + if (Descriptor->ResType =3D=3D ACPI_ADDRESS_SPACE_TYPE_MEM) { + DEBUG ((DEBUG_ERROR, " Granularity/SpecificFlag =3D %ld / %02x= %s\n", + Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag, + ((Descriptor->SpecificFlag & + EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETC= HABLE + ) !=3D 0) ? L" (Prefetchable)" : L"" + )); + } + } + // + // Skip the END descriptor for root bridge + // + ASSERT (Descriptor->Desc =3D=3D ACPI_END_TAG_DESCRIPTOR); + Descriptor =3D (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)( + (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1 + ); + } +} diff --git a/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPciHostBridgeLi= b.inf b/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPciHostBridgeLib.inf new file mode 100644 index 0000000..612fd0e --- /dev/null +++ b/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPciHostBridgeLib.inf @@ -0,0 +1,77 @@ +## @file +# PCI Host Bridge Library instance for Cadence PCIe Root Complex +# +# Copyright (c) 2017, Linaro Ltd. All rights reserved.
+# Copyright (c) 2017, Cadence Design Systems. All rights reserved. +# +# This program and the accompanying materials are licensed and made avail= able +# under the terms and conditions of the BSD License which accompanies this +# distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR +# IMPLIED. +# +# +## + +[Defines] + INF_VERSION =3D 1.25 + BASE_NAME =3D CdnsPciHostBridgeLib + FILE_GUID =3D d92c722c-87f9-4988-843e-dffd6bc8c5e3 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D PciHostBridgeLib|DXE_DRIVER + CONSTRUCTOR =3D HWPciRbInit + +# +# The following information is for reference only and not required by the = build +# tools. +# +# VALID_ARCHITECTURES =3D AARCH64 ARM +# + +[Sources] + CdnsPciHostBridgeLib.c + CdnsPci.c + +[Packages] + ArmPkg/ArmPkg.dec + CadencePkg/CadenceCspPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses] + BaseLib + DebugLib + DevicePathLib + IoLib + MemoryAllocationLib + UefiBootServicesTableLib + +[Pcd] + gArmTokenSpaceGuid.PcdSystemMemoryBase + gArmTokenSpaceGuid.PcdSystemMemorySize + +[FixedPcd] + gArmTokenSpaceGuid.PcdPciBusMin + gArmTokenSpaceGuid.PcdPciBusMax + gArmTokenSpaceGuid.PcdPciIoBase + gArmTokenSpaceGuid.PcdPciIoSize + gArmTokenSpaceGuid.PcdPciIoTranslation + gArmTokenSpaceGuid.PcdPciMmio32Base + gArmTokenSpaceGuid.PcdPciMmio32Size + gArmTokenSpaceGuid.PcdPciMmio32Translation + gArmTokenSpaceGuid.PcdPciMmio64Base + gArmTokenSpaceGuid.PcdPciMmio64Size + gArmTokenSpaceGuid.PcdPciMmio64Translation + gCadenceCspTokenSpaceGuid.PcdPcieRootPortBaseAddress + gCadenceCspTokenSpaceGuid.PcdPcie1RootPortBaseAddress + gCadenceCspTokenSpaceGuid.PcdPciConfigurationSpaceBaseAddress + gCadenceCspTokenSpaceGuid.PcdPciConfigurationSpaceSize + +[Protocols] + gEfiCpuIo2ProtocolGuid ## CONSUMES + +[Depex] + gEfiCpuIo2ProtocolGuid --=20 2.2.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat Apr 27 10:54:59 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zoho.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1496659871109553.9574181061857; Mon, 5 Jun 2017 03:51:11 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id A7FB62095CC6B; Mon, 5 Jun 2017 03:49:50 -0700 (PDT) Received: from mx-sanjose5.cadence.com (keymaster.Cadence.COM [158.140.2.26]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 6597321A6F106 for ; Mon, 5 Jun 2017 03:49:48 -0700 (PDT) Received: from maileu3.global.cadence.com (maileu3.Cadence.COM [10.160.88.99]) by mx-sanjose5.cadence.com (8.13.8+Sun/8.14.4) with ESMTP id v55Aonkh028201; Mon, 5 Jun 2017 03:50:52 -0700 (PDT) Received: from maileu3.global.cadence.com (10.160.88.99) by maileu3.global.cadence.com (10.160.88.99) with Microsoft SMTP Server (TLS) id 15.0.1044.25; Mon, 5 Jun 2017 12:50:44 +0200 Received: from lvloginb.cadence.com (10.165.177.11) by maileu3.global.cadence.com (10.160.88.99) with Microsoft SMTP Server (TLS) id 15.0.1044.25 via Frontend Transport; Mon, 5 Jun 2017 12:50:44 +0200 Received: from lvloginb.cadence.com (localhost [127.0.0.1]) by lvloginb.cadence.com (8.14.4/8.14.4) with ESMTP id v55AohvG000587; Mon, 5 Jun 2017 11:50:43 +0100 Received: (from stelford@localhost) by lvloginb.cadence.com (8.14.4/8.14.4/Submit) id v55Aohfg000586; Mon, 5 Jun 2017 11:50:43 +0100 X-Original-To: edk2-devel@ml01.01.org X-CrossPremisesHeadersFilteredBySendConnector: maileu3.global.cadence.com From: Scott Telford To: , , , , , Date: Mon, 5 Jun 2017 11:50:26 +0100 Message-ID: <1496659828-28702-5-git-send-email-stelford@cadence.com> X-Mailer: git-send-email 2.2.2 In-Reply-To: <1496659828-28702-1-git-send-email-stelford@cadence.com> References: <1496659828-28702-1-git-send-email-stelford@cadence.com> MIME-Version: 1.0 X-OrganizationHeadersPreserved: maileu3.global.cadence.com Subject: [edk2] [staging/cadence-aarch64 PATCH v2 4/6] CadencePkg: Add SEC phase implementation for Cadence CSP platform. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Add SEC phase implementation for Cadence CSP platform configured with a single Cortex-A53 processor and GIC-500. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Scott Telford --- CadencePkg/Sec/AArch64/Arch.c | 25 +++ CadencePkg/Sec/AArch64/ArmCortexA5xHelper.S | 27 +++ CadencePkg/Sec/AArch64/Helper.S | 93 ++++++++ CadencePkg/Sec/AArch64/SecEntryPoint.S | 139 ++++++++++++ CadencePkg/Sec/Sec.c | 335 ++++++++++++++++++++++++= ++++ CadencePkg/Sec/Sec.inf | 85 +++++++ CadencePkg/Sec/SecInternal.h | 105 +++++++++ 7 files changed, 809 insertions(+) create mode 100644 CadencePkg/Sec/AArch64/Arch.c create mode 100644 CadencePkg/Sec/AArch64/ArmCortexA5xHelper.S create mode 100644 CadencePkg/Sec/AArch64/Helper.S create mode 100644 CadencePkg/Sec/AArch64/SecEntryPoint.S create mode 100644 CadencePkg/Sec/Sec.c create mode 100644 CadencePkg/Sec/Sec.inf create mode 100644 CadencePkg/Sec/SecInternal.h diff --git a/CadencePkg/Sec/AArch64/Arch.c b/CadencePkg/Sec/AArch64/Arch.c new file mode 100644 index 0000000..6e7d58e --- /dev/null +++ b/CadencePkg/Sec/AArch64/Arch.c @@ -0,0 +1,25 @@ +/** @file +* +* Copyright (c) 2013, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the B= SD License +* which accompanies this distribution. The full text of the license may = be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#include + +VOID +EFIAPI +ArmSecArchTrustzoneInit ( + VOID + ) +{ + // Do not trap any access to Floating Point and Advanced SIMD in EL3. + ArmWriteCptr (0); +} diff --git a/CadencePkg/Sec/AArch64/ArmCortexA5xHelper.S b/CadencePkg/Sec/A= Arch64/ArmCortexA5xHelper.S new file mode 100644 index 0000000..531de63 --- /dev/null +++ b/CadencePkg/Sec/AArch64/ArmCortexA5xHelper.S @@ -0,0 +1,27 @@ +#-------------------------------------------------------------------------= ----- +# +# Copyright (c) 2013 - 2014, ARM Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BS= D Licese +# which accompanies this distribution. The full text of the license may b= e foun at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. +# +#-------------------------------------------------------------------------= ----- + +#include + +ASM_FUNC(ArmReadCpuExCr) + mrs x0, S3_1_c15_c2_1 + ret + +ASM_FUNC(ArmWriteCpuExCr) + msr S3_1_c15_c2_1, x0 + dsb sy + isb + ret + +ASM_FUNCTION_REMOVE_IF_UNREFERENCED diff --git a/CadencePkg/Sec/AArch64/Helper.S b/CadencePkg/Sec/AArch64/Helpe= r.S new file mode 100644 index 0000000..3b58e12 --- /dev/null +++ b/CadencePkg/Sec/AArch64/Helper.S @@ -0,0 +1,93 @@ +#=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +# Copyright (c) 2011-2014, ARM Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http:#opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +#=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +#include +#include + +#start of the code section +.text +.align 3 + +GCC_ASM_EXPORT(SwitchToNSExceptionLevel1) +GCC_ASM_EXPORT(enter_monitor_mode) +GCC_ASM_EXPORT(return_from_exception) +GCC_ASM_EXPORT(copy_cpsr_into_spsr) +GCC_ASM_EXPORT(set_non_secure_mode) + +// Switch from EL3 to NS-EL1 +ASM_PFX(SwitchToNSExceptionLevel1): + // Now setup our EL1. Controlled by EL2 config on Model + mrs x0, hcr_el2 // Read EL2 Hypervisor configuration Reg= ister + orr x0, x0, #(1 << 31) // Set EL1 to be 64bit + + // Send all interrupts to their respective Exception levels for EL2 + and x0, x0, #~(ARM_HCR_FMO | ARM_HCR_IMO | ARM_HCR_AMO) // Disable = virtual FIQ, IRQ, SError and Abort + msr hcr_el2, x0 // Write back our settings + + msr cptr_el2, xzr // Disable copro traps to EL2 + + msr sctlr_el2, xzr + + // Enable architected timer access + mrs x0, cnthctl_el2 + orr x0, x0, #3 // Enable EL1 access to timers + msr cnthctl_el2, x0 + + mrs x0, cntkctl_el1 + orr x0, x0, #3 // EL0 access to counters + msr cntkctl_el1, x0 + + // Set ID regs + mrs x0, midr_el1 + mrs x1, mpidr_el1 + msr vpidr_el2, x0 + msr vmpidr_el2, x1 + + ret + + +// EL3 on AArch64 is Secure/monitor so this funtion is reduced vs ARMv7 +// we don't need a mode switch, just setup the Arguments and jump. +// x0: Monitor World EntryPoint +// x1: MpId +// x2: SecBootMode +// x3: Secure Monitor mode stack +ASM_PFX(enter_monitor_mode): + mov x4, x0 // Swap EntryPoint and MpId registers + mov x0, x1 + mov x1, x2 + mov x2, x3 + br x4 + +// Put the address in correct ELR_ELx and do a eret. +// We may need to do some config before we change to another Mode. +ASM_PFX(return_from_exception): + msr elr_el3, x0 + eret + +// For AArch64 we need to construct the spsr we want from individual bits = and pieces. +ASM_PFX(copy_cpsr_into_spsr): + mrs x0, CurrentEl // Get the current exception level we are runni= ng at. + mrs x1, SPSel // Which Stack are we using + orr x0, x0, x1 + mrs x1, daif // Which interrupts are enabled + orr x0, x0, x1 + msr spsr_el3, x0 // Write to spsr + ret + +// Get this from platform file. +ASM_PFX(set_non_secure_mode): + msr spsr_el3, x0 + ret + +ASM_FUNCTION_REMOVE_IF_UNREFERENCED diff --git a/CadencePkg/Sec/AArch64/SecEntryPoint.S b/CadencePkg/Sec/AArch6= 4/SecEntryPoint.S new file mode 100644 index 0000000..06bea3c --- /dev/null +++ b/CadencePkg/Sec/AArch64/SecEntryPoint.S @@ -0,0 +1,139 @@ +// +// Copyright (c) 2011-2014, ARM Limited. All rights reserved. +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the = BSD License +// which accompanies this distribution. The full text of the license may= be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR I= MPLIED. +// +// + +#include +#include +#include "SecInternal.h" + +.text +.align 3 + +GCC_ASM_IMPORT(CEntryPoint) +GCC_ASM_IMPORT(ArmPlatformIsPrimaryCore) +GCC_ASM_IMPORT(ArmPlatformGetCorePosition) +GCC_ASM_IMPORT(ArmPlatformSecBootAction) +GCC_ASM_IMPORT(ArmPlatformSecBootMemoryInit) +GCC_ASM_IMPORT(ArmDisableInterrupts) +GCC_ASM_IMPORT(ArmDisableCachesAndMmu) +GCC_ASM_IMPORT(ArmReadMpidr) +GCC_ASM_IMPORT(ArmCallWFE) +GCC_ASM_EXPORT(_ModuleEntryPoint) + +StartupAddr: .8byte ASM_PFX(CEntryPoint) + +ASM_PFX(_ModuleEntryPoint): + +// NOTE: We could be booting from EL3, EL2 or EL1. Need to correctly detect +// and configure the system accordingly. EL2 is default if possible. +// If we started in EL3 we need to switch and run at EL2. +// If we are running at EL2 stay in EL2 +// If we are starting at EL1 stay in EL1. + +// Sec only runs in EL3. Othewise we jump to PEI without changing anything. +// If Sec runs we change to EL2 before switching to PEI. + +// Which EL are we running at? Every EL needs some level of setup... + EL1_OR_EL2_OR_EL3(x0) +1:// If we are at EL1 or EL2 leave SEC for PEI. +2:b ASM_PFX(JumpToPEI) + // If we are at EL3 we need to configure it and switch to EL2 +3:b ASM_PFX(MainEntryPoint) + +ASM_PFX(MainEntryPoint): + // First ensure all interrupts are disabled + bl ASM_PFX(ArmDisableInterrupts) + + // Ensure that the MMU and caches are off + bl ASM_PFX(ArmDisableCachesAndMmu) + + // By default, we are doing a cold boot + mov x10, #ARM_SEC_COLD_BOOT + + // Jump to Platform Specific Boot Action function + bl ASM_PFX(ArmPlatformSecBootAction) + +_IdentifyCpu: + // Identify CPU ID + bl ASM_PFX(ArmReadMpidr) + // Keep a copy of the MpId register value + mov x5, x0 + + // Is it the Primary Core ? + bl ASM_PFX(ArmPlatformIsPrimaryCore) + cmp x0, #1 + // Only the primary core initialize the memory (SMC) + b.eq _InitMem + +_WaitInitMem: + // If we are not doing a cold boot in this case we should assume the Ini= tial Memory to be already initialized + // Otherwise we have to wait the Primary Core to finish the initializati= on + cmp x10, #ARM_SEC_COLD_BOOT + b.ne _SetupSecondaryCoreStack + + // Wait for the primary core to initialize the initial memory (event: BO= OT_MEM_INIT) + bl ASM_PFX(ArmCallWFE) + // Now the Init Mem is initialized, we setup the secondary core stacks + b _SetupSecondaryCoreStack + +_InitMem: + // If we are not doing a cold boot in this case we should assume the Ini= tial Memory to be already initialized + cmp x10, #ARM_SEC_COLD_BOOT + b.ne _SetupPrimaryCoreStack + + // Initialize Init Boot Memory + bl ASM_PFX(ArmPlatformSecBootMemoryInit) + +_SetupPrimaryCoreStack: + // Get the top of the primary stacks (and the base of the secondary stac= ks) + MOV32 (x1, FixedPcdGet32(PcdCPUCoresSecStackBase)) + MOV32 (x2, FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize)) + add x1, x1, x2 + + mov sp, x1 + b _PrepareArguments + +_SetupSecondaryCoreStack: + // Get the top of the primary stacks (and the base of the secondary stac= ks) + MOV32 (x1, FixedPcdGet32(PcdCPUCoresSecStackBase)) + MOV32 (x2, FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize)) + add x6, x1, x2 + + // Get the Core Position + mov x0, x5 + bl ASM_PFX(ArmPlatformGetCorePosition) + // The stack starts at the top of the stack region. Add '1' to the Core = Position to get the top of the stack + add x0, x0, #1 + + // StackOffset =3D CorePos * StackSize + MOV32 (x2, FixedPcdGet32(PcdCPUCoreSecSecondaryStackSize)) + mul x0, x0, x2 + // SP =3D StackBase + StackOffset + add sp, x6, x0 + +_PrepareArguments: + // Move sec startup address into a data register + // Ensure we're jumping to FV version of the code (not boot remapped ali= as) + ldr x3, StartupAddr + + // Jump to SEC C code + // r0 =3D mp_id + // r1 =3D Boot Mode + mov x0, x5 + mov x1, x10 + blr x3 + + ret + +ASM_PFX(JumpToPEI): + MOV32 (x0, FixedPcdGet32(PcdFvBaseAddress)) + blr x0 diff --git a/CadencePkg/Sec/Sec.c b/CadencePkg/Sec/Sec.c new file mode 100644 index 0000000..5b0244e --- /dev/null +++ b/CadencePkg/Sec/Sec.c @@ -0,0 +1,335 @@ +/** @file +* Main file supporting the SEC Phase on ARM Platforms +* +* Copyright (c) 2011-2014, ARM Limited. All rights reserved. +* Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the B= SD License +* which accompanies this distribution. The full text of the license may = be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "SecInternal.h" + +#define SerialPrint(txt) SerialPortWrite ((UINT8*)txt, AsciiStrLen(txt)+1= ); + +#define ARM_GICR_WAKER 0x0014 // GIC Redistributor Wake Register +#define ARM_GICR_IGROUPR0 0x0080 // GIC Redistributor Int Group Reg= 0 +#define ARM_GICR_IGRPMODR0 0x0d00 // GIC Redistributor Int Group Mod= Reg 0 +#define ARM_GICR_ICFGR1 0x0c04 // GIC Redistributor Int Config Re= g 0 + + +VOID +CEntryPoint ( + IN UINTN MpId, + IN UINTN SecBootMode + ) +{ + CHAR8 Buffer[100]; + UINTN CharCount; + UINTN JumpAddress; + + // Invalidate the data cache. Doesn't have to do the Data cache clean. + ArmInvalidateDataCache (); + + // Invalidate Instruction Cache + ArmInvalidateInstructionCache (); + + // Invalidate I & D TLBs + ArmInvalidateTlb (); + + // CPU specific settings + ArmCpuSetup (MpId); + + // Enable Floating Point Coprocessor if supported by the platform + if (FixedPcdGet32 (PcdVFPEnabled)) { + ArmEnableVFP (); + } + + // Initialize peripherals that must be done at the early stage + // Example: Some L2 controller, interconnect, clock, DMC, etc + ArmPlatformSecInitialize (MpId); + + // Primary CPU clears out the SCU tag RAMs, secondaries wait + if (ArmPlatformIsPrimaryCore (MpId) && (SecBootMode =3D=3D ARM_SEC_COLD_= BOOT)) { + if (ArmIsMpCore()) { + // Signal for the initial memory is configured (event: BOOT_MEM_INIT) + ArmCallSEV (); + } + + // SEC phase needs to run library constructors by hand. This assumes w= e are linked against the SerialLib + // In non SEC modules the init call is in autogenerated code. + SerialPortInitialize (); + + // Start talking + if (FixedPcdGetBool (PcdTrustzoneSupport)) { + CharCount =3D AsciiSPrint (Buffer,sizeof (Buffer),"Secure firmware (= version %s built at %a on %a)\n\r", + (CHAR16*)PcdGetPtr(PcdFirmwareVersionString), __TIME__, __DATE__= ); + } else { + CharCount =3D AsciiSPrint (Buffer,sizeof (Buffer),"Boot firmware (ve= rsion %s built at %a on %a)\n\r", + (CHAR16*)PcdGetPtr(PcdFirmwareVersionString), __TIME__, __DATE__= ); + } + SerialPortWrite ((UINT8 *) Buffer, CharCount); + + // Initialize the Debug Agent for Source Level Debugging + InitializeDebugAgent (DEBUG_AGENT_INIT_PREMEM_SEC, NULL, NULL); + SaveAndSetDebugTimerInterrupt (TRUE); + + // Enable the GIC distributor and CPU Interface + // - no other Interrupts are enabled, doesn't have to worry about the= priority. + // - all the cores are in secure state, use secure SGI's + ArmGicEnableDistributor (PcdGet64(PcdGicDistributorBase)); + ArmGicEnableInterruptInterface (PcdGet64(PcdGicInterruptInterfaceBase)= ); + } else { + // Enable the GIC CPU Interface + ArmGicEnableInterruptInterface (PcdGet64(PcdGicInterruptInterfaceBase)= ); + } + + // Enable Full Access to CoProcessors + ArmWriteCpacr (CPACR_CP_FULL_ACCESS); + + // Test if Trustzone is supported on this platform + if (FixedPcdGetBool (PcdTrustzoneSupport)) { + if (ArmIsMpCore ()) { + // Setup SMP in Non Secure world + ArmCpuSetupSmpNonSecure (GET_CORE_ID(MpId)); + } + + // Either we use the Secure Stacks for Secure Monitor (in this case (B= ase =3D=3D 0) && (Size =3D=3D 0)) + // Or we use separate Secure Monitor stacks (but (Base !=3D 0) && (Siz= e !=3D 0)) + ASSERT (((PcdGet64(PcdCPUCoresSecMonStackBase) =3D=3D 0) && (PcdGet32(= PcdCPUCoreSecMonStackSize) =3D=3D 0)) || + ((PcdGet64(PcdCPUCoresSecMonStackBase) !=3D 0) && (PcdGet32(Pc= dCPUCoreSecMonStackSize) !=3D 0))); + + // Enter Monitor Mode + enter_monitor_mode ( + (UINTN)TrustedWorldInitialization, MpId, SecBootMode, + (VOID*) (PcdGet64 (PcdCPUCoresSecMonStackBase) + + (PcdGet32 (PcdCPUCoreSecMonStackSize) * (ArmPlatformGetCorePosit= ion (MpId) + 1))) + ); + } else { + if (ArmPlatformIsPrimaryCore (MpId)) { + SerialPrint ("Trust Zone Configuration is disabled\n\r"); + } + + // With Trustzone support the transition from Sec to Normal world is d= one by return_from_exception(). + // If we want to keep this function call we need to ensure the SVC's S= PSR point to the same Program + // Status Register as the the current one (CPSR). + copy_cpsr_into_spsr (); + + // Call the Platform specific function to execute additional actions i= f required + JumpAddress =3D PcdGet64 (PcdFvBaseAddress); + + ArmPlatformSecExtraAction (MpId, &JumpAddress); + + NonTrustedWorldTransition (MpId, JumpAddress); + } + ASSERT (0); // We must never return from the above function +} + +VOID +TrustedWorldInitialization ( + IN UINTN MpId, + IN UINTN SecBootMode + ) +{ + UINTN JumpAddress; + + //-------------------- Monitor Mode --------------------- + + // Set up Monitor World (Vector Table, etc) + ArmSecureMonitorWorldInitialize (); + + // Transfer the interrupt to Non-secure World + ArmGicV3SetupNonSecure (MpId, PcdGet64(PcdGicDistributorBase), PcdGet64(= PcdGicRedistributorsBase)); + + // Initialize platform specific security policy + ArmPlatformSecTrustzoneInit (MpId); + + // Setup the Trustzone Chipsets + if (SecBootMode =3D=3D ARM_SEC_COLD_BOOT) { + if (ArmPlatformIsPrimaryCore (MpId)) { + if (ArmIsMpCore()) { + // Signal the secondary core the Security settings is done (event:= EVENT_SECURE_INIT) + ArmCallSEV (); + } + } else { + // The secondary cores need to wait until the Trustzone chipsets con= figuration is done + // before switching to Non Secure World + + // Wait for the Primary Core to finish the initialization of the Sec= ure World (event: EVENT_SECURE_INIT) + ArmCallWFE (); + } + } + + // Call the Platform specific function to execute additional actions if = required + JumpAddress =3D PcdGet64 (PcdFvBaseAddress); + + ArmPlatformSecExtraAction (MpId, &JumpAddress); + + // Initialize architecture specific security policy + ArmSecArchTrustzoneInit (); + + // CP15 Secure Configuration Register + ArmWriteScr (PcdGet32 (PcdArmScr)); + + NonTrustedWorldTransition (MpId, JumpAddress); +} + +VOID +NonTrustedWorldTransition ( + IN UINTN MpId, + IN UINTN JumpAddress + ) +{ + // If PcdArmNonSecModeTransition is defined then set this specific mode = to CPSR before the transition + // By not set, the mode for Non Secure World is SVC + if (PcdGet32 (PcdArmNonSecModeTransition) !=3D 0) { + set_non_secure_mode ((ARM_PROCESSOR_MODE)PcdGet32 (PcdArmNonSecModeTra= nsition)); + } + + return_from_exception (JumpAddress); + //-------------------- Non Secure Mode --------------------- + + // PEI Core should always load and never return + ASSERT (FALSE); +} + +/* + * This function configures the all interrupts to be Non-secure. + * + */ +VOID +EFIAPI +ArmGicV3SetupNonSecure ( + IN UINTN MpId, + IN INTN GicDistributorBase, + IN INTN GicRedistributorsBase + ) +{ + UINTN InterruptId; + UINTN Index; + UINTN MaxInterrupts; + UINT32 WakeR; + + // Set priority Mask so that no interrupts get through to CPU + ArmGicV3SetPriorityMask (0); + + // Clear ProcessorSleep bit in GICR_WAKER and wait for ChildrenAsleep to= clear + WakeR =3D MmioRead32 (GicRedistributorsBase + ARM_GICR_WAKER); + WakeR &=3D ~(1 << 1); + MmioWrite32 (GicRedistributorsBase + ARM_GICR_WAKER, WakeR); + do { + WakeR =3D MmioRead32 (GicRedistributorsBase + ARM_GICR_WAKER); + } while ((WakeR & (1 << 2))); + + // Set PPIs to Non-secure Group 1 IRQ + MmioWrite32 (GicRedistributorsBase + ARM_GICR_SGI_PPI_FRAME_SIZE + ARM_G= ICR_IGROUPR0, 0xffff0000); + + InterruptId =3D ArmGicV3AcknowledgeInterrupt(); + MaxInterrupts =3D ArmGicGetMaxNumInterrupts (GicDistributorBase); + + // Only try to clear valid interrupts. Ignore spurious interrupts. + while ((InterruptId & 0x3FF) < MaxInterrupts) { + // Some of the SGI's are still pending, read Ack register and send End= of Interrupt Signal + ArmGicV3EndOfInterrupt (InterruptId); + + // Next + InterruptId =3D ArmGicV3AcknowledgeInterrupt(); + } + + // Only the primary core should set the Non Secure bit to the SPIs (Shar= ed Peripheral Interrupt). + if (ArmPlatformIsPrimaryCore (MpId)) { + // Ensure all GIC interrupts are Non-Secure + for (Index =3D 0; Index < (MaxInterrupts / 32); Index++) { + MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), 0xff= ffffff); + } + } else { + // The secondary cores only set the Non Secure bit to their banked PPIs + MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR, 0xffffffff); + } + + // Ensure all interrupts can get through the priority mask + ArmGicV3SetPriorityMask (0xff); +} + +// +// Previously in ArmCpuLib: +// + +VOID +ArmCpuSetup ( + IN UINTN MpId + ) +{ + // Check if Architectural Timer frequency is valid number (should not be= 0) + ASSERT (PcdGet32 (PcdArmArchTimerFreqInHz)); + ASSERT (ArmIsArchTimerImplemented () !=3D 0); + + // Note: System Counter frequency can only be set in Secure privileged m= ode, + // if security extensions are implemented. + ArmGenericTimerSetTimerFreq (PcdGet32 (PcdArmArchTimerFreqInHz)); + + if (ArmIsMpCore ()) { + // Turn on SMP coherency + ArmSetCpuExCrBit (A5X_FEATURE_SMP); + } + + // + // If CPU is CortexA57 r0p0 apply Errata workarounds + // + if ((ArmReadMidr () & ((ARM_CPU_TYPE_MASK << 4) | ARM_CPU_REV_MASK)) =3D= =3D + ((ARM_CPU_TYPE_A57 << 4) | ARM_CPU_REV(0,0))) { + + // Errata 806969: DisableLoadStoreWB (1ULL << 49) + // Errata 813420: Execute Data Cache clean as Data Cache clean/invalid= ate (ULL << 44) + // Errata 814670: disable DMB nullification (1ULL << 58) + ArmSetCpuActlrBit ( (1ULL << 49) | (1ULL << 44) | (1ULL << 58) ); + } +} + +VOID +ArmCpuSetupSmpNonSecure ( + IN UINTN MpId + ) +{ +} + +VOID +EFIAPI +ArmSetCpuExCrBit ( + IN UINT64 Bits + ) +{ + UINT64 Value; + Value =3D ArmReadCpuExCr (); + Value |=3D Bits; + ArmWriteCpuExCr (Value); +} + +VOID +EFIAPI +ArmUnsetCpuExCrBit ( + IN UINT64 Bits + ) +{ + UINT64 Value; + Value =3D ArmReadCpuExCr (); + Value &=3D ~Bits; + ArmWriteCpuExCr (Value); +} diff --git a/CadencePkg/Sec/Sec.inf b/CadencePkg/Sec/Sec.inf new file mode 100644 index 0000000..cf32f34 --- /dev/null +++ b/CadencePkg/Sec/Sec.inf @@ -0,0 +1,85 @@ +#/** @file +# SEC - Reset vector code that jumps to C and starts the PEI phase +# +# (C) Copyright 2015 Hewlett-Packard Development Company, L.P.
+# Copyright (c) 2011-2013, ARM Limited. All rights reserved. +# Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +#**/ + +[Defines] + INF_VERSION =3D 1.25 + BASE_NAME =3D ArmPlatformSec + FILE_GUID =3D 424b4f2e-ec82-4c57-a188-253060be8a69 + MODULE_TYPE =3D SEC + VERSION_STRING =3D 1.0 + +[Sources] + Sec.c + +[Sources.AARCH64] + AArch64/Arch.c + AArch64/Helper.S + AArch64/SecEntryPoint.S + AArch64/ArmCortexA5xHelper.S | GCC + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + CadencePkg/CadenceCspPkg.dec + +[LibraryClasses] + ArmLib + ArmGenericTimerCounterLib + ArmPlatformLib + ArmPlatformSecLib + ArmTrustedMonitorLib + BaseLib + DebugLib + DebugAgentLib + IoLib + ArmGicLib + PcdLib + PrintLib + SerialPortLib + +[Pcd] + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString + +[FixedPcd.common] + + gArmTokenSpaceGuid.PcdTrustzoneSupport + gArmTokenSpaceGuid.PcdVFPEnabled + + gArmTokenSpaceGuid.PcdArmScr + gArmTokenSpaceGuid.PcdArmNonSecModeTransition + gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz + + gArmTokenSpaceGuid.PcdSecureFvBaseAddress + gArmTokenSpaceGuid.PcdSecureFvSize + + gArmTokenSpaceGuid.PcdFvBaseAddress + + gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase + gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize + gArmPlatformTokenSpaceGuid.PcdCPUCoreSecSecondaryStackSize + gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase + gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize + + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase + gArmTokenSpaceGuid.PcdGicDistributorBase + gArmTokenSpaceGuid.PcdGicRedistributorsBase + +[FixedPcd.ARM] + gArmTokenSpaceGuid.PcdArmNsacr + diff --git a/CadencePkg/Sec/SecInternal.h b/CadencePkg/Sec/SecInternal.h new file mode 100644 index 0000000..221eb57 --- /dev/null +++ b/CadencePkg/Sec/SecInternal.h @@ -0,0 +1,105 @@ +/** @file +* Main file supporting the SEC Phase on ARM PLatforms +* +* Copyright (c) 2011-2013, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the B= SD License +* which accompanies this distribution. The full text of the license may = be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#ifndef __SEC_H__ +#define __SEC_H__ + +#include +#include +#include +#include +#include +#include +#include + +#define IS_ALIGNED(Address, Align) (((UINTN)Address & (Align-1)) =3D=3D 0) + +VOID +TrustedWorldInitialization ( + IN UINTN MpId, + IN UINTN SecBootMode + ); + +VOID +NonTrustedWorldTransition ( + IN UINTN MpId, + IN UINTN JumpAddress + ); + +VOID +ArmGicV3SetupNonSecure ( + IN UINTN MpId, + IN INTN GicDistributorBase, + IN INTN GicRedistributorsBase +); + +VOID +enter_monitor_mode ( + IN UINTN MonitorEntryPoint, + IN UINTN MpId, + IN UINTN SecBootMode, + IN VOID* MonitorStackBase + ); + +VOID +return_from_exception ( + IN UINTN NonSecureBase + ); + +VOID +copy_cpsr_into_spsr ( + VOID + ); + +VOID +set_non_secure_mode ( + IN ARM_PROCESSOR_MODE Mode + ); + +VOID +SecCommonExceptionEntry ( + IN UINT32 Entry, + IN UINTN LR + ); + +VOID +EFIAPI +ArmSecArchTrustzoneInit ( + VOID + ); + +VOID +ArmCpuSetup ( + IN UINTN MpId + ); + +VOID +ArmCpuSetupSmpNonSecure ( + IN UINTN MpId + ); + +VOID +EFIAPI +ArmSetCpuExCrBit ( + IN UINT64 Bits +); + +VOID +EFIAPI +ArmUnsetCpuExCrBit ( + IN UINT64 Bits +); + +#endif --=20 2.2.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat Apr 27 10:54:59 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zoho.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1496659874137456.7991104326629; Mon, 5 Jun 2017 03:51:14 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id E024D21967BC5; Mon, 5 Jun 2017 03:49:51 -0700 (PDT) Received: from mx-sanjose5.cadence.com (keymaster.Cadence.COM [158.140.2.26]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3C5C921C93EF6 for ; Mon, 5 Jun 2017 03:49:50 -0700 (PDT) Received: from maileu3.global.cadence.com (maileu3.Cadence.COM [10.160.88.99]) by mx-sanjose5.cadence.com (8.13.8+Sun/8.14.4) with ESMTP id v55Aonki028201; Mon, 5 Jun 2017 03:50:52 -0700 (PDT) Received: from maileu3.global.cadence.com (10.160.88.99) by maileu3.global.cadence.com (10.160.88.99) with Microsoft SMTP Server (TLS) id 15.0.1044.25; Mon, 5 Jun 2017 12:50:44 +0200 Received: from lvloginb.cadence.com (10.165.177.11) by maileu3.global.cadence.com (10.160.88.99) with Microsoft SMTP Server (TLS) id 15.0.1044.25 via Frontend Transport; Mon, 5 Jun 2017 12:50:44 +0200 Received: from lvloginb.cadence.com (localhost [127.0.0.1]) by lvloginb.cadence.com (8.14.4/8.14.4) with ESMTP id v55AohFn000594; Mon, 5 Jun 2017 11:50:43 +0100 Received: (from stelford@localhost) by lvloginb.cadence.com (8.14.4/8.14.4/Submit) id v55AohEk000592; Mon, 5 Jun 2017 11:50:43 +0100 X-Original-To: edk2-devel@ml01.01.org X-CrossPremisesHeadersFilteredBySendConnector: maileu3.global.cadence.com From: Scott Telford To: , , , , , Date: Mon, 5 Jun 2017 11:50:27 +0100 Message-ID: <1496659828-28702-6-git-send-email-stelford@cadence.com> X-Mailer: git-send-email 2.2.2 In-Reply-To: <1496659828-28702-1-git-send-email-stelford@cadence.com> References: <1496659828-28702-1-git-send-email-stelford@cadence.com> MIME-Version: 1.0 X-OrganizationHeadersPreserved: maileu3.global.cadence.com Subject: [edk2] [staging/cadence-aarch64 PATCH v2 5/6] CadencePkg: Add ACPI tables for Cadence CSP platform. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Add ACPI tables for Cadence CSP platform configured with a single Cortex-A53, GIC-500, Cadence UART and Cadence PCIe Root Complex. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Scott Telford --- CadencePkg/AcpiTables/AcpiTables.inf | 49 +++++ CadencePkg/AcpiTables/CspPlatform.h | 46 +++++ CadencePkg/AcpiTables/Dsdt.asl | 338 +++++++++++++++++++++++++++++++= ++++ CadencePkg/AcpiTables/Fadt.aslc | 87 +++++++++ CadencePkg/AcpiTables/Gtdt.aslc | 80 +++++++++ CadencePkg/AcpiTables/Madt.aslc | 71 ++++++++ CadencePkg/AcpiTables/Mcfg.aslc | 76 ++++++++ CadencePkg/AcpiTables/Spcr.aslc | 89 +++++++++ 8 files changed, 836 insertions(+) create mode 100644 CadencePkg/AcpiTables/AcpiTables.inf create mode 100644 CadencePkg/AcpiTables/CspPlatform.h create mode 100644 CadencePkg/AcpiTables/Dsdt.asl create mode 100644 CadencePkg/AcpiTables/Fadt.aslc create mode 100644 CadencePkg/AcpiTables/Gtdt.aslc create mode 100644 CadencePkg/AcpiTables/Madt.aslc create mode 100644 CadencePkg/AcpiTables/Mcfg.aslc create mode 100644 CadencePkg/AcpiTables/Spcr.aslc diff --git a/CadencePkg/AcpiTables/AcpiTables.inf b/CadencePkg/AcpiTables/A= cpiTables.inf new file mode 100644 index 0000000..7c18cb4 --- /dev/null +++ b/CadencePkg/AcpiTables/AcpiTables.inf @@ -0,0 +1,49 @@ +## @file +# +# ACPI table data and ASL sources required to boot the platform. +# +# Copyright (c) 2014-2016, ARM Ltd. All rights reserved. +# Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D CspAcpiTables + FILE_GUID =3D 7E374E25-8E01-4FEE-87F2-390C23C606CD + MODULE_TYPE =3D USER_DEFINED + VERSION_STRING =3D 1.0 + +[Sources] + Dsdt.asl + Spcr.aslc + Fadt.aslc + Gtdt.aslc + Madt.aslc + Mcfg.aslc + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + CadencePkg/CadenceCspPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + + +[FixedPcd] + gArmTokenSpaceGuid.PcdGicDistributorBase + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase + gArmTokenSpaceGuid.PcdGicRedistributorsBase + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum diff --git a/CadencePkg/AcpiTables/CspPlatform.h b/CadencePkg/AcpiTables/Cs= pPlatform.h new file mode 100644 index 0000000..d3afe9e --- /dev/null +++ b/CadencePkg/AcpiTables/CspPlatform.h @@ -0,0 +1,46 @@ +/** @file +* +* Copyright (c) 2011-2015, ARM Limited. All rights reserved. +* Copyright (c) 2015, Hisilicon Limited. All rights reserved. +* Copyright (c) 2015, Linaro Limited. All rights reserved. +* Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the B= SD License +* which accompanies this distribution. The full text of the license may = be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +* +**/ + + +#ifndef _CSP_PLATFORM_H_ +#define _CSP_PLATFORM_H_ + +// +// ACPI table information used to initialize tables. +// +#define EFI_ACPI_CSP_OEM_ID 'C','D','N','S',' ',' ' // OEMID 6= bytes long +#define EFI_ACPI_CSP_OEM_TABLE_ID SIGNATURE_64('C','S','P',' ',' ',' '= ,' ',' ') // OEM table id 8 bytes long +#define EFI_ACPI_CSP_OEM_REVISION 0x00000002 +#define EFI_ACPI_CSP_CREATOR_ID SIGNATURE_32('C','D','N','S') +#define EFI_ACPI_CSP_CREATOR_REVISION 0x00000001 + +// A macro to initialise the common header part of EFI ACPI tables as defi= ned by +// EFI_ACPI_DESCRIPTION_HEADER structure. +#define ARM_ACPI_HEADER(Signature, Type, Revision) { \ + Signature, /* UINT32 Signature */ \ + sizeof (Type), /* UINT32 Length */ \ + Revision, /* UINT8 Revision */ \ + 0, /* UINT8 Checksum */ \ + { EFI_ACPI_CSP_OEM_ID }, /* UINT8 OemId[6] */ \ + EFI_ACPI_CSP_OEM_TABLE_ID, /* UINT64 OemTableId */ \ + EFI_ACPI_CSP_OEM_REVISION, /* UINT32 OemRevision */ \ + EFI_ACPI_CSP_CREATOR_ID, /* UINT32 CreatorId */ \ + EFI_ACPI_CSP_CREATOR_REVISION /* UINT32 CreatorRevision */ \ + } + +#endif diff --git a/CadencePkg/AcpiTables/Dsdt.asl b/CadencePkg/AcpiTables/Dsdt.asl new file mode 100644 index 0000000..88c4ab0 --- /dev/null +++ b/CadencePkg/AcpiTables/Dsdt.asl @@ -0,0 +1,338 @@ +/* +* Copyright (c) 2013, Al Stone +* Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* 1. Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED +* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +* NB: This License is also known as the "BSD 2-Clause License". +* +* +* +*/ + +DefinitionBlock ( + "dsdt.aml", // output filename + "DSDT", // table signature + 2, // DSDT compliance revision + "CDNS", // OEM ID + "CDNSCSP0", // table ID + 0x00000001) // OEM revision +{ + Scope (\_SB) + { + Method (_OSC, 4, NotSerialized) + { + /* Platform-Wide OSPM Capabilities */ + If(LEqual(Arg0,ToUUID("0811B06E-4A27-44F9-8D60-3CBBC22E7B48"))) + { + /* APEI support unconditionally */ + Return (Arg3) + } Else { + CreateDWordField (Arg3, Zero, CDW1) + /* Set invalid UUID error bit */ + Or (CDW1, 0x04, CDW1) + Return (Arg3) + } + } + + // + // One Emulated aarch64 CPU with 1 core + // + Device(CPU0) { // Cluster 0, Cpu 0 + Name(_HID, "ACPI0007") + Name(_UID, 0) + } + // Cadence UART + Device(COM0) { + Name(_HID, "CDNS0001") + Name(_UID, 0) + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0xFD000000, 0x1000) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 0x20 } + }) + } + + //Legacy IRQs + Name (PR04, Package (0x04) + { + Package (0x04) + { + 0xFFFF, Zero, LNKA, Zero + }, + Package (0x04) + { + 0xFFFF, Zero, LNKB, Zero + }, + Package (0x04) + { + 0xFFFF, Zero, LNKC, Zero + }, + Package (0x04) + { + 0xFFFF, Zero, LNKD, Zero + } + }) + Device (LNKA) + { + Name (_HID, Eisaid ("PNP0C0F")) + Name (_UID, 1) + Name(_PRS, ResourceTemplate(){ + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive, , ,) { 4= 6 } + }) + Method(_DIS) {} + Method(_CRS) { Return (_PRS) } + Method(_SRS, 1) {} + } + Device (LNKB) + { + Name (_HID, Eisaid ("PNP0C0F")) + Name (_UID, 1) + Name(_PRS, ResourceTemplate(){ + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive, , ,) { 4= 6 } + }) + Method(_DIS) {} + Method(_CRS) { Return (_PRS) } + Method(_SRS, 1) {} + } + Device (LNKC) + { + Name (_HID, Eisaid ("PNP0C0F")) + Name (_UID, 1) + Name(_PRS, ResourceTemplate(){ + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive, , ,) { 4= 6 } + }) + Method(_DIS) {} + Method(_CRS) { Return (_PRS) } + Method(_SRS, 1) {} + } + Device (LNKD) + { + Name (_HID, Eisaid ("PNP0C0F")) + Name (_UID, 1) + Name(_PRS, ResourceTemplate(){ + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive, , ,) { 4= 6 } + }) + Method(_DIS) {} + Method(_CRS) { Return (_PRS) } + Method(_SRS, 1) {} + } + + Device (PCI0) + { + Name (_HID, EisaId ("PNP0A08")) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0A03")) // _CID: Compatible ID + Name (_SEG, 0x00) // _SEG: PCI Segment + Name (_BBN, 0x00) // _BBN: BIOS Bus Number + Name(_ADR,Zero) + NAME(_CCA,0) // Cache Coherent Architecture =3D FALSE + // Name(_CBA,0x50000000) + + // + // OS Control Handoff + // + Name(SUPP, Zero) // PCI _OSC Support Field value + Name(CTRL, Zero) // PCI _OSC Control Field value + Method (_OSC, 4, Serialized) // _OSC: Operating System Capabilities + { + Store (Arg3, Local0) + CreateDWordField (Local0, Zero, CDW1) + CreateDWordField (Local0, 0x04, CDW2) + CreateDWordField (Local0, 0x08, CDW3) + // Save Capabilities DWord2 & 3 + Store(CDW2,SUPP) + Store(CDW3,CTRL) + // Never allow SHPC (no SHPC controller in this system) + And(CTRL,0x1D,CTRL) + If(LNotEqual(Arg1,One)) { // Unknown revision + Or(CDW1,0x08,CDW1) + } + // Update DWORD3 in the buffer + Store(CTRL,CDW3) + Return (Local0) + } + + + Name (_UID, Zero) // _UID: Unique ID + Device (RP01) + { + Name (_ADR, 0x001C0000) // _ADR: Address + OperationRegion (PXCS, PCI_Config, Zero, 0x0380) + Field (PXCS, AnyAcc, NoLock, Preserve) + { + VDID, 32, + Offset (0x19), + SCBN, 8, + Offset (0x50), + L0SE, 1, + , 3, + LDIS, 1, + Offset (0x51), + Offset (0x52), + , 13, + LASX, 1, + Offset (0x54), + , 6, + HPCE, 1, + Offset (0x5A), + ABPX, 1, + , 2, + PDCX, 1, + , 2, + PDSX, 1, + Offset (0x5B), + Offset (0x60), + Offset (0x62), + PSPX, 1, + PMEP, 1, + Offset (0xA4), + D3HT, 2, + Offset (0xD8), + , 30, + HPEX, 1, + PMEX, 1, + Offset (0xE2), + , 2, + L23E, 1, + L23R, 1, + Offset (0x324), + , 3, + LEDM, 1 + } + + Field (PXCS, AnyAcc, NoLock, WriteAsZeros) + { + Offset (0xDC), + , 30, + HPSX, 1, + PMSX, 1 + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Name (LTRV, Package (0x04) + { + Zero, + Zero, + Zero, + Zero + }) + + Name (OPTS, Zero) + + Name (RPAV, Zero) + + Method (_REG, 2, NotSerialized) // _REG: Region Availability + { + If (LAnd (LEqual (Arg0, 0x02), LEqual (Arg1, One))) + { + Store (One, RPAV) + } + } + + Method (HPME, 0, Serialized) + { + If (LOr (PSPX, PMEP)) + { + Store (PMEX, Local1) + Store (Zero, PMEX) + Sleep (0x32) + Store (One, PSPX) + Sleep (0x32) + If (PSPX) + { + Store (One, PSPX) + Sleep (0x32) + } + Store (Local1, PMEX) + } + If (PMSX) + { + Store (0xC8, Local0) + While (Local0) + { + Store (One, PMSX) + If (PMSX) + { + Decrement (Local0) + } + Else + { + Store (Zero, Local0) + } + } + } + } + } + Name(_PRT, Package() + { + Package(){0x0000ffff, 0, LNKA, 0}, // Slot 1, INTA + Package(){0x0000ffff, 1, LNKB, 0}, // Slot 1, INTB + Package(){0x0000ffff, 2, LNKC, 0}, // Slot 1, INTC + Package(){0x0000ffff, 3, LNKD, 0}, // Slot 1, INTD + }) + Method (_CRS, 0, Serialized) + { + Name (PRT0, ResourceTemplate () + { + /* bus number is from 0 - 1f */ + WordBusNumber (ResourceConsumer, MinFixed, MaxFixed, SubDecode, + 0x0000, + 0x0000, + 0x001f, + 0x0000, + 0x0020) + DWordMemory (ResourceConsumer, PosDecode, MinFixed, MaxFixed, Ca= cheable, ReadWrite, + 0x00000000, + 0x42000000, + 0x42FFFFFF, + 0x00000000, + 0x01000000) + DWordIO (ResourceConsumer, MinFixed, MaxFixed, PosDecode, Entire= Range, + 0x00000000, + 0x43000000, + 0x43FFFFFF, + 0x00000000, + 0x01000000) + }) + Return (PRT0) + } + } + + // Device(COM0) { + // Name(_HID, "ARMH0011") + // Name(_CID, "PL011") + // Name(_UID, Zero) + + // Name(_CRS, ResourceTemplate() { + // Memory32Fixed(ReadWrite, 0x1c090000, 0x1000) + // Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 0x25= } + // }) + // } + } +} diff --git a/CadencePkg/AcpiTables/Fadt.aslc b/CadencePkg/AcpiTables/Fadt.a= slc new file mode 100644 index 0000000..2035884 --- /dev/null +++ b/CadencePkg/AcpiTables/Fadt.aslc @@ -0,0 +1,87 @@ +/** @file +* Fixed ACPI Description Table (FADT) +* +* Copyright (c) 2012 - 2016, ARM Limited. All rights reserved. +* Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the B= SD License +* which accompanies this distribution. The full text of the license may = be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#include "CspPlatform.h" +#include +#include + +EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE Fadt =3D { + ARM_ACPI_HEADER ( + EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE, + EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION + ), + 0, = // UINT32 FirmwareCtrl + 0, = // UINT32 Dsdt + EFI_ACPI_RESERVED_BYTE, = // UINT8 Reserved0 + EFI_ACPI_6_1_PM_PROFILE_UNSPECIFIED, = // UINT8 PreferredPmProfile + 0, = // UINT16 SciInt + 0, = // UINT32 SmiCmd + 0, = // UINT8 AcpiEnable + 0, = // UINT8 AcpiDisable + 0, = // UINT8 S4BiosReq + 0, = // UINT8 PstateCnt + 0, = // UINT32 Pm1aEvtBlk + 0, = // UINT32 Pm1bEvtBlk + 0, = // UINT32 Pm1aCntBlk + 0, = // UINT32 Pm1bCntBlk + 0, = // UINT32 Pm2CntBlk + 0, = // UINT32 PmTmrBlk + 0, = // UINT32 Gpe0Blk + 0, = // UINT32 Gpe1Blk + 0, = // UINT8 Pm1EvtLen + 0, = // UINT8 Pm1CntLen + 0, = // UINT8 Pm2CntLen + 0, = // UINT8 PmTmrLen + 0, = // UINT8 Gpe0BlkLen + 0, = // UINT8 Gpe1BlkLen + 0, = // UINT8 Gpe1Base + 0, = // UINT8 CstCnt + 0, = // UINT16 PLvl2Lat + 0, = // UINT16 PLvl3Lat + 0, = // UINT16 FlushSize + 0, = // UINT16 FlushStride + 0, = // UINT8 DutyOffset + 0, = // UINT8 DutyWidth + 0, = // UINT8 DayAlrm + 0, = // UINT8 MonAlrm + 0, = // UINT8 Century + 0, = // UINT16 IaPcBootArch + 0, = // UINT8 Reserved1 + EFI_ACPI_6_1_HW_REDUCED_ACPI | EFI_ACPI_6_1_LOW_POWER_S0_IDLE_CAPABLE, = // UINT32 Flags + NULL_GAS, = // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE ResetReg + 0, = // UINT8 ResetValue + 0, //EFI_ACPI_6_1_ARM_PSCI_COMPLIANT, = // UINT16 ArmBootArchFlags + EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, = // UINT8 MinorRevision + 0, = // UINT64 XFirmwareCtrl + 0, = // UINT64 XDsdt + NULL_GAS, = // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk + NULL_GAS, = // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk + NULL_GAS, = // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk + NULL_GAS, = // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk + NULL_GAS, = // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk + NULL_GAS, = // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk + NULL_GAS, = // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk + NULL_GAS, = // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk + NULL_GAS, = // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE SleepControlReg + NULL_GAS = // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE SleepStatusReg +}; + +// +// Reference the table being generated to prevent the optimizer from remov= ing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable =3D &Fadt; diff --git a/CadencePkg/AcpiTables/Gtdt.aslc b/CadencePkg/AcpiTables/Gtdt.a= slc new file mode 100644 index 0000000..ddc88d6 --- /dev/null +++ b/CadencePkg/AcpiTables/Gtdt.aslc @@ -0,0 +1,80 @@ +/** @file +* Generic Timer Description Table (GTDT) +* +* Copyright (c) 2012 - 2016, ARM Limited. All rights reserved. +* Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the B= SD License +* which accompanies this distribution. The full text of the license may = be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#include "CspPlatform.h" +#include +#include +#include + +#define GTDT_GLOBAL_FLAGS_MAPPED EFI_ACPI_6_1_GTDT_GLOBAL_FLAG_MEMORY= _MAPPED_BLOCK_PRESENT +#define GTDT_GLOBAL_FLAGS_NOT_MAPPED 0 +#define GTDT_GLOBAL_FLAGS_EDGE EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_INTERR= UPT_MODE +#define GTDT_GLOBAL_FLAGS_LEVEL 0 + +// Note: We could have a build flag that switches between memory mapped/no= n-memory mapped timer +#ifdef SYSTEM_TIMER_BASE_ADDRESS + #define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_MAPPED | GTDT_G= LOBAL_FLAGS_LEVEL) +#else + #define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_NOT_MAPPED | GT= DT_GLOBAL_FLAGS_LEVEL) + #define SYSTEM_TIMER_BASE_ADDRESS 0xFFFFFFFFFFFFFFFF +#endif + +#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INT= ERRUPT_MODE +#define GTDT_TIMER_LEVEL_TRIGGERED 0 +#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INT= ERRUPT_POLARITY +#define GTDT_TIMER_ACTIVE_HIGH 0 + +#define GTDT_GTIMER_FLAGS (GTDT_TIMER_ACTIVE_LOW | GTDT_TIMER_LE= VEL_TRIGGERED) + +#pragma pack (1) + +typedef struct { + EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt; + EFI_ACPI_6_1_GTDT_GT_BLOCK_STRUCTURE GtBlock; + EFI_ACPI_6_1_GTDT_GT_BLOCK_TIMER_STRUCTURE Frames[0]; + EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE Watchdogs[0]; + } GENERIC_TIMER_DESCRIPTION_TABLE; + +#pragma pack () + + GENERIC_TIMER_DESCRIPTION_TABLE Gtdt =3D { + { + ARM_ACPI_HEADER( + EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE, + GENERIC_TIMER_DESCRIPTION_TABLE, + EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION + ), + SYSTEM_TIMER_BASE_ADDRESS, // UINT64 PhysicalAdd= ress + 0, // UINT32 Reserved + FixedPcdGet32 (PcdArmArchTimerSecIntrNum), // UINT32 SecurePL1Ti= merGSIV + GTDT_GTIMER_FLAGS, // UINT32 SecurePL1Ti= merFlags + FixedPcdGet32 (PcdArmArchTimerIntrNum), // UINT32 NonSecurePL= 1TimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL= 1TimerFlags + FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), // UINT32 VirtualTime= rGSIV + GTDT_GTIMER_FLAGS, // UINT32 VirtualTime= rFlags + FixedPcdGet32 (PcdArmArchTimerHypIntrNum), // UINT32 NonSecurePL= 2TimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL= 2TimerFlags + SYSTEM_TIMER_BASE_ADDRESS, // UINT64 CntReadBase= PhysicalAddress + 0, // UINT32 PlatformTim= erCount + sizeof (EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE) // UINT32 Plat= fromTimerOffset + } + }; + +// +// Reference the table being generated to prevent the optimizer from remov= ing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable =3D &Gtdt; diff --git a/CadencePkg/AcpiTables/Madt.aslc b/CadencePkg/AcpiTables/Madt.a= slc new file mode 100644 index 0000000..68903e0 --- /dev/null +++ b/CadencePkg/AcpiTables/Madt.aslc @@ -0,0 +1,71 @@ +/** @file +* Multiple APIC Description Table (MADT) +* +* Copyright (c) 2012 - 2015, ARM Limited. All rights reserved. +* Copyright (c) 2016 Linaro Ltd. All rights reserved. +* Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the B= SD License +* which accompanies this distribution. The full text of the license may = be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#include "CspPlatform.h" +#include +#include +#include +#include + +// +// Multiple APIC Description Table +// +#pragma pack (1) + +typedef struct { + EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; + EFI_ACPI_6_1_GIC_STRUCTURE GicInterfaces[1]; + EFI_ACPI_6_1_GIC_DISTRIBUTOR_STRUCTURE GicDistributor; + EFI_ACPI_6_1_GICR_STRUCTURE Gicr; +} FVP_MULTIPLE_APIC_DESCRIPTION_TABLE; + +#pragma pack () + +FVP_MULTIPLE_APIC_DESCRIPTION_TABLE Madt =3D { + { + ARM_ACPI_HEADER ( + EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, + FVP_MULTIPLE_APIC_DESCRIPTION_TABLE, + EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION + ), + // + // MADT specific fields + // + 0, // LocalApicAddress + 0, // Flags + }, + { + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( + 0, 0, GET_MPID(0, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, 0, + 0, 0, 0x19, 0, 0), + }, + EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet64 (PcdGicDistributorBas= e), 0, 3), + /* GIC Redistributor */ + { + EFI_ACPI_6_1_GICR, // UINT8 Type + sizeof(EFI_ACPI_6_1_GICR_STRUCTURE), // UINT8 Length + EFI_ACPI_RESERVED_WORD, // UINT16 Reserved + FixedPcdGet64 (PcdGicRedistributorsBase), // UINT64 DiscoveryRangeBas= eAddress + 0x00200000, // UINT32 DiscoveryRangeLen= gth + } +}; + +// +// Reference the table being generated to prevent the optimizer from remov= ing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable =3D &Madt; diff --git a/CadencePkg/AcpiTables/Mcfg.aslc b/CadencePkg/AcpiTables/Mcfg.a= slc new file mode 100644 index 0000000..483258f --- /dev/null +++ b/CadencePkg/AcpiTables/Mcfg.aslc @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2013 Linaro Limited + * Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved. + * + * All rights reserved. This program and the accompanying materials + * are made available under the terms of the BSD License which accompanies + * this distribution, and is available at + * http://opensource.org/licenses/bsd-license.php + * + * Contributors: + * Yi Li - yi.li@linaro.org +*/ +#include "CspPlatform.h" +#include +#include +#include +#include + +#define ACPI_5_0_MCFG_VERSION 0x1 + +#pragma pack(1) +typedef struct +{ + UINT64 ullBaseAddress; + UINT16 usSegGroupNum; + UINT8 ucStartBusNum; + UINT8 ucEndBusNum; + UINT32 Reserved2; +}EFI_ACPI_5_0_MCFG_CONFIG_STRUCTURE; + +typedef struct +{ + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT64 Reserved1; +}EFI_ACPI_5_0_MCFG_TABLE_CONFIG; + +typedef struct +{ + EFI_ACPI_5_0_MCFG_TABLE_CONFIG Acpi_Table_Mcfg; + EFI_ACPI_5_0_MCFG_CONFIG_STRUCTURE Config_Structure[2]; +}EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE; +#pragma pack() + +EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE Mcfg=3D +{ + { + { + EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_AD= DRESS_DESCRIPTION_TABLE_SIGNATURE, + sizeof (EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE= _TABLE), + ACPI_5_0_MCFG_VERSION, + 0x00, // Check= sum will be updated at runtime + {EFI_ACPI_CSP_OEM_ID}, + EFI_ACPI_CSP_OEM_TABLE_ID, + EFI_ACPI_CSP_OEM_REVISION, + EFI_ACPI_CSP_CREATOR_ID, + EFI_ACPI_CSP_CREATOR_REVISION + }, + 0x0000000000000000, //Reserved + }, + { + + { + 0x0000000040000000, //Base Address + 0x0000, //Segment Group = Number + 0x0, //Start Bus Numb= er + 0x1f, //End Bus Number + 0x00000000, //Reserved + }, + } +}; + +// +// Reference the table being generated to prevent the optimizer from remov= ing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable =3D &Mcfg; diff --git a/CadencePkg/AcpiTables/Spcr.aslc b/CadencePkg/AcpiTables/Spcr.a= slc new file mode 100644 index 0000000..6ca20e8 --- /dev/null +++ b/CadencePkg/AcpiTables/Spcr.aslc @@ -0,0 +1,89 @@ +/** @file +* SPCR Table +* +* Copyright (c) 2014 - 2016, ARM Limited. All rights reserved. +* Copyright (c) 2016, Linaro Ltd. All rights reserved. +* Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved. +* +* This program and the accompanying materials are licensed and made availa= ble +* under the terms and conditions of the BSD License which accompanies this +* distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. +* +**/ + +#include "CspPlatform.h" +#include +#include +#include + +/** + * References: + * Serial Port Console Redirection Table Specification Version 1.03 - Augu= st 10, 2015 + **/ + + +/// +/// SPCR Flow Control +/// +#define SPCR_FLOW_CONTROL_NONE 0 + + +STATIC EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr =3D { + ARM_ACPI_HEADER (EFI_ACPI_6_1_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGN= ATURE, + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE, + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_REVISI= ON), + // UINT8 InterfaceType; + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_ARM_PL011_= UART, + // UINT8 Reserved1[3]; + { + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE + }, + // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE BaseAddress; + ARM_GAS32 (0xFD000000), + // UINT8 InterruptType; + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_GIC, + // UINT8 Irq; + 0, // Not used on ARM + // UINT32 GlobalSystemInterrupt; + 0x25, + // UINT8 BaudRate; + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_115200, + // UINT8 Parity; + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_PARITY_NO_PARITY, + // UINT8 StopBits; + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_STOP_BITS_1, + // UINT8 FlowControl; + SPCR_FLOW_CONTROL_NONE, + // UINT8 TerminalType; + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_ANSI, + // UINT8 Reserved2; + EFI_ACPI_RESERVED_BYTE, + // UINT16 PciDeviceId; + 0xFFFF, + // UINT16 PciVendorId; + 0xFFFF, + // UINT8 PciBusNumber; + 0x00, + // UINT8 PciDeviceNumber; + 0x00, + // UINT8 PciFunctionNumber; + 0x00, + // UINT32 PciFlags; + 0x00000000, + // UINT8 PciSegment; + 0x00, + // UINT32 Reserved3; + EFI_ACPI_RESERVED_DWORD +}; + +// +// Reference the table being generated to prevent the optimizer from remov= ing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable =3D &Spcr; --=20 2.2.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat Apr 27 10:54:59 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zoho.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1496659878091213.8224018566956; Mon, 5 Jun 2017 03:51:18 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 26C2E21A6F106; Mon, 5 Jun 2017 03:49:52 -0700 (PDT) Received: from mx-sanjose5.cadence.com (keymaster.Cadence.COM [158.140.2.26]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id DAF8321967BC2 for ; Mon, 5 Jun 2017 03:49:50 -0700 (PDT) Received: from maileu3.global.cadence.com (maileu3.Cadence.COM [10.160.88.99]) by mx-sanjose5.cadence.com (8.13.8+Sun/8.14.4) with ESMTP id v55Aonkj028201; Mon, 5 Jun 2017 03:50:53 -0700 (PDT) Received: from maileu3.global.cadence.com (10.160.88.99) by maileu3.global.cadence.com (10.160.88.99) with Microsoft SMTP Server (TLS) id 15.0.1044.25; Mon, 5 Jun 2017 12:50:45 +0200 Received: from lvloginb.cadence.com (10.165.177.11) by maileu3.global.cadence.com (10.160.88.99) with Microsoft SMTP Server (TLS) id 15.0.1044.25 via Frontend Transport; Mon, 5 Jun 2017 12:50:44 +0200 Received: from lvloginb.cadence.com (localhost [127.0.0.1]) by lvloginb.cadence.com (8.14.4/8.14.4) with ESMTP id v55AohQx000599; Mon, 5 Jun 2017 11:50:43 +0100 Received: (from stelford@localhost) by lvloginb.cadence.com (8.14.4/8.14.4/Submit) id v55Aoh0H000598; Mon, 5 Jun 2017 11:50:43 +0100 X-Original-To: edk2-devel@ml01.01.org X-CrossPremisesHeadersFilteredBySendConnector: maileu3.global.cadence.com From: Scott Telford To: , , , , , Date: Mon, 5 Jun 2017 11:50:28 +0100 Message-ID: <1496659828-28702-7-git-send-email-stelford@cadence.com> X-Mailer: git-send-email 2.2.2 In-Reply-To: <1496659828-28702-1-git-send-email-stelford@cadence.com> References: <1496659828-28702-1-git-send-email-stelford@cadence.com> MIME-Version: 1.0 X-OrganizationHeadersPreserved: maileu3.global.cadence.com Subject: [edk2] [staging/cadence-aarch64 PATCH v2 6/6] CadencePkg: Add .dsc, .fdf and .dec files for Cadence CSP platform. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Add .dsc, .fdf and .dec files for a Cadence CSP platform configured with a single Cortex-A53, GIC-500, Cadence UART and Cadence PCIe Root Complex. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Scott Telford --- CadencePkg/CadenceCsp.dsc | 711 +++++++++++++++++++++++++++++++++++++++= ++++ CadencePkg/CadenceCsp.fdf | 410 +++++++++++++++++++++++++ CadencePkg/CadenceCspPkg.dec | 60 ++++ 3 files changed, 1181 insertions(+) create mode 100644 CadencePkg/CadenceCsp.dsc create mode 100644 CadencePkg/CadenceCsp.fdf create mode 100644 CadencePkg/CadenceCspPkg.dec diff --git a/CadencePkg/CadenceCsp.dsc b/CadencePkg/CadenceCsp.dsc new file mode 100644 index 0000000..e1d864d --- /dev/null +++ b/CadencePkg/CadenceCsp.dsc @@ -0,0 +1,711 @@ +# +# Copyright (c) 2011-2015, ARM Limited. All rights reserved. +# Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +# + +##########################################################################= ###### +# +# Defines Section - statements that will be processed to create a Makefile. +# +##########################################################################= ###### +[Defines] + PLATFORM_NAME =3D CadenceCsp + PLATFORM_GUID =3D 262f8c6b-047b-4afe-b317-7c90b795beb8 + PLATFORM_VERSION =3D 0.1 + DSC_SPECIFICATION =3D 1.25 +!ifdef $(EDK2_OUT_DIR) + OUTPUT_DIRECTORY =3D $(EDK2_OUT_DIR) +!else + OUTPUT_DIRECTORY =3D Build/CadenceCsp +!endif + SUPPORTED_ARCHITECTURES =3D AARCH64 + BUILD_TARGETS =3D DEBUG|RELEASE + SKUID_IDENTIFIER =3D DEFAULT + FLASH_DEFINITION =3D CadencePkg/CadenceCsp.fdf + + SECURE_BOOT_ENABLE =3D FALSE + +[LibraryClasses.common] + ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf + ArmPlatformLib|CadencePkg/Library/CadenceCspLib/CadenceCspLib.inf + ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf + TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf + + # Virtio Support + VirtioLib|OvmfPkg/Library/VirtioLib/VirtioLib.inf + VirtioMmioDeviceLib|OvmfPkg/Library/VirtioMmioDeviceLib/VirtioMmioDevice= Lib.inf +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf +!endif + +!if $(TARGET) =3D=3D RELEASE + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf + UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/U= ncachedMemoryAllocationLib.inf +!else + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf + UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/U= ncachedMemoryAllocationLib.inf +# UncachedMemoryAllocationLib|ArmPkg/Library/DebugUncachedMemoryAllocatio= nLib/DebugUncachedMemoryAllocationLib.inf +!endif + DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseD= ebugPrintErrorLevelLib.inf + + BaseLib|MdePkg/Library/BaseLib/BaseLib.inf + SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchroniza= tionLib.inf + PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibN= ull.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeC= offGetEntryPointLib.inf + PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf + IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf + UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompres= sLib.inf + CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf + + UefiLib|MdePkg/Library/UefiLib/UefiLib.inf + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/U= efiRuntimeServicesTableLib.inf + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBoo= tServicesTableLib.inf + UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManag= erLib.inf + DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableL= ib.inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseRepor= tStatusCodeLibNull.inf + UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntry= Point.inf + UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiA= pplicationEntryPoint.inf + HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf + UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServic= esLib.inf + + UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf + + # + # Assume everything is fixed at build + # + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + #BaseMemoryLib|ArmPkg/Library/BaseMemoryLibStm/BaseMemoryLibStm.inf + + # Networking Requirements + NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf + DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf + UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf + IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf + + # ARM Architectural Libraries + CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMainte= nanceLib.inf + DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/Def= aultExceptionHandlerLib.inf + CpuExceptionHandlerLib|ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf + ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.= inf + DmaLib|ArmPkg/Library/ArmDmaLib/ArmDmaLib.inf + ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf + ArmGicArchLib|ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf + ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatfo= rmStackLib.inf + ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf + ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/Ar= mGenericTimerPhyCounterLib.inf + + PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf + EfiResetSystemLib|CadencePkg/Library/CadenceCspResetSystemLib/CadenceCsp= ResetSystemLib.inf + + RealTimeClockLib|EmbeddedPkg/Library/TemplateRealTimeClockLib/TemplateRe= alTimeClockLib.inf + + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf + GenericBdsLib|IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLi= b.inf + PlatformBdsLib|ArmPlatformPkg/Library/PlatformIntelBdsLib/PlatformIntelB= dsLib.inf + CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/Customize= dDisplayLib.inf + + BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf + + # ARM PL011 UART Driver +# PL011UartLib|ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.inf +# SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPort= Lib.inf + +# CSP Libraries + SerialPortLib|CadencePkg/Library/CadenceCspSerialPortLib/CspSerialPortLi= b.inf + + # + # Uncomment (and comment out the next line) For RealView Debugger. The S= tandard IO window + # in the debugger will show load and unload commands for symbols. You ca= n cut and paste this + # into the command window to load symbols. We should be able to use a sc= ript to do this, but + # the version of RVD I have does not support scripts accessing system me= mory. + # + #PeCoffExtraActionLib|ArmPkg/Library/RvdPeCoffExtraActionLib/RvdPeCoffEx= traActionLib.inf + PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCof= fExtraActionLib.inf + #PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePe= CoffExtraActionLibNull.inf + + DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.i= nf + DebugAgentTimerLib|EmbeddedPkg/Library/DebugAgentTimerLibNull/DebugAgent= TimerLibNull.inf + + SemihostLib|ArmPkg/Library/SemihostLib/SemihostLib.inf + + AcpiLib|EmbeddedPkg/Library/AcpiLib/AcpiLib.inf + FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf + + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf + FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf + SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf + + # + # Secure Boot dependencies + # +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf + OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf + TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTpmMeasure= mentLib.inf + AuthVariableLib|SecurityPkg/Library/AuthVariableLib/AuthVariableLib.inf + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf + + # re-use the UserPhysicalPresent() dummy implementation from the ovmf tr= ee + PlatformSecureLib|OvmfPkg/Library/PlatformSecureLib/PlatformSecureLib.inf +!else + TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurem= entLibNull.inf + AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLib= Null.inf +!endif + VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf + +[LibraryClasses.common.SEC] + ArmPlatformSecLib|CadencePkg/Library/CadenceCspSecLib/CadenceCspSecLib.i= nf + ArmPlatformLib|CadencePkg/Library/CadenceCspLib/CadenceCspLibSec.inf +# ArmPlatformSecExtraActionLib|ArmPlatformPkg/Library/DebugSecExtraAction= Lib/DebugSecExtraActionLib.inf + DebugAgentLib|ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentSymbolsB= aseLib.inf + DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/Def= aultExceptionHandlerLibBase.inf + +!ifdef $(EDK2_SKIP_PEICORE) + PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf + ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib= /PrePiExtractGuidedSectionLib.inf + LzmaDecompressLib|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCusto= mDecompressLib.inf + MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMe= moryAllocationLib.inf + HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf + PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/Pre= PiHobListPointerLib.inf + PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.= inf +!endif + + # Trustzone Support + ArmTrustedMonitorLib|ArmPlatformPkg/Library/ArmTrustedMonitorLibNull/Arm= TrustedMonitorLibNull.inf + + ArmGicArchLib|ArmPkg/Library/ArmGicArchSecLib/ArmGicArchSecLib.inf + + +[LibraryClasses.common.PEI_CORE] + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAlloc= ationLib.inf + PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf + PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.= inf + ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiRepor= tStatusCodeLib.inf + OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHo= okStatusCodeLibNull.inf + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeC= offGetEntryPointLib.inf + UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompres= sLib.inf + ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExt= ractGuidedSectionLib.inf + + PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/Pei= ServicesTablePointerLib.inf + +[LibraryClasses.common.PEIM] + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAlloc= ationLib.inf + PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf + PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.= inf + ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiRepor= tStatusCodeLib.inf + OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHo= okStatusCodeLibNull.inf + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeC= offGetEntryPointLib.inf + PeiResourcePublicationLib|MdePkg/Library/PeiResourcePublicationLib/PeiRe= sourcePublicationLib.inf + UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompres= sLib.inf + ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExt= ractGuidedSectionLib.inf + + PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/Pei= ServicesTablePointerLib.inf + +[LibraryClasses.common.SEC, LibraryClasses.common.PEIM] + MemoryInitPeiLib|ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.inf + +[LibraryClasses.common.DXE_CORE] + HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf + MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeC= oreMemoryAllocationLib.inf + DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf + ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeL= ibFramework/DxeReportStatusCodeLib.inf + ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExt= ractGuidedSectionLib.inf + UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompres= sLib.inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerform= anceLib.inf + +[LibraryClasses.common.DXE_DRIVER] + ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeL= ibFramework/DxeReportStatusCodeLib.inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeS= ecurityManagementLib.inf + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.= inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf + +[LibraryClasses.common.UEFI_APPLICATION] + UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDec= ompressLib/BaseUefiTianoCustomDecompressLib.inf + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.= inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf + HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf + +[LibraryClasses.common.UEFI_DRIVER] + ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeL= ibFramework/DxeReportStatusCodeLib.inf + UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDec= ompressLib/BaseUefiTianoCustomDecompressLib.inf + ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExt= ractGuidedSectionLib.inf + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.= inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf + +[LibraryClasses.common.DXE_RUNTIME_DRIVER] + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf + ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeL= ibFramework/DxeReportStatusCodeLib.inf + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf +!endif + +[LibraryClasses.AARCH64.DXE_RUNTIME_DRIVER] + # + # PSCI support in EL3 may not be available if we are not running under a= PSCI + # compliant secure firmware, but since the default VExpress EfiResetSyst= emLib + # cannot be supported at runtime (due to the fact that the syscfg MMIO r= egisters + # cannot be runtime remapped), it is our best bet to get ResetSystem fun= ctionality + # on these platforms. + # +# EfiResetSystemLib|ArmPkg/Library/ArmPsciResetSystemLib/ArmPsciResetSyst= emLib.inf + +[LibraryClasses.ARM, LibraryClasses.AARCH64] + # + # It is not possible to prevent the ARM compiler for generic intrinsic f= unctions. + # This library provides the instrinsic functions generate by a given com= piler. + # [LibraryClasses.ARM] and NULL mean link this library into all ARM imag= es. + # + NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf + + # Add support for GCC stack protector + NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf + +[LibraryClasses.common.UEFI_DRIVER, LibraryClasses.common.UEFI_APPLICATION= , LibraryClasses.common.DXE_RUNTIME_DRIVER, LibraryClasses.common.DXE_DRIVE= R] + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + PciHostBridgeLib|CadencePkg/Library/CadencePciHostBridgeLib/CdnsPciHostB= ridgeLib.inf + PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.i= nf + PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf + PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf + +[BuildOptions] + GCC:RELEASE_*_*_CC_FLAGS =3D -DMDEPKG_NDEBUG + +[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER] + GCC:*_*_ARM_DLINK_FLAGS =3D -z common-page-size=3D0x1000 + GCC:*_*_AARCH64_DLINK_FLAGS =3D -z common-page-size=3D0x10000 + +##########################################################################= ###### +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +##########################################################################= ###### + +[PcdsFeatureFlag.common] + gEfiMdePkgTokenSpaceGuid.PcdComponentNameDisable|TRUE + gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnosticsDisable|TRUE + gEfiMdePkgTokenSpaceGuid.PcdComponentName2Disable|TRUE + gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnostics2Disable|TRUE + + # + # Control what commands are supported from the UI + # Turn these on and off to add features or save size + # + gEmbeddedTokenSpaceGuid.PcdEmbeddedMacBoot|TRUE + gEmbeddedTokenSpaceGuid.PcdEmbeddedDirCmd|TRUE + gEmbeddedTokenSpaceGuid.PcdEmbeddedHobCmd|TRUE + gEmbeddedTokenSpaceGuid.PcdEmbeddedHwDebugCmd|TRUE + gEmbeddedTokenSpaceGuid.PcdEmbeddedPciDebugCmd|TRUE + gEmbeddedTokenSpaceGuid.PcdEmbeddedIoEnable|FALSE + gEmbeddedTokenSpaceGuid.PcdEmbeddedScriptCmd|FALSE + + gEmbeddedTokenSpaceGuid.PcdCacheEnable|TRUE + + # Use the Vector Table location in CpuDxe. We will not copy the Vector T= able at PcdCpuVectorBaseAddress + gArmTokenSpaceGuid.PcdRelocateVectorTable|FALSE + + gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob|TRUE + + gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE + +[PcdsFixedAtBuild.common] + gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"Cadence CSP" +!ifdef $(FIRMWARE_VER) + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"$(FIRMWARE_VER= )" +!endif + + # Only one core enters UEFI, and PSCI is implemented in EL3 by ATF + gArmPlatformTokenSpaceGuid.PcdCoreCount|1 + gArmTokenSpaceGuid.PcdVFPEnabled|1 + + # Stacks for MPCores in Normal World + # Non-Trusted SRAM + gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x4000 + gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x0 + + # Size of the region used by UEFI in permanent memory (Reserved 64MB) + gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x04000000 + + # + # ARM Pcds + # + # Stacks for MPCores in Secure World + gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0x3F000000 + # Stacks for MPCores in Normal World + gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x3F020000 + + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x10000000 + gArmTokenSpaceGuid.PcdSystemMemorySize|0x30000000 + + ## Trustzone enable (to make the transition from EL3 to NS EL2 in ArmPla= tformPkg/Sec) + gArmTokenSpaceGuid.PcdTrustzoneSupport|TRUE + + # + # ARM PrimeCell + # + + ## PL011 - Serial Terminal +# gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x1c090000 + + ## PL031 RealTimeClock +# gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x1C170000 + + # + # ARM General Interrupt Controller + # + gArmTokenSpaceGuid.PcdGicDistributorBase|0xfd100000 + gArmTokenSpaceGuid.PcdGicRedistributorsBase|0xfd140000 + gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration|FALSE + + # + # Cadence PCIe Root Complex + # + gArmTokenSpaceGuid.PcdPciBusMax|31 + gArmTokenSpaceGuid.PcdPciIoBase|0x0 + gArmTokenSpaceGuid.PcdPciIoSize|0x01000000 + gArmTokenSpaceGuid.PcdPciMmio32Base|0x42000000 + gArmTokenSpaceGuid.PcdPciMmio32Size|0x01000000 + gArmTokenSpaceGuid.PcdPciMmio64Base|0x400000000 + gArmTokenSpaceGuid.PcdPciMmio64Size|0x01000000 + + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x40000000 + gArmTokenSpaceGuid.PcdPciIoTranslation|0x43000000 + gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|24 + + # Use the serial console (ConIn & ConOut) + gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-4= 35F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi()" + gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-43= 5F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi()" + + # + # ARM Architectural Timer Frequency + # + # Set tick frequency value to 100MHz + gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|100000000 + + # the entire address space can be covered by 36 bit VAs + gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|36 + + gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000 + gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000 + gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000 + gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000 + gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF + gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|1 + gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0 + gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320 + + # DEBUG_ASSERT_ENABLED 0x01 + # DEBUG_PRINT_ENABLED 0x02 + # DEBUG_CODE_ENABLED 0x04 + # CLEAR_MEMORY_ENABLED 0x08 + # ASSERT_BREAKPOINT_ENABLED 0x10 + # ASSERT_DEADLOOP_ENABLED 0x20 +!if $(TARGET) =3D=3D RELEASE + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x21 +!else + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2f +!endif + + # DEBUG_INIT 0x00000001 // Initialization + # DEBUG_WARN 0x00000002 // Warnings + # DEBUG_LOAD 0x00000004 // Load events + # DEBUG_FS 0x00000008 // EFI File system + # DEBUG_POOL 0x00000010 // Alloc & Free (pool) + # DEBUG_PAGE 0x00000020 // Alloc & Free (page) + # DEBUG_INFO 0x00000040 // Informational debug messages + # DEBUG_DISPATCH 0x00000080 // PEI/DXE/SMM Dispatchers + # DEBUG_VARIABLE 0x00000100 // Variable + # DEBUG_BM 0x00000400 // Boot Manager + # DEBUG_BLKIO 0x00001000 // BlkIo Driver + # DEBUG_NET 0x00004000 // SNP Driver + # DEBUG_UNDI 0x00010000 // UNDI Driver + # DEBUG_LOADFILE 0x00020000 // LoadFile + # DEBUG_EVENT 0x00080000 // Event messages + # DEBUG_GCD 0x00100000 // Global Coherency Database changes + # DEBUG_CACHE 0x00200000 // Memory range cachability changes + # DEBUG_VERBOSE 0x00400000 // Detailed debug messages that may + # // significantly impact boot performance + # DEBUG_ERROR 0x80000000 // Error +# gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000000F + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000054F + + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 + + gEmbeddedTokenSpaceGuid.PcdEmbeddedAutomaticBootCommand|"" + gEmbeddedTokenSpaceGuid.PcdEmbeddedDefaultTextColor|0x07 + gEmbeddedTokenSpaceGuid.PcdEmbeddedMemVariableStoreSize|0x10000 + + # + # Optional feature to help prevent EFI memory map fragments + # Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob + # Values are in EFI Pages (4K). DXE Core will make sure that + # at least this much of each type of memory can be allocated + # from a single memory range. This way you only end up with + # maximum of two fragements for each type in the memory map + # (the memory used, and the free memory that was prereserved + # but not used). + # + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|80 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|65 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|400 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|20000 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|20 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0 + + # List of Device Paths that support BootMonFs +# gArmPlatformTokenSpaceGuid.PcdBootMonFsSupportedDevicePaths|L"VenHw(E72= 23039-5836-41E1-B542-D7EC736C5E59);VenHw(1F15DA3C-37FF-4070-B471-BB4AF12A72= 4A)" + + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + # override the default values from SecurityPkg to ensure images from all= sources are verified in secure boot + gEfiSecurityPkgTokenSpaceGuid.PcdOptionRomImageVerificationPolicy|0x04 + gEfiSecurityPkgTokenSpaceGuid.PcdFixedMediaImageVerificationPolicy|0x04 + gEfiSecurityPkgTokenSpaceGuid.PcdRemovableMediaImageVerificationPolicy|0= x04 +!endif + +# Generic UART PCDs + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|1 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1 + +# +# Cadence CSP Base Components PCDs +# + gCadenceCspTokenSpaceGuid.PcdCspSysRegBase|0xfd020000 + gCadenceCspTokenSpaceGuid.PcdCspSysRegSize|0x00001000 + gCadenceCspTokenSpaceGuid.PcdCspSerialBase|0xfd000000 + gCadenceCspTokenSpaceGuid.PcdCspSerialSize|0x00001000 + +# Cadence xHCI +# gCadenceCspTokenSpaceGuid.PcdCadenceUsbXhciBaseAddress|0x70000000 +# gCadenceCspTokenSpaceGuid.PcdCadenceUsbXhciSize|0x7009ffff + + gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FAL= SE + gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x0= 4, 0x7C, 0x3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, = 0xD1 } + +##########################################################################= ###### +# +# Components Section - list of all EDK II Modules needed by this Platform +# +##########################################################################= ###### +[Components.common] + + # + # SEC + # + CadencePkg/Sec/Sec.inf { + + # Use the implementation which set the Secure bits + ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf + } + + MdeModulePkg/Universal/PCD/Dxe/Pcd.inf { + + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + } + + # + # SATA Controller + # + MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf + EmbeddedPkg/Drivers/SataSiI3132Dxe/SataSiI3132Dxe.inf + + # + # NVMe boot devices + # + MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf + # + # Networking stack + # + MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf + MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf + MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf + MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf + MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf + MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf + MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf + MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf + MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf + MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf + MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf + MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf + + # FV Filesystem + MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.inf + + # + # UEFI application (Shell Embedded Boot Loader) + # + ShellPkg/Application/Shell/Shell.inf { + + ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellComman= dLib.inf + NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2Comm= andsLib.inf + NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1Comm= andsLib.inf + NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3Comm= andsLib.inf + NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1Co= mmandsLib.inf + NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1Comm= andsLib.inf + NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1= CommandsLib.inf + NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1= CommandsLib.inf + NULL|ShellPkg/Library/UefiShellTftpCommandLib/UefiShellTftpCommandLi= b.inf + HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandlePar= singLib.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcf= gCommandLib.inf + } + + # ARM SBSA ACS app +# AppPkg/Applications/sbsa-acs/uefi_app/SbsaAvs.inf { +# +# SbsaPalLib|AppPkg/Applications/sbsa-acs/platform/pal_uefi/SbsaPalLib.= inf +# SbsaValLib|AppPkg/Applications/sbsa-acs/val/SbsaValLib.inf +# ShellCEntryLib|ShellPkg/Library/UefiShellCEntryLib/UefiShellCEntryLib= .inf +# } + + # + # PEI Phase modules + # +!ifdef EDK2_SKIP_PEICORE + # UEFI is placed in RAM by bootloader + ArmPlatformPkg/PrePi/PeiUniCore.inf { + + ArmPlatformLib|CadencePkg/Library/CadenceCspLib/CadenceCspLib.inf + } +!else + # UEFI lives in FLASH and copies itself to RAM + ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf + MdeModulePkg/Core/Pei/PeiMain.inf + MdeModulePkg/Universal/PCD/Pei/Pcd.inf { + + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + } + ArmPlatformPkg/PlatformPei/PlatformPeim.inf + ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf + ArmPkg/Drivers/CpuPei/CpuPei.inf + IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf + Nt32Pkg/BootModePei/BootModePei.inf + MdeModulePkg/Universal/Variable/Pei/VariablePei.inf + MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf { + + NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompre= ssLib.inf + } +!endif + + # + # DXE + # + MdeModulePkg/Core/Dxe/DxeMain.inf { + + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32Gu= idedSectionExtractLib.inf + } + + # + # Architectural Protocols + # + ArmPkg/Drivers/CpuDxe/CpuDxe.inf + MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf { + + NULL|SecurityPkg/Library/DxeImageVerificationLib/DxeImageVerificatio= nLib.inf + } + SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDx= e.inf +!else + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf +!endif + MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf + MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf +# MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf +# MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf + MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntim= eDxe.inf + EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf + EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + + MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf +# MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf + MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + + MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + + # + # ACPI Support + # + MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf + MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf + CadencePkg/AcpiTables/AcpiTables.inf + + ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + ArmPkg/Drivers/TimerDxe/TimerDxe.inf + # Required by PCI + UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf + + # + # PCI Support + # + MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf + +# CadencePkg/Drivers/IntelUndiPkg/Binary/GigUndiDxe.inf + + # Simple TextIn/TextOut for UEFI Terminal + EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf + + # SMBIOS Support + + MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + + # + # Platform Driver + # + OvmfPkg/VirtioBlkDxe/VirtioBlk.inf + + # + # FAT filesystem + GPT/MBR partitioning + # + MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + FatPkg/EnhancedFatDxe/Fat.inf + MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + + # + # Bds + # + MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf + +[Components.ARM] + # Legacy Linux Loader + ArmPkg/Application/LinuxLoader/LinuxLoader.inf diff --git a/CadencePkg/CadenceCsp.fdf b/CadencePkg/CadenceCsp.fdf new file mode 100644 index 0000000..21c7f1e --- /dev/null +++ b/CadencePkg/CadenceCsp.fdf @@ -0,0 +1,410 @@ +# +# Copyright (c) 2011 - 2015, ARM Limited. All rights reserved. +# Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# + +##########################################################################= ###### +# +# FD Section +# The [FD] Section is made up of the definition statements and a +# description of what goes into the Flash Device Image. Each FD section +# defines one flash "device" image. A flash device image may be one of +# the following: Removable media bootable image (like a boot floppy +# image,) an Option ROM image (that would be "flashed" into an add-in +# card,) a System "Flash" image (that would be burned into a system's +# flash) or an Update ("Capsule") image that will be used to update and +# existing system flash. +# +##########################################################################= ###### +[FD.Sec_CDNS_CSP_AARCH64_EFI] +BaseAddress =3D 0x00000000|gArmTokenSpaceGuid.PcdSecureFdBaseAddress #T= he base address of the Secure FLASH Device. +Size =3D 0x00020000|gArmTokenSpaceGuid.PcdSecureFdSize #T= he size in bytes of the Secure FLASH Device +ErasePolarity =3D 1 +BlockSize =3D 0x00002000 +NumBlocks =3D 0x10 + + +##########################################################################= ###### +# +# Following are lists of FD Region layout which correspond to the location= s of different +# images within the flash device. +# +# Regions must be defined in ascending order and may not overlap. +# +# A Layout Region start with a eight digit hex offset (leading "0x" requir= ed) followed by +# the pipe "|" character, followed by the size of the region, also in hex = with the leading +# "0x" characters. Like: +# Offset|Size +# PcdOffsetCName|PcdSizeCName +# RegionType +# +##########################################################################= ###### + +0x00000000|0x00020000 +gArmTokenSpaceGuid.PcdSecureFvBaseAddress|gArmTokenSpaceGuid.PcdSecureFvSi= ze +FV =3D FVMAIN_SEC + + +[FD.CDNS_CSP_AARCH64_EFI] +BaseAddress =3D 0x0020000|gArmTokenSpaceGuid.PcdFdBaseAddress # The bas= e address of the Firmware in NOR Flash. +Size =3D 0x00400000|gArmTokenSpaceGuid.PcdFdSize # The si= ze in bytes of the FLASH Device +ErasePolarity =3D 1 + +# This one is tricky, it must be: BlockSize * NumBlocks =3D Size +BlockSize =3D 0x00001000 +NumBlocks =3D 0x400 + +##########################################################################= ###### +# +# Following are lists of FD Region layout which correspond to the location= s of different +# images within the flash device. +# +# Regions must be defined in ascending order and may not overlap. +# +# A Layout Region start with a eight digit hex offset (leading "0x" requir= ed) followed by +# the pipe "|" character, followed by the size of the region, also in hex = with the leading +# "0x" characters. Like: +# Offset|Size +# PcdOffsetCName|PcdSizeCName +# RegionType +# +##########################################################################= ###### + +0x00000000|0x00280000 +gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize +FV =3D FVMAIN_COMPACT + +##########################################################################= ###### +# +# FV Section +# +# [FV] section is used to define what components or modules are placed wit= hin a flash +# device file. This section also defines order the components and modules= are positioned +# within the image. The [FV] section consists of define statements, set s= tatements and +# module statements. +# +##########################################################################= ###### + +[FV.FVMAIN_SEC] +FvAlignment =3D 8 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE + + INF CadencePkg/Sec/Sec.inf + + +[FV.FvMain] +BlockSize =3D 0x40 +NumBlocks =3D 0 # This FV gets compressed so make it just= big enough +FvAlignment =3D 16 # FV alignment and FV attributes setting. +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE +FvNameGuid =3D b1e2a5cf-5357-4fc8-9532-49f3ce327bd3 + + INF MdeModulePkg/Core/Dxe/DxeMain.inf + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + + # + # PI DXE Drivers producing Architectural Protocols (EFI Services) + # + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + INF SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConf= igDxe.inf +!endif + INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.= inf +# INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf +# INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.= inf + INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRu= ntimeDxe.inf + INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf + INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + + INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + + # Required by PCI + INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf + + # + # PCI Support + # + INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf +# INF CadencePkg/Drivers/IntelUndiPkg/Binary/GigUndiDxe.inf + + # ACPI Support + # + INF MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf + INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf + INF RuleOverride=3DACPITABLE CadencePkg/AcpiTables/AcpiTables.inf + + # + # Multiple Console IO support + # + INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + + INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf + + # + # FAT filesystem + GPT/MBR partitioning + # + INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + INF FatBinPkg/EnhancedFatDxe/Fat.inf + INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.i= nf + + # SMBIOS Support + # + INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + + # + # Platform Driver + # + INF OvmfPkg/VirtioBlkDxe/VirtioBlk.inf + # + # SATA Controller + # + INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf + INF EmbeddedPkg/Drivers/SataSiI3132Dxe/SataSiI3132Dxe.inf + + # + # NVMe boot devices + # + INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf + + # + # UEFI application (Shell Embedded Boot Loader) + # + INF ShellPkg/Application/Shell/Shell.inf + + # + # Networking stack + # + INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf + INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf + INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf + INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf + INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf + INF MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf + INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf + INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf + INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf + INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf + INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf + INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf + + # ARM SBSA ACS app +# INF AppPkg/Applications/sbsa-acs/uefi_app/SbsaAvs.inf + + # + # Bds + # + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + INF IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf + + # + # TianoCore logo (splash screen) + # + FILE FREEFORM =3D PCD(gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdLogoF= ile) { + SECTION RAW =3D MdeModulePkg/Logo/Logo.bmp + } + + # FV Filesystem + INF MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.i= nf + + # + # FDT installation + # + # The UEFI driver is at the end of the list of the driver to be dispatch= ed + # after the device drivers (eg: Ethernet) to ensure we have support for = them. +# INF EmbeddedPkg/Drivers/FdtPlatformDxe/FdtPlatformDxe.inf + +[FV.FVMAIN_COMPACT] +FvAlignment =3D 16 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE + +!if $(EDK2_SKIP_PEICORE) =3D=3D 1 + INF ArmPlatformPkg/PrePi/PeiUniCore.inf +!else + INF ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf + INF MdeModulePkg/Core/Pei/PeiMain.inf + INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf + INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf + INF ArmPkg/Drivers/CpuPei/CpuPei.inf + INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf + INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf + INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf + INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf +!endif + + FILE FV_IMAGE =3D 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRE= D =3D TRUE { + SECTION FV_IMAGE =3D FVMAIN + } + } + + +##########################################################################= ###### +# +# Rules are use with the [FV] section's module INF type to define +# how an FFS file is created for a given INF file. The following Rule are = the default +# rules for the different module type. User can add the customized rules t= o define the +# content of the FFS file. +# +##########################################################################= ###### + + +##########################################################################= ## +# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section = # +##########################################################################= ## +# +#[Rule.Common.DXE_DRIVER] +# FILE DRIVER =3D $(NAMED_GUID) { +# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_= NAME).depex +# COMPRESS PI_STD { +# GUIDED { +# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi +# UI STRING=3D"$(MODULE_NAME)" Optional +# VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_N= UMBER) +# } +# } +# } +# +##########################################################################= ## + +[Rule.Common.SEC] + FILE SEC =3D $(NAMED_GUID) RELOCS_STRIPPED FIXED { + TE TE Align =3D Auto $(INF_OUTPUT)/$(MODULE_NAME).efi + } + +[Rule.Common.PEI_CORE] + FILE PEI_CORE =3D $(NAMED_GUID) FIXED { + TE TE Align =3D Auto $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING =3D"$(MODULE_NAME)" Optional + } + +[Rule.Common.PEIM] + FILE PEIM =3D $(NAMED_GUID) FIXED { + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + TE TE Align =3D Auto $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + } + +[Rule.Common.PEIM.TIANOCOMPRESSED] + FILE PEIM =3D $(NAMED_GUID) DEBUG_MYTOOLS_IA32 { + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + GUIDED 4caac18f-ffe5-48f2-86a5-23a615120637 PROCESSING_REQUIRED =3D TR= UE { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + } + } + +[Rule.Common.DXE_CORE] + FILE DXE_CORE =3D $(NAMED_GUID) { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + } + +[Rule.Common.UEFI_DRIVER] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NA= ME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + } + +[Rule.Common.DXE_DRIVER] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NA= ME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + } + +[Rule.Common.DXE_RUNTIME_DRIVER] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NA= ME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + } + +[Rule.Common.UEFI_APPLICATION] + FILE APPLICATION =3D $(NAMED_GUID) { + UI STRING =3D"$(MODULE_NAME)" Optional + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + } + +[Rule.Common.UEFI_DRIVER.BINARY] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional |.depex + PE32 PE32 |.efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R) + } + +[Rule.Common.UEFI_APPLICATION.BINARY] + FILE APPLICATION =3D $(NAMED_GUID) { + PE32 PE32 |.efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R) + } + +[Rule.Common.USER_DEFINED.ACPITABLE] + FILE FREEFORM =3D $(NAMED_GUID) { + RAW ACPI |.acpi + RAW ASL |.aml + } diff --git a/CadencePkg/CadenceCspPkg.dec b/CadencePkg/CadenceCspPkg.dec new file mode 100644 index 0000000..cb2b4a0 --- /dev/null +++ b/CadencePkg/CadenceCspPkg.dec @@ -0,0 +1,60 @@ +#/** @file +# Cadence CSP package. +# +# Copyright (c) 2012-2015, ARM Limited. All rights reserved. +# Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved. +# +# This program and the accompanying materials are licensed and made avail= able +# under the terms and conditions of the BSD License which accompanies this +# distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +#**/ + +[Defines] + DEC_SPECIFICATION =3D 1.25 + PACKAGE_NAME =3D CadenceCspPkg + PACKAGE_GUID =3D 593f66c2-fb57-4aa7-8bd0-149d52443f21 + PACKAGE_VERSION =3D 0.1 + +##########################################################################= ###### +# +# Include Section - list of Include Paths that are provided by this packag= e. +# Comments are used for Keywords and Module Types. +# +# Supported Module Types: +# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_D= RIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION +# +##########################################################################= ###### +[Includes.common] + Include # Root include for the package + +[Guids.common] + gCadenceCspTokenSpaceGuid =3D { 0x593f66c2, 0xfb57, 0x4aa7, { 0x8b, = 0xd0, 0x14, 0x9d, 0x52, 0x44, 0x3f, 0x21 } } + +[PcdsFeatureFlag.common] + +[PcdsFixedAtBuild.common] + # Install FDT from NOR Flash +# gCadenceCspTokenSpaceGuid.PcdCspFdtDevicePath|L"VenHw(70f87726-cb5d-41b= 0-b153-1486e467888b)/csp.dtb"|VOID*|0x00000006 + + # + # Cadence CSP + # + + ## Cadence CSP System Registers + gCadenceCspTokenSpaceGuid.PcdCspSysRegBase|0|UINT64|0x000000C0 + gCadenceCspTokenSpaceGuid.PcdCspSysRegSize|0|UINT32|0x000000D0 + + ## Cadence UART + gCadenceCspTokenSpaceGuid.PcdCspSerialBase|0|UINT64|0x000000C1 + gCadenceCspTokenSpaceGuid.PcdCspSerialSize|0|UINT32|0x000000D1 + + # Cadence PCIe + gCadenceCspTokenSpaceGuid.PcdPcieRootPortBaseAddress|0xfb000000|UINT64|0= x0000000C + gCadenceCspTokenSpaceGuid.PcdPcie1RootPortBaseAddress|0xfc000000|UINT64|= 0x000000CD + gCadenceCspTokenSpaceGuid.PcdPciConfigurationSpaceBaseAddress|0x40000000= |UINT64|0x00000011 + gCadenceCspTokenSpaceGuid.PcdPciConfigurationSpaceSize|0x02000000|UINT64= |0x00000012 --=20 2.2.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel