[edk2] [PATCH 2/2] UefiCpuPkg: Modify GetProcessorLocationByApicId() to support AMD.

Leo Duran posted 2 patches 143 weeks ago

[edk2] [PATCH 2/2] UefiCpuPkg: Modify GetProcessorLocationByApicId() to support AMD.

Posted by Leo Duran 143 weeks ago
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Brijesh Singh <brijesh.singh@amd.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Leo Duran <leo.duran@amd.com>
---
 UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c     | 85 +++++++++++++---------
 .../BaseXApicX2ApicLib/BaseXApicX2ApicLib.c        | 85 +++++++++++++---------
 2 files changed, 98 insertions(+), 72 deletions(-)
 mode change 100644 => 100755 UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c

diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
old mode 100644
new mode 100755
index f81bbb2..da45d7a
--- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
+++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
@@ -4,6 +4,8 @@
   This local APIC library instance supports xAPIC mode only.
 
   Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2017, AMD Inc. All rights reserved.<BR>
+
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
   which accompanies this distribution.  The full text of the license may be found at
@@ -15,6 +17,7 @@
 **/
 
 #include <Register/Cpuid.h>
+#include <Register/Amd/Cpuid.h>
 #include <Register/Msr.h>
 #include <Register/LocalApic.h>
 
@@ -966,20 +969,22 @@ GetProcessorLocationByApicId (
   OUT UINT32  *Thread  OPTIONAL
   )
 {
-  BOOLEAN                       TopologyLeafSupported;
-  UINTN                         ThreadBits;
-  UINTN                         CoreBits;
-  CPUID_VERSION_INFO_EBX        VersionInfoEbx;
-  CPUID_VERSION_INFO_EDX        VersionInfoEdx;
-  CPUID_CACHE_PARAMS_EAX        CacheParamsEax;
-  CPUID_EXTENDED_TOPOLOGY_EAX   ExtendedTopologyEax;
-  CPUID_EXTENDED_TOPOLOGY_EBX   ExtendedTopologyEbx;
-  CPUID_EXTENDED_TOPOLOGY_ECX   ExtendedTopologyEcx;
-  UINT32                        MaxCpuIdIndex;
-  UINT32                        SubIndex;
-  UINTN                         LevelType;
-  UINT32                        MaxLogicProcessorsPerPackage;
-  UINT32                        MaxCoresPerPackage;
+  CPUID_VERSION_INFO_EBX            VersionInfoEbx;
+  CPUID_VERSION_INFO_EDX            VersionInfoEdx;
+  CPUID_CACHE_PARAMS_EAX            CacheParamsEax;
+  CPUID_EXTENDED_TOPOLOGY_EAX       ExtendedTopologyEax;
+  CPUID_EXTENDED_TOPOLOGY_EBX       ExtendedTopologyEbx;
+  CPUID_EXTENDED_TOPOLOGY_ECX       ExtendedTopologyEcx;
+  CPUID_AMD_EXTENDED_CPU_SIG_ECX    AmdExtendedCpuSigEcx;
+  CPUID_AMD_PROCESSOR_TOPOLOGY_EBX  AmdProcessorTopologyEbx;
+  UINT32                            MaxStandardCpuIdIndex;
+  UINT32                            MaxExtendedCpuIdIndex;
+  UINT32                            SubIndex;
+  UINTN                             LevelType;
+  UINT32                            MaxLogicProcessorsPerPackage;
+  UINT32                            MaxCoresPerPackage;
+  UINTN                             ThreadBits;
+  UINTN                             CoreBits;
 
   //
   // Check if the processor is capable of supporting more than one logical processor.
@@ -1002,20 +1007,16 @@ GetProcessorLocationByApicId (
   CoreBits = 0;
 
   //
-  // Assume three-level mapping of APIC ID: Package:Core:SMT.
+  // Get the max index of CPUID
   //
-  TopologyLeafSupported = FALSE;
-
-  //
-  // Get the max index of basic CPUID
-  //
-  AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
+  AsmCpuid(CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, NULL);
+  AsmCpuid(CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, NULL, NULL, NULL);
 
   //
   // If the extended topology enumeration leaf is available, it
   // is the preferred mechanism for enumerating topology.
   //
-  if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
+  if (MaxStandardCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
     AsmCpuidEx(
       CPUID_EXTENDED_TOPOLOGY,
       0,
@@ -1030,8 +1031,6 @@ GetProcessorLocationByApicId (
     // supported on that processor.
     //
     if (ExtendedTopologyEbx.Uint32 != 0) {
-      TopologyLeafSupported = TRUE;
-
       //
       // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract
       // the SMT sub-field of x2APIC ID.
@@ -1061,26 +1060,40 @@ GetProcessorLocationByApicId (
         }
         SubIndex++;
       } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
+      goto GetLocation;
     }
   }
 
-  if (!TopologyLeafSupported) {
-    AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);
-    MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
-    if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
-      AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);
+  AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);
+  MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
+
+  if (MaxStandardCpuIdIndex >= CPUID_CACHE_PARAMS) {
+    AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);
+    if (CacheParamsEax.Uint32 != 0) {
       MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
+      goto GetBits;
     }
-    else {
-      //
-      // Must be a single-core processor.
-      //
-      MaxCoresPerPackage = 1;
+  }
+
+  if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY) {
+    AsmCpuid(CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx.Uint32, NULL);
+    if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions != 0) {
+      AsmCpuid(CPUID_AMD_PROCESSOR_TOPOLOGY, NULL, &AmdProcessorTopologyEbx.Uint32, NULL, NULL);
+      MaxCoresPerPackage = MaxLogicProcessorsPerPackage / (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1);
+      goto GetBits;
     }
+  }
+
+  //
+  // Must be a single-thread-per-core processor.
+  //
+  MaxCoresPerPackage = MaxLogicProcessorsPerPackage;
 
-    ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
-    CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1);  }
+GetBits:
+  ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
+  CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1);
 
+GetLocation:
   if (Thread != NULL) {
     *Thread  = InitialApicId & ((1 << ThreadBits) - 1);
   }
diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
index e690d2a..a240a44 100644
--- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
+++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
@@ -5,6 +5,8 @@
   which have xAPIC and x2APIC modes.
 
   Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2017, AMD Inc. All rights reserved.<BR>
+
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
   which accompanies this distribution.  The full text of the license may be found at
@@ -16,6 +18,7 @@
 **/
 
 #include <Register/Cpuid.h>
+#include <Register/Amd/Cpuid.h>
 #include <Register/Msr.h>
 #include <Register/LocalApic.h>
 
@@ -1061,20 +1064,22 @@ GetProcessorLocationByApicId (
   OUT UINT32  *Thread  OPTIONAL
   )
 {
-  BOOLEAN                       TopologyLeafSupported;
-  UINTN                         ThreadBits;
-  UINTN                         CoreBits;
-  CPUID_VERSION_INFO_EBX        VersionInfoEbx;
-  CPUID_VERSION_INFO_EDX        VersionInfoEdx;
-  CPUID_CACHE_PARAMS_EAX        CacheParamsEax;
-  CPUID_EXTENDED_TOPOLOGY_EAX   ExtendedTopologyEax;
-  CPUID_EXTENDED_TOPOLOGY_EBX   ExtendedTopologyEbx;
-  CPUID_EXTENDED_TOPOLOGY_ECX   ExtendedTopologyEcx;
-  UINT32                        MaxCpuIdIndex;
-  UINT32                        SubIndex;
-  UINTN                         LevelType;
-  UINT32                        MaxLogicProcessorsPerPackage;
-  UINT32                        MaxCoresPerPackage;
+  CPUID_VERSION_INFO_EBX            VersionInfoEbx;
+  CPUID_VERSION_INFO_EDX            VersionInfoEdx;
+  CPUID_CACHE_PARAMS_EAX            CacheParamsEax;
+  CPUID_EXTENDED_TOPOLOGY_EAX       ExtendedTopologyEax;
+  CPUID_EXTENDED_TOPOLOGY_EBX       ExtendedTopologyEbx;
+  CPUID_EXTENDED_TOPOLOGY_ECX       ExtendedTopologyEcx;
+  CPUID_AMD_EXTENDED_CPU_SIG_ECX    AmdExtendedCpuSigEcx;
+  CPUID_AMD_PROCESSOR_TOPOLOGY_EBX  AmdProcessorTopologyEbx;
+  UINT32                            MaxStandardCpuIdIndex;
+  UINT32                            MaxExtendedCpuIdIndex;
+  UINT32                            SubIndex;
+  UINTN                             LevelType;
+  UINT32                            MaxLogicProcessorsPerPackage;
+  UINT32                            MaxCoresPerPackage;
+  UINTN                             ThreadBits;
+  UINTN                             CoreBits;
 
   //
   // Check if the processor is capable of supporting more than one logical processor.
@@ -1097,20 +1102,16 @@ GetProcessorLocationByApicId (
   CoreBits = 0;
 
   //
-  // Assume three-level mapping of APIC ID: Package:Core:SMT.
+  // Get the max index of CPUID
   //
-  TopologyLeafSupported = FALSE;
-
-  //
-  // Get the max index of basic CPUID
-  //
-  AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
+  AsmCpuid(CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, NULL);
+  AsmCpuid(CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, NULL, NULL, NULL);
 
   //
   // If the extended topology enumeration leaf is available, it
   // is the preferred mechanism for enumerating topology.
   //
-  if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
+  if (MaxStandardCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
     AsmCpuidEx(
       CPUID_EXTENDED_TOPOLOGY,
       0,
@@ -1125,8 +1126,6 @@ GetProcessorLocationByApicId (
     // supported on that processor.
     //
     if (ExtendedTopologyEbx.Uint32 != 0) {
-      TopologyLeafSupported = TRUE;
-
       //
       // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract
       // the SMT sub-field of x2APIC ID.
@@ -1156,26 +1155,40 @@ GetProcessorLocationByApicId (
         }
         SubIndex++;
       } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
+      goto GetLocation;
     }
   }
 
-  if (!TopologyLeafSupported) {
-    AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);
-    MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
-    if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
-      AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);
+  AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);
+  MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
+
+  if (MaxStandardCpuIdIndex >= CPUID_CACHE_PARAMS) {
+    AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);
+    if (CacheParamsEax.Uint32 != 0) {
       MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
+      goto GetBits;
     }
-    else {
-      //
-      // Must be a single-core processor.
-      //
-      MaxCoresPerPackage = 1;
+  }
+
+  if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY) {
+    AsmCpuid(CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx.Uint32, NULL);
+    if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions != 0) {
+      AsmCpuid(CPUID_AMD_PROCESSOR_TOPOLOGY, NULL, &AmdProcessorTopologyEbx.Uint32, NULL, NULL);
+      MaxCoresPerPackage = MaxLogicProcessorsPerPackage / (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1);
+      goto GetBits;
     }
+  }
+
+  //
+  // Must be a single-thread-per-core processor.
+  //
+  MaxCoresPerPackage = MaxLogicProcessorsPerPackage;
 
-    ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
-    CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1);  }
+GetBits:
+  ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
+  CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1);
 
+GetLocation:
   if (Thread != NULL) {
     *Thread  = InitialApicId & ((1 << ThreadBits) - 1);
   }
-- 
2.7.4

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