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20://VDy7R13jKPjwSpy1PW6BnSIHNP5AQeS9v/FuBmhRMK48+bxlGMMru3dauZ6Cc7HEWDYr+7wihfaBVFGLCPVyhvUSzaSSEFmKBCF19WIfDGnSRfCNtnTLcab/Jo1HhHzAoUPG+zyiVUIIZ+WjhXMUbVNwM4JMSiaZHa26lV6QiFTgVOjop/lbcKiULtjfzz4lWEPKeZLkonhWQ1am+bG81YDFE/a3LgZ8FA758mzfcEn5dI7JpQ5cI5eSmLiOA5 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Mar 2017 23:36:13.8283 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1248 Subject: [edk2] [PATCH] UefiCpuPkg/CpuDxe: Add support for PCD PcdPteMemoryEncryptionAddressOrMask X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Feng Tian , Brijesh Singh , Leo Duran , Laszlo Ersek , Jeff Fan , Star Zeng Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This PCD holds the address mask for page table entries when memory encryption is enabled on AMD processors supporting the Secure Encrypted Virtualization (SEV) feature. The mask is applied when page tables entries are created or modified. CC: Jeff Fan Cc: Feng Tian Cc: Star Zeng Cc: Laszlo Ersek Cc: Brijesh Singh Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leo Duran Reviewed-by: Jeff Fan --- UefiCpuPkg/CpuDxe/CpuDxe.inf | 5 +++++ UefiCpuPkg/CpuDxe/CpuPageTable.c | 30 +++++++++++++++++++++--------- 2 files changed, 26 insertions(+), 9 deletions(-) diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.inf b/UefiCpuPkg/CpuDxe/CpuDxe.inf index e568ceb..ec535e8 100644 --- a/UefiCpuPkg/CpuDxe/CpuDxe.inf +++ b/UefiCpuPkg/CpuDxe/CpuDxe.inf @@ -2,6 +2,8 @@ # CPU driver installs CPU Architecture Protocol and CPU MP protocol. # # Copyright (c) 2008 - 2017, Intel Corporation. All rights reserved.
+# Copyright (c) 2017, AMD Incorporated. All rights reserved.
+# # This program and the accompanying materials # are licensed and made available under the terms and conditions of the B= SD License # which accompanies this distribution. The full text of the license may = be found at @@ -77,6 +79,9 @@ gEfiSecPlatformInformation2PpiGuid ## UNDEFINED # HOB gEfiSecPlatformInformationPpiGuid ## UNDEFINED # HOB =20 + [Pcd] + gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask #= # CONSUMES + [Depex] TRUE =20 diff --git a/UefiCpuPkg/CpuDxe/CpuPageTable.c b/UefiCpuPkg/CpuDxe/CpuPageTa= ble.c index 202d1d9..65f607a 100644 --- a/UefiCpuPkg/CpuDxe/CpuPageTable.c +++ b/UefiCpuPkg/CpuDxe/CpuPageTable.c @@ -2,6 +2,8 @@ Page table management support. =20 Copyright (c) 2017, Intel Corporation. All rights reserved.
+ Copyright (c) 2017, AMD Incorporated. All rights reserved.
+ This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License which accompanies this distribution. The full text of the license may b= e found at @@ -271,6 +273,7 @@ GetPageTableEntry ( UINT64 *L2PageTable; UINT64 *L3PageTable; UINT64 *L4PageTable; + UINT64 AddressEncMask; =20 ASSERT (PagingContext !=3D NULL); =20 @@ -279,6 +282,10 @@ GetPageTableEntry ( Index2 =3D ((UINTN)Address >> 21) & PAGING_PAE_INDEX_MASK; Index1 =3D ((UINTN)Address >> 12) & PAGING_PAE_INDEX_MASK; =20 + // Make sure AddressEncMask is contained to smallest supported address f= ield. + // + AddressEncMask =3D PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & PAGI= NG_1G_ADDRESS_MASK_64; + if (PagingContext->MachineType =3D=3D IMAGE_FILE_MACHINE_X64) { L4PageTable =3D (UINT64 *)(UINTN)PagingContext->ContextData.X64.PageTa= bleBase; if (L4PageTable[Index4] =3D=3D 0) { @@ -286,7 +293,7 @@ GetPageTableEntry ( return NULL; } =20 - L3PageTable =3D (UINT64 *)(UINTN)(L4PageTable[Index4] & PAGING_4K_ADDR= ESS_MASK_64); + L3PageTable =3D (UINT64 *)(UINTN)(L4PageTable[Index4] & ~AddressEncMas= k & PAGING_4K_ADDRESS_MASK_64); } else { ASSERT((PagingContext->ContextData.Ia32.Attributes & PAGE_TABLE_LIB_PA= GING_CONTEXT_IA32_X64_ATTRIBUTES_PAE) !=3D 0); L3PageTable =3D (UINT64 *)(UINTN)PagingContext->ContextData.Ia32.PageT= ableBase; @@ -301,7 +308,7 @@ GetPageTableEntry ( return &L3PageTable[Index3]; } =20 - L2PageTable =3D (UINT64 *)(UINTN)(L3PageTable[Index3] & PAGING_4K_ADDRES= S_MASK_64); + L2PageTable =3D (UINT64 *)(UINTN)(L3PageTable[Index3] & ~AddressEncMask = & PAGING_4K_ADDRESS_MASK_64); if (L2PageTable[Index2] =3D=3D 0) { *PageAttribute =3D PageNone; return NULL; @@ -313,7 +320,7 @@ GetPageTableEntry ( } =20 // 4k - L1PageTable =3D (UINT64 *)(UINTN)(L2PageTable[Index2] & PAGING_4K_ADDRES= S_MASK_64); + L1PageTable =3D (UINT64 *)(UINTN)(L2PageTable[Index2] & ~AddressEncMask = & PAGING_4K_ADDRESS_MASK_64); if ((L1PageTable[Index1] =3D=3D 0) && (Address !=3D 0)) { *PageAttribute =3D PageNone; return NULL; @@ -499,11 +506,16 @@ SplitPage ( UINT64 BaseAddress; UINT64 *NewPageEntry; UINTN Index; + UINT64 AddressEncMask; =20 ASSERT (PageAttribute =3D=3D Page2M || PageAttribute =3D=3D Page1G); =20 ASSERT (AllocatePagesFunc !=3D NULL); =20 + // Make sure AddressEncMask is contained to smallest supported address f= ield. + // + AddressEncMask =3D PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & PAGI= NG_1G_ADDRESS_MASK_64; + if (PageAttribute =3D=3D Page2M) { // // Split 2M to 4K @@ -515,11 +527,11 @@ SplitPage ( if (NewPageEntry =3D=3D NULL) { return RETURN_OUT_OF_RESOURCES; } - BaseAddress =3D *PageEntry & PAGING_2M_ADDRESS_MASK_64; + BaseAddress =3D *PageEntry & ~AddressEncMask & PAGING_2M_ADDRESS_MAS= K_64; for (Index =3D 0; Index < SIZE_4KB / sizeof(UINT64); Index++) { - NewPageEntry[Index] =3D BaseAddress + SIZE_4KB * Index + ((*PageEn= try) & PAGE_PROGATE_BITS); + NewPageEntry[Index] =3D (BaseAddress + SIZE_4KB * Index) | Address= EncMask | ((*PageEntry) & PAGE_PROGATE_BITS); } - (*PageEntry) =3D (UINT64)(UINTN)NewPageEntry + ((*PageEntry) & PAGE_= PROGATE_BITS); + (*PageEntry) =3D (UINT64)(UINTN)NewPageEntry | AddressEncMask | ((*P= ageEntry) & PAGE_PROGATE_BITS); return RETURN_SUCCESS; } else { return RETURN_UNSUPPORTED; @@ -536,11 +548,11 @@ SplitPage ( if (NewPageEntry =3D=3D NULL) { return RETURN_OUT_OF_RESOURCES; } - BaseAddress =3D *PageEntry & PAGING_1G_ADDRESS_MASK_64; + BaseAddress =3D *PageEntry & ~AddressEncMask & PAGING_1G_ADDRESS_MA= SK_64; for (Index =3D 0; Index < SIZE_4KB / sizeof(UINT64); Index++) { - NewPageEntry[Index] =3D BaseAddress + SIZE_2MB * Index + IA32_PG_P= S + ((*PageEntry) & PAGE_PROGATE_BITS); + NewPageEntry[Index] =3D (BaseAddress + SIZE_2MB * Index) | Address= EncMask | IA32_PG_PS | ((*PageEntry) & PAGE_PROGATE_BITS); } - (*PageEntry) =3D (UINT64)(UINTN)NewPageEntry + ((*PageEntry) & PAGE_= PROGATE_BITS); + (*PageEntry) =3D (UINT64)(UINTN)NewPageEntry | AddressEncMask | ((*P= ageEntry) & PAGE_PROGATE_BITS); return RETURN_SUCCESS; } else { return RETURN_UNSUPPORTED; --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel