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20:9y0eRAd+LoTIDMjAikSqbAEXnvdHN/vPsTe7yo/dfR8JuJ0cLsy474cLdvsA78aaytEzTfQD4xTZlTrLi4MZgGQy7T6liu8uM7HG1Hr68UQ/biso709zTG7VH5cpfYKzzGMUUmTM1OS1D6KTd9ql+3HSECs3LLHoWS/OW/UZFULztwnn4HJ4pr6gYcdMeqvCk2D0e8ybaucG3DrbfEEOxuCHG+NEk6J8I9MnDc2yj1O111/TQbGXrNI32dPpiOQS X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Feb 2017 17:43:19.0642 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR12MB1238 Subject: [edk2] [PATCH v4 2/6] MdeModulePkg/Core/DxeIplPeim: Add support for PCD PcdPteMemoryEncryptionAddressOrMask X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laszlo Ersek , Feng Tian , Leo Duran , Brijesh Singh , Star Zeng Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This PCD holds the address mask for page table entries when memory encryption is enabled on AMD processors supporting the Secure Encrypted Virtualization (SEV) feature. The mask is applied when creating page tables. Cc: Feng Tian Cc: Star Zeng Cc: Laszlo Ersek Cc: Brijesh Singh Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leo Duran Reviewed-by: Star Zeng --- MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf | 5 ++- MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c | 12 ++++++-- MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c | 39 +++++++++++++++++++-= ---- MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h | 5 +++ 4 files changed, 50 insertions(+), 11 deletions(-) diff --git a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf b/MdeModulePkg/Core/Dx= eIplPeim/DxeIpl.inf index 2bc41be..d62bd9b 100644 --- a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf +++ b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf @@ -6,6 +6,8 @@ # needed to run the DXE Foundation. # # Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+# Copyright (c) 2017, AMD Incorporated. All rights reserved.
+# # This program and the accompanying materials # are licensed and made available under the terms and conditions of the B= SD License # which accompanies this distribution. The full text of the license may = be found at @@ -111,7 +113,8 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSupportUefiDecompress ## CONSUMES =20 [Pcd.IA32,Pcd.X64] - gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable ## SOMETIM= ES_CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable ##= SOMETIMES_CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask ##= CONSUMES =20 [Pcd.IA32,Pcd.X64,Pcd.ARM,Pcd.AARCH64] gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack ## SOMETIM= ES_CONSUMES diff --git a/MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c b/MdeModulePkg= /Core/DxeIplPeim/Ia32/DxeLoadFunc.c index 8f6a97a..1957326 100644 --- a/MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c +++ b/MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c @@ -2,6 +2,8 @@ Ia32-specific functionality for DxeLoad. =20 Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.
+Copyright (c) 2017, AMD Incorporated. All rights reserved.
+ This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License which accompanies this distribution. The full text of the license may be = found at @@ -82,6 +84,12 @@ Create4GPageTablesIa32Pae ( PAGE_TABLE_ENTRY *PageDirectoryEntry; UINTN TotalPagesNum; UINTN PageAddress; + UINT64 AddressEncMask; + + // + // Make sure AddressEncMask is contained to smallest supported address f= ield + // + AddressEncMask =3D PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & PAGI= NG_1G_ADDRESS_MASK_64; =20 PhysicalAddressBits =3D 32; =20 @@ -111,7 +119,7 @@ Create4GPageTablesIa32Pae ( // // Fill in a Page Directory Pointer Entries // - PageDirectoryPointerEntry->Uint64 =3D (UINT64) (UINTN) PageDirectoryEn= try; + PageDirectoryPointerEntry->Uint64 =3D (UINT64) (UINTN) PageDirectoryEn= try | AddressEncMask; PageDirectoryPointerEntry->Bits.Present =3D 1; =20 for (IndexOfPageDirectoryEntries =3D 0; IndexOfPageDirectoryEntries < = 512; IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PhysicalAddress += =3D SIZE_2MB) { @@ -124,7 +132,7 @@ Create4GPageTablesIa32Pae ( // // Fill in the Page Directory entries // - PageDirectoryEntry->Uint64 =3D (UINT64) PhysicalAddress; + PageDirectoryEntry->Uint64 =3D (UINT64) PhysicalAddress | AddressE= ncMask; PageDirectoryEntry->Bits.ReadWrite =3D 1; PageDirectoryEntry->Bits.Present =3D 1; PageDirectoryEntry->Bits.MustBe1 =3D 1; diff --git a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c b/MdeModulePk= g/Core/DxeIplPeim/X64/VirtualMemory.c index 790f6ab..48150be 100644 --- a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c +++ b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c @@ -16,6 +16,8 @@ 3) IA-32 Intel(R) Architecture Software Developer's Manual Volume 3:Sy= stem Programmer's Guide, Intel =20 Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2017, AMD Incorporated. All rights reserved.
+ This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License which accompanies this distribution. The full text of the license may be = found at @@ -29,6 +31,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER= EXPRESS OR IMPLIED. #include "DxeIpl.h" #include "VirtualMemory.h" =20 + /** Enable Execute Disable Bit. =20 @@ -65,20 +68,27 @@ Split2MPageTo4K ( EFI_PHYSICAL_ADDRESS PhysicalAddress4K; UINTN IndexOfPageTableEntries; PAGE_TABLE_4K_ENTRY *PageTableEntry; + UINT64 AddressEncMask; + + // + // Make sure AddressEncMask is contained to smallest supported address f= ield + // + AddressEncMask =3D PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & PAGI= NG_1G_ADDRESS_MASK_64; =20 PageTableEntry =3D AllocatePages (1); ASSERT (PageTableEntry !=3D NULL); + // // Fill in 2M page entry. // - *PageEntry2M =3D (UINT64) (UINTN) PageTableEntry | IA32_PG_P | IA32_PG_R= W; + *PageEntry2M =3D (UINT64) (UINTN) PageTableEntry | AddressEncMask | IA32= _PG_P | IA32_PG_RW; =20 PhysicalAddress4K =3D PhysicalAddress; for (IndexOfPageTableEntries =3D 0; IndexOfPageTableEntries < 512; Index= OfPageTableEntries++, PageTableEntry++, PhysicalAddress4K +=3D SIZE_4KB) { // // Fill in the Page Table entries // - PageTableEntry->Uint64 =3D (UINT64) PhysicalAddress4K; + PageTableEntry->Uint64 =3D (UINT64) PhysicalAddress4K | AddressEncMask; PageTableEntry->Bits.ReadWrite =3D 1; PageTableEntry->Bits.Present =3D 1; if ((PhysicalAddress4K >=3D StackBase) && (PhysicalAddress4K < StackBa= se + StackSize)) { @@ -110,13 +120,20 @@ Split1GPageTo2M ( EFI_PHYSICAL_ADDRESS PhysicalAddress2M; UINTN IndexOfPageDirectoryEntries; PAGE_TABLE_ENTRY *PageDirectoryEntry; + UINT64 AddressEncMask; + + // + // Make sure AddressEncMask is contained to smallest supported address f= ield + // + AddressEncMask =3D PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & PAGI= NG_1G_ADDRESS_MASK_64; =20 PageDirectoryEntry =3D AllocatePages (1); ASSERT (PageDirectoryEntry !=3D NULL); + // // Fill in 1G page entry. // - *PageEntry1G =3D (UINT64) (UINTN) PageDirectoryEntry | IA32_PG_P | IA32_= PG_RW; + *PageEntry1G =3D (UINT64) (UINTN) PageDirectoryEntry | AddressEncMask | = IA32_PG_P | IA32_PG_RW; =20 PhysicalAddress2M =3D PhysicalAddress; for (IndexOfPageDirectoryEntries =3D 0; IndexOfPageDirectoryEntries < 51= 2; IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PhysicalAddress2M += =3D SIZE_2MB) { @@ -129,7 +146,7 @@ Split1GPageTo2M ( // // Fill in the Page Directory entries // - PageDirectoryEntry->Uint64 =3D (UINT64) PhysicalAddress2M; + PageDirectoryEntry->Uint64 =3D (UINT64) PhysicalAddress2M | AddressE= ncMask; PageDirectoryEntry->Bits.ReadWrite =3D 1; PageDirectoryEntry->Bits.Present =3D 1; PageDirectoryEntry->Bits.MustBe1 =3D 1; @@ -171,6 +188,12 @@ CreateIdentityMappingPageTables ( VOID *Hob; BOOLEAN Page1GSupport; PAGE_TABLE_1G_ENTRY *PageDirectory1GEntry; + UINT64 AddressEncMask; + + // + // Make sure AddressEncMask is contained to smallest supported address f= ield + // + AddressEncMask =3D PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & PAGI= NG_1G_ADDRESS_MASK_64; =20 Page1GSupport =3D FALSE; if (PcdGetBool(PcdUse1GPageTable)) { @@ -248,7 +271,7 @@ CreateIdentityMappingPageTables ( // // Make a PML4 Entry // - PageMapLevel4Entry->Uint64 =3D (UINT64)(UINTN)PageDirectoryPointerEntr= y; + PageMapLevel4Entry->Uint64 =3D (UINT64)(UINTN)PageDirectoryPointerEntr= y | AddressEncMask; PageMapLevel4Entry->Bits.ReadWrite =3D 1; PageMapLevel4Entry->Bits.Present =3D 1; =20 @@ -262,7 +285,7 @@ CreateIdentityMappingPageTables ( // // Fill in the Page Directory entries // - PageDirectory1GEntry->Uint64 =3D (UINT64)PageAddress; + PageDirectory1GEntry->Uint64 =3D (UINT64)PageAddress | AddressEn= cMask; PageDirectory1GEntry->Bits.ReadWrite =3D 1; PageDirectory1GEntry->Bits.Present =3D 1; PageDirectory1GEntry->Bits.MustBe1 =3D 1; @@ -280,7 +303,7 @@ CreateIdentityMappingPageTables ( // // Fill in a Page Directory Pointer Entries // - PageDirectoryPointerEntry->Uint64 =3D (UINT64)(UINTN)PageDirectory= Entry; + PageDirectoryPointerEntry->Uint64 =3D (UINT64)(UINTN)PageDirectory= Entry | AddressEncMask; PageDirectoryPointerEntry->Bits.ReadWrite =3D 1; PageDirectoryPointerEntry->Bits.Present =3D 1; =20 @@ -294,7 +317,7 @@ CreateIdentityMappingPageTables ( // // Fill in the Page Directory entries // - PageDirectoryEntry->Uint64 =3D (UINT64)PageAddress; + PageDirectoryEntry->Uint64 =3D (UINT64)PageAddress | AddressEn= cMask; PageDirectoryEntry->Bits.ReadWrite =3D 1; PageDirectoryEntry->Bits.Present =3D 1; PageDirectoryEntry->Bits.MustBe1 =3D 1; diff --git a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h b/MdeModulePk= g/Core/DxeIplPeim/X64/VirtualMemory.h index 20c31f5..7c9bb49 100644 --- a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h +++ b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h @@ -8,6 +8,8 @@ 4) AMD64 Architecture Programmer's Manual Volume 2: System Programming =20 Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.
+Copyright (c) 2017, AMD Incorporated. All rights reserved.
+ This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License which accompanies this distribution. The full text of the license may be = found at @@ -23,6 +25,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER= EXPRESS OR IMPLIED. =20 #define SYS_CODE64_SEL 0x38 =20 + #pragma pack(1) =20 typedef union { @@ -148,6 +151,8 @@ typedef union { #define IA32_PG_P BIT0 #define IA32_PG_RW BIT1 =20 +#define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull + /** Enable Execute Disable Bit. =20 --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel