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20:YNewy8YMlDnlAlroeUUZ8lG/h7BNHy7KX0VU9FAkZ7gh0VjM27e5U9tEu/ug4L/9Vezg0jvDrjItRvNvV1g54Xo7uDz3wh8LVjqQIKOZWfFIKxrOg+lrmDniiKPceOJ4G2pZwwlGZPXhZoLho9VIClhpe/ksHCYQp3uGQkmUDIl7uvD30vt5DwkXuemrIOxTfFxCd+SeDZllj9KaohfUzTJJQkxjOXEIwXNebO5r8VzDeyl39Eu0OI2ZlnsaI9Uq X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Feb 2017 17:43:18.3816 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR12MB1238 Subject: [edk2] [PATCH v4 1/6] MdeModulePkg: Add PCD PcdPteMemoryEncryptionAddressOrMask X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laszlo Ersek , Feng Tian , Leo Duran , Brijesh Singh , Star Zeng Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This PCD holds the address mask for page table entries when memory encryption is enabled on AMD processors supporting the Secure Encrypted Virtualization (SEV) feature. Cc: Feng Tian Cc: Star Zeng Cc: Laszlo Ersek Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Brijesh Singh Signed-off-by: Leo Duran Reviewed-by: Star Zeng Reviewed-by: Star Zeng to MdeModulePkg changes. --- MdeModulePkg/MdeModulePkg.dec | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MdeModulePkg/MdeModulePkg.dec b/MdeModulePkg/MdeModulePkg.dec index 426634f..f45ca84 100644 --- a/MdeModulePkg/MdeModulePkg.dec +++ b/MdeModulePkg/MdeModulePkg.dec @@ -6,6 +6,8 @@ # Copyright (c) 2007 - 2017, Intel Corporation. All rights reserved.
# Copyright (c) 2016, Linaro Ltd. All rights reserved.
# (C) Copyright 2016 Hewlett Packard Enterprise Development LP
+# Copyright (c) 2017, AMD Incorporated. All rights reserved.
+# # This program and the accompanying materials are licensed and made availa= ble under # the terms and conditions of the BSD License that accompanies this distri= bution. # The full text of the license may be found at @@ -1702,6 +1704,12 @@ # @Prompt A list of system FMP ImageTypeId GUIDs gEfiMdeModulePkgTokenSpaceGuid.PcdSystemFmpCapsuleImageTypeIdGuid|{0x0}|= VOID*|0x30001046 =20 + ## This PCD holds the address mask for page table entries when memory en= cryption is + # enabled on AMD processors supporting the Secure Encrypted Virtualizat= ion (SEV) feature. + # This mask should be applied when creating 1:1 virtual to physical map= ping tables. + # + gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask|0x0|U= INT64|0x30001047 + [PcdsPatchableInModule] ## Specify memory size with page number for PEI code when # Loading Module at Fixed Address feature is enabled. --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat Nov 2 14:41:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zoho.com; 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20:9y0eRAd+LoTIDMjAikSqbAEXnvdHN/vPsTe7yo/dfR8JuJ0cLsy474cLdvsA78aaytEzTfQD4xTZlTrLi4MZgGQy7T6liu8uM7HG1Hr68UQ/biso709zTG7VH5cpfYKzzGMUUmTM1OS1D6KTd9ql+3HSECs3LLHoWS/OW/UZFULztwnn4HJ4pr6gYcdMeqvCk2D0e8ybaucG3DrbfEEOxuCHG+NEk6J8I9MnDc2yj1O111/TQbGXrNI32dPpiOQS X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Feb 2017 17:43:19.0642 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR12MB1238 Subject: [edk2] [PATCH v4 2/6] MdeModulePkg/Core/DxeIplPeim: Add support for PCD PcdPteMemoryEncryptionAddressOrMask X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laszlo Ersek , Feng Tian , Leo Duran , Brijesh Singh , Star Zeng Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This PCD holds the address mask for page table entries when memory encryption is enabled on AMD processors supporting the Secure Encrypted Virtualization (SEV) feature. The mask is applied when creating page tables. Cc: Feng Tian Cc: Star Zeng Cc: Laszlo Ersek Cc: Brijesh Singh Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leo Duran Reviewed-by: Star Zeng --- MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf | 5 ++- MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c | 12 ++++++-- MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c | 39 +++++++++++++++++++-= ---- MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h | 5 +++ 4 files changed, 50 insertions(+), 11 deletions(-) diff --git a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf b/MdeModulePkg/Core/Dx= eIplPeim/DxeIpl.inf index 2bc41be..d62bd9b 100644 --- a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf +++ b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf @@ -6,6 +6,8 @@ # needed to run the DXE Foundation. # # Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+# Copyright (c) 2017, AMD Incorporated. All rights reserved.
+# # This program and the accompanying materials # are licensed and made available under the terms and conditions of the B= SD License # which accompanies this distribution. The full text of the license may = be found at @@ -111,7 +113,8 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSupportUefiDecompress ## CONSUMES =20 [Pcd.IA32,Pcd.X64] - gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable ## SOMETIM= ES_CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable ##= SOMETIMES_CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask ##= CONSUMES =20 [Pcd.IA32,Pcd.X64,Pcd.ARM,Pcd.AARCH64] gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack ## SOMETIM= ES_CONSUMES diff --git a/MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c b/MdeModulePkg= /Core/DxeIplPeim/Ia32/DxeLoadFunc.c index 8f6a97a..1957326 100644 --- a/MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c +++ b/MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c @@ -2,6 +2,8 @@ Ia32-specific functionality for DxeLoad. =20 Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.
+Copyright (c) 2017, AMD Incorporated. All rights reserved.
+ This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License which accompanies this distribution. The full text of the license may be = found at @@ -82,6 +84,12 @@ Create4GPageTablesIa32Pae ( PAGE_TABLE_ENTRY *PageDirectoryEntry; UINTN TotalPagesNum; UINTN PageAddress; + UINT64 AddressEncMask; + + // + // Make sure AddressEncMask is contained to smallest supported address f= ield + // + AddressEncMask =3D PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & PAGI= NG_1G_ADDRESS_MASK_64; =20 PhysicalAddressBits =3D 32; =20 @@ -111,7 +119,7 @@ Create4GPageTablesIa32Pae ( // // Fill in a Page Directory Pointer Entries // - PageDirectoryPointerEntry->Uint64 =3D (UINT64) (UINTN) PageDirectoryEn= try; + PageDirectoryPointerEntry->Uint64 =3D (UINT64) (UINTN) PageDirectoryEn= try | AddressEncMask; PageDirectoryPointerEntry->Bits.Present =3D 1; =20 for (IndexOfPageDirectoryEntries =3D 0; IndexOfPageDirectoryEntries < = 512; IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PhysicalAddress += =3D SIZE_2MB) { @@ -124,7 +132,7 @@ Create4GPageTablesIa32Pae ( // // Fill in the Page Directory entries // - PageDirectoryEntry->Uint64 =3D (UINT64) PhysicalAddress; + PageDirectoryEntry->Uint64 =3D (UINT64) PhysicalAddress | AddressE= ncMask; PageDirectoryEntry->Bits.ReadWrite =3D 1; PageDirectoryEntry->Bits.Present =3D 1; PageDirectoryEntry->Bits.MustBe1 =3D 1; diff --git a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c b/MdeModulePk= g/Core/DxeIplPeim/X64/VirtualMemory.c index 790f6ab..48150be 100644 --- a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c +++ b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c @@ -16,6 +16,8 @@ 3) IA-32 Intel(R) Architecture Software Developer's Manual Volume 3:Sy= stem Programmer's Guide, Intel =20 Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2017, AMD Incorporated. All rights reserved.
+ This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License which accompanies this distribution. The full text of the license may be = found at @@ -29,6 +31,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER= EXPRESS OR IMPLIED. #include "DxeIpl.h" #include "VirtualMemory.h" =20 + /** Enable Execute Disable Bit. =20 @@ -65,20 +68,27 @@ Split2MPageTo4K ( EFI_PHYSICAL_ADDRESS PhysicalAddress4K; UINTN IndexOfPageTableEntries; PAGE_TABLE_4K_ENTRY *PageTableEntry; + UINT64 AddressEncMask; + + // + // Make sure AddressEncMask is contained to smallest supported address f= ield + // + AddressEncMask =3D PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & PAGI= NG_1G_ADDRESS_MASK_64; =20 PageTableEntry =3D AllocatePages (1); ASSERT (PageTableEntry !=3D NULL); + // // Fill in 2M page entry. // - *PageEntry2M =3D (UINT64) (UINTN) PageTableEntry | IA32_PG_P | IA32_PG_R= W; + *PageEntry2M =3D (UINT64) (UINTN) PageTableEntry | AddressEncMask | IA32= _PG_P | IA32_PG_RW; =20 PhysicalAddress4K =3D PhysicalAddress; for (IndexOfPageTableEntries =3D 0; IndexOfPageTableEntries < 512; Index= OfPageTableEntries++, PageTableEntry++, PhysicalAddress4K +=3D SIZE_4KB) { // // Fill in the Page Table entries // - PageTableEntry->Uint64 =3D (UINT64) PhysicalAddress4K; + PageTableEntry->Uint64 =3D (UINT64) PhysicalAddress4K | AddressEncMask; PageTableEntry->Bits.ReadWrite =3D 1; PageTableEntry->Bits.Present =3D 1; if ((PhysicalAddress4K >=3D StackBase) && (PhysicalAddress4K < StackBa= se + StackSize)) { @@ -110,13 +120,20 @@ Split1GPageTo2M ( EFI_PHYSICAL_ADDRESS PhysicalAddress2M; UINTN IndexOfPageDirectoryEntries; PAGE_TABLE_ENTRY *PageDirectoryEntry; + UINT64 AddressEncMask; + + // + // Make sure AddressEncMask is contained to smallest supported address f= ield + // + AddressEncMask =3D PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & PAGI= NG_1G_ADDRESS_MASK_64; =20 PageDirectoryEntry =3D AllocatePages (1); ASSERT (PageDirectoryEntry !=3D NULL); + // // Fill in 1G page entry. // - *PageEntry1G =3D (UINT64) (UINTN) PageDirectoryEntry | IA32_PG_P | IA32_= PG_RW; + *PageEntry1G =3D (UINT64) (UINTN) PageDirectoryEntry | AddressEncMask | = IA32_PG_P | IA32_PG_RW; =20 PhysicalAddress2M =3D PhysicalAddress; for (IndexOfPageDirectoryEntries =3D 0; IndexOfPageDirectoryEntries < 51= 2; IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PhysicalAddress2M += =3D SIZE_2MB) { @@ -129,7 +146,7 @@ Split1GPageTo2M ( // // Fill in the Page Directory entries // - PageDirectoryEntry->Uint64 =3D (UINT64) PhysicalAddress2M; + PageDirectoryEntry->Uint64 =3D (UINT64) PhysicalAddress2M | AddressE= ncMask; PageDirectoryEntry->Bits.ReadWrite =3D 1; PageDirectoryEntry->Bits.Present =3D 1; PageDirectoryEntry->Bits.MustBe1 =3D 1; @@ -171,6 +188,12 @@ CreateIdentityMappingPageTables ( VOID *Hob; BOOLEAN Page1GSupport; PAGE_TABLE_1G_ENTRY *PageDirectory1GEntry; + UINT64 AddressEncMask; + + // + // Make sure AddressEncMask is contained to smallest supported address f= ield + // + AddressEncMask =3D PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & PAGI= NG_1G_ADDRESS_MASK_64; =20 Page1GSupport =3D FALSE; if (PcdGetBool(PcdUse1GPageTable)) { @@ -248,7 +271,7 @@ CreateIdentityMappingPageTables ( // // Make a PML4 Entry // - PageMapLevel4Entry->Uint64 =3D (UINT64)(UINTN)PageDirectoryPointerEntr= y; + PageMapLevel4Entry->Uint64 =3D (UINT64)(UINTN)PageDirectoryPointerEntr= y | AddressEncMask; PageMapLevel4Entry->Bits.ReadWrite =3D 1; PageMapLevel4Entry->Bits.Present =3D 1; =20 @@ -262,7 +285,7 @@ CreateIdentityMappingPageTables ( // // Fill in the Page Directory entries // - PageDirectory1GEntry->Uint64 =3D (UINT64)PageAddress; + PageDirectory1GEntry->Uint64 =3D (UINT64)PageAddress | AddressEn= cMask; PageDirectory1GEntry->Bits.ReadWrite =3D 1; PageDirectory1GEntry->Bits.Present =3D 1; PageDirectory1GEntry->Bits.MustBe1 =3D 1; @@ -280,7 +303,7 @@ CreateIdentityMappingPageTables ( // // Fill in a Page Directory Pointer Entries // - PageDirectoryPointerEntry->Uint64 =3D (UINT64)(UINTN)PageDirectory= Entry; + PageDirectoryPointerEntry->Uint64 =3D (UINT64)(UINTN)PageDirectory= Entry | AddressEncMask; PageDirectoryPointerEntry->Bits.ReadWrite =3D 1; PageDirectoryPointerEntry->Bits.Present =3D 1; =20 @@ -294,7 +317,7 @@ CreateIdentityMappingPageTables ( // // Fill in the Page Directory entries // - PageDirectoryEntry->Uint64 =3D (UINT64)PageAddress; + PageDirectoryEntry->Uint64 =3D (UINT64)PageAddress | AddressEn= cMask; PageDirectoryEntry->Bits.ReadWrite =3D 1; PageDirectoryEntry->Bits.Present =3D 1; PageDirectoryEntry->Bits.MustBe1 =3D 1; diff --git a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h b/MdeModulePk= g/Core/DxeIplPeim/X64/VirtualMemory.h index 20c31f5..7c9bb49 100644 --- a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h +++ b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h @@ -8,6 +8,8 @@ 4) AMD64 Architecture Programmer's Manual Volume 2: System Programming =20 Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.
+Copyright (c) 2017, AMD Incorporated. All rights reserved.
+ This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License which accompanies this distribution. The full text of the license may be = found at @@ -23,6 +25,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER= EXPRESS OR IMPLIED. =20 #define SYS_CODE64_SEL 0x38 =20 + #pragma pack(1) =20 typedef union { @@ -148,6 +151,8 @@ typedef union { #define IA32_PG_P BIT0 #define IA32_PG_RW BIT1 =20 +#define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull + /** Enable Execute Disable Bit. =20 --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat Nov 2 14:41:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zoho.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1488131009388373.10911204386025; Sun, 26 Feb 2017 09:43:29 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 9329E82136; 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20:u3GVnMWZaJN4oCXxUqoyVe0+0xgVsOYq2RTYgpXVeEDCAmmYrP92h3Y9dMaHVgBvm8qARwtfz7liRfrSXuypB1lDHyl4Eg98LBdm0XvnFA6EhOPEOg4xK9qZbo9gH3wMGbFYDszrswDo7p2IVAzXa5XGJ0F0qkIqggd5KZAeKus14hxEFg8OkJtoubtO32cLG6Q1unGF1qiv3xhcURrbOb6h6KieKkUjxKM62HVXh5JgPhJCmtd1UkwvHv3NX0ai X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Feb 2017 17:43:19.6677 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR12MB1238 Subject: [edk2] [PATCH v4 3/6] MdeModulePkg/Universal/CapsulePei: Add support for PCD PcdPteMemoryEncryptionAddressOrMask X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laszlo Ersek , Feng Tian , Leo Duran , Brijesh Singh , Star Zeng Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This PCD holds the address mask for page table entries when memory encryption is enabled on AMD processors supporting the Secure Encrypted Virtualization (SEV) feature. The mask is applied when 4GB tables are created (UefiCapsule.c), and when the tables are expanded on-demand by page-faults above 4GB's (X64Entry.c). Cc: Feng Tian Cc: Star Zeng Cc: Laszlo Ersek Cc: Brijesh Singh Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leo Duran Reviewed-by: Star Zeng --- MdeModulePkg/Universal/CapsulePei/CapsulePei.inf | 2 ++ .../Universal/CapsulePei/Common/CommonHeader.h | 5 +++++ MdeModulePkg/Universal/CapsulePei/UefiCapsule.c | 17 +++++++++++---- MdeModulePkg/Universal/CapsulePei/X64/X64Entry.c | 24 +++++++++++++++---= ---- 4 files changed, 37 insertions(+), 11 deletions(-) diff --git a/MdeModulePkg/Universal/CapsulePei/CapsulePei.inf b/MdeModulePk= g/Universal/CapsulePei/CapsulePei.inf index d2ca0d0..c54bc21 100644 --- a/MdeModulePkg/Universal/CapsulePei/CapsulePei.inf +++ b/MdeModulePkg/Universal/CapsulePei/CapsulePei.inf @@ -7,6 +7,7 @@ # buffer overflow, integer overflow. # # Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+# Copyright (c) 2017, AMD Incorporated. All rights reserved.
# # This program and the accompanying materials # are licensed and made available under the terms and conditions @@ -76,6 +77,7 @@ [Pcd.IA32] gEfiMdeModulePkgTokenSpaceGuid.PcdCapsuleCoalesceFile ## SOMETIMES_C= ONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable ## SOMETIMES_C= ONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask ##= CONSUMES =20 [FeaturePcd.IA32] gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode ## CONSUMES diff --git a/MdeModulePkg/Universal/CapsulePei/Common/CommonHeader.h b/MdeM= odulePkg/Universal/CapsulePei/Common/CommonHeader.h index 7298874..cac4442 100644 --- a/MdeModulePkg/Universal/CapsulePei/Common/CommonHeader.h +++ b/MdeModulePkg/Universal/CapsulePei/Common/CommonHeader.h @@ -2,6 +2,8 @@ Common header file. =20 Copyright (c) 2011 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2017, AMD Incorporated. All rights reserved.
+ This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License which accompanies this distribution. The full text of the license may be = found at @@ -20,6 +22,8 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER= EXPRESS OR IMPLIED. // #define EXTRA_PAGE_TABLE_PAGES 8 =20 +#define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull + // // This capsule PEIM puts its private data at the start of the // coalesced capsule. Here's the structure definition. @@ -60,6 +64,7 @@ typedef struct { EFI_PHYSICAL_ADDRESS MemoryBase64Ptr; EFI_PHYSICAL_ADDRESS MemorySize64Ptr; BOOLEAN Page1GSupport; + UINT64 AddressEncMask; } SWITCH_32_TO_64_CONTEXT; =20 typedef struct { diff --git a/MdeModulePkg/Universal/CapsulePei/UefiCapsule.c b/MdeModulePkg= /Universal/CapsulePei/UefiCapsule.c index 9ac9d22..34b095a 100644 --- a/MdeModulePkg/Universal/CapsulePei/UefiCapsule.c +++ b/MdeModulePkg/Universal/CapsulePei/UefiCapsule.c @@ -2,6 +2,7 @@ Capsule update PEIM for UEFI2.0 =20 Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2017, AMD Incorporated. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions @@ -41,6 +42,7 @@ GLOBAL_REMOVE_IF_UNREFERENCED CONST IA32_DESCRIPTOR mGdt = =3D { (UINTN) mGdtEntries }; =20 + /** The function will check if 1G page is supported. =20 @@ -145,6 +147,12 @@ Create4GPageTables ( PAGE_TABLE_ENTRY *PageDirectoryEntry; UINTN BigPageAddress; PAGE_TABLE_1G_ENTRY *PageDirectory1GEntry; + UINT64 AddressEncMask; + + // + // Make sure AddressEncMask is contained to smallest supported address f= ield. + // + AddressEncMask =3D PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & PAGI= NG_1G_ADDRESS_MASK_64; =20 // // Create 4G page table by default, @@ -187,7 +195,7 @@ Create4GPageTables ( // // Make a PML4 Entry // - PageMapLevel4Entry->Uint64 =3D (UINT64)(UINTN)PageDirectoryPointerEntr= y; + PageMapLevel4Entry->Uint64 =3D (UINT64)(UINTN)PageDirectoryPointerEntr= y | AddressEncMask; PageMapLevel4Entry->Bits.ReadWrite =3D 1; PageMapLevel4Entry->Bits.Present =3D 1; =20 @@ -198,7 +206,7 @@ Create4GPageTables ( // // Fill in the Page Directory entries // - PageDirectory1GEntry->Uint64 =3D (UINT64)PageAddress; + PageDirectory1GEntry->Uint64 =3D (UINT64)PageAddress | AddressEncM= ask; PageDirectory1GEntry->Bits.ReadWrite =3D 1; PageDirectory1GEntry->Bits.Present =3D 1; PageDirectory1GEntry->Bits.MustBe1 =3D 1; @@ -215,7 +223,7 @@ Create4GPageTables ( // // Fill in a Page Directory Pointer Entries // - PageDirectoryPointerEntry->Uint64 =3D (UINT64)(UINTN)PageDirectory= Entry; + PageDirectoryPointerEntry->Uint64 =3D (UINT64)(UINTN)PageDirectory= Entry | AddressEncMask; PageDirectoryPointerEntry->Bits.ReadWrite =3D 1; PageDirectoryPointerEntry->Bits.Present =3D 1; =20 @@ -223,7 +231,7 @@ Create4GPageTables ( // // Fill in the Page Directory entries // - PageDirectoryEntry->Uint64 =3D (UINT64)PageAddress; + PageDirectoryEntry->Uint64 =3D (UINT64)PageAddress | AddressEncM= ask; PageDirectoryEntry->Bits.ReadWrite =3D 1; PageDirectoryEntry->Bits.Present =3D 1; PageDirectoryEntry->Bits.MustBe1 =3D 1; @@ -443,6 +451,7 @@ ModeSwitch ( Context.MemoryBase64Ptr =3D (EFI_PHYSICAL_ADDRESS)(UINTN)&MemoryBa= se64; Context.MemorySize64Ptr =3D (EFI_PHYSICAL_ADDRESS)(UINTN)&MemorySi= ze64; Context.Page1GSupport =3D Page1GSupport; + Context.AddressEncMask =3D PcdGet64 (PcdPteMemoryEncryptionAddres= sOrMask) & PAGING_1G_ADDRESS_MASK_64; =20 // // Prepare data for return back diff --git a/MdeModulePkg/Universal/CapsulePei/X64/X64Entry.c b/MdeModulePk= g/Universal/CapsulePei/X64/X64Entry.c index 5ad95d2..e1871c3 100644 --- a/MdeModulePkg/Universal/CapsulePei/X64/X64Entry.c +++ b/MdeModulePkg/Universal/CapsulePei/X64/X64Entry.c @@ -2,6 +2,8 @@ The X64 entrypoint is used to process capsule in long mode. =20 Copyright (c) 2011 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2017, AMD Incorporated. All rights reserved.
+ This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License which accompanies this distribution. The full text of the license may be = found at @@ -29,6 +31,7 @@ typedef struct _PAGE_FAULT_CONTEXT { UINT64 PhyMask; UINTN PageFaultBuffer; UINTN PageFaultIndex; + UINT64 AddressEncMask; // // Store the uplink information for each page being used. // @@ -114,21 +117,25 @@ AcquirePage ( ) { UINTN Address; + UINT64 AddressEncMask; =20 Address =3D PageFaultContext->PageFaultBuffer + EFI_PAGES_TO_SIZE (PageF= aultContext->PageFaultIndex); ZeroMem ((VOID *) Address, EFI_PAGES_TO_SIZE (1)); =20 + AddressEncMask =3D PageFaultContext->AddressEncMask; + // // Cut the previous uplink if it exists and wasn't overwritten. // - if ((PageFaultContext->PageFaultUplink[PageFaultContext->PageFaultIndex]= !=3D NULL) && ((*PageFaultContext->PageFaultUplink[PageFaultContext->PageF= aultIndex] & PageFaultContext->PhyMask) =3D=3D Address)) { + if ((PageFaultContext->PageFaultUplink[PageFaultContext->PageFaultIndex]= !=3D NULL) && + ((*PageFaultContext->PageFaultUplink[PageFaultContext->PageFaultIndex= ] & ~AddressEncMask & PageFaultContext->PhyMask) =3D=3D Address)) { *PageFaultContext->PageFaultUplink[PageFaultContext->PageFaultIndex] = =3D 0; } =20 // // Link & Record the current uplink. // - *Uplink =3D Address | IA32_PG_P | IA32_PG_RW; + *Uplink =3D Address | AddressEncMask | IA32_PG_P | IA32_PG_RW; PageFaultContext->PageFaultUplink[PageFaultContext->PageFaultIndex] =3D = Uplink; =20 PageFaultContext->PageFaultIndex =3D (PageFaultContext->PageFaultIndex += 1) % EXTRA_PAGE_TABLE_PAGES; @@ -153,6 +160,7 @@ PageFaultHandler ( UINT64 *PageTable; UINT64 PFAddress; UINTN PTIndex; + UINT64 AddressEncMask; =20 // // Get the IDT Descriptor. @@ -163,6 +171,7 @@ PageFaultHandler ( // PageFaultContext =3D (PAGE_FAULT_CONTEXT *) (UINTN) (Idtr.Base - sizeof = (PAGE_FAULT_CONTEXT)); PhyMask =3D PageFaultContext->PhyMask; + AddressEncMask =3D PageFaultContext->AddressEncMask; =20 PFAddress =3D AsmReadCr2 (); DEBUG ((EFI_D_ERROR, "CapsuleX64 - PageFaultHandler: Cr2 - %lx\n", PFAdd= ress)); @@ -179,19 +188,19 @@ PageFaultHandler ( if ((PageTable[PTIndex] & IA32_PG_P) =3D=3D 0) { AcquirePage (PageFaultContext, &PageTable[PTIndex]); } - PageTable =3D (UINT64*)(UINTN)(PageTable[PTIndex] & PhyMask); + PageTable =3D (UINT64*)(UINTN)(PageTable[PTIndex] & ~AddressEncMask & Ph= yMask); PTIndex =3D BitFieldRead64 (PFAddress, 30, 38); // PDPTE if (PageFaultContext->Page1GSupport) { - PageTable[PTIndex] =3D (PFAddress & ~((1ull << 30) - 1)) | IA32_PG_P |= IA32_PG_RW | IA32_PG_PS; + PageTable[PTIndex] =3D ((PFAddress | AddressEncMask) & ~((1ull << 30) = - 1)) | IA32_PG_P | IA32_PG_RW | IA32_PG_PS; } else { if ((PageTable[PTIndex] & IA32_PG_P) =3D=3D 0) { AcquirePage (PageFaultContext, &PageTable[PTIndex]); } - PageTable =3D (UINT64*)(UINTN)(PageTable[PTIndex] & PhyMask); + PageTable =3D (UINT64*)(UINTN)(PageTable[PTIndex] & ~AddressEncMask & = PhyMask); PTIndex =3D BitFieldRead64 (PFAddress, 21, 29); // PD - PageTable[PTIndex] =3D (PFAddress & ~((1ull << 21) - 1)) | IA32_PG_P |= IA32_PG_RW | IA32_PG_PS; + PageTable[PTIndex] =3D ((PFAddress | AddressEncMask) & ~((1ull << 21) = - 1)) | IA32_PG_P | IA32_PG_RW | IA32_PG_PS; } =20 return NULL; @@ -244,6 +253,7 @@ _ModuleEntryPoint ( // Hook page fault handler to handle >4G request. // PageFaultIdtTable.PageFaultContext.Page1GSupport =3D EntrypointContext->= Page1GSupport; + PageFaultIdtTable.PageFaultContext.AddressEncMask =3D EntrypointContext-= >AddressEncMask; IdtEntry =3D (IA32_IDT_GATE_DESCRIPTOR *) (X64Idtr.Base + (14 * sizeof (= IA32_IDT_GATE_DESCRIPTOR))); HookPageFaultHandler (IdtEntry, &(PageFaultIdtTable.PageFaultContext)); =20 @@ -298,4 +308,4 @@ _ModuleEntryPoint ( // ASSERT (FALSE); return EFI_SUCCESS; -} \ No newline at end of file +} --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat Nov 2 14:41:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zoho.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1488131012056950.049233243029; Sun, 26 Feb 2017 09:43:32 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id CB8A782123; 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charset="utf-8" This PCD holds the address mask for page table entries when memory encryption is enabled on AMD processors supporting the Secure Encrypted Virtualization (SEV) feature. The mask is applied when page tables are created (S3Resume.c). CC: Jeff Fan Cc: Feng Tian Cc: Star Zeng Cc: Laszlo Ersek Cc: Brijesh Singh Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leo Duran Reviewed-by: Star Zeng Reviewed-by: Jeff Fan --- UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c | 17 +++++++++++++= ---- UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf | 2 ++ 2 files changed, 15 insertions(+), 4 deletions(-) diff --git a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c b/UefiCpuPkg= /Universal/Acpi/S3Resume2Pei/S3Resume.c index d306fba..a9d1042 100644 --- a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c +++ b/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c @@ -5,6 +5,7 @@ control is passed to OS waking up handler. =20 Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2017, AMD Incorporated. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions @@ -58,6 +59,8 @@ #define STACK_ALIGN_DOWN(Ptr) \ ((UINTN)(Ptr) & ~(UINTN)(CPU_STACK_ALIGNMENT - 1)) =20 +#define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull + #pragma pack(1) typedef union { struct { @@ -614,6 +617,12 @@ RestoreS3PageTables ( VOID *Hob; BOOLEAN Page1GSupport; PAGE_TABLE_1G_ENTRY *PageDirectory1GEntry; + UINT64 AddressEncMask; + + // + // Make sure AddressEncMask is contained to smallest supported address= field + // + AddressEncMask =3D PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & PA= GING_1G_ADDRESS_MASK_64; =20 // // NOTE: We have to ASSUME the page table generation format, because w= e do not know whole page table information. @@ -696,7 +705,7 @@ RestoreS3PageTables ( // // Make a PML4 Entry // - PageMapLevel4Entry->Uint64 =3D (UINT64)(UINTN)PageDirectoryPointerEn= try; + PageMapLevel4Entry->Uint64 =3D (UINT64)(UINTN)PageDirectoryPointerEn= try | AddressEncMask; PageMapLevel4Entry->Bits.ReadWrite =3D 1; PageMapLevel4Entry->Bits.Present =3D 1; =20 @@ -707,7 +716,7 @@ RestoreS3PageTables ( // // Fill in the Page Directory entries // - PageDirectory1GEntry->Uint64 =3D (UINT64)PageAddress; + PageDirectory1GEntry->Uint64 =3D (UINT64)PageAddress | AddressEn= cMask; PageDirectory1GEntry->Bits.ReadWrite =3D 1; PageDirectory1GEntry->Bits.Present =3D 1; PageDirectory1GEntry->Bits.MustBe1 =3D 1; @@ -724,7 +733,7 @@ RestoreS3PageTables ( // // Fill in a Page Directory Pointer Entries // - PageDirectoryPointerEntry->Uint64 =3D (UINT64)(UINTN)PageDirecto= ryEntry; + PageDirectoryPointerEntry->Uint64 =3D (UINT64)(UINTN)PageDirecto= ryEntry | AddressEncMask; PageDirectoryPointerEntry->Bits.ReadWrite =3D 1; PageDirectoryPointerEntry->Bits.Present =3D 1; =20 @@ -732,7 +741,7 @@ RestoreS3PageTables ( // // Fill in the Page Directory entries // - PageDirectoryEntry->Uint64 =3D (UINT64)PageAddress; + PageDirectoryEntry->Uint64 =3D (UINT64)PageAddress | AddressEn= cMask; PageDirectoryEntry->Bits.ReadWrite =3D 1; PageDirectoryEntry->Bits.Present =3D 1; PageDirectoryEntry->Bits.MustBe1 =3D 1; diff --git a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf b/Uefi= CpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf index 73aeca3..d514523 100644 --- a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf +++ b/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf @@ -6,6 +6,7 @@ # control is passed to OS waking up handler. # # Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.
+# Copyright (c) 2017, AMD Incorporated. All rights reserved.
# # This program and the accompanying materials are # licensed and made available under the terms and conditions of the BSD Li= cense @@ -91,6 +92,7 @@ =20 [Pcd] gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable ## SOMETIMES_CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask ##= CONSUMES =20 [Depex] TRUE --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat Nov 2 14:41:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zoho.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1488131014558363.04872553210566; Sun, 26 Feb 2017 09:43:34 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 0A63D8214C; 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20:3NTjlUn3k+Zk9FU7Im0PEi69paR6fg0ElardmolF/4eDlnVk89ULwzjdD5Xh+1Kz6Wpp4LsA7LUakVhRPi7GNLtjVVG5pFNcdzk7OJXbUw0cwDdYDy0UJoOoLWzhoLLJrzXHoDd2mE9LI9dkMJayUJuP+vSi9HHOxbHEMvVPqHqRh8fhsXE7YXfjL9RbXTxx9xRJcSFAnaUgNa1pRyAJzPjX+g1RXcZ5jIgppAh/UFDaIbXEQpvJ0EL/caSMSSdF X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Feb 2017 17:43:21.0688 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR12MB1238 Subject: [edk2] [PATCH v4 5/6] MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe: Add support for PCD PcdPteMemoryEncryptionAddressOrMask X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Feng Tian , Brijesh Singh , Leo Duran , Laszlo Ersek , Jeff Fan , Star Zeng Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This PCD holds the address mask for page table entries when memory encryption is enabled on AMD processors supporting the Secure Encrypted Virtualization (SEV) feature. This module updates the under-4GB page tables configured by the S3-Resume code in UefiCpuPkg/Universal/Acpi/S3Resume2Pei. The mask is saved at module start (ScriptExecute.c), and applied when tables are expanded on-demand by page-faults above 4GB's (SetIdtEntry.c). CC: Jeff Fan Cc: Feng Tian Cc: Star Zeng Cc: Laszlo Ersek Cc: Brijesh Singh Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leo Duran --- .../Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.inf | 2 ++ .../Universal/Acpi/BootScriptExecutorDxe/ScriptExecute.c | 7 +++++++ .../Universal/Acpi/BootScriptExecutorDxe/ScriptExecute.h | 5 +++++ .../Acpi/BootScriptExecutorDxe/X64/SetIdtEntry.c | 15 +++++++++--= ---- 4 files changed, 23 insertions(+), 6 deletions(-) diff --git a/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptEx= ecutorDxe.inf b/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScrip= tExecutorDxe.inf index 7cd38cf..29af7f5 100644 --- a/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorD= xe.inf +++ b/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorD= xe.inf @@ -5,6 +5,7 @@ # depends on any PEI or DXE service. # # Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+# Copyright (c) 2017, AMD Incorporated. All rights reserved.
# # This program and the accompanying materials are # licensed and made available under the terms and conditions of the BSD Li= cense @@ -85,6 +86,7 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable ## SOMETIM= ES_CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdMemoryProfilePropertyMask ## CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiS3Enable ## CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask ##= CONSUMES =20 [Depex] gEfiLockBoxProtocolGuid diff --git a/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/ScriptExecut= e.c b/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/ScriptExecute.c index f67fbca..22d4349 100644 --- a/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/ScriptExecute.c +++ b/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/ScriptExecute.c @@ -5,6 +5,7 @@ in the entry point. The functionality is to interpret and restore the S3= boot script =20 Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2017, AMD Incorporated. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License @@ -23,6 +24,7 @@ EFI_GUID mBootScriptExecutorImageGuid =3D { }; =20 BOOLEAN mPage1GSupport =3D FALSE; +UINT64 mAddressEncMask =3D 0; =20 /** Entry function of Boot script exector. This function will be executed in @@ -408,6 +410,11 @@ BootScriptExecutorEntryPoint ( } =20 // + // Make sure AddressEncMask is contained to smallest supported address f= ield. + // + mAddressEncMask =3D PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & PAG= ING_1G_ADDRESS_MASK_64; + + // // Test if the gEfiCallerIdGuid of this image is already installed. if n= ot, the entry // point is loaded by DXE code which is the first time loaded. or else, = it is already // be reloaded be itself.This is a work-around diff --git a/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/ScriptExecut= e.h b/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/ScriptExecute.h index 772347a..7532756 100644 --- a/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/ScriptExecute.h +++ b/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/ScriptExecute.h @@ -5,6 +5,7 @@ in the entry point. The functionality is to interpret and restore the S3= boot script=20 =20 Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
+Copyright (c) 2017, AMD Incorporated. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License @@ -44,6 +45,9 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER= EXPRESS OR IMPLIED. =20 #include #include + +#define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull + /** a ASM function to transfer control to OS. =20 @@ -87,5 +91,6 @@ SetIdtEntry ( extern UINT32 AsmFixAddress16; extern UINT32 AsmJmpAddr32; extern BOOLEAN mPage1GSupport; +extern UINT64 mAddressEncMask; =20 #endif //_BOOT_SCRIPT_EXECUTOR_H_ diff --git a/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/X64/SetIdtEn= try.c b/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/X64/SetIdtEntry.c index 6674560..d433cf1 100644 --- a/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/X64/SetIdtEntry.c +++ b/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/X64/SetIdtEntry.c @@ -4,6 +4,8 @@ Set a IDT entry for interrupt vector 3 for debug purpose for x64 platform =20 Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.
+Copyright (c) 2017, AMD Incorporated. All rights reserved.
+ =20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License @@ -200,14 +202,15 @@ AcquirePage ( // // Cut the previous uplink if it exists and wasn't overwritten. // - if ((mPageFaultUplink[mPageFaultIndex] !=3D NULL) && ((*mPageFaultUplink= [mPageFaultIndex] & mPhyMask) =3D=3D Address)) { + if ((mPageFaultUplink[mPageFaultIndex] !=3D NULL) && + ((*mPageFaultUplink[mPageFaultIndex] & ~mAddressEncMask & mPhyMask) = =3D=3D Address)) { *mPageFaultUplink[mPageFaultIndex] =3D 0; } =20 // // Link & Record the current uplink. // - *Uplink =3D Address | IA32_PG_P | IA32_PG_RW; + *Uplink =3D Address | mAddressEncMask | IA32_PG_P | IA32_PG_RW; mPageFaultUplink[mPageFaultIndex] =3D Uplink; =20 mPageFaultIndex =3D (mPageFaultIndex + 1) % EXTRA_PAGE_TABLE_PAGES; @@ -245,19 +248,19 @@ PageFaultHandler ( if ((PageTable[PTIndex] & IA32_PG_P) =3D=3D 0) { AcquirePage (&PageTable[PTIndex]); } - PageTable =3D (UINT64*)(UINTN)(PageTable[PTIndex] & mPhyMask); + PageTable =3D (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & m= PhyMask); PTIndex =3D BitFieldRead64 (PFAddress, 30, 38); // PDPTE if (mPage1GSupport) { - PageTable[PTIndex] =3D (PFAddress & ~((1ull << 30) - 1)) | IA32_PG_P |= IA32_PG_RW | IA32_PG_PS; + PageTable[PTIndex] =3D ((PFAddress | mAddressEncMask) & ~((1ull << 30)= - 1)) | IA32_PG_P | IA32_PG_RW | IA32_PG_PS; } else { if ((PageTable[PTIndex] & IA32_PG_P) =3D=3D 0) { AcquirePage (&PageTable[PTIndex]); } - PageTable =3D (UINT64*)(UINTN)(PageTable[PTIndex] & mPhyMask); + PageTable =3D (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask &= mPhyMask); PTIndex =3D BitFieldRead64 (PFAddress, 21, 29); // PD - PageTable[PTIndex] =3D (PFAddress & ~((1ull << 21) - 1)) | IA32_PG_P |= IA32_PG_RW | IA32_PG_PS; + PageTable[PTIndex] =3D ((PFAddress | mAddressEncMask) & ~((1ull << 21)= - 1)) | IA32_PG_P | IA32_PG_RW | IA32_PG_PS; } =20 return TRUE; --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat Nov 2 14:41:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zoho.com; 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20:Gl66P70dzDBRd/0K9zfb8HzI/5D8VW/bqCFOSNor9YflIWW3Hv7XCMiBEjL0cOxJCQQ1QaKlmTu9otrCHMkblhajjoeeDUaPMM4U26CIBq6veya75iKQX/5iz1swnJr6uk6Jdo4Qws+0pCRuSE24AvYThzraHhAI4TdIdw1zq27+N8F6/LoM5H9C6hDUvKFc7I2xGhhFg16mZ+vUPbFf2k9b+Dy+8O/DW2OcfzZhpBC2NMcGdleVn9vvTa/tpI/y X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Feb 2017 17:43:21.7414 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR12MB1238 Subject: [edk2] [PATCH v4 6/6] UefiCpuPkg/PiSmmCpuDxeSmm: Add support for PCD PcdPteMemoryEncryptionAddressOrMask X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Feng Tian , Brijesh Singh , Leo Duran , Laszlo Ersek , Jeff Fan , Star Zeng Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This PCD holds the address mask for page table entries when memory encryption is enabled on AMD processors supporting the Secure Encrypted Virtualization (SEV) feature. The mask is applied when page tables entriees are created or modified. CC: Jeff Fan Cc: Feng Tian Cc: Star Zeng Cc: Laszlo Ersek Cc: Brijesh Singh Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leo Duran Reviewed-by: Star Zeng Reviewed-by: Jeff Fan --- UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c | 6 +- UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 83 +++---------------= ---- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 14 ++++ UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 8 ++- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf | 2 + UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 14 ++-- UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c | 16 +++-- UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | 41 ++++++----- UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.c | 32 +++++---- 9 files changed, 91 insertions(+), 125 deletions(-) mode change 100644 =3D> 100755 UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c b/UefiCpuPkg/PiSmmCpu= DxeSmm/Ia32/PageTbl.c index c1f4b7e..119810a 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c @@ -2,6 +2,8 @@ Page table manipulation functions for IA-32 processors =20 Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2017, AMD Incorporated. All rights reserved.
+ This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License which accompanies this distribution. The full text of the license may be = found at @@ -204,7 +206,7 @@ SetPageTableAttributes ( PageTableSplitted =3D (PageTableSplitted || IsSplitted); =20 for (Index3 =3D 0; Index3 < 4; Index3++) { - L2PageTable =3D (UINT64 *)(UINTN)(L3PageTable[Index3] & PAGING_4K_AD= DRESS_MASK_64); + L2PageTable =3D (UINT64 *)(UINTN)(L3PageTable[Index3] & ~mAddressEnc= Mask & PAGING_4K_ADDRESS_MASK_64); if (L2PageTable =3D=3D NULL) { continue; } @@ -217,7 +219,7 @@ SetPageTableAttributes ( // 2M continue; } - L1PageTable =3D (UINT64 *)(UINTN)(L2PageTable[Index2] & PAGING_4K_= ADDRESS_MASK_64); + L1PageTable =3D (UINT64 *)(UINTN)(L2PageTable[Index2] & ~mAddressE= ncMask & PAGING_4K_ADDRESS_MASK_64); if (L1PageTable =3D=3D NULL) { continue; } diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c b/UefiCpuPkg/PiSmmCpuDxe= Smm/MpService.c index c7aa48b..d99ad46 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c @@ -2,6 +2,8 @@ SMM MP service implementation =20 Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2017, AMD Incorporated. All rights reserved.
+ This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License which accompanies this distribution. The full text of the license may be = found at @@ -781,7 +783,8 @@ Gen4GPageTable ( // Set Page Directory Pointers // for (Index =3D 0; Index < 4; Index++) { - Pte[Index] =3D (UINTN)PageTable + EFI_PAGE_SIZE * (Index + 1) + (Is32B= itPageTable ? IA32_PAE_PDPTE_ATTRIBUTE_BITS : PAGE_ATTRIBUTE_BITS); + Pte[Index] =3D (UINT64)((UINTN)PageTable + EFI_PAGE_SIZE * (Index + 1)= ) | mAddressEncMask | + (Is32BitPageTable ? IA32_PAE_PDPTE_ATTRIBUTE_BITS : PAG= E_ATTRIBUTE_BITS); } Pte +=3D EFI_PAGE_SIZE / sizeof (*Pte); =20 @@ -789,7 +792,7 @@ Gen4GPageTable ( // Fill in Page Directory Entries // for (Index =3D 0; Index < EFI_PAGE_SIZE * 4 / sizeof (*Pte); Index++) { - Pte[Index] =3D (Index << 21) | IA32_PG_PS | PAGE_ATTRIBUTE_BITS; + Pte[Index] =3D (Index << 21) | mAddressEncMask | IA32_PG_PS | PAGE_ATT= RIBUTE_BITS; } =20 if (FeaturePcdGet (PcdCpuSmmStackGuard)) { @@ -797,8 +800,8 @@ Gen4GPageTable ( GuardPage =3D mSmmStackArrayBase + EFI_PAGE_SIZE; Pdpte =3D (UINT64*)PageTable; for (PageIndex =3D Low2MBoundary; PageIndex <=3D High2MBoundary; PageI= ndex +=3D SIZE_2MB) { - Pte =3D (UINT64*)(UINTN)(Pdpte[BitFieldRead32 ((UINT32)PageIndex, 30= , 31)] & ~(EFI_PAGE_SIZE - 1)); - Pte[BitFieldRead32 ((UINT32)PageIndex, 21, 29)] =3D (UINT64)Pages | = PAGE_ATTRIBUTE_BITS; + Pte =3D (UINT64*)(UINTN)(Pdpte[BitFieldRead32 ((UINT32)PageIndex, 30= , 31)] & ~mAddressEncMask & ~(EFI_PAGE_SIZE - 1)); + Pte[BitFieldRead32 ((UINT32)PageIndex, 21, 29)] =3D (UINT64)Pages | = mAddressEncMask | PAGE_ATTRIBUTE_BITS; // // Fill in Page Table Entries // @@ -809,13 +812,13 @@ Gen4GPageTable ( // // Mark the guard page as non-present // - Pte[Index] =3D PageAddress; + Pte[Index] =3D PageAddress | mAddressEncMask; GuardPage +=3D mSmmStackSize; if (GuardPage > mSmmStackArrayEnd) { GuardPage =3D 0; } } else { - Pte[Index] =3D PageAddress | PAGE_ATTRIBUTE_BITS; + Pte[Index] =3D PageAddress | mAddressEncMask | PAGE_ATTRIBUTE_BI= TS; } PageAddress+=3D EFI_PAGE_SIZE; } @@ -827,74 +830,6 @@ Gen4GPageTable ( } =20 /** - Set memory cache ability. - - @param PageTable PageTable Address - @param Address Memory Address to change cache ability - @param Cacheability Cache ability to set - -**/ -VOID -SetCacheability ( - IN UINT64 *PageTable, - IN UINTN Address, - IN UINT8 Cacheability - ) -{ - UINTN PTIndex; - VOID *NewPageTableAddress; - UINT64 *NewPageTable; - UINTN Index; - - ASSERT ((Address & EFI_PAGE_MASK) =3D=3D 0); - - if (sizeof (UINTN) =3D=3D sizeof (UINT64)) { - PTIndex =3D (UINTN)RShiftU64 (Address, 39) & 0x1ff; - ASSERT (PageTable[PTIndex] & IA32_PG_P); - PageTable =3D (UINT64*)(UINTN)(PageTable[PTIndex] & gPhyMask); - } - - PTIndex =3D (UINTN)RShiftU64 (Address, 30) & 0x1ff; - ASSERT (PageTable[PTIndex] & IA32_PG_P); - PageTable =3D (UINT64*)(UINTN)(PageTable[PTIndex] & gPhyMask); - - // - // A perfect implementation should check the original cacheability with = the - // one being set, and break a 2M page entry into pieces only when they - // disagreed. - // - PTIndex =3D (UINTN)RShiftU64 (Address, 21) & 0x1ff; - if ((PageTable[PTIndex] & IA32_PG_PS) !=3D 0) { - // - // Allocate a page from SMRAM - // - NewPageTableAddress =3D AllocatePageTableMemory (1); - ASSERT (NewPageTableAddress !=3D NULL); - - NewPageTable =3D (UINT64 *)NewPageTableAddress; - - for (Index =3D 0; Index < 0x200; Index++) { - NewPageTable[Index] =3D PageTable[PTIndex]; - if ((NewPageTable[Index] & IA32_PG_PAT_2M) !=3D 0) { - NewPageTable[Index] &=3D ~((UINT64)IA32_PG_PAT_2M); - NewPageTable[Index] |=3D (UINT64)IA32_PG_PAT_4K; - } - NewPageTable[Index] |=3D (UINT64)(Index << EFI_PAGE_SHIFT); - } - - PageTable[PTIndex] =3D ((UINTN)NewPageTableAddress & gPhyMask) | PAGE_= ATTRIBUTE_BITS; - } - - ASSERT (PageTable[PTIndex] & IA32_PG_P); - PageTable =3D (UINT64*)(UINTN)(PageTable[PTIndex] & gPhyMask); - - PTIndex =3D (UINTN)RShiftU64 (Address, 12) & 0x1ff; - ASSERT (PageTable[PTIndex] & IA32_PG_P); - PageTable[PTIndex] &=3D ~((UINT64)((IA32_PG_PAT_4K | IA32_PG_CD | IA32_P= G_WT))); - PageTable[PTIndex] |=3D (UINT64)Cacheability; -} - -/** Schedule a procedure to run on the specified CPU. =20 @param[in] Procedure The address of the procedure t= o run diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c b/UefiCpuPkg/PiSmmC= puDxeSmm/PiSmmCpuDxeSmm.c old mode 100644 new mode 100755 index fc7714a..d5b8900 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c @@ -2,6 +2,8 @@ Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU. =20 Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2017, AMD Incorporated. All rights reserved.
+ This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License which accompanies this distribution. The full text of the license may be = found at @@ -97,6 +99,11 @@ BOOLEAN mSmmReadyToLock =3D FALSE; BOOLEAN mSmmCodeAccessCheckEnable =3D FALSE; =20 // +// Global copy of the PcdPteMemoryEncryptionAddressOrMask +// +UINT64 mAddressEncMask =3D 0; + +// // Spin lock used to serialize setting of SMM Code Access Check feature // SPIN_LOCK *mConfigSmmCodeAccessCheckLock =3D NULL; @@ -605,6 +612,13 @@ PiCpuSmmEntry ( DEBUG ((EFI_D_INFO, "PcdCpuSmmCodeAccessCheckEnable =3D %d\n", mSmmCodeA= ccessCheckEnable)); =20 // + // Save the PcdPteMemoryEncryptionAddressOrMask value into a global vari= able. + // Make sure AddressEncMask is contained to smallest supported address f= ield. + // + mAddressEncMask =3D PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & PAG= ING_1G_ADDRESS_MASK_64; + DEBUG ((EFI_D_INFO, "mAddressEncMask =3D 0x%lx\n", mAddressEncMask)); + + // // If support CPU hot plug, we need to allocate resources for possibly h= ot-added processors // if (FeaturePcdGet (PcdCpuHotPlugSupport)) { diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h b/UefiCpuPkg/PiSmmC= puDxeSmm/PiSmmCpuDxeSmm.h index 69c54fb..71af2f1 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h @@ -2,6 +2,8 @@ Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU. =20 Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2017, AMD Incorporated. All rights reserved.
+ This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License which accompanies this distribution. The full text of the license may be = found at @@ -184,7 +186,6 @@ extern EFI_SMM_CPU_PROTOCOL mSmmCpu; /// extern UINT8 mSmmSaveStateRegisterLma; =20 - // // SMM CPU Protocol function prototypes. // @@ -415,6 +416,11 @@ extern SPIN_LOCK *mPFLock; extern SPIN_LOCK *mConfigSmmCodeAccessCheckLock; extern SPIN_LOCK *mMemoryMappedLock; =20 +// +// Copy of the PcdPteMemoryEncryptionAddressOrMask +// +extern UINT64 mAddressEncMask; + /** Create 4G PageTable in SMRAM. =20 diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf b/UefiCpuPkg/PiSm= mCpuDxeSmm/PiSmmCpuDxeSmm.inf index d409edf..099792e 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf @@ -5,6 +5,7 @@ # provides CPU specific services in SMM. # # Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
+# Copyright (c) 2017, AMD Incorporated. All rights reserved.
# # This program and the accompanying materials # are licensed and made available under the terms and conditions of the BS= D License @@ -157,6 +158,7 @@ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmSyncMode ## CONS= UMES gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStaticPageTable ## CONS= UMES gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiS3Enable ## CONS= UMES + gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask ##= CONSUMES =20 [Depex] gEfiMpServiceProtocolGuid diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c b/UefiCpuPk= g/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c index 13323d5..a535389 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c @@ -119,7 +119,7 @@ GetPageTableEntry ( return NULL; } =20 - L3PageTable =3D (UINT64 *)(UINTN)(L4PageTable[Index4] & PAGING_4K_ADDR= ESS_MASK_64); + L3PageTable =3D (UINT64 *)(UINTN)(L4PageTable[Index4] & ~mAddressEncMa= sk & PAGING_4K_ADDRESS_MASK_64); } else { L3PageTable =3D (UINT64 *)GetPageTableBase (); } @@ -133,7 +133,7 @@ GetPageTableEntry ( return &L3PageTable[Index3]; } =20 - L2PageTable =3D (UINT64 *)(UINTN)(L3PageTable[Index3] & PAGING_4K_ADDRES= S_MASK_64); + L2PageTable =3D (UINT64 *)(UINTN)(L3PageTable[Index3] & ~mAddressEncMask= & PAGING_4K_ADDRESS_MASK_64); if (L2PageTable[Index2] =3D=3D 0) { *PageAttribute =3D PageNone; return NULL; @@ -145,7 +145,7 @@ GetPageTableEntry ( } =20 // 4k - L1PageTable =3D (UINT64 *)(UINTN)(L2PageTable[Index2] & PAGING_4K_ADDRES= S_MASK_64); + L1PageTable =3D (UINT64 *)(UINTN)(L2PageTable[Index2] & ~mAddressEncMask= & PAGING_4K_ADDRESS_MASK_64); if ((L1PageTable[Index1] =3D=3D 0) && (Address !=3D 0)) { *PageAttribute =3D PageNone; return NULL; @@ -304,9 +304,9 @@ SplitPage ( } BaseAddress =3D *PageEntry & PAGING_2M_ADDRESS_MASK_64; for (Index =3D 0; Index < SIZE_4KB / sizeof(UINT64); Index++) { - NewPageEntry[Index] =3D BaseAddress + SIZE_4KB * Index + ((*PageEn= try) & PAGE_PROGATE_BITS); + NewPageEntry[Index] =3D (BaseAddress + SIZE_4KB * Index) | mAddres= sEncMask | ((*PageEntry) & PAGE_PROGATE_BITS); } - (*PageEntry) =3D (UINT64)(UINTN)NewPageEntry + PAGE_ATTRIBUTE_BITS; + (*PageEntry) =3D (UINT64)(UINTN)NewPageEntry | mAddressEncMask | PAG= E_ATTRIBUTE_BITS; return RETURN_SUCCESS; } else { return RETURN_UNSUPPORTED; @@ -325,9 +325,9 @@ SplitPage ( } BaseAddress =3D *PageEntry & PAGING_1G_ADDRESS_MASK_64; for (Index =3D 0; Index < SIZE_4KB / sizeof(UINT64); Index++) { - NewPageEntry[Index] =3D BaseAddress + SIZE_2MB * Index + IA32_PG_P= S + ((*PageEntry) & PAGE_PROGATE_BITS); + NewPageEntry[Index] =3D (BaseAddress + SIZE_2MB * Index) | mAddres= sEncMask | IA32_PG_PS | ((*PageEntry) & PAGE_PROGATE_BITS); } - (*PageEntry) =3D (UINT64)(UINTN)NewPageEntry + PAGE_ATTRIBUTE_BITS; + (*PageEntry) =3D (UINT64)(UINTN)NewPageEntry | mAddressEncMask | PAG= E_ATTRIBUTE_BITS; return RETURN_SUCCESS; } else { return RETURN_UNSUPPORTED; diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c b/UefiCpuPkg/PiSmmCpuDx= eSmm/SmmProfile.c index f53819e..1b84e2c 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c @@ -2,6 +2,8 @@ Enable SMM profile. =20 Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2017, AMD Incorporated. All rights reserved.
+ This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License which accompanies this distribution. The full text of the license may be = found at @@ -513,7 +515,7 @@ InitPaging ( // continue; } - Pde =3D (UINT64 *)(UINTN)(Pml4[Level1] & PHYSICAL_ADDRESS_MASK); + Pde =3D (UINT64 *)(UINTN)(Pml4[Level1] & ~mAddressEncMask & PHYSICAL= _ADDRESS_MASK); } else { Pde =3D (UINT64*)(UINTN)mSmmProfileCr3; } @@ -530,7 +532,7 @@ InitPaging ( // continue; } - Pte =3D (UINT64 *)(UINTN)(*Pde & PHYSICAL_ADDRESS_MASK); + Pte =3D (UINT64 *)(UINTN)(*Pde & ~mAddressEncMask & PHYSICAL_ADDRESS= _MASK); if (Pte =3D=3D 0) { continue; } @@ -557,9 +559,9 @@ InitPaging ( =20 // Split it for (Level4 =3D 0; Level4 < SIZE_4KB / sizeof(*Pt); Level4++) { - Pt[Level4] =3D Address + ((Level4 << 12) | PAGE_ATTRIBUTE_BITS= ); + Pt[Level4] =3D Address + ((Level4 << 12) | mAddressEncMask | P= AGE_ATTRIBUTE_BITS); } // end for PT - *Pte =3D (UINTN)Pt | PAGE_ATTRIBUTE_BITS; + *Pte =3D (UINT64)(UINTN)Pt | mAddressEncMask | PAGE_ATTRIBUTE_BI= TS; } // end if IsAddressSplit } // end for PTE } // end for PDE @@ -577,7 +579,7 @@ InitPaging ( // continue; } - Pde =3D (UINT64 *)(UINTN)(Pml4[Level1] & PHYSICAL_ADDRESS_MASK); + Pde =3D (UINT64 *)(UINTN)(Pml4[Level1] & ~mAddressEncMask & PHYSICAL= _ADDRESS_MASK); } else { Pde =3D (UINT64*)(UINTN)mSmmProfileCr3; } @@ -597,7 +599,7 @@ InitPaging ( } continue; } - Pte =3D (UINT64 *)(UINTN)(*Pde & PHYSICAL_ADDRESS_MASK); + Pte =3D (UINT64 *)(UINTN)(*Pde & ~mAddressEncMask & PHYSICAL_ADDRESS= _MASK); if (Pte =3D=3D 0) { continue; } @@ -624,7 +626,7 @@ InitPaging ( } } else { // 4KB page - Pt =3D (UINT64 *)(UINTN)(*Pte & PHYSICAL_ADDRESS_MASK); + Pt =3D (UINT64 *)(UINTN)(*Pte & ~mAddressEncMask & PHYSICAL_ADDR= ESS_MASK); if (Pt =3D=3D 0) { continue; } diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c b/UefiCpuPkg/PiSmmCpuD= xeSmm/X64/PageTbl.c index 17b2f4c..19b19d8 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c @@ -2,6 +2,8 @@ Page Fault (#PF) handler for X64 processors =20 Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2017, AMD Incorporated. All rights reserved.
+ This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License which accompanies this distribution. The full text of the license may be = found at @@ -16,6 +18,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER= EXPRESS OR IMPLIED. =20 #define PAGE_TABLE_PAGES 8 #define ACC_MAX_BIT BIT3 + LIST_ENTRY mPagePool =3D INITIALIZE_LIST_HEAD_VAR= IABLE (mPagePool); BOOLEAN m1GPageTableSupport =3D FALSE; UINT8 mPhysicalAddressBits; @@ -168,13 +171,13 @@ SetStaticPageTable ( // // Each PML4 entry points to a page of Page Directory Pointer entries. // - PageDirectoryPointerEntry =3D (UINT64 *) ((*PageMapLevel4Entry) & gPhy= Mask); + PageDirectoryPointerEntry =3D (UINT64 *) ((*PageMapLevel4Entry) & ~mAd= dressEncMask & gPhyMask); if (PageDirectoryPointerEntry =3D=3D NULL) { PageDirectoryPointerEntry =3D AllocatePageTableMemory (1); ASSERT(PageDirectoryPointerEntry !=3D NULL); ZeroMem (PageDirectoryPointerEntry, EFI_PAGES_TO_SIZE(1)); =20 - *PageMapLevel4Entry =3D ((UINTN)PageDirectoryPointerEntry & gPhyMask= ) | PAGE_ATTRIBUTE_BITS; + *PageMapLevel4Entry =3D (UINT64)(UINTN)PageDirectoryPointerEntry | m= AddressEncMask | PAGE_ATTRIBUTE_BITS; } =20 if (m1GPageTableSupport) { @@ -189,7 +192,7 @@ SetStaticPageTable ( // // Fill in the Page Directory entries // - *PageDirectory1GEntry =3D (PageAddress & gPhyMask) | IA32_PG_PS | = PAGE_ATTRIBUTE_BITS; + *PageDirectory1GEntry =3D PageAddress | mAddressEncMask | IA32_PG_= PS | PAGE_ATTRIBUTE_BITS; } } else { PageAddress =3D BASE_4GB; @@ -204,7 +207,7 @@ SetStaticPageTable ( // Each Directory Pointer entries points to a page of Page Directo= ry entires. // So allocate space for them and fill them in in the IndexOfPageD= irectoryEntries loop. // - PageDirectoryEntry =3D (UINT64 *) ((*PageDirectoryPointerEntry) & = gPhyMask); + PageDirectoryEntry =3D (UINT64 *) ((*PageDirectoryPointerEntry) & = ~mAddressEncMask & gPhyMask); if (PageDirectoryEntry =3D=3D NULL) { PageDirectoryEntry =3D AllocatePageTableMemory (1); ASSERT(PageDirectoryEntry !=3D NULL); @@ -213,14 +216,14 @@ SetStaticPageTable ( // // Fill in a Page Directory Pointer Entries // - *PageDirectoryPointerEntry =3D (UINT64)(UINTN)PageDirectoryEntry= | PAGE_ATTRIBUTE_BITS; + *PageDirectoryPointerEntry =3D (UINT64)(UINTN)PageDirectoryEntry= | mAddressEncMask | PAGE_ATTRIBUTE_BITS; } =20 for (IndexOfPageDirectoryEntries =3D 0; IndexOfPageDirectoryEntrie= s < 512; IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PageAddress += =3D SIZE_2MB) { // // Fill in the Page Directory entries // - *PageDirectoryEntry =3D (UINT64)PageAddress | IA32_PG_PS | PAGE_= ATTRIBUTE_BITS; + *PageDirectoryEntry =3D PageAddress | mAddressEncMask | IA32_PG_= PS | PAGE_ATTRIBUTE_BITS; } } } @@ -276,7 +279,7 @@ SmmInitPageTable ( // PTEntry =3D (UINT64*)AllocatePageTableMemory (1); ASSERT (PTEntry !=3D NULL); - *PTEntry =3D Pages | PAGE_ATTRIBUTE_BITS; + *PTEntry =3D Pages | mAddressEncMask | PAGE_ATTRIBUTE_BITS; ZeroMem (PTEntry + 1, EFI_PAGE_SIZE - sizeof (*PTEntry)); =20 // @@ -457,7 +460,7 @@ ReclaimPages ( // continue; } - Pdpt =3D (UINT64*)(UINTN)(Pml4[Pml4Index] & gPhyMask); + Pdpt =3D (UINT64*)(UINTN)(Pml4[Pml4Index] & ~mAddressEncMask & gPhyMas= k); PML4EIgnore =3D FALSE; for (PdptIndex =3D 0; PdptIndex < EFI_PAGE_SIZE / sizeof (*Pdpt); Pdpt= Index++) { if ((Pdpt[PdptIndex] & IA32_PG_P) =3D=3D 0 || (Pdpt[PdptIndex] & IA3= 2_PG_PMNT) !=3D 0) { @@ -478,7 +481,7 @@ ReclaimPages ( // we will not check PML4 entry more // PML4EIgnore =3D TRUE; - Pdt =3D (UINT64*)(UINTN)(Pdpt[PdptIndex] & gPhyMask); + Pdt =3D (UINT64*)(UINTN)(Pdpt[PdptIndex] & ~mAddressEncMask & gPh= yMask); PDPTEIgnore =3D FALSE; for (PdtIndex =3D 0; PdtIndex < EFI_PAGE_SIZE / sizeof(*Pdt); PdtI= ndex++) { if ((Pdt[PdtIndex] & IA32_PG_P) =3D=3D 0 || (Pdt[PdtIndex] & IA3= 2_PG_PMNT) !=3D 0) { @@ -560,7 +563,7 @@ ReclaimPages ( // // Secondly, insert the page pointed by this entry into page pool and cl= ear this entry // - InsertTailList (&mPagePool, (LIST_ENTRY*)(UINTN)(*ReleasePageAddress & g= PhyMask)); + InsertTailList (&mPagePool, (LIST_ENTRY*)(UINTN)(*ReleasePageAddress & ~= mAddressEncMask & gPhyMask)); *ReleasePageAddress =3D 0; =20 // @@ -572,14 +575,14 @@ ReclaimPages ( // // If 4 KByte Page Table is released, check the PDPT entry // - Pdpt =3D (UINT64*)(UINTN)(Pml4[MinPml4] & gPhyMask); + Pdpt =3D (UINT64*)(UINTN)(Pml4[MinPml4] & ~mAddressEncMask & gPhyMas= k); SubEntriesNum =3D GetSubEntriesNum(Pdpt + MinPdpt); if (SubEntriesNum =3D=3D 0) { // // Release the empty Page Directory table if there was no more 4 K= Byte Page Table entry // clear the Page directory entry // - InsertTailList (&mPagePool, (LIST_ENTRY*)(UINTN)(Pdpt[MinPdpt] & g= PhyMask)); + InsertTailList (&mPagePool, (LIST_ENTRY*)(UINTN)(Pdpt[MinPdpt] & ~= mAddressEncMask & gPhyMask)); Pdpt[MinPdpt] =3D 0; // // Go on checking the PML4 table @@ -603,7 +606,7 @@ ReclaimPages ( // Release the empty PML4 table if there was no more 1G KByte Page= Table entry // clear the Page directory entry // - InsertTailList (&mPagePool, (LIST_ENTRY*)(UINTN)(Pml4[MinPml4] & g= PhyMask)); + InsertTailList (&mPagePool, (LIST_ENTRY*)(UINTN)(Pml4[MinPml4] & ~= mAddressEncMask & gPhyMask)); Pml4[MinPml4] =3D 0; MinPdpt =3D (UINTN)-1; continue; @@ -747,7 +750,7 @@ SmiDefaultPFHandler ( // // If the entry is not present, allocate one page from page pool f= or it // - PageTable[PTIndex] =3D AllocPage () | PAGE_ATTRIBUTE_BITS; + PageTable[PTIndex] =3D AllocPage () | mAddressEncMask | PAGE_ATTRI= BUTE_BITS; } else { // // Save the upper entry address @@ -760,7 +763,7 @@ SmiDefaultPFHandler ( // PageTable[PTIndex] |=3D (UINT64)IA32_PG_A; SetAccNum (PageTable + PTIndex, 7); - PageTable =3D (UINT64*)(UINTN)(PageTable[PTIndex] & gPhyMask); + PageTable =3D (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask= & gPhyMask); } =20 PTIndex =3D BitFieldRead64 (PFAddress, StartBit, StartBit + 8); @@ -776,7 +779,7 @@ SmiDefaultPFHandler ( // // Fill the new entry // - PageTable[PTIndex] =3D (PFAddress & gPhyMask & ~((1ull << EndBit) - 1)= ) | + PageTable[PTIndex] =3D ((PFAddress | mAddressEncMask) & gPhyMask & ~((= 1ull << EndBit) - 1)) | PageAttribute | IA32_PG_A | PAGE_ATTRIBUTE_BITS; if (UpperEntry !=3D NULL) { SetSubEntriesNum (UpperEntry, GetSubEntriesNum (UpperEntry) + 1); @@ -927,7 +930,7 @@ SetPageTableAttributes ( PageTableSplitted =3D (PageTableSplitted || IsSplitted); =20 for (Index4 =3D 0; Index4 < SIZE_4KB/sizeof(UINT64); Index4++) { - L3PageTable =3D (UINT64 *)(UINTN)(L4PageTable[Index4] & PAGING_4K_AD= DRESS_MASK_64); + L3PageTable =3D (UINT64 *)(UINTN)(L4PageTable[Index4] & ~mAddressEnc= Mask & PAGING_4K_ADDRESS_MASK_64); if (L3PageTable =3D=3D NULL) { continue; } @@ -940,7 +943,7 @@ SetPageTableAttributes ( // 1G continue; } - L2PageTable =3D (UINT64 *)(UINTN)(L3PageTable[Index3] & PAGING_4K_= ADDRESS_MASK_64); + L2PageTable =3D (UINT64 *)(UINTN)(L3PageTable[Index3] & ~mAddressE= ncMask & PAGING_4K_ADDRESS_MASK_64); if (L2PageTable =3D=3D NULL) { continue; } @@ -953,7 +956,7 @@ SetPageTableAttributes ( // 2M continue; } - L1PageTable =3D (UINT64 *)(UINTN)(L2PageTable[Index2] & PAGING_4= K_ADDRESS_MASK_64); + L1PageTable =3D (UINT64 *)(UINTN)(L2PageTable[Index2] & ~mAddres= sEncMask & PAGING_4K_ADDRESS_MASK_64); if (L1PageTable =3D=3D NULL) { continue; } diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.c b/UefiCpuPkg/Pi= SmmCpuDxeSmm/X64/SmmProfileArch.c index cc393dc..37da5fb 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.c @@ -2,6 +2,8 @@ X64 processor specific functions to enable SMM profile. =20 Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2017, AMD Incorporated. All rights reserved.
+ This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License which accompanies this distribution. The full text of the license may be = found at @@ -52,7 +54,7 @@ InitSmmS3Cr3 ( // PTEntry =3D (UINT64*)AllocatePageTableMemory (1); ASSERT (PTEntry !=3D NULL); - *PTEntry =3D Pages | PAGE_ATTRIBUTE_BITS; + *PTEntry =3D Pages | mAddressEncMask | PAGE_ATTRIBUTE_BITS; ZeroMem (PTEntry + 1, EFI_PAGE_SIZE - sizeof (*PTEntry)); =20 // @@ -111,14 +113,14 @@ AcquirePage ( // // Cut the previous uplink if it exists and wasn't overwritten // - if ((mPFPageUplink[mPFPageIndex] !=3D NULL) && ((*mPFPageUplink[mPFPageI= ndex] & PHYSICAL_ADDRESS_MASK) =3D=3D Address)) { + if ((mPFPageUplink[mPFPageIndex] !=3D NULL) && ((*mPFPageUplink[mPFPageI= ndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK) =3D=3D Address)) { *mPFPageUplink[mPFPageIndex] =3D 0; } =20 // // Link & Record the current uplink // - *Uplink =3D Address | PAGE_ATTRIBUTE_BITS; + *Uplink =3D Address | mAddressEncMask | PAGE_ATTRIBUTE_BITS; mPFPageUplink[mPFPageIndex] =3D Uplink; =20 mPFPageIndex =3D (mPFPageIndex + 1) % MAX_PF_PAGE_COUNT; @@ -168,33 +170,33 @@ RestorePageTableAbove4G ( PTIndex =3D BitFieldRead64 (PFAddress, 39, 47); if ((PageTable[PTIndex] & IA32_PG_P) !=3D 0) { // PML4E - PageTable =3D (UINT64*)(UINTN)(PageTable[PTIndex] & PHYSICAL_ADDRESS_M= ASK); + PageTable =3D (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask &= PHYSICAL_ADDRESS_MASK); PTIndex =3D BitFieldRead64 (PFAddress, 30, 38); if ((PageTable[PTIndex] & IA32_PG_P) !=3D 0) { // PDPTE - PageTable =3D (UINT64*)(UINTN)(PageTable[PTIndex] & PHYSICAL_ADDRESS= _MASK); + PageTable =3D (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask= & PHYSICAL_ADDRESS_MASK); PTIndex =3D BitFieldRead64 (PFAddress, 21, 29); // PD if ((PageTable[PTIndex] & IA32_PG_PS) !=3D 0) { // // 2MB page // - Address =3D (UINT64)(PageTable[PTIndex] & PHYSICAL_ADDRESS_MASK); - if ((Address & PHYSICAL_ADDRESS_MASK & ~((1ull << 21) - 1)) =3D=3D= ((PFAddress & PHYSICAL_ADDRESS_MASK & ~((1ull << 21) - 1)))) { + Address =3D (UINT64)(PageTable[PTIndex] & ~mAddressEncMask & PHYSI= CAL_ADDRESS_MASK); + if ((Address & ~((1ull << 21) - 1)) =3D=3D ((PFAddress & PHYSICAL_= ADDRESS_MASK & ~((1ull << 21) - 1)))) { Existed =3D TRUE; } } else { // // 4KB page // - PageTable =3D (UINT64*)(UINTN)(PageTable[PTIndex] & PHYSICAL_ADDRE= SS_MASK); + PageTable =3D (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMa= sk& PHYSICAL_ADDRESS_MASK); if (PageTable !=3D 0) { // // When there is a valid entry to map to 4KB page, need not crea= te a new entry to map 2MB. // PTIndex =3D BitFieldRead64 (PFAddress, 12, 20); - Address =3D (UINT64)(PageTable[PTIndex] & PHYSICAL_ADDRESS_MASK); - if ((Address & PHYSICAL_ADDRESS_MASK & ~((1ull << 12) - 1)) =3D= =3D (PFAddress & PHYSICAL_ADDRESS_MASK & ~((1ull << 12) - 1))) { + Address =3D (UINT64)(PageTable[PTIndex] & ~mAddressEncMask & PHY= SICAL_ADDRESS_MASK); + if ((Address & ~((1ull << 12) - 1)) =3D=3D (PFAddress & PHYSICAL= _ADDRESS_MASK & ~((1ull << 12) - 1))) { Existed =3D TRUE; } } @@ -227,13 +229,13 @@ RestorePageTableAbove4G ( PFAddress =3D AsmReadCr2 (); // PML4E PTIndex =3D BitFieldRead64 (PFAddress, 39, 47); - PageTable =3D (UINT64*)(UINTN)(PageTable[PTIndex] & PHYSICAL_ADDRESS_M= ASK); + PageTable =3D (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask &= PHYSICAL_ADDRESS_MASK); // PDPTE PTIndex =3D BitFieldRead64 (PFAddress, 30, 38); - PageTable =3D (UINT64*)(UINTN)(PageTable[PTIndex] & PHYSICAL_ADDRESS_M= ASK); + PageTable =3D (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask &= PHYSICAL_ADDRESS_MASK); // PD PTIndex =3D BitFieldRead64 (PFAddress, 21, 29); - Address =3D PageTable[PTIndex] & PHYSICAL_ADDRESS_MASK; + Address =3D PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_M= ASK; // // Check if 2MB-page entry need be changed to 4KB-page entry. // @@ -241,9 +243,9 @@ RestorePageTableAbove4G ( AcquirePage (&PageTable[PTIndex]); =20 // PTE - PageTable =3D (UINT64*)(UINTN)(PageTable[PTIndex] & PHYSICAL_ADDRESS= _MASK); + PageTable =3D (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask= & PHYSICAL_ADDRESS_MASK); for (Index =3D 0; Index < 512; Index++) { - PageTable[Index] =3D Address | PAGE_ATTRIBUTE_BITS; + PageTable[Index] =3D Address | mAddressEncMask | PAGE_ATTRIBUTE_BI= TS; if (!IsAddressValid (Address, &Nx)) { PageTable[Index] =3D PageTable[Index] & (INTN)(INT32)(~PAGE_ATTR= IBUTE_BITS); } --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel