From nobody Sat Nov 2 16:37:42 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zoho.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 14879995850741002.736894533585; Fri, 24 Feb 2017 21:13:05 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 255B7821A1; Fri, 24 Feb 2017 21:12:59 -0800 (PST) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 827CB8219C for ; Fri, 24 Feb 2017 21:12:56 -0800 (PST) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Feb 2017 21:12:56 -0800 Received: from shwdeopenpsi014.ccr.corp.intel.com ([10.239.9.13]) by orsmga002.jf.intel.com with ESMTP; 24 Feb 2017 21:12:55 -0800 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.35,202,1484035200"; d="scan'208";a="52624029" From: Hao Wu To: edk2-devel@lists.01.org Date: Sat, 25 Feb 2017 13:12:28 +0800 Message-Id: <1487999555-9764-6-git-send-email-hao.a.wu@intel.com> X-Mailer: git-send-email 1.9.5.msysgit.0 In-Reply-To: <1487999555-9764-1-git-send-email-hao.a.wu@intel.com> References: <1487999555-9764-1-git-send-email-hao.a.wu@intel.com> Subject: [edk2] [PATCH v3 05/12] IntelFsp2WrapperPkg: Refine casting expression result to bigger size X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Hao Wu , Jiewen Yao MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" There are cases that the operands of an expression are all with rank less than UINT64/INT64 and the result of the expression is explicitly cast to UINT64/INT64 to fit the target size. An example will be: UINT32 a,b; // a and b can be any unsigned int type with rank less than UINT64, like // UINT8, UINT16, etc. UINT64 c; c =3D (UINT64) (a + b); Some static code checkers may warn that the expression result might overflow within the rank of "int" (integer promotions) and the result is then cast to a bigger size. The commit refines codes by the following rules: 1). When the expression is possible to overflow the range of unsigned int/ int: c =3D (UINT64)a + b; 2). When the expression will not overflow within the rank of "int", remove the explicit type casts: c =3D a + b; 3). When the expression will be cast to pointer of possible greater size: UINT32 a,b; VOID *c; c =3D (VOID *)(UINTN)(a + b); --> c =3D (VOID *)((UINTN)a + b); 4). When one side of a comparison expression contains only operands with rank less than UINT32: UINT8 a; UINT16 b; UINTN c; if ((UINTN)(a + b) > c) {...} --> if (((UINT32)a + b) > c) {...} For rule 4), if we remove the 'UINTN' type cast like: if (a + b > c) {...} The VS compiler will complain with warning C4018 (signed/unsigned mismatch, level 3 warning) due to promoting 'a + b' to type 'int'. Cc: Jiewen Yao Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu Reviewed-by: jiewen.yao@intel.com --- IntelFsp2WrapperPkg/FspWrapperNotifyDxe/LoadBelow4G.c | 4 += +-- IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/FspWrapperApiLib.c | 10 += ++++----- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/IntelFsp2WrapperPkg/FspWrapperNotifyDxe/LoadBelow4G.c b/IntelF= sp2WrapperPkg/FspWrapperNotifyDxe/LoadBelow4G.c index ff2f563..dc5ef89 100644 --- a/IntelFsp2WrapperPkg/FspWrapperNotifyDxe/LoadBelow4G.c +++ b/IntelFsp2WrapperPkg/FspWrapperNotifyDxe/LoadBelow4G.c @@ -1,6 +1,6 @@ /** @file =20 -Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions @@ -115,7 +115,7 @@ RelocateImageUnder4GIfNeeded ( // Align buffer on section boundary // ImageContext.ImageAddress +=3D ImageContext.SectionAlignment - 1; - ImageContext.ImageAddress &=3D ~((EFI_PHYSICAL_ADDRESS)(ImageContext.Sec= tionAlignment - 1)); + ImageContext.ImageAddress &=3D ~((EFI_PHYSICAL_ADDRESS)ImageContext.Sect= ionAlignment - 1); // // Load the image to our new buffer // diff --git a/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/FspWrapperApi= Lib.c b/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/FspWrapperApiLib.c index 8cf136f..38de415 100644 --- a/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/FspWrapperApiLib.c +++ b/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/FspWrapperApiLib.c @@ -1,7 +1,7 @@ /** @file Provide FSP API related function. =20 - Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License which accompanies this distribution. The full text of the license may b= e found at @@ -99,7 +99,7 @@ CallFspNotifyPhase ( return EFI_DEVICE_ERROR; } =20 - NotifyPhaseApi =3D (FSP_NOTIFY_PHASE)(UINTN)(FspHeader->ImageBase + FspH= eader->NotifyPhaseEntryOffset); + NotifyPhaseApi =3D (FSP_NOTIFY_PHASE)((UINTN)FspHeader->ImageBase + FspH= eader->NotifyPhaseEntryOffset); InterruptState =3D SaveAndDisableInterrupts (); Status =3D Execute32BitCode ((UINTN)NotifyPhaseApi, (UINTN)NotifyPhasePa= rams, (UINTN)NULL); SetInterruptState (InterruptState); @@ -132,7 +132,7 @@ CallFspMemoryInit ( return EFI_DEVICE_ERROR; } =20 - FspMemoryInitApi =3D (FSP_MEMORY_INIT)(UINTN)(FspHeader->ImageBase + Fsp= Header->FspMemoryInitEntryOffset); + FspMemoryInitApi =3D (FSP_MEMORY_INIT)((UINTN)FspHeader->ImageBase + Fsp= Header->FspMemoryInitEntryOffset); InterruptState =3D SaveAndDisableInterrupts (); Status =3D Execute32BitCode ((UINTN)FspMemoryInitApi, (UINTN)FspmUpdData= Ptr, (UINTN)HobListPtr); SetInterruptState (InterruptState); @@ -163,7 +163,7 @@ CallTempRamExit ( return EFI_DEVICE_ERROR; } =20 - TempRamExitApi =3D (FSP_TEMP_RAM_EXIT)(UINTN)(FspHeader->ImageBase + Fsp= Header->TempRamExitEntryOffset); + TempRamExitApi =3D (FSP_TEMP_RAM_EXIT)((UINTN)FspHeader->ImageBase + Fsp= Header->TempRamExitEntryOffset); InterruptState =3D SaveAndDisableInterrupts (); Status =3D Execute32BitCode ((UINTN)TempRamExitApi, (UINTN)TempRamExitPa= ram, (UINTN)NULL); SetInterruptState (InterruptState); @@ -194,7 +194,7 @@ CallFspSiliconInit ( return EFI_DEVICE_ERROR; } =20 - FspSiliconInitApi =3D (FSP_SILICON_INIT)(UINTN)(FspHeader->ImageBase + F= spHeader->FspSiliconInitEntryOffset); + FspSiliconInitApi =3D (FSP_SILICON_INIT)((UINTN)FspHeader->ImageBase + F= spHeader->FspSiliconInitEntryOffset); InterruptState =3D SaveAndDisableInterrupts (); Status =3D Execute32BitCode ((UINTN)FspSiliconInitApi, (UINTN)FspsUpdDat= aPtr, (UINTN)NULL); SetInterruptState (InterruptState); --=20 1.9.5.msysgit.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel