From nobody Sat Nov 2 14:41:02 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zoho.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1487999574884302.71208720024083; Fri, 24 Feb 2017 21:12:54 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 49F0B8214E; Fri, 24 Feb 2017 21:12:53 -0800 (PST) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id C70368213A for ; Fri, 24 Feb 2017 21:12:51 -0800 (PST) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Feb 2017 21:12:51 -0800 Received: from shwdeopenpsi014.ccr.corp.intel.com ([10.239.9.13]) by orsmga002.jf.intel.com with ESMTP; 24 Feb 2017 21:12:50 -0800 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.35,202,1484035200"; d="scan'208";a="52624002" From: Hao Wu To: edk2-devel@lists.01.org Date: Sat, 25 Feb 2017 13:12:24 +0800 Message-Id: <1487999555-9764-2-git-send-email-hao.a.wu@intel.com> X-Mailer: git-send-email 1.9.5.msysgit.0 In-Reply-To: <1487999555-9764-1-git-send-email-hao.a.wu@intel.com> References: <1487999555-9764-1-git-send-email-hao.a.wu@intel.com> Subject: [edk2] [PATCH v3 01/12] MdePkg: Refine casting expression result to bigger size X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Hao Wu , Michael Kinney , Liming Gao MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" There are cases that the operands of an expression are all with rank less than UINT64/INT64 and the result of the expression is explicitly cast to UINT64/INT64 to fit the target size. An example will be: UINT32 a,b; // a and b can be any unsigned int type with rank less than UINT64, like // UINT8, UINT16, etc. UINT64 c; c =3D (UINT64) (a + b); Some static code checkers may warn that the expression result might overflow within the rank of "int" (integer promotions) and the result is then cast to a bigger size. The commit refines codes by the following rules: 1). When the expression is possible to overflow the range of unsigned int/ int: c =3D (UINT64)a + b; 2). When the expression will not overflow within the rank of "int", remove the explicit type casts: c =3D a + b; 3). When the expression will be cast to pointer of possible greater size: UINT32 a,b; VOID *c; c =3D (VOID *)(UINTN)(a + b); --> c =3D (VOID *)((UINTN)a + b); 4). When one side of a comparison expression contains only operands with rank less than UINT32: UINT8 a; UINT16 b; UINTN c; if ((UINTN)(a + b) > c) {...} --> if (((UINT32)a + b) > c) {...} For rule 4), if we remove the 'UINTN' type cast like: if (a + b > c) {...} The VS compiler will complain with warning C4018 (signed/unsigned mismatch, level 3 warning) due to promoting 'a + b' to type 'int'. Cc: Michael Kinney Cc: Liming Gao Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu Reviewed-by: Laszlo Ersek --- MdePkg/Library/BaseLib/String.c | 4 ++-- MdePkg/Library/BasePeCoffLib/BasePeCoff.c | 12 +++++---= ---- MdePkg/Library/BaseS3PciLib/S3PciLib.c | 4 ++-- MdePkg/Library/SmmMemoryAllocationLib/MemoryAllocationLib.c | 4 ++-- MdePkg/Library/UefiMemoryAllocationLib/MemoryAllocationLib.c | 4 ++-- 5 files changed, 13 insertions(+), 15 deletions(-) diff --git a/MdePkg/Library/BaseLib/String.c b/MdePkg/Library/BaseLib/Strin= g.c index e84bf50..4151e0e 100644 --- a/MdePkg/Library/BaseLib/String.c +++ b/MdePkg/Library/BaseLib/String.c @@ -586,7 +586,7 @@ InternalHexCharToUintn ( return Char - L'0'; } =20 - return (UINTN) (10 + InternalCharToUpper (Char) - L'A'); + return (10 + InternalCharToUpper (Char) - L'A'); } =20 /** @@ -1211,7 +1211,7 @@ InternalAsciiHexCharToUintn ( return Char - '0'; } =20 - return (UINTN) (10 + InternalBaseLibAsciiToUpper (Char) - 'A'); + return (10 + InternalBaseLibAsciiToUpper (Char) - 'A'); } =20 =20 diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoff.c b/MdePkg/Library/Bas= ePeCoffLib/BasePeCoff.c index 33cad23..8d1daba 100644 --- a/MdePkg/Library/BasePeCoffLib/BasePeCoff.c +++ b/MdePkg/Library/BasePeCoffLib/BasePeCoff.c @@ -15,7 +15,7 @@ PeCoffLoaderGetPeHeader() routine will do basic check for PE/COFF header. PeCoffLoaderGetImageInfo() routine will do basic check for whole PE/COFF= image. =20 - Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
+ Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -703,12 +703,10 @@ PeCoffLoaderGetImageInfo ( // DebugDirectoryEntryFileOffset =3D 0; =20 - SectionHeaderOffset =3D (UINTN)( - ImageContext->PeCoffHeaderOffset + - sizeof (UINT32) + - sizeof (EFI_IMAGE_FILE_HEADER) + - Hdr.Pe32->FileHeader.SizeOfOptionalHeader - ); + SectionHeaderOffset =3D ImageContext->PeCoffHeaderOffset + + sizeof (UINT32) + + sizeof (EFI_IMAGE_FILE_HEADER) + + Hdr.Pe32->FileHeader.SizeOfOptionalHeader; =20 for (Index =3D 0; Index < Hdr.Pe32->FileHeader.NumberOfSections; Ind= ex++) { // diff --git a/MdePkg/Library/BaseS3PciLib/S3PciLib.c b/MdePkg/Library/BaseS3= PciLib/S3PciLib.c index e29f7fe..27342b0 100644 --- a/MdePkg/Library/BaseS3PciLib/S3PciLib.c +++ b/MdePkg/Library/BaseS3PciLib/S3PciLib.c @@ -3,7 +3,7 @@ the PCI operations to be replayed during an S3 resume. This library class maps directly on top of the PciLib class.=20 =20 - Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.
+ Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions @@ -25,7 +25,7 @@ #include =20 #define PCILIB_TO_COMMON_ADDRESS(Address) \ - ((UINT64) ((((UINTN) ((Address>>20) & 0xff)) << 24) + (((UINTN) ((= Address>>15) & 0x1f)) << 16) + (((UINTN) ((Address>>12) & 0x07)) << 8) + ((= UINTN) (Address & 0xfff )))) + ((((UINTN) ((Address>>20) & 0xff)) << 24) + (((UINTN) ((Address>>1= 5) & 0x1f)) << 16) + (((UINTN) ((Address>>12) & 0x07)) << 8) + ((UINTN) (Ad= dress & 0xfff ))) =20 /** Saves a PCI configuration value to the boot script. diff --git a/MdePkg/Library/SmmMemoryAllocationLib/MemoryAllocationLib.c b/= MdePkg/Library/SmmMemoryAllocationLib/MemoryAllocationLib.c index 937165a..592cced 100644 --- a/MdePkg/Library/SmmMemoryAllocationLib/MemoryAllocationLib.c +++ b/MdePkg/Library/SmmMemoryAllocationLib/MemoryAllocationLib.c @@ -12,7 +12,7 @@ allocation for the Reserved memory types are not supported and will alwa= ys=20 return NULL. =20 - Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.
+ Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials =20 are licensed and made available under the terms and conditions of the BS= D License =20 which accompanies this distribution. The full text of the license may b= e found at =20 @@ -343,7 +343,7 @@ InternalAllocateAlignedPages ( Status =3D gSmst->SmmFreePages (Memory, UnalignedPages); ASSERT_EFI_ERROR (Status); } - Memory =3D (EFI_PHYSICAL_ADDRESS) (AlignedMemory + EFI_PAGES_T= O_SIZE (Pages)); + Memory =3D AlignedMemory + EFI_PAGES_TO_SIZE (Pages); UnalignedPages =3D RealPages - Pages - UnalignedPages; if (UnalignedPages > 0) { // diff --git a/MdePkg/Library/UefiMemoryAllocationLib/MemoryAllocationLib.c b= /MdePkg/Library/UefiMemoryAllocationLib/MemoryAllocationLib.c index 3da5e211..3bd3aef 100644 --- a/MdePkg/Library/UefiMemoryAllocationLib/MemoryAllocationLib.c +++ b/MdePkg/Library/UefiMemoryAllocationLib/MemoryAllocationLib.c @@ -2,7 +2,7 @@ Support routines for memory allocation routines based=20 on boot services for Dxe phase drivers. =20 - Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.
+ Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials =20 are licensed and made available under the terms and conditions of the BS= D License =20 which accompanies this distribution. The full text of the license may b= e found at =20 @@ -216,7 +216,7 @@ InternalAllocateAlignedPages ( Status =3D gBS->FreePages (Memory, UnalignedPages); ASSERT_EFI_ERROR (Status); } - Memory =3D (EFI_PHYSICAL_ADDRESS) (AlignedMemory + EFI_PAGES_T= O_SIZE (Pages)); + Memory =3D AlignedMemory + EFI_PAGES_TO_SIZE (Pages); UnalignedPages =3D RealPages - Pages - UnalignedPages; if (UnalignedPages > 0) { // --=20 1.9.5.msysgit.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat Nov 2 14:41:02 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zoho.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1487999577345427.8141970373682; Fri, 24 Feb 2017 21:12:57 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 85FD182151; Fri, 24 Feb 2017 21:12:55 -0800 (PST) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 689FC82151 for ; Fri, 24 Feb 2017 21:12:53 -0800 (PST) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Feb 2017 21:12:53 -0800 Received: from shwdeopenpsi014.ccr.corp.intel.com ([10.239.9.13]) by orsmga002.jf.intel.com with ESMTP; 24 Feb 2017 21:12:51 -0800 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.35,202,1484035200"; d="scan'208";a="52624009" From: Hao Wu To: edk2-devel@lists.01.org Date: Sat, 25 Feb 2017 13:12:25 +0800 Message-Id: <1487999555-9764-3-git-send-email-hao.a.wu@intel.com> X-Mailer: git-send-email 1.9.5.msysgit.0 In-Reply-To: <1487999555-9764-1-git-send-email-hao.a.wu@intel.com> References: <1487999555-9764-1-git-send-email-hao.a.wu@intel.com> Subject: [edk2] [PATCH v3 02/12] MdeModulePkg: Refine casting expression result to bigger size X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Hao Wu , Feng Tian , Star Zeng MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" There are cases that the operands of an expression are all with rank less than UINT64/INT64 and the result of the expression is explicitly cast to UINT64/INT64 to fit the target size. An example will be: UINT32 a,b; // a and b can be any unsigned int type with rank less than UINT64, like // UINT8, UINT16, etc. UINT64 c; c =3D (UINT64) (a + b); Some static code checkers may warn that the expression result might overflow within the rank of "int" (integer promotions) and the result is then cast to a bigger size. The commit refines codes by the following rules: 1). When the expression is possible to overflow the range of unsigned int/ int: c =3D (UINT64)a + b; 2). When the expression will not overflow within the rank of "int", remove the explicit type casts: c =3D a + b; 3). When the expression will be cast to pointer of possible greater size: UINT32 a,b; VOID *c; c =3D (VOID *)(UINTN)(a + b); --> c =3D (VOID *)((UINTN)a + b); 4). When one side of a comparison expression contains only operands with rank less than UINT32: UINT8 a; UINT16 b; UINTN c; if ((UINTN)(a + b) > c) {...} --> if (((UINT32)a + b) > c) {...} For rule 4), if we remove the 'UINTN' type cast like: if (a + b > c) {...} The VS compiler will complain with warning C4018 (signed/unsigned mismatch, level 3 warning) due to promoting 'a + b' to type 'int'. Cc: Feng Tian Cc: Star Zeng Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu Reviewed-by: Feng Tian --- MdeModulePkg/Application/UiApp/FrontPage.c = | 4 ++-- MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.c = | 8 ++++---- MdeModulePkg/Bus/Pci/IdeBusPei/AtapiPeim.c = | 4 ++-- MdeModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.c = | 2 +- MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c = | 20 ++++++++++---------- MdeModulePkg/Bus/Ufs/UfsBlockIoPei/UfsHci.c = | 6 +++--- MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThruHci.c = | 6 +++--- MdeModulePkg/Core/Dxe/Image/Image.c = | 14 ++++++-------- MdeModulePkg/Core/Dxe/Misc/DebugImageInfo.c = | 4 ++-- MdeModulePkg/Core/Pei/Image/Image.c = | 12 +++++------- MdeModulePkg/Core/PiSmmCore/Dispatcher.c = | 18 ++++++++---------- MdeModulePkg/Core/PiSmmCore/PiSmmIpl.c = | 12 +++++------- MdeModulePkg/Library/DxeCapsuleLibFmp/DxeCapsuleLib.c = | 4 ++-- MdeModulePkg/Library/DxeCoreMemoryAllocationLib/MemoryAllocationLib.c = | 4 ++-- MdeModulePkg/Library/DxeNetLib/DxeNetLib.c = | 4 ++-- MdeModulePkg/Library/PiDxeS3BootScriptLib/BootScriptSave.c = | 4 ++-- MdeModulePkg/Library/PiSmmCoreMemoryAllocationLib/MemoryAllocationLib.c = | 4 ++-- MdeModulePkg/Library/SmmMemoryAllocationProfileLib/MemoryAllocationLib.c = | 4 ++-- MdeModulePkg/Library/UefiBootManagerLib/BmMisc.c = | 4 ++-- MdeModulePkg/Library/UefiHiiLib/HiiLib.c = | 4 ++-- MdeModulePkg/Library/UefiMemoryAllocationProfileLib/MemoryAllocationLib.c = | 4 ++-- MdeModulePkg/Library/VarCheckHiiLib/VarCheckHiiLibNullClass.c = | 6 +++--- MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/ScriptExecute.c = | 4 ++-- MdeModulePkg/Universal/Acpi/S3SaveStateDxe/AcpiS3ContextSave.c = | 6 +++--- MdeModulePkg/Universal/CapsulePei/Common/CapsuleCoalesce.c = | 4 ++-- MdeModulePkg/Universal/DisplayEngineDxe/FormDisplay.c = | 8 ++++---- MdeModulePkg/Universal/EbcDxe/EbcExecute.c = | 10 +++++----- MdeModulePkg/Universal/FaultTolerantWriteDxe/UpdateWorkingBlock.c = | 4 ++-- MdeModulePkg/Universal/HiiDatabaseDxe/Font.c = | 20 ++++++++++---------- MdeModulePkg/Universal/Network/UefiPxeBcDxe/PxeBcImpl.c = | 6 +++--- MdeModulePkg/Universal/PCD/Dxe/Service.c = | 4 ++-- MdeModulePkg/Universal/PCD/Pei/Service.c = | 4 ++-- MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.c = | 6 +++--- MdeModulePkg/Universal/Variable/RuntimeDxe/Variable.c = | 6 +++--- 34 files changed, 113 insertions(+), 121 deletions(-) diff --git a/MdeModulePkg/Application/UiApp/FrontPage.c b/MdeModulePkg/Appl= ication/UiApp/FrontPage.c index bda5ff9..c2393eb 100644 --- a/MdeModulePkg/Application/UiApp/FrontPage.c +++ b/MdeModulePkg/Application/UiApp/FrontPage.c @@ -1,7 +1,7 @@ /** @file FrontPage routines to handle the callbacks and browser calls =20 -Copyright (c) 2004 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2004 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License which accompanies this distribution. The full text of the license may be = found at @@ -399,7 +399,7 @@ ConvertProcessorToString ( =20 if (Base10Exponent >=3D 6) { FreqMhz =3D ProcessorFrequency; - for (Index =3D 0; Index < (UINTN) (Base10Exponent - 6); Index++) { + for (Index =3D 0; Index < (UINT32) Base10Exponent - 6; Index++) { FreqMhz *=3D 10; } } else { diff --git a/MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.c b/MdeModulePkg/Bus/Pci/= EhciDxe/EhciReg.c index 3a6ed02..34836ec 100644 --- a/MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.c +++ b/MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.c @@ -2,7 +2,7 @@ =20 The EHCI register operation routines. =20 -Copyright (c) 2007 - 2012, Intel Corporation. All rights reserved.
+Copyright (c) 2007 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License which accompanies this distribution. The full text of the license may be = found at @@ -76,7 +76,7 @@ EhcReadDbgRegister ( Ehc->PciIo, EfiPciIoWidthUint32, Ehc->DebugPortBarNum, - (UINT64) (Ehc->DebugPortOffset + Offset), + Ehc->DebugPortOffset + Offset, 1, &Data ); @@ -115,7 +115,7 @@ EhcReadOpReg ( Ehc->PciIo, EfiPciIoWidthUint32, EHC_BAR_INDEX, - (UINT64) (Ehc->CapLen + Offset), + Ehc->CapLen + Offset, 1, &Data ); @@ -152,7 +152,7 @@ EhcWriteOpReg ( Ehc->PciIo, EfiPciIoWidthUint32, EHC_BAR_INDEX, - (UINT64) (Ehc->CapLen + Offset), + Ehc->CapLen + Offset, 1, &Data ); diff --git a/MdeModulePkg/Bus/Pci/IdeBusPei/AtapiPeim.c b/MdeModulePkg/Bus/= Pci/IdeBusPei/AtapiPeim.c index be1b829..b1ab34d 100644 --- a/MdeModulePkg/Bus/Pci/IdeBusPei/AtapiPeim.c +++ b/MdeModulePkg/Bus/Pci/IdeBusPei/AtapiPeim.c @@ -5,7 +5,7 @@ ATA controllers in the platform. This PPI can be consumed by PEIM which produce gEfiPeiDeviceRecoveryModule= PpiGuid for Atapi CD ROM device. =20 -Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions @@ -593,7 +593,7 @@ AtapiEnumerateDevices ( // // Pata & Sata, Primary & Secondary channel, Master & Slave device // - DevicePosition =3D (UINTN) (Index1 * 2 + Index2); + DevicePosition =3D Index1 * 2 + Index2; =20 if (DiscoverAtapiDevice (AtapiBlkIoDev, DevicePosition, &MediaInfo, = &MediaInfo2)) { // diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.c b/MdeModu= lePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.c index d2ad94e..3713c07 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.c @@ -305,7 +305,7 @@ GetOpRomInfo ( return EFI_NOT_FOUND; } =20 - PciIoDevice->RomSize =3D (UINT64) ((~AllOnes) + 1); + PciIoDevice->RomSize =3D (~AllOnes) + 1; return EFI_SUCCESS; } =20 diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c b/MdeModulePkg/Bus/Pci/= XhciDxe/XhciReg.c index 0e1c86c..4d5937d 100644 --- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c +++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c @@ -2,7 +2,7 @@ =20 The XHCI register operation routines. =20 -Copyright (c) 2011 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2011 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License which accompanies this distribution. The full text of the license may be = found at @@ -112,7 +112,7 @@ XhcReadOpReg ( Xhc->PciIo, EfiPciIoWidthUint32, XHC_BAR_INDEX, - (UINT64) (Xhc->CapLength + Offset), + Xhc->CapLength + Offset, 1, &Data ); @@ -148,7 +148,7 @@ XhcWriteOpReg ( Xhc->PciIo, EfiPciIoWidthUint32, XHC_BAR_INDEX, - (UINT64) (Xhc->CapLength + Offset), + Xhc->CapLength + Offset, 1, &Data ); @@ -181,7 +181,7 @@ XhcWriteOpReg16 ( Xhc->PciIo, EfiPciIoWidthUint16, XHC_BAR_INDEX, - (UINT64) (Xhc->CapLength + Offset), + Xhc->CapLength + Offset, 1, &Data ); @@ -215,7 +215,7 @@ XhcReadDoorBellReg ( Xhc->PciIo, EfiPciIoWidthUint32, XHC_BAR_INDEX, - (UINT64) (Xhc->DBOff + Offset), + Xhc->DBOff + Offset, 1, &Data ); @@ -251,7 +251,7 @@ XhcWriteDoorBellReg ( Xhc->PciIo, EfiPciIoWidthUint32, XHC_BAR_INDEX, - (UINT64) (Xhc->DBOff + Offset), + Xhc->DBOff + Offset, 1, &Data ); @@ -285,7 +285,7 @@ XhcReadRuntimeReg ( Xhc->PciIo, EfiPciIoWidthUint32, XHC_BAR_INDEX, - (UINT64) (Xhc->RTSOff + Offset), + Xhc->RTSOff + Offset, 1, &Data ); @@ -321,7 +321,7 @@ XhcWriteRuntimeReg ( Xhc->PciIo, EfiPciIoWidthUint32, XHC_BAR_INDEX, - (UINT64) (Xhc->RTSOff + Offset), + Xhc->RTSOff + Offset, 1, &Data ); @@ -355,7 +355,7 @@ XhcReadExtCapReg ( Xhc->PciIo, EfiPciIoWidthUint32, XHC_BAR_INDEX, - (UINT64) (Xhc->ExtCapRegBase + Offset), + Xhc->ExtCapRegBase + Offset, 1, &Data ); @@ -391,7 +391,7 @@ XhcWriteExtCapReg ( Xhc->PciIo, EfiPciIoWidthUint32, XHC_BAR_INDEX, - (UINT64) (Xhc->ExtCapRegBase + Offset), + Xhc->ExtCapRegBase + Offset, 1, &Data ); diff --git a/MdeModulePkg/Bus/Ufs/UfsBlockIoPei/UfsHci.c b/MdeModulePkg/Bus= /Ufs/UfsBlockIoPei/UfsHci.c index 332ce7e..1ef6c88 100644 --- a/MdeModulePkg/Bus/Ufs/UfsBlockIoPei/UfsHci.c +++ b/MdeModulePkg/Bus/Ufs/UfsBlockIoPei/UfsHci.c @@ -1,6 +1,6 @@ /** @file =20 - Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License which accompanies this distribution. The full text of the license may b= e found at @@ -589,9 +589,9 @@ UfsCreateDMCommandDesc ( Trd->UcdBaU =3D (UINT32)RShiftU64 ((UINT64)(UINTN)QueryReqUpiu, 32); if (Opcode =3D=3D UtpQueryFuncOpcodeWrDesc) { Trd->RuL =3D (UINT16)DivU64x32 ((UINT64)ROUNDUP8 (sizeof (UTP_QUERY_R= ESP_UPIU)), sizeof (UINT32)); - Trd->RuO =3D (UINT16)DivU64x32 ((UINT64)(ROUNDUP8 (sizeof (UTP_QUERY_= REQ_UPIU)) + ROUNDUP8 (DataSize)), sizeof (UINT32)); + Trd->RuO =3D (UINT16)DivU64x32 ((UINT64)ROUNDUP8 (sizeof (UTP_QUERY_R= EQ_UPIU)) + ROUNDUP8 (DataSize), sizeof (UINT32)); } else { - Trd->RuL =3D (UINT16)DivU64x32 ((UINT64)(ROUNDUP8 (sizeof (UTP_QUERY_= RESP_UPIU)) + ROUNDUP8 (DataSize)), sizeof (UINT32)); + Trd->RuL =3D (UINT16)DivU64x32 ((UINT64)ROUNDUP8 (sizeof (UTP_QUERY_R= ESP_UPIU)) + ROUNDUP8 (DataSize), sizeof (UINT32)); Trd->RuO =3D (UINT16)DivU64x32 ((UINT64)ROUNDUP8 (sizeof (UTP_QUERY_R= EQ_UPIU)), sizeof (UINT32)); } =20 diff --git a/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThruHci.c b/MdeModu= lePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThruHci.c index bc39cf8..3dd8cbf 100644 --- a/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThruHci.c +++ b/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThruHci.c @@ -2,7 +2,7 @@ UfsPassThruDxe driver is used to produce EFI_EXT_SCSI_PASS_THRU protocol= interface for upper layer application to execute UFS-supported SCSI cmds. =20 - Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License which accompanies this distribution. The full text of the license may b= e found at @@ -666,9 +666,9 @@ UfsCreateDMCommandDesc ( Trd->UcdBaU =3D (UINT32)RShiftU64 ((UINT64)CmdDescPhyAddr, 32); if (Opcode =3D=3D UtpQueryFuncOpcodeWrDesc) { Trd->RuL =3D (UINT16)DivU64x32 ((UINT64)ROUNDUP8 (sizeof (UTP_QUERY_R= ESP_UPIU)), sizeof (UINT32)); - Trd->RuO =3D (UINT16)DivU64x32 ((UINT64)(ROUNDUP8 (sizeof (UTP_QUERY_= REQ_UPIU)) + ROUNDUP8 (DataSize)), sizeof (UINT32)); + Trd->RuO =3D (UINT16)DivU64x32 ((UINT64)ROUNDUP8 (sizeof (UTP_QUERY_R= EQ_UPIU)) + ROUNDUP8 (DataSize), sizeof (UINT32)); } else { - Trd->RuL =3D (UINT16)DivU64x32 ((UINT64)(ROUNDUP8 (sizeof (UTP_QUERY_= RESP_UPIU)) + ROUNDUP8 (DataSize)), sizeof (UINT32)); + Trd->RuL =3D (UINT16)DivU64x32 ((UINT64)ROUNDUP8 (sizeof (UTP_QUERY_R= ESP_UPIU)) + ROUNDUP8 (DataSize), sizeof (UINT32)); Trd->RuO =3D (UINT16)DivU64x32 ((UINT64)ROUNDUP8 (sizeof (UTP_QUERY_R= EQ_UPIU)), sizeof (UINT32)); } =20 diff --git a/MdeModulePkg/Core/Dxe/Image/Image.c b/MdeModulePkg/Core/Dxe/Im= age/Image.c index 652da8b..80128e7 100644 --- a/MdeModulePkg/Core/Dxe/Image/Image.c +++ b/MdeModulePkg/Core/Dxe/Image/Image.c @@ -313,8 +313,8 @@ CheckAndMarkFixLoadingMemoryUsageBitMap ( // // Test if the memory is avalaible or not. //=20 - BaseOffsetPageNumber =3D (UINTN)EFI_SIZE_TO_PAGES((UINT32)(ImageBase - = DxeCodeBase)); - TopOffsetPageNumber =3D (UINTN)EFI_SIZE_TO_PAGES((UINT32)(ImageBase + = ImageSize - DxeCodeBase)); + BaseOffsetPageNumber =3D EFI_SIZE_TO_PAGES((UINT32)(ImageBase - DxeCode= Base)); + TopOffsetPageNumber =3D EFI_SIZE_TO_PAGES((UINT32)(ImageBase + ImageSi= ze - DxeCodeBase)); for (Index =3D BaseOffsetPageNumber; Index < TopOffsetPageNumber; Index= ++) { if ((mDxeCodeMemoryRangeUsageBitMap[Index / 64] & LShiftU64(1, (Index= % 64))) !=3D 0) { // @@ -366,12 +366,10 @@ GetPeCoffImageFixLoadingAssignedAddress( // Handle =3D (IMAGE_FILE_HANDLE*)ImageContext->Handle; ImgHdr =3D (EFI_IMAGE_OPTIONAL_HEADER_UNION *)((CHAR8* )Handle->Source = + ImageContext->PeCoffHeaderOffset); - SectionHeaderOffset =3D (UINTN)( - ImageContext->PeCoffHeaderOffset + - sizeof (UINT32) + - sizeof (EFI_IMAGE_FILE_HEADER) + - ImgHdr->Pe32.FileHeader.SizeOfOptionalHea= der - ); + SectionHeaderOffset =3D ImageContext->PeCoffHeaderOffset + + sizeof (UINT32) + + sizeof (EFI_IMAGE_FILE_HEADER) + + ImgHdr->Pe32.FileHeader.SizeOfOptionalHeader; NumberOfSections =3D ImgHdr->Pe32.FileHeader.NumberOfSections; =20 // diff --git a/MdeModulePkg/Core/Dxe/Misc/DebugImageInfo.c b/MdeModulePkg/Cor= e/Dxe/Misc/DebugImageInfo.c index 4766072..fda6d44 100644 --- a/MdeModulePkg/Core/Dxe/Misc/DebugImageInfo.c +++ b/MdeModulePkg/Core/Dxe/Misc/DebugImageInfo.c @@ -2,7 +2,7 @@ Support functions for managing debug image info table when loading and u= nloading images. =20 -Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License which accompanies this distribution. The full text of the license may be = found at @@ -103,7 +103,7 @@ CoreInitializeDebugImageInfoTable ( Status =3D CoreFreePages (Memory, UnalignedPages); ASSERT_EFI_ERROR (Status); } - Memory =3D (EFI_PHYSICAL_ADDRESS)(AlignedMemory + EFI_PAGES_TO_S= IZE (Pages)); + Memory =3D AlignedMemory + EFI_PAGES_TO_SIZE (Pages); UnalignedPages =3D RealPages - Pages - UnalignedPages; if (UnalignedPages > 0) { // diff --git a/MdeModulePkg/Core/Pei/Image/Image.c b/MdeModulePkg/Core/Pei/Im= age/Image.c index d659de8..381a23f 100644 --- a/MdeModulePkg/Core/Pei/Image/Image.c +++ b/MdeModulePkg/Core/Pei/Image/Image.c @@ -1,7 +1,7 @@ /** @file Pei Core Load Image Support =20 -Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License which accompanies this distribution. The full text of the license may be = found at @@ -250,12 +250,10 @@ GetPeCoffImageFixLoadingAssignedAddress( SectionHeaderOffset =3D sizeof (EFI_TE_IMAGE_HEADER); NumberOfSections =3D ImgHdr->Te.NumberOfSections; } else { - SectionHeaderOffset =3D (UINTN)( - ImageContext->PeCoffHeaderOffset + - sizeof (UINT32) + - sizeof (EFI_IMAGE_FILE_HEADER) + - ImgHdr->Pe32.FileHeader.SizeOfOptionalHea= der - ); + SectionHeaderOffset =3D ImageContext->PeCoffHeaderOffset + + sizeof (UINT32) + + sizeof (EFI_IMAGE_FILE_HEADER) + + ImgHdr->Pe32.FileHeader.SizeOfOptionalHeader; NumberOfSections =3D ImgHdr->Pe32.FileHeader.NumberOfSections; } // diff --git a/MdeModulePkg/Core/PiSmmCore/Dispatcher.c b/MdeModulePkg/Core/P= iSmmCore/Dispatcher.c index 1bddaf1..b2a6822 100644 --- a/MdeModulePkg/Core/PiSmmCore/Dispatcher.c +++ b/MdeModulePkg/Core/PiSmmCore/Dispatcher.c @@ -28,7 +28,7 @@ Depex - Dependency Expresion. =20 Copyright (c) 2014, Hewlett-Packard Development Company, L.P. - Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made availa= ble=20 under the terms and conditions of the BSD License which accompanies this=20 distribution. The full text of the license may be found at =20 @@ -183,8 +183,8 @@ CheckAndMarkFixLoadingMemoryUsageBitMap ( // // Test if the memory is avalaible or not. //=20 - BaseOffsetPageNumber =3D (UINTN)EFI_SIZE_TO_PAGES((UINT32)(ImageBase - = SmmCodeBase)); - TopOffsetPageNumber =3D (UINTN)EFI_SIZE_TO_PAGES((UINT32)(ImageBase + = ImageSize - SmmCodeBase)); + BaseOffsetPageNumber =3D EFI_SIZE_TO_PAGES((UINT32)(ImageBase - SmmCode= Base)); + TopOffsetPageNumber =3D EFI_SIZE_TO_PAGES((UINT32)(ImageBase + ImageSi= ze - SmmCodeBase)); for (Index =3D BaseOffsetPageNumber; Index < TopOffsetPageNumber; Index= ++) { if ((mSmmCodeMemoryRangeUsageBitMap[Index / 64] & LShiftU64(1, (Index= % 64))) !=3D 0) { // @@ -234,12 +234,10 @@ GetPeCoffImageFixLoadingAssignedAddress( // Get PeHeader pointer // ImgHdr =3D (EFI_IMAGE_OPTIONAL_HEADER_UNION *)((CHAR8* )ImageContext->Ha= ndle + ImageContext->PeCoffHeaderOffset); - SectionHeaderOffset =3D (UINTN)( - ImageContext->PeCoffHeaderOffset + - sizeof (UINT32) + - sizeof (EFI_IMAGE_FILE_HEADER) + - ImgHdr->Pe32.FileHeader.SizeOfOptionalHea= der - ); + SectionHeaderOffset =3D ImageContext->PeCoffHeaderOffset + + sizeof (UINT32) + + sizeof (EFI_IMAGE_FILE_HEADER) + + ImgHdr->Pe32.FileHeader.SizeOfOptionalHeader; NumberOfSections =3D ImgHdr->Pe32.FileHeader.NumberOfSections; =20 // @@ -520,7 +518,7 @@ SmmLoadImage ( // Align buffer on section boundary // ImageContext.ImageAddress +=3D ImageContext.SectionAlignment - 1; - ImageContext.ImageAddress &=3D ~((EFI_PHYSICAL_ADDRESS)(ImageContext.Sec= tionAlignment - 1)); + ImageContext.ImageAddress &=3D ~((EFI_PHYSICAL_ADDRESS)ImageContext.Sect= ionAlignment - 1); =20 // // Load the image to our new buffer diff --git a/MdeModulePkg/Core/PiSmmCore/PiSmmIpl.c b/MdeModulePkg/Core/PiS= mmCore/PiSmmIpl.c index 26b71f1..feb846e 100644 --- a/MdeModulePkg/Core/PiSmmCore/PiSmmIpl.c +++ b/MdeModulePkg/Core/PiSmmCore/PiSmmIpl.c @@ -846,12 +846,10 @@ GetPeCoffImageFixLoadingAssignedAddress( // Get PeHeader pointer // ImgHdr =3D (EFI_IMAGE_OPTIONAL_HEADER_UNION *)((CHAR8* )ImageContext->H= andle + ImageContext->PeCoffHeaderOffset); - SectionHeaderOffset =3D (UINTN)( - ImageContext->PeCoffHeaderOffset + - sizeof (UINT32) + - sizeof (EFI_IMAGE_FILE_HEADER) + - ImgHdr->Pe32.FileHeader.SizeOfOptionalHea= der - ); + SectionHeaderOffset =3D ImageContext->PeCoffHeaderOffset + + sizeof (UINT32) + + sizeof (EFI_IMAGE_FILE_HEADER) + + ImgHdr->Pe32.FileHeader.SizeOfOptionalHeader; NumberOfSections =3D ImgHdr->Pe32.FileHeader.NumberOfSections; =20 // @@ -1022,7 +1020,7 @@ ExecuteSmmCoreFromSmram ( } =20 ImageContext.ImageAddress +=3D ImageContext.SectionAlignment - 1; - ImageContext.ImageAddress &=3D ~((EFI_PHYSICAL_ADDRESS)(ImageContext.Sec= tionAlignment - 1)); + ImageContext.ImageAddress &=3D ~((EFI_PHYSICAL_ADDRESS)ImageContext.Sect= ionAlignment - 1); =20 // // Print debug message showing SMM Core load address. diff --git a/MdeModulePkg/Library/DxeCapsuleLibFmp/DxeCapsuleLib.c b/MdeMod= ulePkg/Library/DxeCapsuleLibFmp/DxeCapsuleLib.c index d7abcc8..7f500a9 100644 --- a/MdeModulePkg/Library/DxeCapsuleLibFmp/DxeCapsuleLib.c +++ b/MdeModulePkg/Library/DxeCapsuleLibFmp/DxeCapsuleLib.c @@ -585,7 +585,7 @@ DisplayCapsuleImage ( EFI_GRAPHICS_OUTPUT_PROTOCOL *GraphicsOutput; =20 ImagePayload =3D (DISPLAY_DISPLAY_PAYLOAD *)(CapsuleHeader + 1); - PayloadSize =3D (UINTN)(CapsuleHeader->CapsuleImageSize - sizeof(EFI_CAP= SULE_HEADER)); + PayloadSize =3D CapsuleHeader->CapsuleImageSize - sizeof(EFI_CAPSULE_HEA= DER); =20 if (ImagePayload->Version !=3D 1) { return EFI_UNSUPPORTED; @@ -733,7 +733,7 @@ DumpFmpCapsule ( for (Index =3D 0; Index < FmpCapsuleHeader->EmbeddedDriverCount; Index++= ) { DEBUG((DEBUG_VERBOSE, " ItemOffsetList[%d] - 0x%lx\n", Index, It= emOffsetList[Index])); } - for (; Index < (UINTN)(FmpCapsuleHeader->EmbeddedDriverCount + FmpCapsul= eHeader->PayloadItemCount); Index++) { + for (; Index < (UINT32)FmpCapsuleHeader->EmbeddedDriverCount + FmpCapsul= eHeader->PayloadItemCount; Index++) { DEBUG((DEBUG_VERBOSE, " ItemOffsetList[%d] - 0x%lx\n", Index, It= emOffsetList[Index])); ImageHeader =3D (EFI_FIRMWARE_MANAGEMENT_CAPSULE_IMAGE_HEADER *)((UINT= 8 *)FmpCapsuleHeader + ItemOffsetList[Index]); =20 diff --git a/MdeModulePkg/Library/DxeCoreMemoryAllocationLib/MemoryAllocati= onLib.c b/MdeModulePkg/Library/DxeCoreMemoryAllocationLib/MemoryAllocationL= ib.c index 89c19e7..95725c8 100644 --- a/MdeModulePkg/Library/DxeCoreMemoryAllocationLib/MemoryAllocationLib.c +++ b/MdeModulePkg/Library/DxeCoreMemoryAllocationLib/MemoryAllocationLib.c @@ -3,7 +3,7 @@ on DxeCore Memory Allocation services for DxeCore, with memory profile support. =20 - Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials =20 are licensed and made available under the terms and conditions of the BS= D License =20 which accompanies this distribution. The full text of the license may b= e found at =20 @@ -258,7 +258,7 @@ InternalAllocateAlignedPages ( Status =3D CoreFreePages (Memory, UnalignedPages); ASSERT_EFI_ERROR (Status); } - Memory =3D (EFI_PHYSICAL_ADDRESS) (AlignedMemory + EFI_PAGES_T= O_SIZE (Pages)); + Memory =3D AlignedMemory + EFI_PAGES_TO_SIZE (Pages); UnalignedPages =3D RealPages - Pages - UnalignedPages; if (UnalignedPages > 0) { // diff --git a/MdeModulePkg/Library/DxeNetLib/DxeNetLib.c b/MdeModulePkg/Libr= ary/DxeNetLib/DxeNetLib.c index 0a7117c..c015aa6 100644 --- a/MdeModulePkg/Library/DxeNetLib/DxeNetLib.c +++ b/MdeModulePkg/Library/DxeNetLib/DxeNetLib.c @@ -1,7 +1,7 @@ /** @file Network library. =20 -Copyright (c) 2005 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2005 - 2017, Intel Corporation. All rights reserved.
(C) Copyright 2015 Hewlett Packard Enterprise Development LP
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License @@ -3299,7 +3299,7 @@ NetLibGetSystemGuid ( return EFI_NOT_FOUND; } Smbios.Hdr =3D (SMBIOS_STRUCTURE *) (UINTN) SmbiosTable->TableAddre= ss; - SmbiosEnd.Raw =3D (UINT8 *) (UINTN) (SmbiosTable->TableAddress + Smbio= sTable->TableLength); + SmbiosEnd.Raw =3D (UINT8 *) ((UINTN) SmbiosTable->TableAddress + Smbio= sTable->TableLength); } =20 do { diff --git a/MdeModulePkg/Library/PiDxeS3BootScriptLib/BootScriptSave.c b/M= deModulePkg/Library/PiDxeS3BootScriptLib/BootScriptSave.c index 1f8aaf4..fe2d3a0 100644 --- a/MdeModulePkg/Library/PiDxeS3BootScriptLib/BootScriptSave.c +++ b/MdeModulePkg/Library/PiDxeS3BootScriptLib/BootScriptSave.c @@ -691,7 +691,7 @@ S3BootScriptGetBootTimeEntryAddAddress ( // Here we do not count the reserved memory for runtime script table. PageNumber =3D (UINT16) (mS3BootScriptTablePtr->TableMemoryPageNumber -= PcdGet16(PcdS3BootScriptRuntimeTableReservePageNumber)); TableLength =3D mS3BootScriptTablePtr->TableLength; - if ((UINTN) EFI_PAGES_TO_SIZE ((UINTN) PageNumber) < (UINTN) (TableLeng= th + EntryLength + sizeof (EFI_BOOT_SCRIPT_TERMINATE))) { + if (EFI_PAGES_TO_SIZE ((UINTN) PageNumber) < (TableLength + EntryLength= + sizeof (EFI_BOOT_SCRIPT_TERMINATE))) { // // The buffer is too small to hold the table, Reallocate the buffer // @@ -752,7 +752,7 @@ S3BootScriptGetRuntimeEntryAddAddress ( // // Check if the memory range reserved for S3 Boot Script table is large= enough to hold the node. // - if ((UINTN) (mS3BootScriptTablePtr->TableLength + EntryLength + sizeof = (EFI_BOOT_SCRIPT_TERMINATE)) <=3D (UINTN) EFI_PAGES_TO_SIZE ((UINTN) (mS3Bo= otScriptTablePtr->TableMemoryPageNumber))) { + if ((mS3BootScriptTablePtr->TableLength + EntryLength + sizeof (EFI_BOO= T_SCRIPT_TERMINATE)) <=3D EFI_PAGES_TO_SIZE ((UINTN) (mS3BootScriptTablePtr= ->TableMemoryPageNumber))) { NewEntryPtr =3D mS3BootScriptTablePtr->TableBase + mS3BootScriptTable= Ptr->TableLength; mS3BootScriptTablePtr->TableLength =3D mS3BootScriptTablePtr->TableLe= ngth + EntryLength; // diff --git a/MdeModulePkg/Library/PiSmmCoreMemoryAllocationLib/MemoryAlloca= tionLib.c b/MdeModulePkg/Library/PiSmmCoreMemoryAllocationLib/MemoryAllocat= ionLib.c index bd21468..96cb275 100644 --- a/MdeModulePkg/Library/PiSmmCoreMemoryAllocationLib/MemoryAllocationLib= .c +++ b/MdeModulePkg/Library/PiSmmCoreMemoryAllocationLib/MemoryAllocationLib= .c @@ -11,7 +11,7 @@ In addition, allocation for the Reserved memory types are not supported = and will=20 always return NULL. =20 - Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials =20 are licensed and made available under the terms and conditions of the BS= D License =20 which accompanies this distribution. The full text of the license may b= e found at =20 @@ -293,7 +293,7 @@ InternalAllocateAlignedPages ( Status =3D SmmFreePages (Memory, UnalignedPages); ASSERT_EFI_ERROR (Status); } - Memory =3D (EFI_PHYSICAL_ADDRESS) (AlignedMemory + EFI_PAGES_T= O_SIZE (Pages)); + Memory =3D AlignedMemory + EFI_PAGES_TO_SIZE (Pages); UnalignedPages =3D RealPages - Pages - UnalignedPages; if (UnalignedPages > 0) { // diff --git a/MdeModulePkg/Library/SmmMemoryAllocationProfileLib/MemoryAlloc= ationLib.c b/MdeModulePkg/Library/SmmMemoryAllocationProfileLib/MemoryAlloc= ationLib.c index e9bbf02..2a18155 100644 --- a/MdeModulePkg/Library/SmmMemoryAllocationProfileLib/MemoryAllocationLi= b.c +++ b/MdeModulePkg/Library/SmmMemoryAllocationProfileLib/MemoryAllocationLi= b.c @@ -12,7 +12,7 @@ allocation for the Reserved memory types are not supported and will alwa= ys=20 return NULL. =20 - Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials =20 are licensed and made available under the terms and conditions of the BS= D License =20 which accompanies this distribution. The full text of the license may b= e found at =20 @@ -371,7 +371,7 @@ InternalAllocateAlignedPages ( Status =3D gSmst->SmmFreePages (Memory, UnalignedPages); ASSERT_EFI_ERROR (Status); } - Memory =3D (EFI_PHYSICAL_ADDRESS) (AlignedMemory + EFI_PAGES_T= O_SIZE (Pages)); + Memory =3D AlignedMemory + EFI_PAGES_TO_SIZE (Pages); UnalignedPages =3D RealPages - Pages - UnalignedPages; if (UnalignedPages > 0) { // diff --git a/MdeModulePkg/Library/UefiBootManagerLib/BmMisc.c b/MdeModulePk= g/Library/UefiBootManagerLib/BmMisc.c index e11d842..11ab867 100644 --- a/MdeModulePkg/Library/UefiBootManagerLib/BmMisc.c +++ b/MdeModulePkg/Library/UefiBootManagerLib/BmMisc.c @@ -413,11 +413,11 @@ BmCharToUint ( ) { if ((Char >=3D L'0') && (Char <=3D L'9')) { - return (UINTN) (Char - L'0'); + return (Char - L'0'); } =20 if ((Char >=3D L'A') && (Char <=3D L'F')) { - return (UINTN) (Char - L'A' + 0xA); + return (Char - L'A' + 0xA); } =20 ASSERT (FALSE); diff --git a/MdeModulePkg/Library/UefiHiiLib/HiiLib.c b/MdeModulePkg/Librar= y/UefiHiiLib/HiiLib.c index 8579501..0b5b0a9 100644 --- a/MdeModulePkg/Library/UefiHiiLib/HiiLib.c +++ b/MdeModulePkg/Library/UefiHiiLib/HiiLib.c @@ -1,7 +1,7 @@ /** @file HII Library implementation that uses DXE protocols and services. =20 - Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License which accompanies this distribution. The full text of the license may b= e found at @@ -1853,7 +1853,7 @@ GetBlockDataInfo ( // // Check whether VarBuffer is enough // - if ((UINTN) (Offset + Width) > MaxBufferSize) { + if ((UINT32)Offset + Width > MaxBufferSize) { DataBuffer =3D ReallocatePool ( MaxBufferSize, Offset + Width + HII_LIB_DEFAULT_VARSTORE_SIZE, diff --git a/MdeModulePkg/Library/UefiMemoryAllocationProfileLib/MemoryAllo= cationLib.c b/MdeModulePkg/Library/UefiMemoryAllocationProfileLib/MemoryAll= ocationLib.c index 370827d..cef7fc0 100644 --- a/MdeModulePkg/Library/UefiMemoryAllocationProfileLib/MemoryAllocationL= ib.c +++ b/MdeModulePkg/Library/UefiMemoryAllocationProfileLib/MemoryAllocationL= ib.c @@ -2,7 +2,7 @@ Support routines for memory allocation routines based=20 on boot services for Dxe phase drivers, with memory profile support. =20 - Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials =20 are licensed and made available under the terms and conditions of the BS= D License =20 which accompanies this distribution. The full text of the license may b= e found at =20 @@ -257,7 +257,7 @@ InternalAllocateAlignedPages ( Status =3D gBS->FreePages (Memory, UnalignedPages); ASSERT_EFI_ERROR (Status); } - Memory =3D (EFI_PHYSICAL_ADDRESS) (AlignedMemory + EFI_PAGES_T= O_SIZE (Pages)); + Memory =3D AlignedMemory + EFI_PAGES_TO_SIZE (Pages); UnalignedPages =3D RealPages - Pages - UnalignedPages; if (UnalignedPages > 0) { // diff --git a/MdeModulePkg/Library/VarCheckHiiLib/VarCheckHiiLibNullClass.c = b/MdeModulePkg/Library/VarCheckHiiLib/VarCheckHiiLibNullClass.c index b9ca908..93ff934 100644 --- a/MdeModulePkg/Library/VarCheckHiiLib/VarCheckHiiLibNullClass.c +++ b/MdeModulePkg/Library/VarCheckHiiLib/VarCheckHiiLibNullClass.c @@ -1,7 +1,7 @@ /** @file Var Check Hii handler. =20 -Copyright (c) 2015, Intel Corporation. All rights reserved.
+Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License which accompanies this distribution. The full text of the license may be = found at @@ -94,7 +94,7 @@ VarCheckHiiQuestion ( UINT8 Index; UINT8 MaxContainers; =20 - if ((UINTN) (HiiQuestion->VarOffset + HiiQuestion->StorageWidth) > DataS= ize) { + if (((UINT32) HiiQuestion->VarOffset + HiiQuestion->StorageWidth) > Data= Size) { DEBUG ((EFI_D_INFO, "VarCheckHiiQuestion fail: (VarOffset(0x%04x) + St= orageWidth(0x%02x)) > Size(0x%x)\n", HiiQuestion->VarOffset, HiiQuestion->S= torageWidth, DataSize)); return FALSE; } @@ -155,7 +155,7 @@ VarCheckHiiQuestion ( =20 case EFI_IFR_ORDERED_LIST_OP: MaxContainers =3D ((VAR_CHECK_HII_QUESTION_ORDEREDLIST *) HiiQuestio= n)->MaxContainers; - if ((UINTN) (HiiQuestion->VarOffset + HiiQuestion->StorageWidth * Ma= xContainers) > DataSize) { + if (((UINT32) HiiQuestion->VarOffset + HiiQuestion->StorageWidth * M= axContainers) > DataSize) { DEBUG ((EFI_D_INFO, "VarCheckHiiQuestion fail: (VarOffset(0x%04x) = + StorageWidth(0x%02x) * MaxContainers(0x%02x)) > Size(0x%x)\n", HiiQuestio= n->VarOffset, HiiQuestion->StorageWidth, MaxContainers, DataSize)); return FALSE; } diff --git a/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/ScriptExecut= e.c b/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/ScriptExecute.c index f67fbca..16551ae 100644 --- a/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/ScriptExecute.c +++ b/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/ScriptExecute.c @@ -4,7 +4,7 @@ This driver is dispatched by Dxe core and the driver will reload itself = to ACPI reserved memory in the entry point. The functionality is to interpret and restore the S3= boot script =20 -Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License @@ -325,7 +325,7 @@ ReadyToLockEventNotify ( // Align buffer on section boundary // ImageContext.ImageAddress +=3D ImageContext.SectionAlignment - 1; - ImageContext.ImageAddress &=3D ~((EFI_PHYSICAL_ADDRESS)(ImageContext.Sec= tionAlignment - 1)); + ImageContext.ImageAddress &=3D ~((EFI_PHYSICAL_ADDRESS)ImageContext.Sect= ionAlignment - 1); // // Load the image to our new buffer // diff --git a/MdeModulePkg/Universal/Acpi/S3SaveStateDxe/AcpiS3ContextSave.c= b/MdeModulePkg/Universal/Acpi/S3SaveStateDxe/AcpiS3ContextSave.c index a973d2d..dcfd61c 100644 --- a/MdeModulePkg/Universal/Acpi/S3SaveStateDxe/AcpiS3ContextSave.c +++ b/MdeModulePkg/Universal/Acpi/S3SaveStateDxe/AcpiS3ContextSave.c @@ -1,7 +1,7 @@ /** @file This is the implementation to save ACPI S3 Context. =20 -Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions @@ -401,9 +401,9 @@ S3AllocatePageTablesBuffer ( // We need calculate whole page size then allocate once, because S3 re= store page table does not know each page in Nvs. // if (!Page1GSupport) { - TotalPageTableSize =3D (UINTN)(1 + NumberOfPml4EntriesNeeded + Numbe= rOfPml4EntriesNeeded * NumberOfPdpEntriesNeeded); + TotalPageTableSize =3D 1 + NumberOfPml4EntriesNeeded + NumberOfPml4E= ntriesNeeded * NumberOfPdpEntriesNeeded; } else { - TotalPageTableSize =3D (UINTN)(1 + NumberOfPml4EntriesNeeded); + TotalPageTableSize =3D 1 + NumberOfPml4EntriesNeeded; } =20 TotalPageTableSize +=3D ExtraPageTablePages; diff --git a/MdeModulePkg/Universal/CapsulePei/Common/CapsuleCoalesce.c b/M= deModulePkg/Universal/CapsulePei/Common/CapsuleCoalesce.c index 9e8315e..3e7054c 100644 --- a/MdeModulePkg/Universal/CapsulePei/Common/CapsuleCoalesce.c +++ b/MdeModulePkg/Universal/CapsulePei/Common/CapsuleCoalesce.c @@ -10,7 +10,7 @@ into memory. =20 (C) Copyright 2014 Hewlett-Packard Development Company, L.P.
-Copyright (c) 2011 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2011 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License which accompanies this distribution. The full text of the license may be = found at @@ -1247,7 +1247,7 @@ CapsuleDataCoalesce ( // ASSERT (PrivateDataPtr->Signature =3D=3D EFI_CAPSULE_PEIM_PRIVATE_= DATA_SIGNATURE); ASSERT ((UINTN)DestPtr >=3D (UINTN)CapsuleImageBase); - PrivateDataPtr->CapsuleOffset[CapsuleIndex++] =3D (UINT64)((UINTN)= DestPtr - (UINTN)CapsuleImageBase); + PrivateDataPtr->CapsuleOffset[CapsuleIndex++] =3D (UINTN)DestPtr -= (UINTN)CapsuleImageBase; } =20 // diff --git a/MdeModulePkg/Universal/DisplayEngineDxe/FormDisplay.c b/MdeMod= ulePkg/Universal/DisplayEngineDxe/FormDisplay.c index 0eb7ddd..e1ac5a3 100644 --- a/MdeModulePkg/Universal/DisplayEngineDxe/FormDisplay.c +++ b/MdeModulePkg/Universal/DisplayEngineDxe/FormDisplay.c @@ -1,7 +1,7 @@ /** @file Entry and initialization module for the browser. =20 -Copyright (c) 2007 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2007 - 2017, Intel Corporation. All rights reserved.
Copyright (c) 2014, Hewlett-Packard Development Company, L.P.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License @@ -540,7 +540,7 @@ GetLineByWidth ( // // Need extra glyph info and '\0' info, so +2. // - *OutputString =3D AllocateZeroPool (((UINTN) (StrOffset + 2) * sizeof(CH= AR16))); + *OutputString =3D AllocateZeroPool ((StrOffset + 2) * sizeof(CHAR16)); if (*OutputString =3D=3D NULL) { return 0; } @@ -2972,7 +2972,7 @@ UiDisplayMenu ( gST->ConOut->SetAttribute (gST->ConOut, GetInfoTextColor ()); for (Index =3D 0; Index < HelpHeaderLine; Index++) { ASSERT (HelpHeaderLine =3D=3D 1); - ASSERT (GetStringWidth (HelpHeaderString) / 2 < (UINTN) (gHelpBl= ockWidth - 1)); + ASSERT (GetStringWidth (HelpHeaderString) / 2 < ((UINT32) gHelpB= lockWidth - 1)); PrintStringAtWithWidth ( gStatementDimensions.RightColumn - gHelpBlockWidth, Index + TopRow, @@ -3053,7 +3053,7 @@ UiDisplayMenu ( gST->ConOut->SetAttribute (gST->ConOut, GetInfoTextColor ()); for (Index =3D 0; Index < HelpBottomLine; Index++) { ASSERT (HelpBottomLine =3D=3D 1); - ASSERT (GetStringWidth (HelpBottomString) / 2 < (UINTN) (gHelpBl= ockWidth - 1));=20 + ASSERT (GetStringWidth (HelpBottomString) / 2 < ((UINT32) gHelpB= lockWidth - 1)); PrintStringAtWithWidth ( gStatementDimensions.RightColumn - gHelpBlockWidth, BottomRow + Index - HelpBottomLine + 1, diff --git a/MdeModulePkg/Universal/EbcDxe/EbcExecute.c b/MdeModulePkg/Univ= ersal/EbcDxe/EbcExecute.c index e5d290a..2dfed8e 100644 --- a/MdeModulePkg/Universal/EbcDxe/EbcExecute.c +++ b/MdeModulePkg/Universal/EbcDxe/EbcExecute.c @@ -1,7 +1,7 @@ /** @file Contains code that implements the virtual machine. =20 -Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License which accompanies this distribution. The full text of the license may be = found at @@ -2867,7 +2867,7 @@ ExecutePOPn ( if (OPERAND1_INDIRECT (Operands)) { VmWriteMemN (VmPtr, (UINTN) (VmPtr->Gpr[OPERAND1_REGNUM (Operands)] + = Index16), DataN); } else { - VmPtr->Gpr[OPERAND1_REGNUM (Operands)] =3D (INT64) (UINT64) ((UINTN) D= ataN + Index16); + VmPtr->Gpr[OPERAND1_REGNUM (Operands)] =3D (INT64) (UINT64) (UINTN) (D= ataN + Index16); } =20 return EFI_SUCCESS; @@ -3592,7 +3592,7 @@ ExecuteSUB ( if ((*VmPtr->Ip & DATAMANIP_M_64) !=3D 0) { return (UINT64) ((INT64) ((INT64) Op1 - (INT64) Op2)); } else { - return (UINT64) ((INT64) ((INT32) Op1 - (INT32) Op2)); + return (UINT64) ((INT64) ((INT32) ((INT32) Op1 - (INT32) Op2))); } } =20 @@ -3620,7 +3620,7 @@ ExecuteMUL ( if ((*VmPtr->Ip & DATAMANIP_M_64) !=3D 0) { return MultS64x64 ((INT64)Op1, (INT64)Op2); } else { - return (UINT64) ((INT64) ((INT32) Op1 * (INT32) Op2)); + return (UINT64) ((INT64) ((INT32) ((INT32) Op1 * (INT32) Op2))); } } =20 @@ -3648,7 +3648,7 @@ ExecuteMULU ( if ((*VmPtr->Ip & DATAMANIP_M_64) !=3D 0) { return MultU64x64 (Op1, Op2); } else { - return (UINT64) ((UINT32) Op1 * (UINT32) Op2); + return (UINT64) ((UINT32) ((UINT32) Op1 * (UINT32) Op2)); } } =20 diff --git a/MdeModulePkg/Universal/FaultTolerantWriteDxe/UpdateWorkingBloc= k.c b/MdeModulePkg/Universal/FaultTolerantWriteDxe/UpdateWorkingBlock.c index d46a37f..b4327b5 100644 --- a/MdeModulePkg/Universal/FaultTolerantWriteDxe/UpdateWorkingBlock.c +++ b/MdeModulePkg/Universal/FaultTolerantWriteDxe/UpdateWorkingBlock.c @@ -2,7 +2,7 @@ =20 Internal functions to operate Working Block Space. =20 -Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials =20 are licensed and made available under the terms and conditions of the BSD = License =20 which accompanies this distribution. The full text of the license may be = found at =20 @@ -55,7 +55,7 @@ InitializeLocalWorkSpaceHeader ( &gEdkiiWorkingBlockSignatureGuid, sizeof (EFI_GUID) ); - mWorkingBlockHeader.WriteQueueSize =3D (UINT64) (PcdGet32 (PcdFlashNvSto= rageFtwWorkingSize) - sizeof (EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER)); + mWorkingBlockHeader.WriteQueueSize =3D PcdGet32 (PcdFlashNvStorageFtwWor= kingSize) - sizeof (EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER); =20 // // Crc is calculated with all the fields except Crc and STATE, so leave = them as FTW_ERASED_BYTE. diff --git a/MdeModulePkg/Universal/HiiDatabaseDxe/Font.c b/MdeModulePkg/Un= iversal/HiiDatabaseDxe/Font.c index 9bef064..b85cf88 100644 --- a/MdeModulePkg/Universal/HiiDatabaseDxe/Font.c +++ b/MdeModulePkg/Universal/HiiDatabaseDxe/Font.c @@ -2,7 +2,7 @@ Implementation for EFI_HII_FONT_PROTOCOL. =20 =20 -Copyright (c) 2007 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2007 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License which accompanies this distribution. The full text of the license may be = found at @@ -411,7 +411,7 @@ GlyphToBlt ( // The glyph's upper left hand corner pixel is the most significant bit = of the // first bitmap byte. // - for (Ypos =3D 0; Ypos < Cell->Height && ((UINTN) (Ypos + YposOffset) < R= owHeight); Ypos++) { + for (Ypos =3D 0; Ypos < Cell->Height && (((UINT32) Ypos + YposOffset) < = RowHeight); Ypos++) { OffsetY =3D BITMAP_LEN_1_BIT (Cell->Width, Ypos); =20 // @@ -419,7 +419,7 @@ GlyphToBlt ( // for (Xpos =3D 0; Xpos < Cell->Width / 8; Xpos++) { Data =3D *(GlyphBuffer + OffsetY + Xpos); - for (Index =3D 0; Index < 8 && ((UINTN) (Xpos * 8 + Index + Cell->Of= fsetX) < RowWidth); Index++) { + for (Index =3D 0; Index < 8 && (((UINT32) Xpos * 8 + Index + Cell->O= ffsetX) < RowWidth); Index++) { if ((Data & (1 << (8 - Index - 1))) !=3D 0) { BltBuffer[Ypos * ImageWidth + Xpos * 8 + Index] =3D Foreground; } else { @@ -435,7 +435,7 @@ GlyphToBlt ( // There are some padding bits in this byte. Ignore them. // Data =3D *(GlyphBuffer + OffsetY + Xpos); - for (Index =3D 0; Index < Cell->Width % 8 && ((UINTN) (Xpos * 8 + In= dex + Cell->OffsetX) < RowWidth); Index++) { + for (Index =3D 0; Index < Cell->Width % 8 && (((UINT32) Xpos * 8 + I= ndex + Cell->OffsetX) < RowWidth); Index++) { if ((Data & (1 << (8 - Index - 1))) !=3D 0) { BltBuffer[Ypos * ImageWidth + Xpos * 8 + Index] =3D Foreground; } else { @@ -1927,7 +1927,7 @@ HiiStringToImage ( // If this character is the last character of a row, we need not // draw its (AdvanceX - Width - OffsetX) for next character. // - LineWidth -=3D (UINTN) (Cell[Index].AdvanceX - Cell[Index].Width - Cel= l[Index].OffsetX); + LineWidth -=3D (Cell[Index].AdvanceX - Cell[Index].Width - Cell[Index]= .OffsetX); =20 // // Clip the right-most character if cannot fit when EFI_HII_OUT_FLAG_C= LEAN_X is set. @@ -1950,8 +1950,8 @@ HiiStringToImage ( // // Don't draw the last char on this row. And, don't draw the secon= d last char (AdvanceX - Width - OffsetX). // - LineWidth -=3D (UINTN) (Cell[Index].Width + Cell[Index].OffsetX); - LineWidth -=3D (UINTN) (Cell[Index - 1].AdvanceX - Cell[Index - 1]= .Width - Cell[Index - 1].OffsetX); + LineWidth -=3D (Cell[Index].Width + Cell[Index].OffsetX); + LineWidth -=3D (Cell[Index - 1].AdvanceX - Cell[Index - 1].Width -= Cell[Index - 1].OffsetX); RowInfo[RowIndex].EndIndex =3D Index - 1; RowInfo[RowIndex].LineWidth =3D LineWidth; RowInfo[RowIndex].LineHeight =3D LineHeight; @@ -2008,7 +2008,7 @@ HiiStringToImage ( if (Index1 =3D=3D RowInfo[RowIndex].StartIndex) { LineWidth =3D 0; } else { - LineWidth -=3D (UINTN) (Cell[Index1 - 1].AdvanceX - Cell[Index= 1 - 1].Width - Cell[Index1 - 1].OffsetX); + LineWidth -=3D (Cell[Index1 - 1].AdvanceX - Cell[Index1 - 1].W= idth - Cell[Index1 - 1].OffsetX); } RowInfo[RowIndex].LineWidth =3D LineWidth; } @@ -2025,8 +2025,8 @@ HiiStringToImage ( // // Don't draw the last char on this row. And, don't draw the s= econd last char (AdvanceX - Width - OffsetX). // - LineWidth -=3D (UINTN) (Cell[Index1].Width + Cell[Index1].Offs= etX); - LineWidth -=3D (UINTN) (Cell[Index1 - 1].AdvanceX - Cell[Index= 1 - 1].Width - Cell[Index1 - 1].OffsetX); + LineWidth -=3D (Cell[Index1].Width + Cell[Index1].OffsetX); + LineWidth -=3D (Cell[Index1 - 1].AdvanceX - Cell[Index1 - 1].W= idth - Cell[Index1 - 1].OffsetX); RowInfo[RowIndex].EndIndex =3D Index1 - 1; RowInfo[RowIndex].LineWidth =3D LineWidth; } else { diff --git a/MdeModulePkg/Universal/Network/UefiPxeBcDxe/PxeBcImpl.c b/MdeM= odulePkg/Universal/Network/UefiPxeBcDxe/PxeBcImpl.c index 639da48..cd00f5c 100644 --- a/MdeModulePkg/Universal/Network/UefiPxeBcDxe/PxeBcImpl.c +++ b/MdeModulePkg/Universal/Network/UefiPxeBcDxe/PxeBcImpl.c @@ -1,7 +1,7 @@ /** @file Interface routines for PxeBc. =20 -Copyright (c) 2007 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2007 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License which accompanies this distribution. The full text of the license may be = found at @@ -353,8 +353,8 @@ EfiPxeBcStart ( // // Configure block size for TFTP as a default value to handle all link l= ayers. //=20 - Private->BlockSize =3D (UINTN) (MIN (Private->Ip4MaxPacketSize, PXEBC_= DEFAULT_PACKET_SIZE) -=20 - PXEBC_DEFAULT_UDP_OVERHEAD_SIZE - PXEBC_DEFAULT= _TFTP_OVERHEAD_SIZE); + Private->BlockSize =3D MIN (Private->Ip4MaxPacketSize, PXEBC_DEFAULT_P= ACKET_SIZE) - + PXEBC_DEFAULT_UDP_OVERHEAD_SIZE - PXEBC_DEFAULT= _TFTP_OVERHEAD_SIZE; // // If PcdTftpBlockSize is set to non-zero, override the default value. // diff --git a/MdeModulePkg/Universal/PCD/Dxe/Service.c b/MdeModulePkg/Univer= sal/PCD/Dxe/Service.c index bf77130..efe7248 100644 --- a/MdeModulePkg/Universal/PCD/Dxe/Service.c +++ b/MdeModulePkg/Universal/PCD/Dxe/Service.c @@ -2,7 +2,7 @@ Help functions used by PCD DXE driver. =20 Copyright (c) 2014, Hewlett-Packard Development Company, L.P.
-Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
(C) Copyright 2016 Hewlett Packard Enterprise Development LP
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License @@ -452,7 +452,7 @@ GetWorker ( switch (LocalTokenNumber & PCD_TYPE_ALL_SET) { case PCD_TYPE_VPD: VpdHead =3D (VPD_HEAD *) ((UINT8 *) PcdDb + Offset); - RetPtr =3D (VOID *) (UINTN) (PcdGet32 (PcdVpdBaseAddress) + VpdHead-= >Offset); + RetPtr =3D (VOID *) ((UINTN) PcdGet32 (PcdVpdBaseAddress) + VpdHead-= >Offset); =20 break; =20 diff --git a/MdeModulePkg/Universal/PCD/Pei/Service.c b/MdeModulePkg/Univer= sal/PCD/Pei/Service.c index 66ca892..5e1cb72 100644 --- a/MdeModulePkg/Universal/PCD/Pei/Service.c +++ b/MdeModulePkg/Universal/PCD/Pei/Service.c @@ -2,7 +2,7 @@ The driver internal functions are implmented here. They build Pei PCD database, and provide access service to PCD database. =20 -Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License which accompanies this distribution. The full text of the license may be = found at @@ -985,7 +985,7 @@ GetWorker ( { VPD_HEAD *VpdHead; VpdHead =3D (VPD_HEAD *) ((UINT8 *)PeiPcdDb + Offset); - return (VOID *) (UINTN) (PcdGet32 (PcdVpdBaseAddress) + VpdHead->Off= set); + return (VOID *) ((UINTN) PcdGet32 (PcdVpdBaseAddress) + VpdHead->Off= set); } =20 case PCD_TYPE_HII|PCD_TYPE_STRING: diff --git a/MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.c b/MdeModulePkg/Un= iversal/SmbiosDxe/SmbiosDxe.c index ea762d5..4e757e1 100644 --- a/MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.c +++ b/MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.c @@ -2,7 +2,7 @@ This code produces the Smbios protocol. It also responsible for construc= ting=20 SMBIOS table into system table. =20 -Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials =20 are licensed and made available under the terms and conditions of the BSD = License =20 which accompanies this distribution. The full text of the license may be = found at =20 @@ -1138,7 +1138,7 @@ SmbiosCreateTable ( EntryPointStructure->MaxStructureSize =3D (UINT16) sizeof (EndStructur= e); } =20 - if ((UINTN) EFI_SIZE_TO_PAGES (EntryPointStructure->TableLength) > mPreA= llocatedPages) { + if (EFI_SIZE_TO_PAGES ((UINT32) EntryPointStructure->TableLength) > mPre= AllocatedPages) { // // If new SMBIOS table size exceeds the previous allocated page,=20 // it is time to re-allocate memory (below 4GB). @@ -1307,7 +1307,7 @@ SmbiosCreate64BitTable ( EndStructure.Tailing[1] =3D 0; Smbios30EntryPointStructure->TableMaximumSize =3D (UINT32) (Smbios30Entr= yPointStructure->TableMaximumSize + sizeof (EndStructure)); =20 - if ((UINTN) EFI_SIZE_TO_PAGES (Smbios30EntryPointStructure->TableMaximum= Size) > mPre64BitAllocatedPages) { + if (EFI_SIZE_TO_PAGES (Smbios30EntryPointStructure->TableMaximumSize) > = mPre64BitAllocatedPages) { // // If new SMBIOS table size exceeds the previous allocated page,=20 // it is time to re-allocate memory at anywhere. diff --git a/MdeModulePkg/Universal/Variable/RuntimeDxe/Variable.c b/MdeMod= ulePkg/Universal/Variable/RuntimeDxe/Variable.c index b0c7434..0a325de 100644 --- a/MdeModulePkg/Universal/Variable/RuntimeDxe/Variable.c +++ b/MdeModulePkg/Universal/Variable/RuntimeDxe/Variable.c @@ -3754,8 +3754,8 @@ InitNonVolatileVariableStore ( return EFI_VOLUME_CORRUPTED; } =20 - VariableStoreBase =3D (EFI_PHYSICAL_ADDRESS) ((UINTN) FvHeader + FvHeade= r->HeaderLength); - VariableStoreLength =3D (UINT64) (NvStorageSize - FvHeader->HeaderLength= ); + VariableStoreBase =3D (UINTN) FvHeader + FvHeader->HeaderLength; + VariableStoreLength =3D NvStorageSize - FvHeader->HeaderLength; =20 mNvFvHeaderCache =3D FvHeader; mVariableModuleGlobal->VariableGlobal.NonVolatileVariableBase =3D Variab= leStoreBase; @@ -4099,7 +4099,7 @@ VariableCommonInitialize ( GuidHob =3D GetFirstGuidHob (VariableGuid); if (GuidHob !=3D NULL) { VariableStoreHeader =3D GET_GUID_HOB_DATA (GuidHob); - VariableStoreLength =3D (UINT64) (GuidHob->Header.HobLength - sizeof (= EFI_HOB_GUID_TYPE)); + VariableStoreLength =3D GuidHob->Header.HobLength - sizeof (EFI_HOB_GU= ID_TYPE); if (GetVariableStoreStatus (VariableStoreHeader) =3D=3D EfiValid) { mVariableModuleGlobal->VariableGlobal.HobVariableBase =3D (EFI_PHYSI= CAL_ADDRESS) (UINTN) AllocateRuntimeCopyPool ((UINTN) VariableStoreLength, = (VOID *) VariableStoreHeader); if (mVariableModuleGlobal->VariableGlobal.HobVariableBase =3D=3D 0) { --=20 1.9.5.msysgit.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat Nov 2 14:41:02 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zoho.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1487999579418993.2213933849353; Fri, 24 Feb 2017 21:12:59 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id B856B82158; Fri, 24 Feb 2017 21:12:55 -0800 (PST) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 5BD4282151 for ; Fri, 24 Feb 2017 21:12:54 -0800 (PST) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Feb 2017 21:12:54 -0800 Received: from shwdeopenpsi014.ccr.corp.intel.com ([10.239.9.13]) by orsmga002.jf.intel.com with ESMTP; 24 Feb 2017 21:12:53 -0800 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.35,202,1484035200"; d="scan'208";a="52624013" From: Hao Wu To: edk2-devel@lists.01.org Date: Sat, 25 Feb 2017 13:12:26 +0800 Message-Id: <1487999555-9764-4-git-send-email-hao.a.wu@intel.com> X-Mailer: git-send-email 1.9.5.msysgit.0 In-Reply-To: <1487999555-9764-1-git-send-email-hao.a.wu@intel.com> References: <1487999555-9764-1-git-send-email-hao.a.wu@intel.com> Subject: [edk2] [PATCH v3 03/12] FatPkg: Refine casting expression result to bigger size X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Hao Wu , Ruiyu Ni MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" There are cases that the operands of an expression are all with rank less than UINT64/INT64 and the result of the expression is explicitly cast to UINT64/INT64 to fit the target size. An example will be: UINT32 a,b; // a and b can be any unsigned int type with rank less than UINT64, like // UINT8, UINT16, etc. UINT64 c; c =3D (UINT64) (a + b); Some static code checkers may warn that the expression result might overflow within the rank of "int" (integer promotions) and the result is then cast to a bigger size. The commit refines codes by the following rules: 1). When the expression is possible to overflow the range of unsigned int/ int: c =3D (UINT64)a + b; 2). When the expression will not overflow within the rank of "int", remove the explicit type casts: c =3D a + b; 3). When the expression will be cast to pointer of possible greater size: UINT32 a,b; VOID *c; c =3D (VOID *)(UINTN)(a + b); --> c =3D (VOID *)((UINTN)a + b); 4). When one side of a comparison expression contains only operands with rank less than UINT32: UINT8 a; UINT16 b; UINTN c; if ((UINTN)(a + b) > c) {...} --> if (((UINT32)a + b) > c) {...} For rule 4), if we remove the 'UINTN' type cast like: if (a + b > c) {...} The VS compiler will complain with warning C4018 (signed/unsigned mismatch, level 3 warning) due to promoting 'a + b' to type 'int'. Cc: Ruiyu Ni Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu Reviewed-by: Ruiyu Ni --- FatPkg/EnhancedFatDxe/ReadWrite.c | 4 ++-- FatPkg/FatPei/FatLiteAccess.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/FatPkg/EnhancedFatDxe/ReadWrite.c b/FatPkg/EnhancedFatDxe/Read= Write.c index a6e0ec4..ad3c260 100644 --- a/FatPkg/EnhancedFatDxe/ReadWrite.c +++ b/FatPkg/EnhancedFatDxe/ReadWrite.c @@ -1,7 +1,7 @@ /** @file Functions that perform file read/write. =20 -Copyright (c) 2005 - 2015, Intel Corporation. All rights reserved.
+Copyright (c) 2005 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at @@ -173,7 +173,7 @@ Done: // Update IFile->Position, if everything is all right // CurrentPos =3D ODir->CurrentPos; - IFile->Position =3D (UINT64) (CurrentPos * sizeof (FAT_DIRECTORY_ENTRY= )); + IFile->Position =3D CurrentPos * sizeof (FAT_DIRECTORY_ENTRY); } =20 return Status; diff --git a/FatPkg/FatPei/FatLiteAccess.c b/FatPkg/FatPei/FatLiteAccess.c index 1106345..a92c5bf 100644 --- a/FatPkg/FatPei/FatLiteAccess.c +++ b/FatPkg/FatPei/FatLiteAccess.c @@ -1,7 +1,7 @@ /** @file FAT file system access routines for FAT recovery PEIM =20 -Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this @@ -393,7 +393,7 @@ FatReadFile ( } else { =20 if ((File->Attributes & FAT_ATTR_DIRECTORY) =3D=3D 0) { - Size =3D Size < (File->FileSize - File->CurrentPos) ? Size : (UINTN)= (File->FileSize - File->CurrentPos); + Size =3D Size < (File->FileSize - File->CurrentPos) ? Size : (File->= FileSize - File->CurrentPos); } // // This is a normal cluster based file --=20 1.9.5.msysgit.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat Nov 2 14:41:02 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zoho.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1487999582505827.3384441349517; Fri, 24 Feb 2017 21:13:02 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id EA2DC8219D; Fri, 24 Feb 2017 21:12:58 -0800 (PST) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 7140B8213A for ; Fri, 24 Feb 2017 21:12:55 -0800 (PST) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Feb 2017 21:12:55 -0800 Received: from shwdeopenpsi014.ccr.corp.intel.com ([10.239.9.13]) by orsmga002.jf.intel.com with ESMTP; 24 Feb 2017 21:12:54 -0800 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.35,202,1484035200"; d="scan'208";a="52624021" From: Hao Wu To: edk2-devel@lists.01.org Date: Sat, 25 Feb 2017 13:12:27 +0800 Message-Id: <1487999555-9764-5-git-send-email-hao.a.wu@intel.com> X-Mailer: git-send-email 1.9.5.msysgit.0 In-Reply-To: <1487999555-9764-1-git-send-email-hao.a.wu@intel.com> References: <1487999555-9764-1-git-send-email-hao.a.wu@intel.com> Subject: [edk2] [PATCH v3 04/12] IntelFrameworkModulePkg: Refine casting expression result to bigger size X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Hao Wu , Jeff Fan MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" There are cases that the operands of an expression are all with rank less than UINT64/INT64 and the result of the expression is explicitly cast to UINT64/INT64 to fit the target size. An example will be: UINT32 a,b; // a and b can be any unsigned int type with rank less than UINT64, like // UINT8, UINT16, etc. UINT64 c; c =3D (UINT64) (a + b); Some static code checkers may warn that the expression result might overflow within the rank of "int" (integer promotions) and the result is then cast to a bigger size. The commit refines codes by the following rules: 1). When the expression is possible to overflow the range of unsigned int/ int: c =3D (UINT64)a + b; 2). When the expression will not overflow within the rank of "int", remove the explicit type casts: c =3D a + b; 3). When the expression will be cast to pointer of possible greater size: UINT32 a,b; VOID *c; c =3D (VOID *)(UINTN)(a + b); --> c =3D (VOID *)((UINTN)a + b); 4). When one side of a comparison expression contains only operands with rank less than UINT32: UINT8 a; UINT16 b; UINTN c; if ((UINTN)(a + b) > c) {...} --> if (((UINT32)a + b) > c) {...} For rule 4), if we remove the 'UINTN' type cast like: if (a + b > c) {...} The VS compiler will complain with warning C4018 (signed/unsigned mismatch, level 3 warning) due to promoting 'a + b' to type 'int'. Cc: Jeff Fan Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu Reviewed-by: Jeff Fan --- IntelFrameworkModulePkg/Csm/BiosThunk/KeyboardDxe/BiosKeyboard.c | 4 ++-- IntelFrameworkModulePkg/Csm/BiosThunk/Snp16Dxe/BiosSnp16.c | 4 ++-- IntelFrameworkModulePkg/Csm/BiosThunk/Snp16Dxe/Misc.c | 14 ++++= +++------- IntelFrameworkModulePkg/Csm/BiosThunk/VideoDxe/BiosVideo.c | 4 ++-- IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBios.c | 6 +++-= -- IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBootSupport.c | 4 ++-- IntelFrameworkModulePkg/Library/GenericBdsLib/BdsBoot.c | 2 +- IntelFrameworkModulePkg/Library/GenericBdsLib/BdsMisc.c | 4 ++-- IntelFrameworkModulePkg/Library/LegacyBootManagerLib/LegacyBm.c | 2 +- IntelFrameworkModulePkg/Universal/BdsDxe/FrontPage.c | 4 ++-- IntelFrameworkModulePkg/Universal/CpuIoDxe/CpuIo.c | 4 ++-- 11 files changed, 26 insertions(+), 26 deletions(-) diff --git a/IntelFrameworkModulePkg/Csm/BiosThunk/KeyboardDxe/BiosKeyboard= .c b/IntelFrameworkModulePkg/Csm/BiosThunk/KeyboardDxe/BiosKeyboard.c index a597d99..742d009 100644 --- a/IntelFrameworkModulePkg/Csm/BiosThunk/KeyboardDxe/BiosKeyboard.c +++ b/IntelFrameworkModulePkg/Csm/BiosThunk/KeyboardDxe/BiosKeyboard.c @@ -1,7 +1,7 @@ /** @file ConsoleOut Routines that speak VGA. =20 -Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions @@ -418,7 +418,7 @@ BiosKeyboardDriverBindingStart ( // Check bit 6 of Feature Byte 2. // If it is set, then Int 16 Func 09 is supported // - if (*(UINT8 *)(UINTN) ((Regs.X.ES << 4) + Regs.X.BX + 0x06) & 0x40) { + if (*(UINT8 *) (((UINTN) Regs.X.ES << 4) + Regs.X.BX + 0x06) & 0x40) { // // Get Keyboard Functionality // diff --git a/IntelFrameworkModulePkg/Csm/BiosThunk/Snp16Dxe/BiosSnp16.c b/I= ntelFrameworkModulePkg/Csm/BiosThunk/Snp16Dxe/BiosSnp16.c index a2a7797..b586a91 100644 --- a/IntelFrameworkModulePkg/Csm/BiosThunk/Snp16Dxe/BiosSnp16.c +++ b/IntelFrameworkModulePkg/Csm/BiosThunk/Snp16Dxe/BiosSnp16.c @@ -1,6 +1,6 @@ /** @file =20 -Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved.
+Copyright (c) 1999 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions @@ -1858,7 +1858,7 @@ Undi16SimpleNetworkIsr ( =20 CopyMem ( Frame, - (VOID *)(UINTN) ((SimpleNetworkDevice->Isr.FrameSegSel << 4) + Sim= pleNetworkDevice->Isr.FrameOffset), + (VOID *) (((UINTN) SimpleNetworkDevice->Isr.FrameSegSel << 4) + Si= mpleNetworkDevice->Isr.FrameOffset), SimpleNetworkDevice->Isr.BufferLength ); Frame =3D Frame + SimpleNetworkDevice->Isr.BufferLength; diff --git a/IntelFrameworkModulePkg/Csm/BiosThunk/Snp16Dxe/Misc.c b/IntelF= rameworkModulePkg/Csm/BiosThunk/Snp16Dxe/Misc.c index 4750b2f..a1dc867 100644 --- a/IntelFrameworkModulePkg/Csm/BiosThunk/Snp16Dxe/Misc.c +++ b/IntelFrameworkModulePkg/Csm/BiosThunk/Snp16Dxe/Misc.c @@ -1,7 +1,7 @@ /** @file Helper Routines that use a PXE-enabled NIC option ROM. =20 -Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved.
+Copyright (c) 1999 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions @@ -49,7 +49,7 @@ CacheVectorAddress ( { UINT32 *Address; =20 - Address =3D (UINT32 *)(UINTN) (IVT_BASE + Vecto= rNumber * 4); + Address =3D (UINT32 *) ((UINTN) IVT_BASE + Vect= orNumber * 4); CachedVectorAddress[VectorNumber] =3D *Address; return EFI_SUCCESS; } @@ -68,7 +68,7 @@ RestoreCachedVectorAddress ( { UINT32 *Address; =20 - Address =3D (UINT32 *)(UINTN) (IVT_BASE + VectorNumber * 4); + Address =3D (UINT32 *) ((UINTN) IVT_BASE + VectorNumber * 4); *Address =3D CachedVectorAddress[VectorNumber]; return EFI_SUCCESS; } @@ -469,7 +469,7 @@ LaunchBaseCode ( =20 RomIdTableAddress =3D (UNDI_ROMID_T *) (RomAddress + OPTION_ROM_PTR->Pxe= RomIdOffset); =20 - if ((UINTN) (OPTION_ROM_PTR->PxeRomIdOffset + RomIdTableAddress->StructL= ength) > RomLength) { + if (((UINT32)OPTION_ROM_PTR->PxeRomIdOffset + RomIdTableAddress->StructL= ength) > RomLength) { DEBUG ((DEBUG_ERROR, "ROM ID Offset Error\n\r")); return EFI_NOT_FOUND; } @@ -754,10 +754,10 @@ LaunchBaseCode ( Print_Undi_Loader_Table (UndiLoaderTable); =20 DEBUG ((DEBUG_NET, "Display the PXENV+ and !PXE tables exported by NIC\n= \r")); - Print_PXENV_Table ((VOID *)(UINTN)((UndiLoaderTable->PXENVptr.Segment <<= 4) | UndiLoaderTable->PXENVptr.Offset)); - Print_PXE_Table ((VOID *)(UINTN)((UndiLoaderTable->PXEptr.Segment << 4) = + UndiLoaderTable->PXEptr.Offset)); + Print_PXENV_Table ((VOID *)(((UINTN)UndiLoaderTable->PXENVptr.Segment <<= 4) | UndiLoaderTable->PXENVptr.Offset)); + Print_PXE_Table ((VOID *)(((UINTN)UndiLoaderTable->PXEptr.Segment << 4) = + UndiLoaderTable->PXEptr.Offset)); =20 - Pxe =3D (PXE_T *)(UINTN)((UndiLoaderTable->PXEptr.Segment << 4) + UndiLo= aderTable->PXEptr.Offset); + Pxe =3D (PXE_T *)(((UINTN)UndiLoaderTable->PXEptr.Segment << 4) + UndiLo= aderTable->PXEptr.Offset); SimpleNetworkDevice->Nii.Id =3D (UINT64)(UINTN) Pxe; =20 gBS->FreePool (Buffer); diff --git a/IntelFrameworkModulePkg/Csm/BiosThunk/VideoDxe/BiosVideo.c b/I= ntelFrameworkModulePkg/Csm/BiosThunk/VideoDxe/BiosVideo.c index f1c8b29..08672cf 100644 --- a/IntelFrameworkModulePkg/Csm/BiosThunk/VideoDxe/BiosVideo.c +++ b/IntelFrameworkModulePkg/Csm/BiosThunk/VideoDxe/BiosVideo.c @@ -1,7 +1,7 @@ /** @file ConsoleOut Routines that speak VGA. =20 -Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.
+Copyright (c) 2007 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions @@ -1714,7 +1714,7 @@ BiosVideoCheckForVbe ( // // Make sure the FrameBufferSize does not exceed the max available fra= me buffer size reported by VEB. // - ASSERT (CurrentModeData->FrameBufferSize <=3D (UINTN)(BiosVideoPrivate= ->VbeInformationBlock->TotalMemory * 64 * 1024)); + ASSERT (CurrentModeData->FrameBufferSize <=3D ((UINT32)BiosVideoPrivat= e->VbeInformationBlock->TotalMemory * 64 * 1024)); =20 BiosVideoPrivate->ModeData =3D ModeBuffer; } diff --git a/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBios.c b/Intel= FrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBios.c index dd2e2b9..3ead2d9 100644 --- a/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBios.c +++ b/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBios.c @@ -1,6 +1,6 @@ /** @file =20 -Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions @@ -144,7 +144,7 @@ LegacyBiosGetLegacyRegion ( ); =20 if (Regs.X.AX =3D=3D 0) { - *LegacyMemoryAddress =3D (VOID *) (UINTN) ((Regs.X.DS << 4) + Regs.X.= BX); + *LegacyMemoryAddress =3D (VOID *) (((UINTN) Regs.X.DS << 4) + Regs.X.= BX); Status =3D EFI_SUCCESS; } else { Status =3D EFI_OUT_OF_RESOURCES; @@ -728,7 +728,7 @@ InstallSmbiosEventCallback ( } =20 if ((mStructureTableAddress !=3D 0) &&=20 - (mStructureTablePages < (UINTN) EFI_SIZE_TO_PAGES (EntryPointStructu= re->TableLength))) { + (mStructureTablePages < EFI_SIZE_TO_PAGES ((UINT32)EntryPointStructu= re->TableLength))) { // // If original buffer is not enough for the new SMBIOS table, free ori= ginal buffer and re-allocate // diff --git a/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBootSupport.c = b/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBootSupport.c index 52bcae2..1e098b3 100644 --- a/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBootSupport.c +++ b/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBootSupport.c @@ -1,6 +1,6 @@ /** @file =20 -Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions @@ -91,7 +91,7 @@ PrintBbsTable ( // // Print DescString // - String =3D (CHAR8 *)(UINTN)((BbsTable[Index].DescStringSegment << 4) += BbsTable[Index].DescStringOffset); + String =3D (CHAR8 *)(((UINTN)BbsTable[Index].DescStringSegment << 4) += BbsTable[Index].DescStringOffset); if (String !=3D NULL) { DEBUG ((EFI_D_INFO," (")); for (SubIndex =3D 0; String[SubIndex] !=3D 0; SubIndex++) { diff --git a/IntelFrameworkModulePkg/Library/GenericBdsLib/BdsBoot.c b/Inte= lFrameworkModulePkg/Library/GenericBdsLib/BdsBoot.c index 628424d..d1da635 100644 --- a/IntelFrameworkModulePkg/Library/GenericBdsLib/BdsBoot.c +++ b/IntelFrameworkModulePkg/Library/GenericBdsLib/BdsBoot.c @@ -227,7 +227,7 @@ BdsBuildLegacyDevNameString ( // // If current BBS entry has its description then use it. // - StringDesc =3D (UINT8 *) (UINTN) ((CurBBSEntry->DescStringSegment << 4) = + CurBBSEntry->DescStringOffset); + StringDesc =3D (UINT8 *) (((UINTN) CurBBSEntry->DescStringSegment << 4) = + CurBBSEntry->DescStringOffset); if (NULL !=3D StringDesc) { // // Only get fisrt 32 characters, this is suggested by BBS spec diff --git a/IntelFrameworkModulePkg/Library/GenericBdsLib/BdsMisc.c b/Inte= lFrameworkModulePkg/Library/GenericBdsLib/BdsMisc.c index 2ba511a..48938b0 100644 --- a/IntelFrameworkModulePkg/Library/GenericBdsLib/BdsMisc.c +++ b/IntelFrameworkModulePkg/Library/GenericBdsLib/BdsMisc.c @@ -569,11 +569,11 @@ CharToUint ( ) { if ((Char >=3D L'0') && (Char <=3D L'9')) { - return (UINTN) (Char - L'0'); + return (Char - L'0'); } =20 if ((Char >=3D L'A') && (Char <=3D L'F')) { - return (UINTN) (Char - L'A' + 0xA); + return (Char - L'A' + 0xA); } =20 ASSERT (FALSE); diff --git a/IntelFrameworkModulePkg/Library/LegacyBootManagerLib/LegacyBm.= c b/IntelFrameworkModulePkg/Library/LegacyBootManagerLib/LegacyBm.c index 080a436..76902ec 100644 --- a/IntelFrameworkModulePkg/Library/LegacyBootManagerLib/LegacyBm.c +++ b/IntelFrameworkModulePkg/Library/LegacyBootManagerLib/LegacyBm.c @@ -176,7 +176,7 @@ LegacyBmBuildLegacyDevNameString ( // // If current BBS entry has its description then use it. // - StringDesc =3D (CHAR8 *) (UINTN) ((CurBBSEntry->DescStringSegment << 4) = + CurBBSEntry->DescStringOffset); + StringDesc =3D (CHAR8 *) (((UINTN) CurBBSEntry->DescStringSegment << 4) = + CurBBSEntry->DescStringOffset); if (NULL !=3D StringDesc) { // // Only get fisrt 32 characters, this is suggested by BBS spec diff --git a/IntelFrameworkModulePkg/Universal/BdsDxe/FrontPage.c b/IntelFr= ameworkModulePkg/Universal/BdsDxe/FrontPage.c index c771974..3bae0be 100644 --- a/IntelFrameworkModulePkg/Universal/BdsDxe/FrontPage.c +++ b/IntelFrameworkModulePkg/Universal/BdsDxe/FrontPage.c @@ -1,7 +1,7 @@ /** @file FrontPage routines to handle the callbacks and browser calls =20 -Copyright (c) 2004 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2004 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License which accompanies this distribution. The full text of the license may be = found at @@ -620,7 +620,7 @@ ConvertProcessorToString ( =20 if (Base10Exponent >=3D 6) { FreqMhz =3D ProcessorFrequency; - for (Index =3D 0; Index < (UINTN) (Base10Exponent - 6); Index++) { + for (Index =3D 0; Index < ((UINT32)Base10Exponent - 6); Index++) { FreqMhz *=3D 10; } } else { diff --git a/IntelFrameworkModulePkg/Universal/CpuIoDxe/CpuIo.c b/IntelFram= eworkModulePkg/Universal/CpuIoDxe/CpuIo.c index 9db9dbe..9474606 100644 --- a/IntelFrameworkModulePkg/Universal/CpuIoDxe/CpuIo.c +++ b/IntelFrameworkModulePkg/Universal/CpuIoDxe/CpuIo.c @@ -1,7 +1,7 @@ /** @file Uses the services of the I/O Library to produce the CPU I/O Protocol =20 -Copyright (c) 2004 - 2012, Intel Corporation. All rights reserved.
+Copyright (c) 2004 - 2017, Intel Corporation. All rights reserved.
Copyright (c) 2017, AMD Incorporated. All rights reserved.
=20 This program and the accompanying materials =20 @@ -141,7 +141,7 @@ CpuIoCheckParameter ( // // Check to see if Address is aligned // - if ((Address & (UINT64)(mInStride[Width] - 1)) !=3D 0) { + if ((Address & ((UINT64)mInStride[Width] - 1)) !=3D 0) { return EFI_UNSUPPORTED; } =20 --=20 1.9.5.msysgit.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat Nov 2 14:41:02 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zoho.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 14879995850741002.736894533585; Fri, 24 Feb 2017 21:13:05 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 255B7821A1; Fri, 24 Feb 2017 21:12:59 -0800 (PST) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 827CB8219C for ; Fri, 24 Feb 2017 21:12:56 -0800 (PST) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Feb 2017 21:12:56 -0800 Received: from shwdeopenpsi014.ccr.corp.intel.com ([10.239.9.13]) by orsmga002.jf.intel.com with ESMTP; 24 Feb 2017 21:12:55 -0800 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.35,202,1484035200"; d="scan'208";a="52624029" From: Hao Wu To: edk2-devel@lists.01.org Date: Sat, 25 Feb 2017 13:12:28 +0800 Message-Id: <1487999555-9764-6-git-send-email-hao.a.wu@intel.com> X-Mailer: git-send-email 1.9.5.msysgit.0 In-Reply-To: <1487999555-9764-1-git-send-email-hao.a.wu@intel.com> References: <1487999555-9764-1-git-send-email-hao.a.wu@intel.com> Subject: [edk2] [PATCH v3 05/12] IntelFsp2WrapperPkg: Refine casting expression result to bigger size X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Hao Wu , Jiewen Yao MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" There are cases that the operands of an expression are all with rank less than UINT64/INT64 and the result of the expression is explicitly cast to UINT64/INT64 to fit the target size. An example will be: UINT32 a,b; // a and b can be any unsigned int type with rank less than UINT64, like // UINT8, UINT16, etc. UINT64 c; c =3D (UINT64) (a + b); Some static code checkers may warn that the expression result might overflow within the rank of "int" (integer promotions) and the result is then cast to a bigger size. The commit refines codes by the following rules: 1). When the expression is possible to overflow the range of unsigned int/ int: c =3D (UINT64)a + b; 2). When the expression will not overflow within the rank of "int", remove the explicit type casts: c =3D a + b; 3). When the expression will be cast to pointer of possible greater size: UINT32 a,b; VOID *c; c =3D (VOID *)(UINTN)(a + b); --> c =3D (VOID *)((UINTN)a + b); 4). When one side of a comparison expression contains only operands with rank less than UINT32: UINT8 a; UINT16 b; UINTN c; if ((UINTN)(a + b) > c) {...} --> if (((UINT32)a + b) > c) {...} For rule 4), if we remove the 'UINTN' type cast like: if (a + b > c) {...} The VS compiler will complain with warning C4018 (signed/unsigned mismatch, level 3 warning) due to promoting 'a + b' to type 'int'. Cc: Jiewen Yao Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu Reviewed-by: jiewen.yao@intel.com --- IntelFsp2WrapperPkg/FspWrapperNotifyDxe/LoadBelow4G.c | 4 += +-- IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/FspWrapperApiLib.c | 10 += ++++----- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/IntelFsp2WrapperPkg/FspWrapperNotifyDxe/LoadBelow4G.c b/IntelF= sp2WrapperPkg/FspWrapperNotifyDxe/LoadBelow4G.c index ff2f563..dc5ef89 100644 --- a/IntelFsp2WrapperPkg/FspWrapperNotifyDxe/LoadBelow4G.c +++ b/IntelFsp2WrapperPkg/FspWrapperNotifyDxe/LoadBelow4G.c @@ -1,6 +1,6 @@ /** @file =20 -Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions @@ -115,7 +115,7 @@ RelocateImageUnder4GIfNeeded ( // Align buffer on section boundary // ImageContext.ImageAddress +=3D ImageContext.SectionAlignment - 1; - ImageContext.ImageAddress &=3D ~((EFI_PHYSICAL_ADDRESS)(ImageContext.Sec= tionAlignment - 1)); + ImageContext.ImageAddress &=3D ~((EFI_PHYSICAL_ADDRESS)ImageContext.Sect= ionAlignment - 1); // // Load the image to our new buffer // diff --git a/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/FspWrapperApi= Lib.c b/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/FspWrapperApiLib.c index 8cf136f..38de415 100644 --- a/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/FspWrapperApiLib.c +++ b/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/FspWrapperApiLib.c @@ -1,7 +1,7 @@ /** @file Provide FSP API related function. =20 - Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License which accompanies this distribution. The full text of the license may b= e found at @@ -99,7 +99,7 @@ CallFspNotifyPhase ( return EFI_DEVICE_ERROR; } =20 - NotifyPhaseApi =3D (FSP_NOTIFY_PHASE)(UINTN)(FspHeader->ImageBase + FspH= eader->NotifyPhaseEntryOffset); + NotifyPhaseApi =3D (FSP_NOTIFY_PHASE)((UINTN)FspHeader->ImageBase + FspH= eader->NotifyPhaseEntryOffset); InterruptState =3D SaveAndDisableInterrupts (); Status =3D Execute32BitCode ((UINTN)NotifyPhaseApi, (UINTN)NotifyPhasePa= rams, (UINTN)NULL); SetInterruptState (InterruptState); @@ -132,7 +132,7 @@ CallFspMemoryInit ( return EFI_DEVICE_ERROR; } =20 - FspMemoryInitApi =3D (FSP_MEMORY_INIT)(UINTN)(FspHeader->ImageBase + Fsp= Header->FspMemoryInitEntryOffset); + FspMemoryInitApi =3D (FSP_MEMORY_INIT)((UINTN)FspHeader->ImageBase + Fsp= Header->FspMemoryInitEntryOffset); InterruptState =3D SaveAndDisableInterrupts (); Status =3D Execute32BitCode ((UINTN)FspMemoryInitApi, (UINTN)FspmUpdData= Ptr, (UINTN)HobListPtr); SetInterruptState (InterruptState); @@ -163,7 +163,7 @@ CallTempRamExit ( return EFI_DEVICE_ERROR; } =20 - TempRamExitApi =3D (FSP_TEMP_RAM_EXIT)(UINTN)(FspHeader->ImageBase + Fsp= Header->TempRamExitEntryOffset); + TempRamExitApi =3D (FSP_TEMP_RAM_EXIT)((UINTN)FspHeader->ImageBase + Fsp= Header->TempRamExitEntryOffset); InterruptState =3D SaveAndDisableInterrupts (); Status =3D Execute32BitCode ((UINTN)TempRamExitApi, (UINTN)TempRamExitPa= ram, (UINTN)NULL); SetInterruptState (InterruptState); @@ -194,7 +194,7 @@ CallFspSiliconInit ( return EFI_DEVICE_ERROR; } =20 - FspSiliconInitApi =3D (FSP_SILICON_INIT)(UINTN)(FspHeader->ImageBase + F= spHeader->FspSiliconInitEntryOffset); + FspSiliconInitApi =3D (FSP_SILICON_INIT)((UINTN)FspHeader->ImageBase + F= spHeader->FspSiliconInitEntryOffset); InterruptState =3D SaveAndDisableInterrupts (); Status =3D Execute32BitCode ((UINTN)FspSiliconInitApi, (UINTN)FspsUpdDat= aPtr, (UINTN)NULL); SetInterruptState (InterruptState); --=20 1.9.5.msysgit.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat Nov 2 14:41:02 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zoho.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1487999587874894.6380093232154; Fri, 24 Feb 2017 21:13:07 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 54FEE821A4; Fri, 24 Feb 2017 21:12:59 -0800 (PST) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 923418219C for ; Fri, 24 Feb 2017 21:12:57 -0800 (PST) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Feb 2017 21:12:57 -0800 Received: from shwdeopenpsi014.ccr.corp.intel.com ([10.239.9.13]) by orsmga002.jf.intel.com with ESMTP; 24 Feb 2017 21:12:56 -0800 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.35,202,1484035200"; d="scan'208";a="52624034" From: Hao Wu To: edk2-devel@lists.01.org Date: Sat, 25 Feb 2017 13:12:29 +0800 Message-Id: <1487999555-9764-7-git-send-email-hao.a.wu@intel.com> X-Mailer: git-send-email 1.9.5.msysgit.0 In-Reply-To: <1487999555-9764-1-git-send-email-hao.a.wu@intel.com> References: <1487999555-9764-1-git-send-email-hao.a.wu@intel.com> Subject: [edk2] [PATCH v3 06/12] IntelFspWrapperPkg: Refine casting expression result to bigger size X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Hao Wu , Jiewen Yao MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" There are cases that the operands of an expression are all with rank less than UINT64/INT64 and the result of the expression is explicitly cast to UINT64/INT64 to fit the target size. An example will be: UINT32 a,b; // a and b can be any unsigned int type with rank less than UINT64, like // UINT8, UINT16, etc. UINT64 c; c =3D (UINT64) (a + b); Some static code checkers may warn that the expression result might overflow within the rank of "int" (integer promotions) and the result is then cast to a bigger size. The commit refines codes by the following rules: 1). When the expression is possible to overflow the range of unsigned int/ int: c =3D (UINT64)a + b; 2). When the expression will not overflow within the rank of "int", remove the explicit type casts: c =3D a + b; 3). When the expression will be cast to pointer of possible greater size: UINT32 a,b; VOID *c; c =3D (VOID *)(UINTN)(a + b); --> c =3D (VOID *)((UINTN)a + b); 4). When one side of a comparison expression contains only operands with rank less than UINT32: UINT8 a; UINT16 b; UINTN c; if ((UINTN)(a + b) > c) {...} --> if (((UINT32)a + b) > c) {...} For rule 4), if we remove the 'UINTN' type cast like: if (a + b > c) {...} The VS compiler will complain with warning C4018 (signed/unsigned mismatch, level 3 warning) due to promoting 'a + b' to type 'int'. Cc: Jiewen Yao Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu Reviewed-by: jiewen.yao@intel.com --- IntelFspWrapperPkg/FspNotifyDxe/LoadBelow4G.c | 4 ++-- IntelFspWrapperPkg/Library/BaseFspApiLib/FspApiLib.c | 12 ++++++------ 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/IntelFspWrapperPkg/FspNotifyDxe/LoadBelow4G.c b/IntelFspWrappe= rPkg/FspNotifyDxe/LoadBelow4G.c index 6f06e24..089413c 100644 --- a/IntelFspWrapperPkg/FspNotifyDxe/LoadBelow4G.c +++ b/IntelFspWrapperPkg/FspNotifyDxe/LoadBelow4G.c @@ -1,6 +1,6 @@ /** @file =20 -Copyright (c) 2015, Intel Corporation. All rights reserved.
+Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions @@ -115,7 +115,7 @@ RelocateImageUnder4GIfNeeded ( // Align buffer on section boundary // ImageContext.ImageAddress +=3D ImageContext.SectionAlignment - 1; - ImageContext.ImageAddress &=3D ~((EFI_PHYSICAL_ADDRESS)(ImageContext.Sec= tionAlignment - 1)); + ImageContext.ImageAddress &=3D ~((EFI_PHYSICAL_ADDRESS)ImageContext.Sect= ionAlignment - 1); // // Load the image to our new buffer // diff --git a/IntelFspWrapperPkg/Library/BaseFspApiLib/FspApiLib.c b/IntelFs= pWrapperPkg/Library/BaseFspApiLib/FspApiLib.c index 162d244..accd6e4 100644 --- a/IntelFspWrapperPkg/Library/BaseFspApiLib/FspApiLib.c +++ b/IntelFspWrapperPkg/Library/BaseFspApiLib/FspApiLib.c @@ -1,7 +1,7 @@ /** @file Provide FSP API related function. =20 - Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.
+ Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License which accompanies this distribution. The full text of the license may b= e found at @@ -98,7 +98,7 @@ CallFspInit ( EFI_STATUS Status; BOOLEAN InterruptState; =20 - FspInitApi =3D (FSP_INIT)(UINTN)(FspHeader->ImageBase + FspHeader->FspIn= itEntryOffset); + FspInitApi =3D (FSP_INIT)((UINTN)FspHeader->ImageBase + FspHeader->FspIn= itEntryOffset); InterruptState =3D SaveAndDisableInterrupts (); Status =3D Execute32BitCode ((UINTN)FspInitApi, (UINTN)FspInitParams); SetInterruptState (InterruptState); @@ -125,7 +125,7 @@ CallFspNotifyPhase ( EFI_STATUS Status; BOOLEAN InterruptState; =20 - NotifyPhaseApi =3D (FSP_NOTIFY_PHASE)(UINTN)(FspHeader->ImageBase + FspH= eader->NotifyPhaseEntryOffset); + NotifyPhaseApi =3D (FSP_NOTIFY_PHASE)((UINTN)FspHeader->ImageBase + FspH= eader->NotifyPhaseEntryOffset); InterruptState =3D SaveAndDisableInterrupts (); Status =3D Execute32BitCode ((UINTN)NotifyPhaseApi, (UINTN)NotifyPhasePa= rams); SetInterruptState (InterruptState); @@ -152,7 +152,7 @@ CallFspMemoryInit ( EFI_STATUS Status; BOOLEAN InterruptState; =20 - FspMemoryInitApi =3D (FSP_MEMORY_INIT)(UINTN)(FspHeader->ImageBase + Fsp= Header->FspMemoryInitEntryOffset); + FspMemoryInitApi =3D (FSP_MEMORY_INIT)((UINTN)FspHeader->ImageBase + Fsp= Header->FspMemoryInitEntryOffset); InterruptState =3D SaveAndDisableInterrupts (); Status =3D Execute32BitCode ((UINTN)FspMemoryInitApi, (UINTN)FspMemoryIn= itParams); SetInterruptState (InterruptState); @@ -179,7 +179,7 @@ CallTempRamExit ( EFI_STATUS Status; BOOLEAN InterruptState; =20 - TempRamExitApi =3D (FSP_TEMP_RAM_EXIT)(UINTN)(FspHeader->ImageBase + Fsp= Header->TempRamExitEntryOffset); + TempRamExitApi =3D (FSP_TEMP_RAM_EXIT)((UINTN)FspHeader->ImageBase + Fsp= Header->TempRamExitEntryOffset); InterruptState =3D SaveAndDisableInterrupts (); Status =3D Execute32BitCode ((UINTN)TempRamExitApi, (UINTN)TempRamExitPa= ram); SetInterruptState (InterruptState); @@ -206,7 +206,7 @@ CallFspSiliconInit ( EFI_STATUS Status; BOOLEAN InterruptState; =20 - FspSiliconInitApi =3D (FSP_SILICON_INIT)(UINTN)(FspHeader->ImageBase + F= spHeader->FspSiliconInitEntryOffset); + FspSiliconInitApi =3D (FSP_SILICON_INIT)((UINTN)FspHeader->ImageBase + F= spHeader->FspSiliconInitEntryOffset); InterruptState =3D SaveAndDisableInterrupts (); Status =3D Execute32BitCode ((UINTN)FspSiliconInitApi, (UINTN)FspSilicon= InitParam); SetInterruptState (InterruptState); --=20 1.9.5.msysgit.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat Nov 2 14:41:02 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zoho.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1487999590531627.1070415205578; Fri, 24 Feb 2017 21:13:10 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 8612C821A3; Fri, 24 Feb 2017 21:13:02 -0800 (PST) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id CD03782156 for ; Fri, 24 Feb 2017 21:12:58 -0800 (PST) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Feb 2017 21:12:58 -0800 Received: from shwdeopenpsi014.ccr.corp.intel.com ([10.239.9.13]) by orsmga002.jf.intel.com with ESMTP; 24 Feb 2017 21:12:57 -0800 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.35,202,1484035200"; d="scan'208";a="52624038" From: Hao Wu To: edk2-devel@lists.01.org Date: Sat, 25 Feb 2017 13:12:30 +0800 Message-Id: <1487999555-9764-8-git-send-email-hao.a.wu@intel.com> X-Mailer: git-send-email 1.9.5.msysgit.0 In-Reply-To: <1487999555-9764-1-git-send-email-hao.a.wu@intel.com> References: <1487999555-9764-1-git-send-email-hao.a.wu@intel.com> Subject: [edk2] [PATCH v3 07/12] NetworkPkg: Refine casting expression result to bigger size X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Hao Wu , Siyuan Fu , Jiaxin Wu MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" There are cases that the operands of an expression are all with rank less than UINT64/INT64 and the result of the expression is explicitly cast to UINT64/INT64 to fit the target size. An example will be: UINT32 a,b; // a and b can be any unsigned int type with rank less than UINT64, like // UINT8, UINT16, etc. UINT64 c; c =3D (UINT64) (a + b); Some static code checkers may warn that the expression result might overflow within the rank of "int" (integer promotions) and the result is then cast to a bigger size. The commit refines codes by the following rules: 1). When the expression is possible to overflow the range of unsigned int/ int: c =3D (UINT64)a + b; 2). When the expression will not overflow within the rank of "int", remove the explicit type casts: c =3D a + b; 3). When the expression will be cast to pointer of possible greater size: UINT32 a,b; VOID *c; c =3D (VOID *)(UINTN)(a + b); --> c =3D (VOID *)((UINTN)a + b); 4). When one side of a comparison expression contains only operands with rank less than UINT32: UINT8 a; UINT16 b; UINTN c; if ((UINTN)(a + b) > c) {...} --> if (((UINT32)a + b) > c) {...} For rule 4), if we remove the 'UINTN' type cast like: if (a + b > c) {...} The VS compiler will complain with warning C4018 (signed/unsigned mismatch, level 3 warning) due to promoting 'a + b' to type 'int'. Cc: Siyuan Fu Cc: Jiaxin Wu Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu Reviewed-by: Wu Jiaxin --- NetworkPkg/IpSecDxe/Ikev2/Payload.c | 4 ++-- NetworkPkg/IpSecDxe/IpSecConfigImpl.c | 8 ++++---- NetworkPkg/IpSecDxe/IpSecConfigImpl.h | 4 ++-- NetworkPkg/Mtftp6Dxe/Mtftp6Support.c | 4 ++-- NetworkPkg/UefiPxeBcDxe/PxeBcImpl.c | 10 +++++----- 5 files changed, 15 insertions(+), 15 deletions(-) diff --git a/NetworkPkg/IpSecDxe/Ikev2/Payload.c b/NetworkPkg/IpSecDxe/Ikev= 2/Payload.c index f32b3a8..237743b 100644 --- a/NetworkPkg/IpSecDxe/Ikev2/Payload.c +++ b/NetworkPkg/IpSecDxe/Ikev2/Payload.c @@ -2,7 +2,7 @@ The implementation of Payloads Creation. =20 (C) Copyright 2015 Hewlett-Packard Development Company, L.P.
- Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2010 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -1748,7 +1748,7 @@ Ikev2EncodeSa ( Transform->Header.NextPayload =3D IKE_TRANSFORM_NEXT_PAYLOAD_MORE; Transform->Header.PayloadLength =3D HTONS ((UINT16)TransformSize); =20 - if (TransformIndex =3D=3D (UINTN)(ProposalData->NumTransforms - 1)) { + if (TransformIndex =3D=3D ((UINT32)ProposalData->NumTransforms - 1))= { Transform->Header.NextPayload =3D IKE_TRANSFORM_NEXT_PAYLOAD_NONE; } =20 diff --git a/NetworkPkg/IpSecDxe/IpSecConfigImpl.c b/NetworkPkg/IpSecDxe/Ip= SecConfigImpl.c index cfee978..4a51bff 100644 --- a/NetworkPkg/IpSecDxe/IpSecConfigImpl.c +++ b/NetworkPkg/IpSecDxe/IpSecConfigImpl.c @@ -1,7 +1,7 @@ /** @file The implementation of IPSEC_CONFIG_PROTOCOL. =20 - Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -1152,7 +1152,7 @@ SetSpdEntry ( // Do Padding for the different Arch. // SpdEntrySize =3D ALIGN_VARIABLE (sizeof (IPSEC_SPD_ENTRY)); - SpdEntrySize =3D ALIGN_VARIABLE (SpdEntrySize + (UINTN)SIZE_OF_SPD_SELE= CTOR (SpdSel)); + SpdEntrySize =3D ALIGN_VARIABLE (SpdEntrySize + SIZE_OF_SPD_SELECTOR (S= pdSel)); SpdEntrySize +=3D IpSecGetSizeOfEfiSpdData (SpdData); =20 SpdEntry =3D AllocateZeroPool (SpdEntrySize); @@ -1357,7 +1357,7 @@ SetSadEntry ( } =20 if (SaData->SpdSelector !=3D NULL) { - SadEntrySize +=3D SadEntrySize + (UINTN)SIZE_OF_SPD_SELECTOR (SaData->= SpdSelector); + SadEntrySize +=3D SadEntrySize + SIZE_OF_SPD_SELECTOR (SaData->SpdSele= ctor); } SadEntry =3D AllocateZeroPool (SadEntrySize); =20 @@ -1458,7 +1458,7 @@ SetSadEntry ( SadEntry->Data->SpdEntry =3D SpdEntry; SadEntry->Data->SpdSelector =3D (EFI_IPSEC_SPD_SELECTOR *)((UINT8 *)= SadEntry + SadEntrySi= ze - - (UINTN)SIZ= E_OF_SPD_SELECTOR (SaData->SpdSelector) + SIZE_OF_SP= D_SELECTOR (SaData->SpdSelector) ); DuplicateSpdSelector ( (EFI_IPSEC_CONFIG_SELECTOR *) SadEntry->Data->SpdSelector, diff --git a/NetworkPkg/IpSecDxe/IpSecConfigImpl.h b/NetworkPkg/IpSecDxe/Ip= SecConfigImpl.h index 3e365da..23e6880 100644 --- a/NetworkPkg/IpSecDxe/IpSecConfigImpl.h +++ b/NetworkPkg/IpSecDxe/IpSecConfigImpl.h @@ -1,7 +1,7 @@ /** @file Definitions related to IPSEC_CONFIG_PROTOCOL implementations. =20 - Copyright (c) 2009 - 2011, Intel Corporation. All rights reserved.
+ Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -38,7 +38,7 @@ #define IPSECCONFIG_VARIABLE_NAME L"IpSecConfig" #define IPSECCONFIG_STATUS_NAME L"IpSecStatus" =20 -#define SIZE_OF_SPD_SELECTOR(x) (UINTN) (sizeof (EFI_IPSEC_SPD_SELECTOR) \ +#define SIZE_OF_SPD_SELECTOR(x) (sizeof (EFI_IPSEC_SPD_SELECTOR) \ + sizeof (EFI_IP_ADDRESS_INFO) * ((x)->LocalAddressCount + (x)->Rem= oteAddressCount)) =20 #define FIX_REF_BUF_ADDR(addr, base) addr =3D (VOID *) ((UINTN) (addr) = - (UINTN) (base)) diff --git a/NetworkPkg/Mtftp6Dxe/Mtftp6Support.c b/NetworkPkg/Mtftp6Dxe/Mt= ftp6Support.c index 64df901..e6b4127 100644 --- a/NetworkPkg/Mtftp6Dxe/Mtftp6Support.c +++ b/NetworkPkg/Mtftp6Dxe/Mtftp6Support.c @@ -1,7 +1,7 @@ /** @file Mtftp6 support functions implementation. =20 - Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -223,7 +223,7 @@ Mtftp6RemoveBlockNum ( *TotalBlock =3D Num; =20 if (Range->Round > 0) { - *TotalBlock +=3D Range->Bound + MultU64x32 ((UINT64) (Range->Roun= d -1), (UINT32)(Range->Bound + 1)) + 1; + *TotalBlock +=3D Range->Bound + MultU64x32 (Range->Round - 1, (UI= NT32)(Range->Bound + 1)) + 1; } =20 if (Range->Start > Range->Bound) { diff --git a/NetworkPkg/UefiPxeBcDxe/PxeBcImpl.c b/NetworkPkg/UefiPxeBcDxe/= PxeBcImpl.c index e24c573..36477e9 100644 --- a/NetworkPkg/UefiPxeBcDxe/PxeBcImpl.c +++ b/NetworkPkg/UefiPxeBcDxe/PxeBcImpl.c @@ -1,7 +1,7 @@ /** @file This implementation of EFI_PXE_BASE_CODE_PROTOCOL and EFI_LOAD_FILE_PROT= OCOL. =20 - Copyright (c) 2007 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2007 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -95,8 +95,8 @@ EfiPxeBcStart ( // // Configure block size for TFTP as a default value to handle all link= layers. // - Private->BlockSize =3D (UINTN) (Private->Ip6MaxPacketSize - - PXEBC_DEFAULT_UDP_OVERHEAD_SIZE - PXEBC_DEFAULT= _TFTP_OVERHEAD_SIZE); + Private->BlockSize =3D Private->Ip6MaxPacketSize - + PXEBC_DEFAULT_UDP_OVERHEAD_SIZE - PXEBC_DEFAULT= _TFTP_OVERHEAD_SIZE; =20 // // PXE over IPv6 starts here, initialize the fields and list header. @@ -148,8 +148,8 @@ EfiPxeBcStart ( // // Configure block size for TFTP as a default value to handle all link= layers. // - Private->BlockSize =3D (UINTN) (Private->Ip4MaxPacketSize - - PXEBC_DEFAULT_UDP_OVERHEAD_SIZE - PXEBC_DEFAULT= _TFTP_OVERHEAD_SIZE); + Private->BlockSize =3D Private->Ip4MaxPacketSize - + PXEBC_DEFAULT_UDP_OVERHEAD_SIZE - PXEBC_DEFAULT= _TFTP_OVERHEAD_SIZE; =20 // // PXE over IPv4 starts here, initialize the fields. --=20 1.9.5.msysgit.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat Nov 2 14:41:02 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zoho.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1487999593369697.2629021199868; Fri, 24 Feb 2017 21:13:13 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id B61A5821AA; Fri, 24 Feb 2017 21:13:02 -0800 (PST) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id D615B821A7 for ; Fri, 24 Feb 2017 21:12:59 -0800 (PST) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Feb 2017 21:12:59 -0800 Received: from shwdeopenpsi014.ccr.corp.intel.com ([10.239.9.13]) by orsmga002.jf.intel.com with ESMTP; 24 Feb 2017 21:12:58 -0800 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.35,202,1484035200"; d="scan'208";a="52624043" From: Hao Wu To: edk2-devel@lists.01.org Date: Sat, 25 Feb 2017 13:12:31 +0800 Message-Id: <1487999555-9764-9-git-send-email-hao.a.wu@intel.com> X-Mailer: git-send-email 1.9.5.msysgit.0 In-Reply-To: <1487999555-9764-1-git-send-email-hao.a.wu@intel.com> References: <1487999555-9764-1-git-send-email-hao.a.wu@intel.com> Subject: [edk2] [PATCH v3 08/12] PcAtChipsetPkg: Refine casting expression result to bigger size X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Hao Wu , Ruiyu Ni MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" There are cases that the operands of an expression are all with rank less than UINT64/INT64 and the result of the expression is explicitly cast to UINT64/INT64 to fit the target size. An example will be: UINT32 a,b; // a and b can be any unsigned int type with rank less than UINT64, like // UINT8, UINT16, etc. UINT64 c; c =3D (UINT64) (a + b); Some static code checkers may warn that the expression result might overflow within the rank of "int" (integer promotions) and the result is then cast to a bigger size. The commit refines codes by the following rules: 1). When the expression is possible to overflow the range of unsigned int/ int: c =3D (UINT64)a + b; 2). When the expression will not overflow within the rank of "int", remove the explicit type casts: c =3D a + b; 3). When the expression will be cast to pointer of possible greater size: UINT32 a,b; VOID *c; c =3D (VOID *)(UINTN)(a + b); --> c =3D (VOID *)((UINTN)a + b); 4). When one side of a comparison expression contains only operands with rank less than UINT32: UINT8 a; UINT16 b; UINTN c; if ((UINTN)(a + b) > c) {...} --> if (((UINT32)a + b) > c) {...} For rule 4), if we remove the 'UINTN' type cast like: if (a + b > c) {...} The VS compiler will complain with warning C4018 (signed/unsigned mismatch, level 3 warning) due to promoting 'a + b' to type 'int'. Cc: Ruiyu Ni Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu Reviewed-by: Ruiyu Ni --- PcAtChipsetPkg/Library/SerialIoLib/SerialPortLib.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/PcAtChipsetPkg/Library/SerialIoLib/SerialPortLib.c b/PcAtChips= etPkg/Library/SerialIoLib/SerialPortLib.c index dcb43fa..95e0db7 100644 --- a/PcAtChipsetPkg/Library/SerialIoLib/SerialPortLib.c +++ b/PcAtChipsetPkg/Library/SerialIoLib/SerialPortLib.c @@ -1,7 +1,7 @@ /** @file UART Serial Port library functions =20 - Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License which accompanies this distribution. The full text of the license may b= e found at @@ -91,19 +91,19 @@ SerialPortInitialize ( // Set communications format // OutputData =3D (UINT8) ((DLAB << 7) | (gBreakSet << 6) | (gParity << 3) = | (gStop << 2) | Data); - IoWrite8 ((UINTN) (gUartBase + LCR_OFFSET), OutputData); + IoWrite8 (gUartBase + LCR_OFFSET, OutputData); =20 // // Configure baud rate // - IoWrite8 ((UINTN) (gUartBase + BAUD_HIGH_OFFSET), (UINT8) (Divisor >> 8)= ); - IoWrite8 ((UINTN) (gUartBase + BAUD_LOW_OFFSET), (UINT8) (Divisor & 0xff= )); + IoWrite8 (gUartBase + BAUD_HIGH_OFFSET, (UINT8) (Divisor >> 8)); + IoWrite8 (gUartBase + BAUD_LOW_OFFSET, (UINT8) (Divisor & 0xff)); =20 // // Switch back to bank 0 // OutputData =3D (UINT8) ((~DLAB << 7) | (gBreakSet << 6) | (gParity << 3)= | (gStop << 2) | Data); - IoWrite8 ((UINTN) (gUartBase + LCR_OFFSET), OutputData); + IoWrite8 (gUartBase + LCR_OFFSET, OutputData); =20 return RETURN_SUCCESS; } @@ -470,19 +470,19 @@ SerialPortSetAttributes ( // Set communications format // OutputData =3D (UINT8) ((DLAB << 7) | (gBreakSet << 6) | (LcrParity << 3= ) | (LcrStop << 2) | LcrData); - IoWrite8 ((UINTN) (gUartBase + LCR_OFFSET), OutputData); + IoWrite8 (gUartBase + LCR_OFFSET, OutputData); =20 // // Configure baud rate // - IoWrite8 ((UINTN) (gUartBase + BAUD_HIGH_OFFSET), (UINT8) (Divisor >> 8)= ); - IoWrite8 ((UINTN) (gUartBase + BAUD_LOW_OFFSET), (UINT8) (Divisor & 0xff= )); + IoWrite8 (gUartBase + BAUD_HIGH_OFFSET, (UINT8) (Divisor >> 8)); + IoWrite8 (gUartBase + BAUD_LOW_OFFSET, (UINT8) (Divisor & 0xff)); =20 // // Switch back to bank 0 // OutputData =3D (UINT8) ((~DLAB << 7) | (gBreakSet << 6) | (LcrParity << = 3) | (LcrStop << 2) | LcrData); - IoWrite8 ((UINTN) (gUartBase + LCR_OFFSET), OutputData); + IoWrite8 (gUartBase + LCR_OFFSET, OutputData); =20 return RETURN_SUCCESS; } --=20 1.9.5.msysgit.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat Nov 2 14:41:02 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zoho.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1487999596185227.9049635032335; Fri, 24 Feb 2017 21:13:16 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id E64C8821AF; Fri, 24 Feb 2017 21:13:02 -0800 (PST) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3933A8219C for ; Fri, 24 Feb 2017 21:13:01 -0800 (PST) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Feb 2017 21:13:01 -0800 Received: from shwdeopenpsi014.ccr.corp.intel.com ([10.239.9.13]) by orsmga002.jf.intel.com with ESMTP; 24 Feb 2017 21:12:59 -0800 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.35,202,1484035200"; d="scan'208";a="52624049" From: Hao Wu To: edk2-devel@lists.01.org Date: Sat, 25 Feb 2017 13:12:32 +0800 Message-Id: <1487999555-9764-10-git-send-email-hao.a.wu@intel.com> X-Mailer: git-send-email 1.9.5.msysgit.0 In-Reply-To: <1487999555-9764-1-git-send-email-hao.a.wu@intel.com> References: <1487999555-9764-1-git-send-email-hao.a.wu@intel.com> Subject: [edk2] [PATCH v3 09/12] SecurityPkg/Opal: Refine casting expression result to bigger size X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Hao Wu , Feng Tian , Eric Dong , Chao Zhang MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" There are cases that the operands of an expression are all with rank less than UINT64/INT64 and the result of the expression is explicitly cast to UINT64/INT64 to fit the target size. An example will be: UINT32 a,b; // a and b can be any unsigned int type with rank less than UINT64, like // UINT8, UINT16, etc. UINT64 c; c =3D (UINT64) (a + b); Some static code checkers may warn that the expression result might overflow within the rank of "int" (integer promotions) and the result is then cast to a bigger size. The commit refines codes by the following rules: 1). When the expression is possible to overflow the range of unsigned int/ int: c =3D (UINT64)a + b; 2). When the expression will not overflow within the rank of "int", remove the explicit type casts: c =3D a + b; 3). When the expression will be cast to pointer of possible greater size: UINT32 a,b; VOID *c; c =3D (VOID *)(UINTN)(a + b); --> c =3D (VOID *)((UINTN)a + b); 4). When one side of a comparison expression contains only operands with rank less than UINT32: UINT8 a; UINT16 b; UINTN c; if ((UINTN)(a + b) > c) {...} --> if (((UINT32)a + b) > c) {...} For rule 4), if we remove the 'UINTN' type cast like: if (a + b > c) {...} The VS compiler will complain with warning C4018 (signed/unsigned mismatch, level 3 warning) due to promoting 'a + b' to type 'int'. Cc: Eric Dong Cc: Feng Tian Cc: Chao Zhang Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu Reviewed-by: Eric Dong --- SecurityPkg/Tcg/Opal/OpalPasswordSmm/OpalNvmeMode.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/SecurityPkg/Tcg/Opal/OpalPasswordSmm/OpalNvmeMode.c b/Security= Pkg/Tcg/Opal/OpalPasswordSmm/OpalNvmeMode.c index 9e90d54..a47d276 100644 --- a/SecurityPkg/Tcg/Opal/OpalPasswordSmm/OpalNvmeMode.c +++ b/SecurityPkg/Tcg/Opal/OpalPasswordSmm/OpalNvmeMode.c @@ -1,7 +1,7 @@ /** @file Provide functions to initialize NVME controller and perform NVME commands =20 -Copyright (c) 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License which accompanies this distribution. The full text of the license may be = found at @@ -52,7 +52,7 @@ enum { /// /// All of base memories are 4K(0x1000) alignment /// -#define NVME_MEM_BASE(Nvme) (Nvme->BaseMem) +#define NVME_MEM_BASE(Nvme) ((UINTN)(Nvme->BaseMem)) #define NVME_CONTROL_DATA_BASE(Nvme) (ALIGN (NVME_MEM_BASE(Nvme) + = ((NvmeGetBaseMemPages (BASEMEM_CONTROLLER_DATA)) * E= FI_PAGE_SIZE), EFI_PAGE_SIZE)) #define NVME_NAMESPACE_DATA_BASE(Nvme) (ALIGN (NVME_MEM_BASE(Nvme) + = ((NvmeGetBaseMemPages (BASEMEM_IDENTIFY_DATA)) * E= FI_PAGE_SIZE), EFI_PAGE_SIZE)) #define NVME_ASQ_BASE(Nvme) (ALIGN (NVME_MEM_BASE(Nvme) + = ((NvmeGetBaseMemPages (BASEMEM_ASQ)) * E= FI_PAGE_SIZE), EFI_PAGE_SIZE)) --=20 1.9.5.msysgit.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat Nov 2 14:41:02 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zoho.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1487999599224782.7677022017631; Fri, 24 Feb 2017 21:13:19 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 2B10B821AE; Fri, 24 Feb 2017 21:13:05 -0800 (PST) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 6EFA18219C for ; Fri, 24 Feb 2017 21:13:02 -0800 (PST) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Feb 2017 21:13:02 -0800 Received: from shwdeopenpsi014.ccr.corp.intel.com ([10.239.9.13]) by orsmga002.jf.intel.com with ESMTP; 24 Feb 2017 21:13:01 -0800 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.35,202,1484035200"; d="scan'208";a="52624056" From: Hao Wu To: edk2-devel@lists.01.org Date: Sat, 25 Feb 2017 13:12:33 +0800 Message-Id: <1487999555-9764-11-git-send-email-hao.a.wu@intel.com> X-Mailer: git-send-email 1.9.5.msysgit.0 In-Reply-To: <1487999555-9764-1-git-send-email-hao.a.wu@intel.com> References: <1487999555-9764-1-git-send-email-hao.a.wu@intel.com> Subject: [edk2] [PATCH v3 10/12] ShellPkg: Refine casting expression result to bigger size X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Hao Wu , Jaben Carsey , Ruiyu Ni MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" There are cases that the operands of an expression are all with rank less than UINT64/INT64 and the result of the expression is explicitly cast to UINT64/INT64 to fit the target size. An example will be: UINT32 a,b; // a and b can be any unsigned int type with rank less than UINT64, like // UINT8, UINT16, etc. UINT64 c; c =3D (UINT64) (a + b); Some static code checkers may warn that the expression result might overflow within the rank of "int" (integer promotions) and the result is then cast to a bigger size. The commit refines codes by the following rules: 1). When the expression is possible to overflow the range of unsigned int/ int: c =3D (UINT64)a + b; 2). When the expression will not overflow within the rank of "int", remove the explicit type casts: c =3D a + b; 3). When the expression will be cast to pointer of possible greater size: UINT32 a,b; VOID *c; c =3D (VOID *)(UINTN)(a + b); --> c =3D (VOID *)((UINTN)a + b); 4). When one side of a comparison expression contains only operands with rank less than UINT32: UINT8 a; UINT16 b; UINTN c; if ((UINTN)(a + b) > c) {...} --> if (((UINT32)a + b) > c) {...} For rule 4), if we remove the 'UINTN' type cast like: if (a + b > c) {...} The VS compiler will complain with warning C4018 (signed/unsigned mismatch, level 3 warning) due to promoting 'a + b' to type 'int'. Cc: Jaben Carsey Cc: Ruiyu Ni Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu Reviewed-by: Jaben Carsey Reviewed-by: Ruiyu Ni --- ShellPkg/Library/UefiShellDebug1CommandsLib/HexEdit/BufferImage.c |= 8 ++++---- ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.c |= 4 ++-- ShellPkg/Library/UefiShellLib/UefiShellLib.c |= 4 ++-- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/ShellPkg/Library/UefiShellDebug1CommandsLib/HexEdit/BufferImag= e.c b/ShellPkg/Library/UefiShellDebug1CommandsLib/HexEdit/BufferImage.c index 68d2443..1048ecd 100644 --- a/ShellPkg/Library/UefiShellDebug1CommandsLib/HexEdit/BufferImage.c +++ b/ShellPkg/Library/UefiShellDebug1CommandsLib/HexEdit/BufferImage.c @@ -2,7 +2,7 @@ Defines HBufferImage - the view of the file that is visible at any point, as well as the event handlers for editing the file =20 - Copyright (c) 2005 - 2014, Intel Corporation. All rights reserved.
+ Copyright (c) 2005 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License which accompanies this distribution. The full text of the license may b= e found at @@ -1108,15 +1108,15 @@ HBufferImageCharToHex ( // change the character to hex // if (Char >=3D L'0' && Char <=3D L'9') { - return (INTN) (Char - L'0'); + return (Char - L'0'); } =20 if (Char >=3D L'a' && Char <=3D L'f') { - return (INTN) (Char - L'a' + 10); + return (Char - L'a' + 10); } =20 if (Char >=3D L'A' && Char <=3D L'F') { - return (INTN) (Char - L'A' + 10); + return (Char - L'A' + 10); } =20 return -1; diff --git a/ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1Com= mandsLib.c b/ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1Com= mandsLib.c index 6ebf002..a0e249e 100644 --- a/ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLi= b.c +++ b/ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLi= b.c @@ -1,7 +1,7 @@ /** @file Main file for NULL named library for debug1 profile shell command functi= ons. =20 - Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.
+ Copyright (c) 2010 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License which accompanies this distribution. The full text of the license may b= e found at @@ -193,7 +193,7 @@ HexCharToUintn ( return Char - L'0'; } =20 - return (UINTN) (10 + CharToUpper (Char) - L'A'); + return (10 + CharToUpper (Char) - L'A'); } =20 /** diff --git a/ShellPkg/Library/UefiShellLib/UefiShellLib.c b/ShellPkg/Librar= y/UefiShellLib/UefiShellLib.c index 536db3c..55e8a67 100644 --- a/ShellPkg/Library/UefiShellLib/UefiShellLib.c +++ b/ShellPkg/Library/UefiShellLib/UefiShellLib.c @@ -3,7 +3,7 @@ =20 (C) Copyright 2016 Hewlett Packard Enterprise Development LP
Copyright 2016 Dell Inc. - Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License which accompanies this distribution. The full text of the license may b= e found at @@ -3755,7 +3755,7 @@ InternalShellHexCharToUintn ( return Char - L'0'; } =20 - return (UINTN) (10 + InternalShellCharToUpper (Char) - L'A'); + return (10 + InternalShellCharToUpper (Char) - L'A'); } =20 /** --=20 1.9.5.msysgit.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat Nov 2 14:41:02 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zoho.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1487999601858833.0457778816725; Fri, 24 Feb 2017 21:13:21 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 609A8821B5; Fri, 24 Feb 2017 21:13:05 -0800 (PST) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 84CDA821B4 for ; Fri, 24 Feb 2017 21:13:03 -0800 (PST) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Feb 2017 21:13:03 -0800 Received: from shwdeopenpsi014.ccr.corp.intel.com ([10.239.9.13]) by orsmga002.jf.intel.com with ESMTP; 24 Feb 2017 21:13:02 -0800 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.35,202,1484035200"; d="scan'208";a="52624065" From: Hao Wu To: edk2-devel@lists.01.org Date: Sat, 25 Feb 2017 13:12:34 +0800 Message-Id: <1487999555-9764-12-git-send-email-hao.a.wu@intel.com> X-Mailer: git-send-email 1.9.5.msysgit.0 In-Reply-To: <1487999555-9764-1-git-send-email-hao.a.wu@intel.com> References: <1487999555-9764-1-git-send-email-hao.a.wu@intel.com> Subject: [edk2] [PATCH v3 11/12] SourceLevelDebugPkg: Refine casting expression result to bigger size X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Hao Wu , Jeff Fan MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" There are cases that the operands of an expression are all with rank less than UINT64/INT64 and the result of the expression is explicitly cast to UINT64/INT64 to fit the target size. An example will be: UINT32 a,b; // a and b can be any unsigned int type with rank less than UINT64, like // UINT8, UINT16, etc. UINT64 c; c =3D (UINT64) (a + b); Some static code checkers may warn that the expression result might overflow within the rank of "int" (integer promotions) and the result is then cast to a bigger size. The commit refines codes by the following rules: 1). When the expression is possible to overflow the range of unsigned int/ int: c =3D (UINT64)a + b; 2). When the expression will not overflow within the rank of "int", remove the explicit type casts: c =3D a + b; 3). When the expression will be cast to pointer of possible greater size: UINT32 a,b; VOID *c; c =3D (VOID *)(UINTN)(a + b); --> c =3D (VOID *)((UINTN)a + b); 4). When one side of a comparison expression contains only operands with rank less than UINT32: UINT8 a; UINT16 b; UINTN c; if ((UINTN)(a + b) > c) {...} --> if (((UINT32)a + b) > c) {...} For rule 4), if we remove the 'UINTN' type cast like: if (a + b > c) {...} The VS compiler will complain with warning C4018 (signed/unsigned mismatch, level 3 warning) due to promoting 'a + b' to type 'int'. Cc: Jeff Fan Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu Reviewed-by: Jeff Fan --- SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgent/DxeDebugAgentLib.c = | 6 +++--- SourceLevelDebugPkg/Library/DebugAgent/SecPeiDebugAgent/SecPeiDebugAgentLi= b.c | 8 ++++---- SourceLevelDebugPkg/Library/DebugAgent/SmmDebugAgent/SmmDebugAgentLib.c = | 6 +++--- SourceLevelDebugPkg/Library/DebugCommunicationLibUsb/DebugCommunicationLib= Usb.c | 18 +++++++++--------- 4 files changed, 19 insertions(+), 19 deletions(-) diff --git a/SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgent/DxeDebugA= gentLib.c b/SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgent/DxeDebugAg= entLib.c index a63932c..c74a1f6 100644 --- a/SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgent/DxeDebugAgentLib= .c +++ b/SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgent/DxeDebugAgentLib= .c @@ -1,7 +1,7 @@ /** @file Debug Agent library implementition for Dxe Core and Dxr modules. =20 - Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.
+ Copyright (c) 2010 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License which accompanies this distribution. The full text of the license may b= e found at @@ -512,8 +512,8 @@ InitializeDebugAgent ( if (Context !=3D NULL) { Ia32Idtr =3D (IA32_DESCRIPTOR *) Context; Ia32IdtEntry =3D (IA32_IDT_ENTRY *)(Ia32Idtr->Base); - MailboxLocation =3D (UINT64 *) (UINTN) (Ia32IdtEntry[DEBUG_MAILBOX_V= ECTOR].Bits.OffsetLow + - (UINT32) (Ia32IdtEntry[DEBUG_MAILBOX_VEC= TOR].Bits.OffsetHigh << 16)); + MailboxLocation =3D (UINT64 *) ((UINTN) Ia32IdtEntry[DEBUG_MAILBOX_V= ECTOR].Bits.OffsetLow + + ((UINTN) Ia32IdtEntry[DEBUG_MAILBOX_VEC= TOR].Bits.OffsetHigh << 16)); Mailbox =3D (DEBUG_AGENT_MAILBOX *)(UINTN)(*MailboxLocation); VerifyMailboxChecksum (Mailbox); } diff --git a/SourceLevelDebugPkg/Library/DebugAgent/SecPeiDebugAgent/SecPei= DebugAgentLib.c b/SourceLevelDebugPkg/Library/DebugAgent/SecPeiDebugAgent/S= ecPeiDebugAgentLib.c index 128c69f..b717e33 100644 --- a/SourceLevelDebugPkg/Library/DebugAgent/SecPeiDebugAgent/SecPeiDebugAg= entLib.c +++ b/SourceLevelDebugPkg/Library/DebugAgent/SecPeiDebugAgent/SecPeiDebugAg= entLib.c @@ -1,7 +1,7 @@ /** @file SEC Core Debug Agent Library instance implementition. =20 - Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.
+ Copyright (c) 2010 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License which accompanies this distribution. The full text of the license may b= e found at @@ -213,7 +213,7 @@ GetMailboxPointer ( // Fix up Debug Port handler and save new mailbox in IDT entry // Mailbox =3D (DEBUG_AGENT_MAILBOX *)((UINTN)Mailbox + ((UINTN)(MailboxL= ocationInHob) - (UINTN)MailboxLocationInIdt)); - DebugPortHandle =3D (UINT64)((UINTN)Mailbox->DebugPortHandle + ((UINTN= )(MailboxLocationInHob) - (UINTN)MailboxLocationInIdt)); + DebugPortHandle =3D (UINTN)Mailbox->DebugPortHandle + ((UINTN)(Mailbox= LocationInHob) - (UINTN)MailboxLocationInIdt); UpdateMailboxContent (Mailbox, DEBUG_MAILBOX_DEBUG_PORT_HANDLE_INDEX, = DebugPortHandle); *MailboxLocationInHob =3D (UINT64)(UINTN)Mailbox; SetLocationSavedMailboxPointerInIdtEntry (MailboxLocationInHob); @@ -582,8 +582,8 @@ InitializeDebugAgent ( } else { Ia32Idtr =3D (IA32_DESCRIPTOR *) Context; Ia32IdtEntry =3D (IA32_IDT_ENTRY *)(Ia32Idtr->Base); - MailboxLocationPointer =3D (UINT64 *) (UINTN) (Ia32IdtEntry[DEBUG_MA= ILBOX_VECTOR].Bits.OffsetLow + - (UINT32) (Ia32IdtEntry[DEBUG_MAIL= BOX_VECTOR].Bits.OffsetHigh << 16)); + MailboxLocationPointer =3D (UINT64 *) ((UINTN) Ia32IdtEntry[DEBUG_MA= ILBOX_VECTOR].Bits.OffsetLow + + ((UINTN) Ia32IdtEntry[DEBUG_MAIL= BOX_VECTOR].Bits.OffsetHigh << 16)); Mailbox =3D (DEBUG_AGENT_MAILBOX *) (UINTN)(*MailboxLocationPointer); // // Mailbox should valid and setup before executing thunk code diff --git a/SourceLevelDebugPkg/Library/DebugAgent/SmmDebugAgent/SmmDebugA= gentLib.c b/SourceLevelDebugPkg/Library/DebugAgent/SmmDebugAgent/SmmDebugAg= entLib.c index 6216142..11afd32 100644 --- a/SourceLevelDebugPkg/Library/DebugAgent/SmmDebugAgent/SmmDebugAgentLib= .c +++ b/SourceLevelDebugPkg/Library/DebugAgent/SmmDebugAgent/SmmDebugAgentLib= .c @@ -1,7 +1,7 @@ /** @file Debug Agent library implementition. =20 - Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2010 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License which accompanies this distribution. The full text of the license may b= e found at @@ -336,8 +336,8 @@ InitializeDebugAgent ( } else { Ia32Idtr =3D (IA32_DESCRIPTOR *) Context; Ia32IdtEntry =3D (IA32_IDT_ENTRY *)(Ia32Idtr->Base); - MailboxLocation =3D (UINT64 *) (UINTN) (Ia32IdtEntry[DEBUG_MAILBOX_V= ECTOR].Bits.OffsetLow +=20 - (UINT32) (Ia32IdtEntry[DEBUG_MAILBOX_VEC= TOR].Bits.OffsetHigh << 16)); + MailboxLocation =3D (UINT64 *) ((UINTN) Ia32IdtEntry[DEBUG_MAILBOX_V= ECTOR].Bits.OffsetLow + + ((UINTN) Ia32IdtEntry[DEBUG_MAILBOX_VEC= TOR].Bits.OffsetHigh << 16)); mMailboxPointer =3D (DEBUG_AGENT_MAILBOX *)(UINTN)(*MailboxLocation); VerifyMailboxChecksum (mMailboxPointer); // diff --git a/SourceLevelDebugPkg/Library/DebugCommunicationLibUsb/DebugComm= unicationLibUsb.c b/SourceLevelDebugPkg/Library/DebugCommunicationLibUsb/De= bugCommunicationLibUsb.c index d7829c2..d996f80 100644 --- a/SourceLevelDebugPkg/Library/DebugCommunicationLibUsb/DebugCommunicati= onLibUsb.c +++ b/SourceLevelDebugPkg/Library/DebugCommunicationLibUsb/DebugCommunicati= onLibUsb.c @@ -1,7 +1,7 @@ /** @file Debug Port Library implementation based on usb debug port. =20 - Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.
+ Copyright (c) 2010 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License which accompanies this distribution. The full text of the license may b= e found at @@ -559,7 +559,7 @@ NeedReinitializeHardware( // // If the owner and in_use bit is not set, it means system is doing cold= /warm boot or EHCI host controller is reset by system software. // - UsbDebugPortRegister =3D (USB_DEBUG_PORT_REGISTER *)(UINTN)(Handle->UsbD= ebugPortMemoryBase + Handle->DebugPortOffset); + UsbDebugPortRegister =3D (USB_DEBUG_PORT_REGISTER *)((UINTN)Handle->UsbD= ebugPortMemoryBase + Handle->DebugPortOffset); if ((MmioRead32((UINTN)&UsbDebugPortRegister->ControlStatus) & (USB_DEBU= G_PORT_OWNER | USB_DEBUG_PORT_ENABLE | USB_DEBUG_PORT_IN_USE)) !=3D (USB_DEBUG_PORT_OWNER | USB_DEBUG_PORT_ENABLE | USB_DEBUG_PORT= _IN_USE)) { Status =3D TRUE; @@ -604,10 +604,10 @@ InitializeUsbDebugHardware ( UINT8 DebugPortNumber; UINT8 Length; =20 - UsbDebugPortRegister =3D (USB_DEBUG_PORT_REGISTER *)(UINTN)(Handle->UsbD= ebugPortMemoryBase + Handle->DebugPortOffset); - UsbHCSParam =3D (UINT32 *)(UINTN)(Handle->EhciMemoryBase + 0x04); - UsbCmd =3D (UINT32 *)(UINTN)(Handle->EhciMemoryBase + 0x20); - UsbStatus =3D (UINT32 *)(UINTN)(Handle->EhciMemoryBase + 0x24); + UsbDebugPortRegister =3D (USB_DEBUG_PORT_REGISTER *)((UINTN)Handle->UsbD= ebugPortMemoryBase + Handle->DebugPortOffset); + UsbHCSParam =3D (UINT32 *)((UINTN)Handle->EhciMemoryBase + 0x04); + UsbCmd =3D (UINT32 *)((UINTN)Handle->EhciMemoryBase + 0x20); + UsbStatus =3D (UINT32 *)((UINTN)Handle->EhciMemoryBase + 0x24); =20 // // Check if the debug port is enabled and owned by myself. @@ -652,7 +652,7 @@ InitializeUsbDebugHardware ( // // Should find a device is connected at debug port // - PortStatus =3D (UINT32 *)(UINTN)(Handle->EhciMemoryBase + 0x64 + (DebugP= ortNumber - 1) * 4); + PortStatus =3D (UINT32 *)((UINTN)Handle->EhciMemoryBase + 0x64 + (DebugP= ortNumber - 1) * 4); if (!(MmioRead32((UINTN)PortStatus) & BIT0)) { Handle->Initialized =3D USBDBG_NO_DEV; return RETURN_NOT_FOUND; @@ -870,7 +870,7 @@ DebugPortWriteBuffer ( } } =20 - UsbDebugPortRegister =3D (USB_DEBUG_PORT_REGISTER *)(UINTN)(UsbDebugPort= Handle->UsbDebugPortMemoryBase + UsbDebugPortHandle->DebugPortOffset); + UsbDebugPortRegister =3D (USB_DEBUG_PORT_REGISTER *)((UINTN)UsbDebugPort= Handle->UsbDebugPortMemoryBase + UsbDebugPortHandle->DebugPortOffset); =20 while ((Total < NumberOfBytes)) { if (NumberOfBytes - Total > USB_DEBUG_PORT_MAX_PACKET_SIZE) { @@ -950,7 +950,7 @@ DebugPortPollBuffer ( return TRUE; } =20 - UsbDebugPortRegister =3D (USB_DEBUG_PORT_REGISTER *)(UINTN)(UsbDebugPort= Handle->UsbDebugPortMemoryBase + UsbDebugPortHandle->DebugPortOffset); + UsbDebugPortRegister =3D (USB_DEBUG_PORT_REGISTER *)((UINTN)UsbDebugPort= Handle->UsbDebugPortMemoryBase + UsbDebugPortHandle->DebugPortOffset); =20 UsbDebugPortRegister->TokenPid =3D INPUT_PID; if (UsbDebugPortHandle->BulkInToggle =3D=3D 0) { --=20 1.9.5.msysgit.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat Nov 2 14:41:02 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zoho.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1487999604783214.13084527061926; Fri, 24 Feb 2017 21:13:24 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 926A9821BB; Fri, 24 Feb 2017 21:13:05 -0800 (PST) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 99DC68219F for ; Fri, 24 Feb 2017 21:13:04 -0800 (PST) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Feb 2017 21:13:04 -0800 Received: from shwdeopenpsi014.ccr.corp.intel.com ([10.239.9.13]) by orsmga002.jf.intel.com with ESMTP; 24 Feb 2017 21:13:03 -0800 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.35,202,1484035200"; d="scan'208";a="52624071" From: Hao Wu To: edk2-devel@lists.01.org Date: Sat, 25 Feb 2017 13:12:35 +0800 Message-Id: <1487999555-9764-13-git-send-email-hao.a.wu@intel.com> X-Mailer: git-send-email 1.9.5.msysgit.0 In-Reply-To: <1487999555-9764-1-git-send-email-hao.a.wu@intel.com> References: <1487999555-9764-1-git-send-email-hao.a.wu@intel.com> Subject: [edk2] [PATCH v3 12/12] UefiCpuPkg: Refine casting expression result to bigger size X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Hao Wu , Jeff Fan MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" There are cases that the operands of an expression are all with rank less than UINT64/INT64 and the result of the expression is explicitly cast to UINT64/INT64 to fit the target size. An example will be: UINT32 a,b; // a and b can be any unsigned int type with rank less than UINT64, like // UINT8, UINT16, etc. UINT64 c; c =3D (UINT64) (a + b); Some static code checkers may warn that the expression result might overflow within the rank of "int" (integer promotions) and the result is then cast to a bigger size. The commit refines codes by the following rules: 1). When the expression is possible to overflow the range of unsigned int/ int: c =3D (UINT64)a + b; 2). When the expression will not overflow within the rank of "int", remove the explicit type casts: c =3D a + b; 3). When the expression will be cast to pointer of possible greater size: UINT32 a,b; VOID *c; c =3D (VOID *)(UINTN)(a + b); --> c =3D (VOID *)((UINTN)a + b); 4). When one side of a comparison expression contains only operands with rank less than UINT32: UINT8 a; UINT16 b; UINTN c; if ((UINTN)(a + b) > c) {...} --> if (((UINT32)a + b) > c) {...} For rule 4), if we remove the 'UINTN' type cast like: if (a + b > c) {...} The VS compiler will complain with warning C4018 (signed/unsigned mismatch, level 3 warning) due to promoting 'a + b' to type 'int'. Cc: Jeff Fan Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu Reviewed-by: Jeff Fan --- UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.c | 4 ++-- UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.c | 4 ++-- UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c | 8 ++++---- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 4 ++-- UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c | 6 +++--- 5 files changed, 13 insertions(+), 13 deletions(-) diff --git a/UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.c b/UefiCpuPkg/CpuIo2Dxe/CpuIo2= Dxe.c index 60f4bbc..d19349d 100644 --- a/UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.c +++ b/UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.c @@ -1,7 +1,7 @@ /** @file Produces the CPU I/O 2 Protocol. =20 -Copyright (c) 2009 - 2012, Intel Corporation. All rights reserved.
+Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.
Copyright (c) 2017, AMD Incorporated. All rights reserved.
=20 This program and the accompanying materials =20 @@ -141,7 +141,7 @@ CpuIoCheckParameter ( // // Check to see if Address is aligned // - if ((Address & (UINT64)(mInStride[Width] - 1)) !=3D 0) { + if ((Address & ((UINT64)mInStride[Width] - 1)) !=3D 0) { return EFI_UNSUPPORTED; } =20 diff --git a/UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.c b/UefiCpuPkg/CpuIo2Smm/CpuIo2= Smm.c index 7b1ad37..20b8350 100644 --- a/UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.c +++ b/UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.c @@ -1,7 +1,7 @@ /** @file Produces the SMM CPU I/O Protocol. =20 -Copyright (c) 2009 - 2012, Intel Corporation. All rights reserved.
+Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials =20 are licensed and made available under the terms and conditions of the BSD = License =20 which accompanies this distribution. The full text of the license may be = found at =20 @@ -126,7 +126,7 @@ CpuIoCheckParameter ( // // Check to see if Address is aligned // - if ((Address & (UINT64)(mStride[Width] - 1)) !=3D 0) { + if ((Address & ((UINT64)mStride[Width] - 1)) !=3D 0) { return EFI_UNSUPPORTED; } =20 diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c b/UefiCpuPkg/Lib= rary/SmmCpuFeaturesLib/SmmStm.c index bb123ba..03937dc 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c @@ -1,7 +1,7 @@ /** @file SMM STM support functions =20 - Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License which accompanies this distribution. The full text of the license may b= e found at @@ -276,8 +276,8 @@ SmmCpuFeaturesInstallSmiHandler ( UINT32 RegEdx; EFI_PROCESSOR_INFORMATION ProcessorInfo; =20 - CopyMem ((VOID *)(UINTN)(SmBase + TXT_SMM_PSD_OFFSET), &gcStmPsd, sizeof= (gcStmPsd)); - Psd =3D (TXT_PROCESSOR_SMM_DESCRIPTOR *)(VOID *)(UINTN)(SmBase + TXT_SMM= _PSD_OFFSET); + CopyMem ((VOID *)((UINTN)SmBase + TXT_SMM_PSD_OFFSET), &gcStmPsd, sizeof= (gcStmPsd)); + Psd =3D (TXT_PROCESSOR_SMM_DESCRIPTOR *)(VOID *)((UINTN)SmBase + TXT_SMM= _PSD_OFFSET); Psd->SmmGdtPtr =3D GdtBase; Psd->SmmGdtSize =3D (UINT32)GdtSize; =20 @@ -317,7 +317,7 @@ SmmCpuFeaturesInstallSmiHandler ( // Copy template to CPU specific SMI handler location // CopyMem ( - (VOID*)(UINTN)(SmBase + SMM_HANDLER_OFFSET), + (VOID*)((UINTN)SmBase + SMM_HANDLER_OFFSET), (VOID*)gcStmSmiHandlerTemplate, gcStmSmiHandlerSize ); diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c b/UefiCpuPkg/PiSmmC= puDxeSmm/PiSmmCpuDxeSmm.c index fc7714a..2519e28 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c @@ -1,7 +1,7 @@ /** @file Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU. =20 -Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License which accompanies this distribution. The full text of the license may be = found at @@ -1268,7 +1268,7 @@ AllocateAlignedCodePages ( Status =3D gSmst->SmmFreePages (Memory, UnalignedPages); ASSERT_EFI_ERROR (Status); } - Memory =3D (EFI_PHYSICAL_ADDRESS) (AlignedMemory + EFI_PAGES_T= O_SIZE (Pages)); + Memory =3D AlignedMemory + EFI_PAGES_TO_SIZE (Pages); UnalignedPages =3D RealPages - Pages - UnalignedPages; if (UnalignedPages > 0) { // diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c b/UefiCpuPkg/PiSmmC= puDxeSmm/SmramSaveState.c index b4bc0ec..3188d43 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c @@ -1,7 +1,7 @@ /** @file Provides services to access SMRAM Save State Map =20 -Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2010 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License which accompanies this distribution. The full text of the license may be = found at @@ -690,7 +690,7 @@ InstallSmiHandler ( // // Initialize PROCESSOR_SMM_DESCRIPTOR // - Psd =3D (PROCESSOR_SMM_DESCRIPTOR *)(VOID *)(UINTN)(SmBase + SMM_PSD_OFF= SET); + Psd =3D (PROCESSOR_SMM_DESCRIPTOR *)(VOID *)((UINTN)SmBase + SMM_PSD_OFF= SET); CopyMem (Psd, &gcPsd, sizeof (gcPsd)); Psd->SmmGdtPtr =3D (UINT64)GdtBase; Psd->SmmGdtSize =3D (UINT32)GdtSize; @@ -731,7 +731,7 @@ InstallSmiHandler ( // Copy template to CPU specific SMI handler location // CopyMem ( - (VOID*)(UINTN)(SmBase + SMM_HANDLER_OFFSET), + (VOID*)((UINTN)SmBase + SMM_HANDLER_OFFSET), (VOID*)gcSmiHandlerTemplate, gcSmiHandlerSize ); --=20 1.9.5.msysgit.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel