From nobody Sat Nov 2 16:23:46 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zoho.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1487756321182667.4802147252032; Wed, 22 Feb 2017 01:38:41 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 167768224C; Wed, 22 Feb 2017 01:38:40 -0800 (PST) Received: from mail-wm0-x232.google.com (mail-wm0-x232.google.com [IPv6:2a00:1450:400c:c09::232]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 059B08224C for ; Wed, 22 Feb 2017 01:38:38 -0800 (PST) Received: by mail-wm0-x232.google.com with SMTP id r141so6493762wmg.1 for ; Wed, 22 Feb 2017 01:38:37 -0800 (PST) Received: from localhost.localdomain ([160.163.32.105]) by smtp.gmail.com with ESMTPSA id c36sm976544wrc.49.2017.02.22.01.38.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 22 Feb 2017 01:38:35 -0800 (PST) X-Original-To: edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=dB2/gmjxDiXfuhv7aqOGbB2K+a1YBbFPm48PkW26zaY=; b=eJGK0XX+fjfVFoxNtbSLNvD19yAr+aR8OFmj69GIOzn23h2xPKnzzyNEwvZkuW8s4T sNl9gCreZjbGs/9viFhC02IwhC93tN6iOmZ4myBRZG9dWEw3hr6500IkzXftw/BacFrO IFGZyqzpb9WYDl5W07wj6iouGOwTtc+nP9XAc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=dB2/gmjxDiXfuhv7aqOGbB2K+a1YBbFPm48PkW26zaY=; b=Alq2pCjCpHJfDq2JKnuKFyEHWAPknooqjkKbgqk57flc6rHm2pEiQaf+npRVgiwqGk krrcdRsXNXoVL7MjzUtCaNWZXBNfJZNBukKxsU2bF1VuPKFerB4LQNEEPVbErzsBfUEq 4Fdp0nc6f3S6kqjDwp3MmyepKy19Xjnl68RBf1Rl6P8WM8I4/e7ZmerNYSIh+MVR1NpJ 9yjzSnRI+kCgQlITV/QgXVcLPcrIsdLkbiwPlEFhuhMmhAzdQAw+/Fu9GiL5ns6B0HNG lu/M263NgTSQyZCZc1uWTyKXD95WF5C4HCiMa4cFZZbZDpQbPieUNsB3YK2fA5ojDeiL ShOQ== X-Gm-Message-State: AMke39ndTiuyf8UX168i8c69qA02bR9iPYI7N1qLvm9zlSUiqydn96rIJmo+FqwFUVnJ89LN X-Received: by 10.28.35.142 with SMTP id j136mr1448401wmj.11.1487756316618; Wed, 22 Feb 2017 01:38:36 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org, leif.lindholm@linaro.org Date: Wed, 22 Feb 2017 09:38:21 +0000 Message-Id: <1487756301-15646-5-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1487756301-15646-1-git-send-email-ard.biesheuvel@linaro.org> References: <1487756301-15646-1-git-send-email-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH 4/4] ArmPkg/ArmMmuLib: AARCH64: enable stack alignment checking X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: heyi.guo@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Enable the hardware stack alignment check, as mandated by the UEFI spec. This ensures that the stack pointer is 16 byte aligned at each instance where it is used as the base address in a load/store operation. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c | 1 + 1 file changed, 1 insertion(+) diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/ArmPkg/Libr= ary/ArmMmuLib/AArch64/ArmMmuLibCore.c index 9e0593ce598b..2f8f99d44a31 100644 --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c @@ -734,6 +734,7 @@ ArmConfigureMmu ( MAIR_ATTR(TT_ATTR_INDX_MEMORY_WRITE_BACK, MAIR_ATTR_NORMAL_M= EMORY_WRITE_BACK)); // mapped to EFI_MEMORY_WB =20 ArmDisableAlignmentCheck (); + ArmEnableStackAlignmentCheck (); ArmEnableInstructionCache (); ArmEnableDataCache (); =20 --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel