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20:p/BD3UIhW7oWr0cxtltaVyMrDURSsa8CGRoc3eeZTQ9uC0vPM3BTALboS/e2lQIEYKSpRPHTR487n39bF27+C8ItPbL3NSFhEze4UmqRM5J/Lm92zEh0OGLeHFKF1IFTmE2N+PzCrU+N4EBk1X4il23KeAYKIxy1LgLCUvStywfu/u1Ea76xFIV7u1ansGq3J2EBOzp0lGlAPk6hbFKUbWEM5FA57sBvLCdolzC1WRogjIP/ewJJISlwj3mi71RC X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Feb 2017 21:02:28.7437 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR12MB1236 Subject: [edk2] [PATCH v3 3/4] UefiCpuPkg/Universal/Acpi/S3Resume2Pei: Add support for PCD PcdPteMemoryEncryptionAddressOrMask X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Feng Tian , Brijesh Singh , Leo Duran , Laszlo Ersek , Jeff Fan , Star Zeng Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This PCD holds the address mask for page table entries when memory encryption is enabled on AMD processors supporting the Secure Encrypted Virtualization (SEV) feature. The mask is applied when page tables are created (S3Resume.c). CC: Jeff Fan Cc: Feng Tian Cc: Star Zeng Cc: Laszlo Ersek Cc: Brijesh Singh Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leo Duran Reviewed-by: Star Zeng --- UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c | 16 ++++++++++++-= --- UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf | 2 ++ 2 files changed, 14 insertions(+), 4 deletions(-) diff --git a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c b/UefiCpuPkg= /Universal/Acpi/S3Resume2Pei/S3Resume.c index d306fba..3701957 100644 --- a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c +++ b/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c @@ -5,6 +5,7 @@ control is passed to OS waking up handler. =20 Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2017, AMD Incorporated. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions @@ -58,6 +59,10 @@ #define STACK_ALIGN_DOWN(Ptr) \ ((UINTN)(Ptr) & ~(UINTN)(CPU_STACK_ALIGNMENT - 1)) =20 +#define PAGING_4K_ADDRESS_MASK_64 0x000FFFFFFFFFF000ull +#define PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull +#define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull + #pragma pack(1) typedef union { struct { @@ -614,6 +619,7 @@ RestoreS3PageTables ( VOID *Hob; BOOLEAN Page1GSupport; PAGE_TABLE_1G_ENTRY *PageDirectory1GEntry; + UINT64 AddressSetMask; =20 // // NOTE: We have to ASSUME the page table generation format, because w= e do not know whole page table information. @@ -682,6 +688,8 @@ RestoreS3PageTables ( NumberOfPml4EntriesNeeded =3D (UINT32)LShiftU64 (1, (PhysicalAddress= Bits - 39)); NumberOfPdpEntriesNeeded =3D 512; } + + AddressSetMask =3D PcdGet64 (PcdPteMemoryEncryptionAddressOrMask); =20 PageMapLevel4Entry =3D PageMap; PageAddress =3D 0; @@ -696,7 +704,7 @@ RestoreS3PageTables ( // // Make a PML4 Entry // - PageMapLevel4Entry->Uint64 =3D (UINT64)(UINTN)PageDirectoryPointerEn= try; + PageMapLevel4Entry->Uint64 =3D (UINT64)(UINTN)PageDirectoryPointerEn= try | (AddressSetMask & PAGING_4K_ADDRESS_MASK_64); PageMapLevel4Entry->Bits.ReadWrite =3D 1; PageMapLevel4Entry->Bits.Present =3D 1; =20 @@ -707,7 +715,7 @@ RestoreS3PageTables ( // // Fill in the Page Directory entries // - PageDirectory1GEntry->Uint64 =3D (UINT64)PageAddress; + PageDirectory1GEntry->Uint64 =3D (UINT64)PageAddress | (AddressS= etMask & PAGING_1G_ADDRESS_MASK_64); PageDirectory1GEntry->Bits.ReadWrite =3D 1; PageDirectory1GEntry->Bits.Present =3D 1; PageDirectory1GEntry->Bits.MustBe1 =3D 1; @@ -724,7 +732,7 @@ RestoreS3PageTables ( // // Fill in a Page Directory Pointer Entries // - PageDirectoryPointerEntry->Uint64 =3D (UINT64)(UINTN)PageDirecto= ryEntry; + PageDirectoryPointerEntry->Uint64 =3D (UINT64)(UINTN)PageDirecto= ryEntry | (AddressSetMask & PAGING_4K_ADDRESS_MASK_64); PageDirectoryPointerEntry->Bits.ReadWrite =3D 1; PageDirectoryPointerEntry->Bits.Present =3D 1; =20 @@ -732,7 +740,7 @@ RestoreS3PageTables ( // // Fill in the Page Directory entries // - PageDirectoryEntry->Uint64 =3D (UINT64)PageAddress; + PageDirectoryEntry->Uint64 =3D (UINT64)PageAddress | (AddressS= etMask & PAGING_2M_ADDRESS_MASK_64); PageDirectoryEntry->Bits.ReadWrite =3D 1; PageDirectoryEntry->Bits.Present =3D 1; PageDirectoryEntry->Bits.MustBe1 =3D 1; diff --git a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf b/Uefi= CpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf index 73aeca3..d514523 100644 --- a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf +++ b/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf @@ -6,6 +6,7 @@ # control is passed to OS waking up handler. # # Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.
+# Copyright (c) 2017, AMD Incorporated. All rights reserved.
# # This program and the accompanying materials are # licensed and made available under the terms and conditions of the BSD Li= cense @@ -91,6 +92,7 @@ =20 [Pcd] gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable ## SOMETIMES_CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask ##= CONSUMES =20 [Depex] TRUE --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel