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20:8+CP2Rbd56OJnOUDj0gzFn6bMSRuNNeh1mrTEm0LuhR/zLvS6dLATZdvdeY60X9/vmq9aoJwigqEje58gwWfR9M+1nhbJZIx0FV2T3RGHotNpk/lD3fsC9IP3l/KJ0XodxpSP8ntYMpDgVn5V1c3shvXazTTVHkUeS2xiQSwZ4iLxiuKmnbnZ1u51AHcuX0XtnpYXrqen6ZRhEiJJnX4nZHAnDM1O6mwFpVEZ16HK4p+KozPIJ11AjzoF53P1+6q X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Feb 2017 21:02:26.6169 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR12MB1236 Subject: [edk2] [PATCH v3 1/4] MdeModulePkg: Add PCD PcdPteMemoryEncryptionAddressOrMask X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laszlo Ersek , Feng Tian , Leo Duran , Brijesh Singh , Star Zeng Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This PCD holds the address mask for page table entries when memory encryption is enabled on AMD processors supporting the Secure Encrypted Virtualization (SEV) feature. Cc: Feng Tian Cc: Star Zeng Cc: Laszlo Ersek Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Brijesh Singh Signed-off-by: Leo Duran Reviewed-by: Star Zeng --- MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf | 5 +++- MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c | 29 +++++++++++++++++---= ---- MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h | 6 +++++ MdeModulePkg/MdeModulePkg.dec | 8 +++++++ 4 files changed, 39 insertions(+), 9 deletions(-) diff --git a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf b/MdeModulePkg/Core/Dx= eIplPeim/DxeIpl.inf index 2bc41be..d62bd9b 100644 --- a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf +++ b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf @@ -6,6 +6,8 @@ # needed to run the DXE Foundation. # # Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+# Copyright (c) 2017, AMD Incorporated. All rights reserved.
+# # This program and the accompanying materials # are licensed and made available under the terms and conditions of the B= SD License # which accompanies this distribution. The full text of the license may = be found at @@ -111,7 +113,8 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSupportUefiDecompress ## CONSUMES =20 [Pcd.IA32,Pcd.X64] - gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable ## SOMETIM= ES_CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable ##= SOMETIMES_CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask ##= CONSUMES =20 [Pcd.IA32,Pcd.X64,Pcd.ARM,Pcd.AARCH64] gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack ## SOMETIM= ES_CONSUMES diff --git a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c b/MdeModulePk= g/Core/DxeIplPeim/X64/VirtualMemory.c index 790f6ab..89b116a 100644 --- a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c +++ b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c @@ -16,6 +16,8 @@ 3) IA-32 Intel(R) Architecture Software Developer's Manual Volume 3:Sy= stem Programmer's Guide, Intel =20 Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2017, AMD Incorporated. All rights reserved.
+ This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License which accompanies this distribution. The full text of the license may be = found at @@ -65,20 +67,24 @@ Split2MPageTo4K ( EFI_PHYSICAL_ADDRESS PhysicalAddress4K; UINTN IndexOfPageTableEntries; PAGE_TABLE_4K_ENTRY *PageTableEntry; + UINT64 AddressSetMask; =20 PageTableEntry =3D AllocatePages (1); ASSERT (PageTableEntry !=3D NULL); + + AddressSetMask =3D PcdGet64 (PcdPteMemoryEncryptionAddressOrMask); + // // Fill in 2M page entry. // - *PageEntry2M =3D (UINT64) (UINTN) PageTableEntry | IA32_PG_P | IA32_PG_R= W; + *PageEntry2M =3D (UINT64)(UINTN)PageTableEntry | (AddressSetMask & PAGIN= G_2M_ADDRESS_MASK_64) | IA32_PG_P | IA32_PG_RW; =20 PhysicalAddress4K =3D PhysicalAddress; for (IndexOfPageTableEntries =3D 0; IndexOfPageTableEntries < 512; Index= OfPageTableEntries++, PageTableEntry++, PhysicalAddress4K +=3D SIZE_4KB) { // // Fill in the Page Table entries // - PageTableEntry->Uint64 =3D (UINT64) PhysicalAddress4K; + PageTableEntry->Uint64 =3D (UINT64)PhysicalAddress4K | (AddressSetMask= & PAGING_4K_ADDRESS_MASK_64); PageTableEntry->Bits.ReadWrite =3D 1; PageTableEntry->Bits.Present =3D 1; if ((PhysicalAddress4K >=3D StackBase) && (PhysicalAddress4K < StackBa= se + StackSize)) { @@ -110,13 +116,17 @@ Split1GPageTo2M ( EFI_PHYSICAL_ADDRESS PhysicalAddress2M; UINTN IndexOfPageDirectoryEntries; PAGE_TABLE_ENTRY *PageDirectoryEntry; + UINT64 AddressSetMask; =20 PageDirectoryEntry =3D AllocatePages (1); ASSERT (PageDirectoryEntry !=3D NULL); + + AddressSetMask =3D PcdGet64 (PcdPteMemoryEncryptionAddressOrMask); + // // Fill in 1G page entry. // - *PageEntry1G =3D (UINT64) (UINTN) PageDirectoryEntry | IA32_PG_P | IA32_= PG_RW; + *PageEntry1G =3D (UINT64)(UINTN)PageDirectoryEntry | (AddressSetMask & P= AGING_1G_ADDRESS_MASK_64) | IA32_PG_P | IA32_PG_RW; =20 PhysicalAddress2M =3D PhysicalAddress; for (IndexOfPageDirectoryEntries =3D 0; IndexOfPageDirectoryEntries < 51= 2; IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PhysicalAddress2M += =3D SIZE_2MB) { @@ -129,7 +139,7 @@ Split1GPageTo2M ( // // Fill in the Page Directory entries // - PageDirectoryEntry->Uint64 =3D (UINT64) PhysicalAddress2M; + PageDirectoryEntry->Uint64 =3D (UINT64)PhysicalAddress2M | (AddressS= etMask & PAGING_2M_ADDRESS_MASK_64); PageDirectoryEntry->Bits.ReadWrite =3D 1; PageDirectoryEntry->Bits.Present =3D 1; PageDirectoryEntry->Bits.MustBe1 =3D 1; @@ -171,6 +181,7 @@ CreateIdentityMappingPageTables ( VOID *Hob; BOOLEAN Page1GSupport; PAGE_TABLE_1G_ENTRY *PageDirectory1GEntry; + UINT64 AddressSetMask; =20 Page1GSupport =3D FALSE; if (PcdGetBool(PcdUse1GPageTable)) { @@ -229,6 +240,8 @@ CreateIdentityMappingPageTables ( BigPageAddress =3D (UINTN) AllocatePages (TotalPagesNum); ASSERT (BigPageAddress !=3D 0); =20 + AddressSetMask =3D PcdGet64 (PcdPteMemoryEncryptionAddressOrMask); + // // By architecture only one PageMapLevel4 exists - so lets allocate stor= age for it. // @@ -248,7 +261,7 @@ CreateIdentityMappingPageTables ( // // Make a PML4 Entry // - PageMapLevel4Entry->Uint64 =3D (UINT64)(UINTN)PageDirectoryPointerEntr= y; + PageMapLevel4Entry->Uint64 =3D (UINT64)(UINTN)PageDirectoryPointerEntr= y | (AddressSetMask & PAGING_4K_ADDRESS_MASK_64); PageMapLevel4Entry->Bits.ReadWrite =3D 1; PageMapLevel4Entry->Bits.Present =3D 1; =20 @@ -262,7 +275,7 @@ CreateIdentityMappingPageTables ( // // Fill in the Page Directory entries // - PageDirectory1GEntry->Uint64 =3D (UINT64)PageAddress; + PageDirectory1GEntry->Uint64 =3D (UINT64)PageAddress | (AddressS= etMask & PAGING_1G_ADDRESS_MASK_64); PageDirectory1GEntry->Bits.ReadWrite =3D 1; PageDirectory1GEntry->Bits.Present =3D 1; PageDirectory1GEntry->Bits.MustBe1 =3D 1; @@ -280,7 +293,7 @@ CreateIdentityMappingPageTables ( // // Fill in a Page Directory Pointer Entries // - PageDirectoryPointerEntry->Uint64 =3D (UINT64)(UINTN)PageDirectory= Entry; + PageDirectoryPointerEntry->Uint64 =3D (UINT64)(UINTN)PageDirectory= Entry | (AddressSetMask & PAGING_4K_ADDRESS_MASK_64); PageDirectoryPointerEntry->Bits.ReadWrite =3D 1; PageDirectoryPointerEntry->Bits.Present =3D 1; =20 @@ -294,7 +307,7 @@ CreateIdentityMappingPageTables ( // // Fill in the Page Directory entries // - PageDirectoryEntry->Uint64 =3D (UINT64)PageAddress; + PageDirectoryEntry->Uint64 =3D (UINT64)PageAddress | (AddressS= etMask & PAGING_2M_ADDRESS_MASK_64); PageDirectoryEntry->Bits.ReadWrite =3D 1; PageDirectoryEntry->Bits.Present =3D 1; PageDirectoryEntry->Bits.MustBe1 =3D 1; diff --git a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h b/MdeModulePk= g/Core/DxeIplPeim/X64/VirtualMemory.h index 20c31f5..2e0691e 100644 --- a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h +++ b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h @@ -8,6 +8,8 @@ 4) AMD64 Architecture Programmer's Manual Volume 2: System Programming =20 Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.
+Copyright (c) 2017, AMD Incorporated. All rights reserved.
+ This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License which accompanies this distribution. The full text of the license may be = found at @@ -23,6 +25,10 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHE= R EXPRESS OR IMPLIED. =20 #define SYS_CODE64_SEL 0x38 =20 +#define PAGING_4K_ADDRESS_MASK_64 0x000FFFFFFFFFF000ull +#define PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull +#define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull + #pragma pack(1) =20 typedef union { diff --git a/MdeModulePkg/MdeModulePkg.dec b/MdeModulePkg/MdeModulePkg.dec index 273cd7e..15119d0 100644 --- a/MdeModulePkg/MdeModulePkg.dec +++ b/MdeModulePkg/MdeModulePkg.dec @@ -6,6 +6,8 @@ # Copyright (c) 2007 - 2017, Intel Corporation. All rights reserved.
# Copyright (c) 2016, Linaro Ltd. All rights reserved.
# (C) Copyright 2016 Hewlett Packard Enterprise Development LP
+# Copyright (c) 2017, AMD Incorporated. All rights reserved.
+# # This program and the accompanying materials are licensed and made availa= ble under # the terms and conditions of the BSD License that accompanies this distri= bution. # The full text of the license may be found at @@ -1682,6 +1684,12 @@ # @Prompt A list of system FMP ImageTypeId GUIDs gEfiMdeModulePkgTokenSpaceGuid.PcdSystemFmpCapsuleImageTypeIdGuid|{0x0}|= VOID*|0x30001046 =20 + ## This PCD holds the address mask for page table entries when memory en= cryption is + # enabled on AMD processors supporting the Secure Encrypted Virtualizat= ion (SEV) feature. + # This mask should be applied when creating 1:1 virtual to physical map= ping tables. + # + gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask|0x0|U= INT64|0x30001047 + [PcdsPatchableInModule] ## Specify memory size with page number for PEI code when # Loading Module at Fixed Address feature is enabled. --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat Nov 2 14:37:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zoho.com; 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20:iSBHlhCHPUWLpjN7XjI1Ek75RRZYYRTapeTmN0ZkJIkCeq1JPVrUujUwyMu+GPr3JDsc7NMI4zQeQP3Lt/qtIZ6e1v4shTxDsUSQ/JDrDXCKAs3CygsRwjQ0rR36Az3+rjrmFkH7H74UlzjC4vf2isEC3N+NARcjM5d9JpmilcrMjbJI5w6ZCI4ZPgOPikRTB6lWJrgHDx0wvUD8ZPfC10HFvFCFWkT4qFqjHSxwObaBEavfyake9yXXxtQTLIX7 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Feb 2017 21:02:27.4776 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR12MB1236 Subject: [edk2] [PATCH v3 2/4] MdeModulePkg/Universal/CapsulePei: Add support for PCD PcdPteMemoryEncryptionAddressOrMask X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laszlo Ersek , Feng Tian , Leo Duran , Brijesh Singh , Star Zeng Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This PCD holds the address mask for page table entries when memory encryption is enabled on AMD processors supporting the Secure Encrypted Virtualization (SEV) feature. The mask is applied when 4GB tables are created (UefiCapsule.c), and when the tables are expanded on-demand by page-faults above 4GB's (X64Entry.c). Cc: Feng Tian Cc: Star Zeng Cc: Laszlo Ersek Cc: Brijesh Singh Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leo Duran Reviewed-by: Star Zeng --- MdeModulePkg/Universal/CapsulePei/CapsulePei.inf | 2 ++ .../Universal/CapsulePei/Common/CommonHeader.h | 7 +++++++ MdeModulePkg/Universal/CapsulePei/UefiCapsule.c | 13 ++++++++---- MdeModulePkg/Universal/CapsulePei/X64/X64Entry.c | 23 +++++++++++++++---= ---- 4 files changed, 34 insertions(+), 11 deletions(-) diff --git a/MdeModulePkg/Universal/CapsulePei/CapsulePei.inf b/MdeModulePk= g/Universal/CapsulePei/CapsulePei.inf index d2ca0d0..c54bc21 100644 --- a/MdeModulePkg/Universal/CapsulePei/CapsulePei.inf +++ b/MdeModulePkg/Universal/CapsulePei/CapsulePei.inf @@ -7,6 +7,7 @@ # buffer overflow, integer overflow. # # Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+# Copyright (c) 2017, AMD Incorporated. All rights reserved.
# # This program and the accompanying materials # are licensed and made available under the terms and conditions @@ -76,6 +77,7 @@ [Pcd.IA32] gEfiMdeModulePkgTokenSpaceGuid.PcdCapsuleCoalesceFile ## SOMETIMES_C= ONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable ## SOMETIMES_C= ONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask ##= CONSUMES =20 [FeaturePcd.IA32] gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode ## CONSUMES diff --git a/MdeModulePkg/Universal/CapsulePei/Common/CommonHeader.h b/MdeM= odulePkg/Universal/CapsulePei/Common/CommonHeader.h index 7298874..0a9761e 100644 --- a/MdeModulePkg/Universal/CapsulePei/Common/CommonHeader.h +++ b/MdeModulePkg/Universal/CapsulePei/Common/CommonHeader.h @@ -2,6 +2,8 @@ Common header file. =20 Copyright (c) 2011 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2017, AMD Incorporated. All rights reserved.
+ This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License which accompanies this distribution. The full text of the license may be = found at @@ -20,6 +22,10 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHE= R EXPRESS OR IMPLIED. // #define EXTRA_PAGE_TABLE_PAGES 8 =20 +#define PAGING_4K_ADDRESS_MASK_64 0x000FFFFFFFFFF000ull +#define PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull +#define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull + // // This capsule PEIM puts its private data at the start of the // coalesced capsule. Here's the structure definition. @@ -60,6 +66,7 @@ typedef struct { EFI_PHYSICAL_ADDRESS MemoryBase64Ptr; EFI_PHYSICAL_ADDRESS MemorySize64Ptr; BOOLEAN Page1GSupport; + UINT64 PteMemoryEncryptionAddressOrMask; } SWITCH_32_TO_64_CONTEXT; =20 typedef struct { diff --git a/MdeModulePkg/Universal/CapsulePei/UefiCapsule.c b/MdeModulePkg= /Universal/CapsulePei/UefiCapsule.c index 9ac9d22..7c651f6 100644 --- a/MdeModulePkg/Universal/CapsulePei/UefiCapsule.c +++ b/MdeModulePkg/Universal/CapsulePei/UefiCapsule.c @@ -2,6 +2,7 @@ Capsule update PEIM for UEFI2.0 =20 Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2017, AMD Incorporated. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions @@ -145,6 +146,7 @@ Create4GPageTables ( PAGE_TABLE_ENTRY *PageDirectoryEntry; UINTN BigPageAddress; PAGE_TABLE_1G_ENTRY *PageDirectory1GEntry; + UINT64 AddressSetMask; =20 // // Create 4G page table by default, @@ -168,6 +170,8 @@ Create4GPageTables ( // BigPageAddress =3D (UINTN) PageTablesAddress; =20 + AddressSetMask =3D PcdGet64 (PcdPteMemoryEncryptionAddressOrMask); + // // By architecture only one PageMapLevel4 exists - so lets allocate stor= age for it. // @@ -187,7 +191,7 @@ Create4GPageTables ( // // Make a PML4 Entry // - PageMapLevel4Entry->Uint64 =3D (UINT64)(UINTN)PageDirectoryPointerEntr= y; + PageMapLevel4Entry->Uint64 =3D (UINT64)(UINTN)PageDirectoryPointerEntr= y | (AddressSetMask & PAGING_4K_ADDRESS_MASK_64); PageMapLevel4Entry->Bits.ReadWrite =3D 1; PageMapLevel4Entry->Bits.Present =3D 1; =20 @@ -198,7 +202,7 @@ Create4GPageTables ( // // Fill in the Page Directory entries // - PageDirectory1GEntry->Uint64 =3D (UINT64)PageAddress; + PageDirectory1GEntry->Uint64 =3D (UINT64)PageAddress | (AddressSet= Mask & PAGING_1G_ADDRESS_MASK_64); PageDirectory1GEntry->Bits.ReadWrite =3D 1; PageDirectory1GEntry->Bits.Present =3D 1; PageDirectory1GEntry->Bits.MustBe1 =3D 1; @@ -215,7 +219,7 @@ Create4GPageTables ( // // Fill in a Page Directory Pointer Entries // - PageDirectoryPointerEntry->Uint64 =3D (UINT64)(UINTN)PageDirectory= Entry; + PageDirectoryPointerEntry->Uint64 =3D (UINT64)(UINTN)PageDirectory= Entry | (AddressSetMask & PAGING_4K_ADDRESS_MASK_64); PageDirectoryPointerEntry->Bits.ReadWrite =3D 1; PageDirectoryPointerEntry->Bits.Present =3D 1; =20 @@ -223,7 +227,7 @@ Create4GPageTables ( // // Fill in the Page Directory entries // - PageDirectoryEntry->Uint64 =3D (UINT64)PageAddress; + PageDirectoryEntry->Uint64 =3D (UINT64)PageAddress | (AddressSet= Mask & PAGING_2M_ADDRESS_MASK_64); PageDirectoryEntry->Bits.ReadWrite =3D 1; PageDirectoryEntry->Bits.Present =3D 1; PageDirectoryEntry->Bits.MustBe1 =3D 1; @@ -443,6 +447,7 @@ ModeSwitch ( Context.MemoryBase64Ptr =3D (EFI_PHYSICAL_ADDRESS)(UINTN)&MemoryBa= se64; Context.MemorySize64Ptr =3D (EFI_PHYSICAL_ADDRESS)(UINTN)&MemorySi= ze64; Context.Page1GSupport =3D Page1GSupport; + Context.PteMemoryEncryptionAddressOrMask =3D PcdGet64 (PcdPteMemoryEncry= ptionAddressOrMask); =20 // // Prepare data for return back diff --git a/MdeModulePkg/Universal/CapsulePei/X64/X64Entry.c b/MdeModulePk= g/Universal/CapsulePei/X64/X64Entry.c index 5ad95d2..2197502 100644 --- a/MdeModulePkg/Universal/CapsulePei/X64/X64Entry.c +++ b/MdeModulePkg/Universal/CapsulePei/X64/X64Entry.c @@ -2,6 +2,8 @@ The X64 entrypoint is used to process capsule in long mode. =20 Copyright (c) 2011 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2017, AMD Incorporated. All rights reserved.
+ This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License which accompanies this distribution. The full text of the license may be = found at @@ -29,6 +31,7 @@ typedef struct _PAGE_FAULT_CONTEXT { UINT64 PhyMask; UINTN PageFaultBuffer; UINTN PageFaultIndex; + UINT64 PteMemoryEncryptionAddressOrMask; // // Store the uplink information for each page being used. // @@ -114,6 +117,7 @@ AcquirePage ( ) { UINTN Address; + UINT64 AddressSetMask; =20 Address =3D PageFaultContext->PageFaultBuffer + EFI_PAGES_TO_SIZE (PageF= aultContext->PageFaultIndex); ZeroMem ((VOID *) Address, EFI_PAGES_TO_SIZE (1)); @@ -121,14 +125,16 @@ AcquirePage ( // // Cut the previous uplink if it exists and wasn't overwritten. // - if ((PageFaultContext->PageFaultUplink[PageFaultContext->PageFaultIndex]= !=3D NULL) && ((*PageFaultContext->PageFaultUplink[PageFaultContext->PageF= aultIndex] & PageFaultContext->PhyMask) =3D=3D Address)) { + if ((PageFaultContext->PageFaultUplink[PageFaultContext->PageFaultIndex]= !=3D NULL) && + ((*PageFaultContext->PageFaultUplink[PageFaultContext->PageFaultIndex= ] & PageFaultContext->PhyMask) =3D=3D Address)) { *PageFaultContext->PageFaultUplink[PageFaultContext->PageFaultIndex] = =3D 0; } =20 // // Link & Record the current uplink. // - *Uplink =3D Address | IA32_PG_P | IA32_PG_RW; + AddressSetMask =3D PageFaultContext->PteMemoryEncryptionAddressOrMask; + *Uplink =3D Address | (AddressSetMask & PAGING_4K_ADDRESS_MASK_64) | IA3= 2_PG_P | IA32_PG_RW; PageFaultContext->PageFaultUplink[PageFaultContext->PageFaultIndex] =3D = Uplink; =20 PageFaultContext->PageFaultIndex =3D (PageFaultContext->PageFaultIndex += 1) % EXTRA_PAGE_TABLE_PAGES; @@ -153,6 +159,7 @@ PageFaultHandler ( UINT64 *PageTable; UINT64 PFAddress; UINTN PTIndex; + UINT64 AddressSetMask; =20 // // Get the IDT Descriptor. @@ -163,6 +170,7 @@ PageFaultHandler ( // PageFaultContext =3D (PAGE_FAULT_CONTEXT *) (UINTN) (Idtr.Base - sizeof = (PAGE_FAULT_CONTEXT)); PhyMask =3D PageFaultContext->PhyMask; + AddressSetMask =3D PageFaultContext->PteMemoryEncryptionAddressOrMask; =20 PFAddress =3D AsmReadCr2 (); DEBUG ((EFI_D_ERROR, "CapsuleX64 - PageFaultHandler: Cr2 - %lx\n", PFAdd= ress)); @@ -179,19 +187,19 @@ PageFaultHandler ( if ((PageTable[PTIndex] & IA32_PG_P) =3D=3D 0) { AcquirePage (PageFaultContext, &PageTable[PTIndex]); } - PageTable =3D (UINT64*)(UINTN)(PageTable[PTIndex] & PhyMask); + PageTable =3D (UINT64*)(UINTN)((PageTable[PTIndex] & ~(AddressSetMask & = PAGING_4K_ADDRESS_MASK_64)) & PhyMask); PTIndex =3D BitFieldRead64 (PFAddress, 30, 38); // PDPTE if (PageFaultContext->Page1GSupport) { - PageTable[PTIndex] =3D (PFAddress & ~((1ull << 30) - 1)) | IA32_PG_P |= IA32_PG_RW | IA32_PG_PS; + PageTable[PTIndex] =3D ((PFAddress | (AddressSetMask & PAGING_1G_ADDRE= SS_MASK_64)) & ~((1ull << 30) - 1)) | IA32_PG_P | IA32_PG_RW | IA32_PG_PS; } else { if ((PageTable[PTIndex] & IA32_PG_P) =3D=3D 0) { AcquirePage (PageFaultContext, &PageTable[PTIndex]); } - PageTable =3D (UINT64*)(UINTN)(PageTable[PTIndex] & PhyMask); + PageTable =3D (UINT64*)(UINTN)((PageTable[PTIndex] & ~(AddressSetMask = & PAGING_4K_ADDRESS_MASK_64)) & PhyMask); PTIndex =3D BitFieldRead64 (PFAddress, 21, 29); // PD - PageTable[PTIndex] =3D (PFAddress & ~((1ull << 21) - 1)) | IA32_PG_P |= IA32_PG_RW | IA32_PG_PS; + PageTable[PTIndex] =3D ((PFAddress | (AddressSetMask & PAGING_2M_ADDRE= SS_MASK_64)) & ~((1ull << 21) - 1)) | IA32_PG_P | IA32_PG_RW | IA32_PG_PS; } =20 return NULL; @@ -244,6 +252,7 @@ _ModuleEntryPoint ( // Hook page fault handler to handle >4G request. // PageFaultIdtTable.PageFaultContext.Page1GSupport =3D EntrypointContext->= Page1GSupport; + PageFaultIdtTable.PageFaultContext.PteMemoryEncryptionAddressOrMask =3D = EntrypointContext->PteMemoryEncryptionAddressOrMask; IdtEntry =3D (IA32_IDT_GATE_DESCRIPTOR *) (X64Idtr.Base + (14 * sizeof (= IA32_IDT_GATE_DESCRIPTOR))); HookPageFaultHandler (IdtEntry, &(PageFaultIdtTable.PageFaultContext)); =20 @@ -298,4 +307,4 @@ _ModuleEntryPoint ( // ASSERT (FALSE); return EFI_SUCCESS; -} \ No newline at end of file +} --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat Nov 2 14:37:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zoho.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; 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20:p/BD3UIhW7oWr0cxtltaVyMrDURSsa8CGRoc3eeZTQ9uC0vPM3BTALboS/e2lQIEYKSpRPHTR487n39bF27+C8ItPbL3NSFhEze4UmqRM5J/Lm92zEh0OGLeHFKF1IFTmE2N+PzCrU+N4EBk1X4il23KeAYKIxy1LgLCUvStywfu/u1Ea76xFIV7u1ansGq3J2EBOzp0lGlAPk6hbFKUbWEM5FA57sBvLCdolzC1WRogjIP/ewJJISlwj3mi71RC X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Feb 2017 21:02:28.7437 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR12MB1236 Subject: [edk2] [PATCH v3 3/4] UefiCpuPkg/Universal/Acpi/S3Resume2Pei: Add support for PCD PcdPteMemoryEncryptionAddressOrMask X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Feng Tian , Brijesh Singh , Leo Duran , Laszlo Ersek , Jeff Fan , Star Zeng Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This PCD holds the address mask for page table entries when memory encryption is enabled on AMD processors supporting the Secure Encrypted Virtualization (SEV) feature. The mask is applied when page tables are created (S3Resume.c). CC: Jeff Fan Cc: Feng Tian Cc: Star Zeng Cc: Laszlo Ersek Cc: Brijesh Singh Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leo Duran Reviewed-by: Star Zeng --- UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c | 16 ++++++++++++-= --- UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf | 2 ++ 2 files changed, 14 insertions(+), 4 deletions(-) diff --git a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c b/UefiCpuPkg= /Universal/Acpi/S3Resume2Pei/S3Resume.c index d306fba..3701957 100644 --- a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c +++ b/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c @@ -5,6 +5,7 @@ control is passed to OS waking up handler. =20 Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2017, AMD Incorporated. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions @@ -58,6 +59,10 @@ #define STACK_ALIGN_DOWN(Ptr) \ ((UINTN)(Ptr) & ~(UINTN)(CPU_STACK_ALIGNMENT - 1)) =20 +#define PAGING_4K_ADDRESS_MASK_64 0x000FFFFFFFFFF000ull +#define PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull +#define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull + #pragma pack(1) typedef union { struct { @@ -614,6 +619,7 @@ RestoreS3PageTables ( VOID *Hob; BOOLEAN Page1GSupport; PAGE_TABLE_1G_ENTRY *PageDirectory1GEntry; + UINT64 AddressSetMask; =20 // // NOTE: We have to ASSUME the page table generation format, because w= e do not know whole page table information. @@ -682,6 +688,8 @@ RestoreS3PageTables ( NumberOfPml4EntriesNeeded =3D (UINT32)LShiftU64 (1, (PhysicalAddress= Bits - 39)); NumberOfPdpEntriesNeeded =3D 512; } + + AddressSetMask =3D PcdGet64 (PcdPteMemoryEncryptionAddressOrMask); =20 PageMapLevel4Entry =3D PageMap; PageAddress =3D 0; @@ -696,7 +704,7 @@ RestoreS3PageTables ( // // Make a PML4 Entry // - PageMapLevel4Entry->Uint64 =3D (UINT64)(UINTN)PageDirectoryPointerEn= try; + PageMapLevel4Entry->Uint64 =3D (UINT64)(UINTN)PageDirectoryPointerEn= try | (AddressSetMask & PAGING_4K_ADDRESS_MASK_64); PageMapLevel4Entry->Bits.ReadWrite =3D 1; PageMapLevel4Entry->Bits.Present =3D 1; =20 @@ -707,7 +715,7 @@ RestoreS3PageTables ( // // Fill in the Page Directory entries // - PageDirectory1GEntry->Uint64 =3D (UINT64)PageAddress; + PageDirectory1GEntry->Uint64 =3D (UINT64)PageAddress | (AddressS= etMask & PAGING_1G_ADDRESS_MASK_64); PageDirectory1GEntry->Bits.ReadWrite =3D 1; PageDirectory1GEntry->Bits.Present =3D 1; PageDirectory1GEntry->Bits.MustBe1 =3D 1; @@ -724,7 +732,7 @@ RestoreS3PageTables ( // // Fill in a Page Directory Pointer Entries // - PageDirectoryPointerEntry->Uint64 =3D (UINT64)(UINTN)PageDirecto= ryEntry; + PageDirectoryPointerEntry->Uint64 =3D (UINT64)(UINTN)PageDirecto= ryEntry | (AddressSetMask & PAGING_4K_ADDRESS_MASK_64); PageDirectoryPointerEntry->Bits.ReadWrite =3D 1; PageDirectoryPointerEntry->Bits.Present =3D 1; =20 @@ -732,7 +740,7 @@ RestoreS3PageTables ( // // Fill in the Page Directory entries // - PageDirectoryEntry->Uint64 =3D (UINT64)PageAddress; + PageDirectoryEntry->Uint64 =3D (UINT64)PageAddress | (AddressS= etMask & PAGING_2M_ADDRESS_MASK_64); PageDirectoryEntry->Bits.ReadWrite =3D 1; PageDirectoryEntry->Bits.Present =3D 1; PageDirectoryEntry->Bits.MustBe1 =3D 1; diff --git a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf b/Uefi= CpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf index 73aeca3..d514523 100644 --- a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf +++ b/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf @@ -6,6 +6,7 @@ # control is passed to OS waking up handler. # # Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.
+# Copyright (c) 2017, AMD Incorporated. All rights reserved.
# # This program and the accompanying materials are # licensed and made available under the terms and conditions of the BSD Li= cense @@ -91,6 +92,7 @@ =20 [Pcd] gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable ## SOMETIMES_CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask ##= CONSUMES =20 [Depex] TRUE --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat Nov 2 14:37:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zoho.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1487278958879335.79366704957147; Thu, 16 Feb 2017 13:02:38 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 237948210B; 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20:FTaGt64T4t2aCz92x/YKZDtb8oWAZ6yCfBSh4uy7imoemMGJRmqOJjWtOcSVPdcBJUEPVgJfmvwqPouET7Iteqkr0hdNV359t1Q+tlR89nWYjT8c0t6ZFA8NnXp074ijnWZn5PfpDn0laQD+QW1/+TUqUz2q4uU+8vmDxqBLucaYum6HeyVqJFAubHJC+DxstPm8iSz0HhGRREQJLAhRuzCBCKvrStTc16bpLAmOWYIV/i7NVtPt0UA7pfDAeWaN X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Feb 2017 21:02:29.8326 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR12MB1236 Subject: [edk2] [PATCH v3 4/4] MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe: Add support for PCD PcdPteMemoryEncryptionAddressOrMask X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Feng Tian , Brijesh Singh , Leo Duran , Laszlo Ersek , Jeff Fan , Star Zeng Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This PCD holds the address mask for page table entries when memory encryption is enabled on AMD processors supporting the Secure Encrypted Virtualization (SEV) feature. This module updates the under-4GB page tables configured by the S3-Resume code in UefiCpuPkg/Universal/Acpi/S3Resume2Pei. The mask is saved at module start (ScriptExecute.c), and applied when tables are expanded on-demand by page-faults above 4GB's (SetIdtEntry.c). CC: Jeff Fan Cc: Feng Tian Cc: Star Zeng Cc: Laszlo Ersek Cc: Brijesh Singh Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leo Duran --- .../Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.inf | 2 ++ .../Universal/Acpi/BootScriptExecutorDxe/ScriptExecute.c | 7 +++++++ .../Universal/Acpi/BootScriptExecutorDxe/ScriptExecute.h | 2 ++ .../Acpi/BootScriptExecutorDxe/X64/SetIdtEntry.c | 16 +++++++++++-= ---- 4 files changed, 22 insertions(+), 5 deletions(-) diff --git a/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptEx= ecutorDxe.inf b/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScrip= tExecutorDxe.inf index 7cd38cf..29af7f5 100644 --- a/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorD= xe.inf +++ b/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorD= xe.inf @@ -5,6 +5,7 @@ # depends on any PEI or DXE service. # # Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+# Copyright (c) 2017, AMD Incorporated. All rights reserved.
# # This program and the accompanying materials are # licensed and made available under the terms and conditions of the BSD Li= cense @@ -85,6 +86,7 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable ## SOMETIM= ES_CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdMemoryProfilePropertyMask ## CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiS3Enable ## CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask ##= CONSUMES =20 [Depex] gEfiLockBoxProtocolGuid diff --git a/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/ScriptExecut= e.c b/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/ScriptExecute.c index f67fbca..5146b33 100644 --- a/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/ScriptExecute.c +++ b/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/ScriptExecute.c @@ -5,6 +5,7 @@ in the entry point. The functionality is to interpret and restore the S3= boot script =20 Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2017, AMD Incorporated. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License @@ -23,6 +24,7 @@ EFI_GUID mBootScriptExecutorImageGuid =3D { }; =20 BOOLEAN mPage1GSupport =3D FALSE; +UINT64 mPteMemoryEncryptionAddressOrMask =3D 0; =20 /** Entry function of Boot script exector. This function will be executed in @@ -440,6 +442,11 @@ BootScriptExecutorEntryPoint ( } } =20 + // + // Save OrMask to fix-up Address field in page-fault handler + // + mPteMemoryEncryptionAddressOrMask =3D PcdGet64 (PcdPteMemoryEncrypti= onAddressOrMask); + BufferSize =3D sizeof (BOOT_SCRIPT_EXECUTOR_VARIABLE); =20 BootScriptExecutorBuffer =3D 0xFFFFFFFF; diff --git a/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/ScriptExecut= e.h b/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/ScriptExecute.h index 772347a..cb88549 100644 --- a/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/ScriptExecute.h +++ b/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/ScriptExecute.h @@ -5,6 +5,7 @@ in the entry point. The functionality is to interpret and restore the S3= boot script=20 =20 Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
+Copyright (c) 2017, AMD Incorporated. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License @@ -87,5 +88,6 @@ SetIdtEntry ( extern UINT32 AsmFixAddress16; extern UINT32 AsmJmpAddr32; extern BOOLEAN mPage1GSupport; +extern UINT64 mPteMemoryEncryptionAddressOrMask; =20 #endif //_BOOT_SCRIPT_EXECUTOR_H_ diff --git a/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/X64/SetIdtEn= try.c b/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/X64/SetIdtEntry.c index 6674560..37724f0 100644 --- a/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/X64/SetIdtEntry.c +++ b/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/X64/SetIdtEntry.c @@ -4,6 +4,8 @@ Set a IDT entry for interrupt vector 3 for debug purpose for x64 platform =20 Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.
+Copyright (c) 2017, AMD Incorporated. All rights reserved.
+ =20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License @@ -25,6 +27,10 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHE= R EXPRESS OR IMPLIED. #define IA32_PG_RW BIT1 #define IA32_PG_PS BIT7 =20 +#define PAGING_4K_ADDRESS_MASK_64 0x000FFFFFFFFFF000ull +#define PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull +#define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull + UINT64 mPhyMask; VOID *mOriginalHandler; UINTN mPageFaultBuffer; @@ -207,7 +213,7 @@ AcquirePage ( // // Link & Record the current uplink. // - *Uplink =3D Address | IA32_PG_P | IA32_PG_RW; + *Uplink =3D Address | (mPteMemoryEncryptionAddressOrMask & PAGING_4K_ADD= RESS_MASK_64) | IA32_PG_P | IA32_PG_RW; mPageFaultUplink[mPageFaultIndex] =3D Uplink; =20 mPageFaultIndex =3D (mPageFaultIndex + 1) % EXTRA_PAGE_TABLE_PAGES; @@ -245,19 +251,19 @@ PageFaultHandler ( if ((PageTable[PTIndex] & IA32_PG_P) =3D=3D 0) { AcquirePage (&PageTable[PTIndex]); } - PageTable =3D (UINT64*)(UINTN)(PageTable[PTIndex] & mPhyMask); + PageTable =3D (UINT64*)(UINTN)((PageTable[PTIndex] & ~(mPteMemoryEncrypt= ionAddressOrMask & PAGING_4K_ADDRESS_MASK_64)) & mPhyMask); PTIndex =3D BitFieldRead64 (PFAddress, 30, 38); // PDPTE if (mPage1GSupport) { - PageTable[PTIndex] =3D (PFAddress & ~((1ull << 30) - 1)) | IA32_PG_P |= IA32_PG_RW | IA32_PG_PS; + PageTable[PTIndex] =3D ((PFAddress | (mPteMemoryEncryptionAddressOrMas= k & PAGING_1G_ADDRESS_MASK_64)) & ~((1ull << 30) - 1)) | IA32_PG_P | IA32_P= G_RW | IA32_PG_PS; } else { if ((PageTable[PTIndex] & IA32_PG_P) =3D=3D 0) { AcquirePage (&PageTable[PTIndex]); } - PageTable =3D (UINT64*)(UINTN)(PageTable[PTIndex] & mPhyMask); + PageTable =3D (UINT64*)(UINTN)((PageTable[PTIndex] & ~(mPteMemoryEncry= ptionAddressOrMask & PAGING_4K_ADDRESS_MASK_64)) & mPhyMask); PTIndex =3D BitFieldRead64 (PFAddress, 21, 29); // PD - PageTable[PTIndex] =3D (PFAddress & ~((1ull << 21) - 1)) | IA32_PG_P |= IA32_PG_RW | IA32_PG_PS; + PageTable[PTIndex] =3D ((PFAddress | (mPteMemoryEncryptionAddressOrMas= k & PAGING_2M_ADDRESS_MASK_64)) & ~((1ull << 21) - 1)) | IA32_PG_P | IA32_P= G_RW | IA32_PG_PS; } =20 return TRUE; --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel