From nobody Sat Nov 2 16:38:39 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zoho.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1487178736633629.4319768634317; Wed, 15 Feb 2017 09:12:16 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 783D3820DD; Wed, 15 Feb 2017 09:12:14 -0800 (PST) Received: from mail-wm0-x236.google.com (mail-wm0-x236.google.com [IPv6:2a00:1450:400c:c09::236]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 96BF982090 for ; Wed, 15 Feb 2017 09:12:11 -0800 (PST) Received: by mail-wm0-x236.google.com with SMTP id c85so47347266wmi.1 for ; Wed, 15 Feb 2017 09:12:11 -0800 (PST) Received: from localhost.localdomain ([196.80.229.213]) by smtp.gmail.com with ESMTPSA id n13sm5606276wrn.40.2017.02.15.09.12.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 15 Feb 2017 09:12:09 -0800 (PST) X-Original-To: edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=m4Y8WM4JDyEPDYX3z9h9l9eAl6ffcxatKdYSTNyImPQ=; b=K1hfaqruHe5PB1z4k4LNghyDGPFDvem1MWgfos5XdEenpwhpQmRxt+QlBFMwSmQquD oKPgCq41QV58uGS4H5TepUjlaB4CXbN5ulnW9XS4vMWzLgF7mBYPCvUJ7HQdcQPAlTcU Y+eqg5nxPp14IGWr3v3unUN3HHd0J4EmZxwQQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=m4Y8WM4JDyEPDYX3z9h9l9eAl6ffcxatKdYSTNyImPQ=; b=MjSi2hQe615KlZDzOYqtWNQy+mAtlR6wy/qyKSAOf+rr1UGgAXpIOiTBT3NlnDc2Ld elhoiz9eNyz6/CFa3Xkr8VzWZp2H0oDnEqTMW05wKzmKJtH0pQgTHUfwYYXkY08CYdAQ CWNoqPBXYbyEoz6uf7GWR0+tccK3BBbrJP/CuSSsyzV+DhkhnIuuvcRwAMYJ1zRdnldU r5IuVJVZeLFV5k5yoVDldPOlk/+6Gw6IIf+GbMxaVYTaRpCwTLizCz9WnHQ5PQVBpNai h1UcYox1XJq1XLha1ttarTwpQcaDuf5uY7AbupEW7SQ2MlAgvI5SX51gEzFK/QC4QClZ gbLQ== X-Gm-Message-State: AMke39lqJ5I66hV9OdfCqdfF1if0/caJ6rz17mUolsSNOG0Oo/C6IQt9Bjaq3p/GreJAhwBg X-Received: by 10.28.167.68 with SMTP id q65mr9369445wme.126.1487178729856; Wed, 15 Feb 2017 09:12:09 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org, leif.lindholm@linaro.org Date: Wed, 15 Feb 2017 17:11:53 +0000 Message-Id: <1487178716-24569-2-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1487178716-24569-1-git-send-email-ard.biesheuvel@linaro.org> References: <1487178716-24569-1-git-send-email-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH v2 1/4] ArmPkg/CpuDxe: Correct EFI_MEMORY_RO usage X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jiewen.yao@intel.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Jiewen Yao Current Arm CpuDxe driver uses EFI_MEMORY_WP for write protection, according to UEFI spec, we should use EFI_MEMORY_RO for write protection. The EFI_MEMORY_WP is the cache attribute instead of memory attribute. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao Reviewed-by: Leif Lindholm Reviewed-by: Ard Biesheuvel --- ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c | 3 ++- ArmPkg/Drivers/CpuDxe/Arm/Mmu.c | 14 ++++++-------- ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c | 5 +++-- ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c | 3 ++- 4 files changed, 13 insertions(+), 12 deletions(-) diff --git a/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c b/ArmPkg/Drivers/CpuDxe/AA= rch64/Mmu.c index d8bb41978066..15d5a8173233 100644 --- a/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c +++ b/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c @@ -3,6 +3,7 @@ Copyright (c) 2009, Hewlett-Packard Company. All rights reserved.
Portions copyright (c) 2010, Apple Inc. All rights reserved.
Portions copyright (c) 2011-2013, ARM Ltd. All rights reserved.
+Copyright (c) 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License @@ -224,7 +225,7 @@ EfiAttributeToArmAttribute ( ArmAttributes |=3D TT_AF; =20 // Determine protection attributes - if (EfiAttributes & EFI_MEMORY_WP) { + if (EfiAttributes & EFI_MEMORY_RO) { ArmAttributes |=3D TT_AP_RO_RO; } =20 diff --git a/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c b/ArmPkg/Drivers/CpuDxe/Arm/Mm= u.c index 14fc22d7a59f..6dcfba69e879 100644 --- a/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c +++ b/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c @@ -3,6 +3,7 @@ Copyright (c) 2009, Hewlett-Packard Company. All rights reserved.
Portions copyright (c) 2010, Apple Inc. All rights reserved.
Portions copyright (c) 2013, ARM Ltd. All rights reserved.
+Copyright (c) 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License @@ -62,7 +63,7 @@ SectionToGcdAttributes ( // determine protection attributes switch(SectionAttributes & TT_DESCRIPTOR_SECTION_AP_MASK) { case TT_DESCRIPTOR_SECTION_AP_NO_NO: // no read, no write - //*GcdAttributes |=3D EFI_MEMORY_WP | EFI_MEMORY_RP; + //*GcdAttributes |=3D EFI_MEMORY_RO | EFI_MEMORY_RP; break; =20 case TT_DESCRIPTOR_SECTION_AP_RW_NO: @@ -73,7 +74,7 @@ SectionToGcdAttributes ( // read only cases map to write-protect case TT_DESCRIPTOR_SECTION_AP_RO_NO: case TT_DESCRIPTOR_SECTION_AP_RO_RO: - *GcdAttributes |=3D EFI_MEMORY_WP; + *GcdAttributes |=3D EFI_MEMORY_RO; break; =20 default: @@ -126,7 +127,7 @@ PageToGcdAttributes ( // determine protection attributes switch(PageAttributes & TT_DESCRIPTOR_PAGE_AP_MASK) { case TT_DESCRIPTOR_PAGE_AP_NO_NO: // no read, no write - //*GcdAttributes |=3D EFI_MEMORY_WP | EFI_MEMORY_RP; + //*GcdAttributes |=3D EFI_MEMORY_RO | EFI_MEMORY_RP; break; =20 case TT_DESCRIPTOR_PAGE_AP_RW_NO: @@ -137,7 +138,7 @@ PageToGcdAttributes ( // read only cases map to write-protect case TT_DESCRIPTOR_PAGE_AP_RO_NO: case TT_DESCRIPTOR_PAGE_AP_RO_RO: - *GcdAttributes |=3D EFI_MEMORY_WP; + *GcdAttributes |=3D EFI_MEMORY_RO; break; =20 default: @@ -730,9 +731,6 @@ EfiAttributeToArmAttribute ( ArmAttributes =3D TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLO= C; // TEX [2:0] =3D 001, C=3D1, B=3D1 break; =20 - case EFI_MEMORY_WP: - case EFI_MEMORY_XP: - case EFI_MEMORY_RP: case EFI_MEMORY_UCE: default: // Cannot be implemented UEFI definition unclear for ARM @@ -743,7 +741,7 @@ EfiAttributeToArmAttribute ( } =20 // Determine protection attributes - if (EfiAttributes & EFI_MEMORY_WP) { + if (EfiAttributes & EFI_MEMORY_RO) { ArmAttributes |=3D TT_DESCRIPTOR_SECTION_AP_RO_RO; } else { ArmAttributes |=3D TT_DESCRIPTOR_SECTION_AP_RW_RW; diff --git a/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c b/ArmPkg/Drivers/CpuDxe/C= puMmuCommon.c index 723604d1df96..54d9b0163331 100644 --- a/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c +++ b/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c @@ -1,6 +1,7 @@ /** @file * * Copyright (c) 2013, ARM Limited. All rights reserved. +* Copyright (c) 2017, Intel Corporation. All rights reserved.
* * This program and the accompanying materials * are licensed and made available under the terms and conditions of the B= SD License @@ -236,7 +237,7 @@ CpuConvertPagesToUncachedVirtualAddress ( // be the PCI address. Code should always use the CPU address, and we wi= ll or in VirtualMask // to that address. // - Status =3D SetMemoryAttributes (Address, Length, EFI_MEMORY_WP, 0); + Status =3D SetMemoryAttributes (Address, Length, EFI_MEMORY_RO, 0); if (!EFI_ERROR (Status)) { Status =3D SetMemoryAttributes (Address | VirtualMask, Length, EFI_MEM= ORY_UC, VirtualMask); } @@ -264,7 +265,7 @@ CpuReconvertPages ( // // Unmap the aliased Address // - Status =3D SetMemoryAttributes (Address | VirtualMask, Length, EFI_MEMOR= Y_WP, 0); + Status =3D SetMemoryAttributes (Address | VirtualMask, Length, EFI_MEMOR= Y_RO, 0); if (!EFI_ERROR (Status)) { // // Restore atttributes diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/ArmPkg/Libr= ary/ArmMmuLib/AArch64/ArmMmuLibCore.c index 540069a59b2e..6aa970bc0514 100644 --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c @@ -3,6 +3,7 @@ * * Copyright (c) 2011-2014, ARM Limited. All rights reserved. * Copyright (c) 2016, Linaro Limited. All rights reserved. +* Copyright (c) 2017, Intel Corporation. All rights reserved.
* * This program and the accompanying materials * are licensed and made available under the terms and conditions of the B= SD License @@ -89,7 +90,7 @@ PageAttributeToGcdAttribute ( // Determine protection attributes if (((PageAttributes & TT_AP_MASK) =3D=3D TT_AP_NO_RO) || ((PageAttribut= es & TT_AP_MASK) =3D=3D TT_AP_RO_RO)) { // Read only cases map to write-protect - GcdAttributes |=3D EFI_MEMORY_WP; + GcdAttributes |=3D EFI_MEMORY_RO; } =20 // Process eXecute Never attribute --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel