From nobody Sat Nov 2 14:26:21 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zoho.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1486624840055975.039510486809; Wed, 8 Feb 2017 23:20:40 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id E742D82081; Wed, 8 Feb 2017 23:20:37 -0800 (PST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id A0E0781FD1 for ; Wed, 8 Feb 2017 23:20:36 -0800 (PST) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga102.jf.intel.com with ESMTP; 08 Feb 2017 23:20:36 -0800 Received: from jyao1-mobl.ccr.corp.intel.com ([10.254.176.87]) by fmsmga002.fm.intel.com with ESMTP; 08 Feb 2017 23:20:36 -0800 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.35,349,1484035200"; d="scan'208";a="1124128248" From: Jiewen Yao To: edk2-devel@lists.01.org Date: Wed, 8 Feb 2017 23:20:29 -0800 Message-Id: <1486624832-15736-2-git-send-email-jiewen.yao@intel.com> X-Mailer: git-send-email 2.7.4.windows.1 In-Reply-To: <1486624832-15736-1-git-send-email-jiewen.yao@intel.com> References: <1486624832-15736-1-git-send-email-jiewen.yao@intel.com> Subject: [edk2] [PATCH V3 1/4] UefiCpuPkg/CpuDxe: Add memory attribute setting. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Kinney , Jeff Fan MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Add memory attribute setting in CpuArch protocol. Previous SetMemoryAttributes() API only supports cache attribute setting. This patch updated SetMemoryAttributes() API to support memory attribute setting by updating CPU page table. Cc: Jeff Fan Cc: Michael Kinney Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao --- UefiCpuPkg/CpuDxe/CpuDxe.c | 141 ++-- UefiCpuPkg/CpuDxe/CpuDxe.inf | 5 +- UefiCpuPkg/CpuDxe/CpuPageTable.c | 779 ++++++++++++++++++++ UefiCpuPkg/CpuDxe/CpuPageTable.h | 113 +++ 4 files changed, 977 insertions(+), 61 deletions(-) diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.c b/UefiCpuPkg/CpuDxe/CpuDxe.c index f6d0a67..3f3ddad 100644 --- a/UefiCpuPkg/CpuDxe/CpuDxe.c +++ b/UefiCpuPkg/CpuDxe/CpuDxe.c @@ -1,7 +1,7 @@ /** @file CPU DXE Module to produce CPU ARCH Protocol. =20 - Copyright (c) 2008 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2008 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License which accompanies this distribution. The full text of the license may b= e found at @@ -14,6 +14,10 @@ =20 #include "CpuDxe.h" #include "CpuMp.h" +#include "CpuPageTable.h" + +#define CACHE_ATTRIBUTE_MASK (EFI_MEMORY_UC | EFI_MEMORY_WC | EFI_MEMORY= _WT | EFI_MEMORY_WB | EFI_MEMORY_UCE | EFI_MEMORY_WP) +#define MEMORY_ATTRIBUTE_MASK (EFI_MEMORY_RP | EFI_MEMORY_XP | EFI_MEMORY= _RO) =20 // // Global Variables @@ -368,10 +372,9 @@ CpuSetMemoryAttributes ( EFI_STATUS MpStatus; EFI_MP_SERVICES_PROTOCOL *MpService; MTRR_SETTINGS MtrrSettings; - - if (!IsMtrrSupported ()) { - return EFI_UNSUPPORTED; - } + UINT64 CacheAttributes; + UINT64 MemoryAttributes; + MTRR_MEMORY_CACHE_TYPE CurrentCacheType; =20 // // If this function is called because GCD SetMemorySpaceAttributes () is= called @@ -384,69 +387,87 @@ CpuSetMemoryAttributes ( return EFI_SUCCESS; } =20 - switch (Attributes) { - case EFI_MEMORY_UC: - CacheType =3D CacheUncacheable; - break; =20 - case EFI_MEMORY_WC: - CacheType =3D CacheWriteCombining; - break; + CacheAttributes =3D Attributes & CACHE_ATTRIBUTE_MASK; + MemoryAttributes =3D Attributes & MEMORY_ATTRIBUTE_MASK; =20 - case EFI_MEMORY_WT: - CacheType =3D CacheWriteThrough; - break; + if (Attributes !=3D (CacheAttributes | MemoryAttributes)) { + return EFI_INVALID_PARAMETER; + } =20 - case EFI_MEMORY_WP: - CacheType =3D CacheWriteProtected; - break; + if (CacheAttributes !=3D 0) { + if (!IsMtrrSupported ()) { + return EFI_UNSUPPORTED; + } =20 - case EFI_MEMORY_WB: - CacheType =3D CacheWriteBack; - break; + switch (CacheAttributes) { + case EFI_MEMORY_UC: + CacheType =3D CacheUncacheable; + break; =20 - case EFI_MEMORY_UCE: - case EFI_MEMORY_RP: - case EFI_MEMORY_XP: - case EFI_MEMORY_RUNTIME: - return EFI_UNSUPPORTED; + case EFI_MEMORY_WC: + CacheType =3D CacheWriteCombining; + break; =20 - default: - return EFI_INVALID_PARAMETER; - } - // - // call MTRR libary function - // - Status =3D MtrrSetMemoryAttribute ( - BaseAddress, - Length, - CacheType - ); + case EFI_MEMORY_WT: + CacheType =3D CacheWriteThrough; + break; =20 - if (!RETURN_ERROR (Status)) { - MpStatus =3D gBS->LocateProtocol ( - &gEfiMpServiceProtocolGuid, - NULL, - (VOID **)&MpService - ); - // - // Synchronize the update with all APs - // - if (!EFI_ERROR (MpStatus)) { - MtrrGetAllMtrrs (&MtrrSettings); - MpStatus =3D MpService->StartupAllAPs ( - MpService, // This - SetMtrrsFromBuffer, // Procedure - FALSE, // SingleThread - NULL, // WaitEvent - 0, // TimeoutInMicrosecsond - &MtrrSettings, // ProcedureArgument - NULL // FailedCpuList - ); - ASSERT (MpStatus =3D=3D EFI_SUCCESS || MpStatus =3D=3D EFI_NOT_START= ED); + case EFI_MEMORY_WP: + CacheType =3D CacheWriteProtected; + break; + + case EFI_MEMORY_WB: + CacheType =3D CacheWriteBack; + break; + + default: + return EFI_INVALID_PARAMETER; + } + CurrentCacheType =3D MtrrGetMemoryAttribute(BaseAddress); + if (CurrentCacheType !=3D CacheType) { + // + // call MTRR libary function + // + Status =3D MtrrSetMemoryAttribute ( + BaseAddress, + Length, + CacheType + ); + + if (!RETURN_ERROR (Status)) { + MpStatus =3D gBS->LocateProtocol ( + &gEfiMpServiceProtocolGuid, + NULL, + (VOID **)&MpService + ); + // + // Synchronize the update with all APs + // + if (!EFI_ERROR (MpStatus)) { + MtrrGetAllMtrrs (&MtrrSettings); + MpStatus =3D MpService->StartupAllAPs ( + MpService, // This + SetMtrrsFromBuffer, // Procedure + FALSE, // SingleThread + NULL, // WaitEvent + 0, // TimeoutInMicrosec= sond + &MtrrSettings, // ProcedureArgument + NULL // FailedCpuList + ); + ASSERT (MpStatus =3D=3D EFI_SUCCESS || MpStatus =3D=3D EFI_NOT_S= TARTED); + } + } + if (EFI_ERROR(Status)) { + return Status; + } } } - return (EFI_STATUS) Status; + + // + // Set memory attribute by page table + // + return AssignMemoryPageAttributes (NULL, BaseAddress, Length, MemoryAttr= ibutes, AllocatePages); } =20 /** @@ -888,6 +909,8 @@ InitializeCpu ( { EFI_STATUS Status; EFI_EVENT IdleLoopEvent; + =20 + InitializePageTableLib(); =20 InitializeFloatingPointUnits (); =20 diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.inf b/UefiCpuPkg/CpuDxe/CpuDxe.inf index bf389bb..f61b2c9 100644 --- a/UefiCpuPkg/CpuDxe/CpuDxe.inf +++ b/UefiCpuPkg/CpuDxe/CpuDxe.inf @@ -1,7 +1,7 @@ ## @file # CPU driver installs CPU Architecture Protocol and CPU MP protocol. # -# Copyright (c) 2008 - 2016, Intel Corporation. All rights reserved.
+# Copyright (c) 2008 - 2017, Intel Corporation. All rights reserved.
# This program and the accompanying materials # are licensed and made available under the terms and conditions of the B= SD License # which accompanies this distribution. The full text of the license may = be found at @@ -19,7 +19,6 @@ FILE_GUID =3D 1A1E4886-9517-440e-9FDE-3BE44CEE2136 MODULE_TYPE =3D DXE_DRIVER VERSION_STRING =3D 1.0 - ENTRY_POINT =3D InitializeCpu =20 [Packages] @@ -52,6 +51,8 @@ CpuGdt.h CpuMp.c CpuMp.h + CpuPageTable.h + CpuPageTable.c =20 [Sources.IA32] Ia32/CpuAsm.asm diff --git a/UefiCpuPkg/CpuDxe/CpuPageTable.c b/UefiCpuPkg/CpuDxe/CpuPageTa= ble.c new file mode 100644 index 0000000..c9c6fcb --- /dev/null +++ b/UefiCpuPkg/CpuDxe/CpuPageTable.c @@ -0,0 +1,779 @@ +/** @file + Page table management support. + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "CpuPageTable.h" + +/// +/// Page Table Entry +/// +#define IA32_PG_P BIT0 +#define IA32_PG_RW BIT1 +#define IA32_PG_U BIT2 +#define IA32_PG_WT BIT3 +#define IA32_PG_CD BIT4 +#define IA32_PG_A BIT5 +#define IA32_PG_D BIT6 +#define IA32_PG_PS BIT7 +#define IA32_PG_PAT_2M BIT12 +#define IA32_PG_PAT_4K IA32_PG_PS +#define IA32_PG_PMNT BIT62 +#define IA32_PG_NX BIT63 + +#define PAGE_ATTRIBUTE_BITS (IA32_PG_D | IA32_PG_A | IA32_PG_U | I= A32_PG_RW | IA32_PG_P) +// +// Bits 1, 2, 5, 6 are reserved in the IA32 PAE PDPTE +// X64 PAE PDPTE does not have such restriction +// +#define IA32_PAE_PDPTE_ATTRIBUTE_BITS (IA32_PG_P) + +#define PAGE_PROGATE_BITS (IA32_PG_NX | PAGE_ATTRIBUTE_BITS) + +#define PAGING_4K_MASK 0xFFF +#define PAGING_2M_MASK 0x1FFFFF +#define PAGING_1G_MASK 0x3FFFFFFF + +#define PAGING_PAE_INDEX_MASK 0x1FF + +#define PAGING_4K_ADDRESS_MASK_64 0x000FFFFFFFFFF000ull +#define PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull +#define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull + +typedef enum { + PageNone, + Page4K, + Page2M, + Page1G, +} PAGE_ATTRIBUTE; + +typedef struct { + PAGE_ATTRIBUTE Attribute; + UINT64 Length; + UINT64 AddressMask; +} PAGE_ATTRIBUTE_TABLE; + +typedef enum { + PageActionAssign, + PageActionSet, + PageActionClear, +} PAGE_ACTION; + +PAGE_ATTRIBUTE_TABLE mPageAttributeTable[] =3D { + {Page4K, SIZE_4KB, PAGING_4K_ADDRESS_MASK_64}, + {Page2M, SIZE_2MB, PAGING_2M_ADDRESS_MASK_64}, + {Page1G, SIZE_1GB, PAGING_1G_ADDRESS_MASK_64}, +}; + +/** + Enable write protection function for AP. + + @param[in,out] Buffer The pointer to private data buffer. +**/ +VOID +EFIAPI +SyncCpuEnableWriteProtection ( + IN OUT VOID *Buffer + ) +{ + AsmWriteCr0 (AsmReadCr0 () | BIT16); +} + +/** + CpuFlushTlb function for AP. + + @param[in,out] Buffer The pointer to private data buffer. +**/ +VOID +EFIAPI +SyncCpuFlushTlb ( + IN OUT VOID *Buffer + ) +{ + CpuFlushTlb(); +} + +/** + Sync memory page attributes for AP. + + @param[in] Procedure A pointer to the function to be run on e= nabled APs of + the system. +**/ +VOID +SyncMemoryPageAttributesAp ( + IN EFI_AP_PROCEDURE Procedure + ) +{ + EFI_STATUS Status; + EFI_MP_SERVICES_PROTOCOL *MpService; + + Status =3D gBS->LocateProtocol ( + &gEfiMpServiceProtocolGuid, + NULL, + (VOID **)&MpService + ); + // + // Synchronize the update with all APs + // + if (!EFI_ERROR (Status)) { + Status =3D MpService->StartupAllAPs ( + MpService, // This + Procedure, // Procedure + FALSE, // SingleThread + NULL, // WaitEvent + 0, // TimeoutInMicrosecsond + NULL, // ProcedureArgument + NULL // FailedCpuList + ); + ASSERT (Status =3D=3D EFI_SUCCESS || Status =3D=3D EFI_NOT_STARTED); + } +} + +/** + Return current paging context. + + @param[in,out] PagingContext The paging context. +**/ +VOID +GetCurrentPagingContext ( + IN OUT PAGE_TABLE_LIB_PAGING_CONTEXT *PagingContext + ) +{ + UINT32 RegEax; + UINT32 RegEdx; + + ZeroMem(PagingContext, sizeof(*PagingContext)); + if (sizeof(UINTN) =3D=3D sizeof(UINT64)) { + PagingContext->MachineType =3D IMAGE_FILE_MACHINE_X64; + } else { + PagingContext->MachineType =3D IMAGE_FILE_MACHINE_I386; + } + if ((AsmReadCr0 () & BIT31) !=3D 0) { + PagingContext->ContextData.X64.PageTableBase =3D (AsmReadCr3 () & PAGI= NG_4K_ADDRESS_MASK_64); + if ((AsmReadCr0 () & BIT16) =3D=3D 0) { + AsmWriteCr0 (AsmReadCr0 () | BIT16); + SyncMemoryPageAttributesAp (SyncCpuEnableWriteProtection); + } + } else { + PagingContext->ContextData.X64.PageTableBase =3D 0; + } + + if ((AsmReadCr4 () & BIT4) !=3D 0) { + PagingContext->ContextData.Ia32.Attributes |=3D PAGE_TABLE_LIB_PAGING_= CONTEXT_IA32_X64_ATTRIBUTES_PSE; + } + if ((AsmReadCr4 () & BIT5) !=3D 0) { + PagingContext->ContextData.Ia32.Attributes |=3D PAGE_TABLE_LIB_PAGING_= CONTEXT_IA32_X64_ATTRIBUTES_PAE; + } + if ((AsmReadCr0 () & BIT16) !=3D 0) { + PagingContext->ContextData.Ia32.Attributes |=3D PAGE_TABLE_LIB_PAGING_= CONTEXT_IA32_X64_ATTRIBUTES_WP_ENABLE; + } + + AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL); + if (RegEax > 0x80000000) { + AsmCpuid (0x80000001, NULL, NULL, NULL, &RegEdx); + if ((RegEdx & BIT20) !=3D 0) { + // XD supported + if ((AsmReadMsr64 (0x000001A0) & BIT34) =3D=3D 0) { + // XD enabled + if ((AsmReadMsr64 (0xC0000080) & BIT11) !=3D 0) { + // XD activated + PagingContext->ContextData.Ia32.Attributes |=3D PAGE_TABLE_LIB_P= AGING_CONTEXT_IA32_X64_ATTRIBUTES_XD_ACTIVATED; + } + } + } + if ((RegEdx & BIT26) !=3D 0) { + PagingContext->ContextData.Ia32.Attributes |=3D PAGE_TABLE_LIB_PAGIN= G_CONTEXT_IA32_X64_ATTRIBUTES_PAGE_1G_SUPPORT; + } + } +} + +/** + Return length according to page attributes. + + @param[in] PageAttributes The page attribute of the page entry. + + @return The length of page entry. +**/ +UINTN +PageAttributeToLength ( + IN PAGE_ATTRIBUTE PageAttribute + ) +{ + UINTN Index; + for (Index =3D 0; Index < sizeof(mPageAttributeTable)/sizeof(mPageAttrib= uteTable[0]); Index++) { + if (PageAttribute =3D=3D mPageAttributeTable[Index].Attribute) { + return (UINTN)mPageAttributeTable[Index].Length; + } + } + return 0; +} + +/** + Return address mask according to page attributes. + + @param[in] PageAttributes The page attribute of the page entry. + + @return The address mask of page entry. +**/ +UINTN +PageAttributeToMask ( + IN PAGE_ATTRIBUTE PageAttribute + ) +{ + UINTN Index; + for (Index =3D 0; Index < sizeof(mPageAttributeTable)/sizeof(mPageAttrib= uteTable[0]); Index++) { + if (PageAttribute =3D=3D mPageAttributeTable[Index].Attribute) { + return (UINTN)mPageAttributeTable[Index].AddressMask; + } + } + return 0; +} + +/** + Return page table entry to match the address. + + @param[in] PagingContext The paging context. + @param[in] Address The address to be checked. + @param[out] PageAttributes The page attribute of the page entry. + + @return The page entry. +**/ +VOID * +GetPageTableEntry ( + IN PAGE_TABLE_LIB_PAGING_CONTEXT *PagingContext, + IN PHYSICAL_ADDRESS Address, + OUT PAGE_ATTRIBUTE *PageAttribute + ) +{ + UINTN Index1; + UINTN Index2; + UINTN Index3; + UINTN Index4; + UINT64 *L1PageTable; + UINT64 *L2PageTable; + UINT64 *L3PageTable; + UINT64 *L4PageTable; + + ASSERT (PagingContext !=3D NULL); + + Index4 =3D ((UINTN)RShiftU64 (Address, 39)) & PAGING_PAE_INDEX_MASK; + Index3 =3D ((UINTN)Address >> 30) & PAGING_PAE_INDEX_MASK; + Index2 =3D ((UINTN)Address >> 21) & PAGING_PAE_INDEX_MASK; + Index1 =3D ((UINTN)Address >> 12) & PAGING_PAE_INDEX_MASK; + + if (PagingContext->MachineType =3D=3D IMAGE_FILE_MACHINE_X64) { + L4PageTable =3D (UINT64 *)(UINTN)PagingContext->ContextData.X64.PageTa= bleBase; + if (L4PageTable[Index4] =3D=3D 0) { + *PageAttribute =3D PageNone; + return NULL; + } + + L3PageTable =3D (UINT64 *)(UINTN)(L4PageTable[Index4] & PAGING_4K_ADDR= ESS_MASK_64); + } else { + ASSERT((PagingContext->ContextData.Ia32.Attributes & PAGE_TABLE_LIB_PA= GING_CONTEXT_IA32_X64_ATTRIBUTES_PAE) !=3D 0); + L3PageTable =3D (UINT64 *)(UINTN)PagingContext->ContextData.Ia32.PageT= ableBase; + } + if (L3PageTable[Index3] =3D=3D 0) { + *PageAttribute =3D PageNone; + return NULL; + } + if ((L3PageTable[Index3] & IA32_PG_PS) !=3D 0) { + // 1G + *PageAttribute =3D Page1G; + return &L3PageTable[Index3]; + } + + L2PageTable =3D (UINT64 *)(UINTN)(L3PageTable[Index3] & PAGING_4K_ADDRES= S_MASK_64); + if (L2PageTable[Index2] =3D=3D 0) { + *PageAttribute =3D PageNone; + return NULL; + } + if ((L2PageTable[Index2] & IA32_PG_PS) !=3D 0) { + // 2M + *PageAttribute =3D Page2M; + return &L2PageTable[Index2]; + } + + // 4k + L1PageTable =3D (UINT64 *)(UINTN)(L2PageTable[Index2] & PAGING_4K_ADDRES= S_MASK_64); + if ((L1PageTable[Index1] =3D=3D 0) && (Address !=3D 0)) { + *PageAttribute =3D PageNone; + return NULL; + } + *PageAttribute =3D Page4K; + return &L1PageTable[Index1]; +} + +/** + Return memory attributes of page entry. + + @param[in] PageEntry The page entry. + + @return Memory attributes of page entry. +**/ +UINT64 +GetAttributesFromPageEntry ( + IN UINT64 *PageEntry + ) +{ + UINT64 Attributes; + Attributes =3D 0; + if ((*PageEntry & IA32_PG_P) =3D=3D 0) { + Attributes |=3D EFI_MEMORY_RP; + } + if ((*PageEntry & IA32_PG_RW) =3D=3D 0) { + Attributes |=3D EFI_MEMORY_RO; + } + if ((*PageEntry & IA32_PG_NX) !=3D 0) { + Attributes |=3D EFI_MEMORY_XP; + } + return Attributes; +} + +/** + Modify memory attributes of page entry. + + @param[in] PagingContext The paging context. + @param[in] PageEntry The page entry. + @param[in] Attributes The bit mask of attributes to modify for th= e memory region. + @param[in] PageAction The page action. + @param[out] IsModified TRUE means page table modified. FALSE means= page table not modified. +**/ +VOID +ConvertPageEntryAttribute ( + IN PAGE_TABLE_LIB_PAGING_CONTEXT *PagingContext, + IN UINT64 *PageEntry, + IN UINT64 Attributes, + IN PAGE_ACTION PageAction, + OUT BOOLEAN *IsModified + ) +{ + UINT64 CurrentPageEntry; + UINT64 NewPageEntry; + + CurrentPageEntry =3D *PageEntry; + NewPageEntry =3D CurrentPageEntry; + if ((Attributes & EFI_MEMORY_RP) !=3D 0) { + switch (PageAction) { + case PageActionAssign: + case PageActionSet: + NewPageEntry &=3D ~(UINT64)IA32_PG_P; + break; + case PageActionClear: + NewPageEntry |=3D IA32_PG_P; + break; + } + } else { + switch (PageAction) { + case PageActionAssign: + NewPageEntry |=3D IA32_PG_P; + break; + case PageActionSet: + case PageActionClear: + break; + } + } + if ((Attributes & EFI_MEMORY_RO) !=3D 0) { + switch (PageAction) { + case PageActionAssign: + case PageActionSet: + NewPageEntry &=3D ~(UINT64)IA32_PG_RW; + break; + case PageActionClear: + NewPageEntry |=3D IA32_PG_RW; + break; + } + } else { + switch (PageAction) { + case PageActionAssign: + NewPageEntry |=3D IA32_PG_RW; + break; + case PageActionSet: + case PageActionClear: + break; + } + } + if ((PagingContext->ContextData.Ia32.Attributes & PAGE_TABLE_LIB_PAGING_= CONTEXT_IA32_X64_ATTRIBUTES_XD_ACTIVATED) !=3D 0) { + if ((Attributes & EFI_MEMORY_XP) !=3D 0) { + switch (PageAction) { + case PageActionAssign: + case PageActionSet: + NewPageEntry |=3D IA32_PG_NX; + break; + case PageActionClear: + NewPageEntry &=3D ~IA32_PG_NX; + break; + } + } else { + switch (PageAction) { + case PageActionAssign: + NewPageEntry &=3D ~IA32_PG_NX; + break; + case PageActionSet: + case PageActionClear: + break; + } + } + } + *PageEntry =3D NewPageEntry; + if (CurrentPageEntry !=3D NewPageEntry) { + *IsModified =3D TRUE; + DEBUG ((DEBUG_INFO, "ConvertPageEntryAttribute 0x%lx", CurrentPageEntr= y)); + DEBUG ((DEBUG_INFO, "->0x%lx\n", NewPageEntry)); + } else { + *IsModified =3D FALSE; + } +} + +/** + This function returns if there is need to split page entry. + + @param[in] BaseAddress The base address to be checked. + @param[in] Length The length to be checked. + @param[in] PageEntry The page entry to be checked. + @param[in] PageAttribute The page attribute of the page entry. + + @retval SplitAttributes on if there is need to split page entry. +**/ +PAGE_ATTRIBUTE +NeedSplitPage ( + IN PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + IN UINT64 *PageEntry, + IN PAGE_ATTRIBUTE PageAttribute + ) +{ + UINT64 PageEntryLength; + + PageEntryLength =3D PageAttributeToLength (PageAttribute); + + if (((BaseAddress & (PageEntryLength - 1)) =3D=3D 0) && (Length >=3D Pag= eEntryLength)) { + return PageNone; + } + + if (((BaseAddress & PAGING_2M_MASK) !=3D 0) || (Length < SIZE_2MB)) { + return Page4K; + } + + return Page2M; +} + +/** + This function splits one page entry to small page entries. + + @param[in] PageEntry The page entry to be splitted. + @param[in] PageAttribute The page attribute of the page entry. + @param[in] SplitAttribute How to split the page entry. + @param[in] AllocatePagesFunc If page split is needed, this function is = used to allocate more pages. + + @retval RETURN_SUCCESS The page entry is splitted. + @retval RETURN_UNSUPPORTED The page entry does not support to be = splitted. + @retval RETURN_OUT_OF_RESOURCES No resource to split page entry. +**/ +RETURN_STATUS +SplitPage ( + IN UINT64 *PageEntry, + IN PAGE_ATTRIBUTE PageAttribute, + IN PAGE_ATTRIBUTE SplitAttribute, + IN PAGE_TABLE_LIB_ALLOCATE_PAGES AllocatePagesFunc + ) +{ + UINT64 BaseAddress; + UINT64 *NewPageEntry; + UINTN Index; + + ASSERT (PageAttribute =3D=3D Page2M || PageAttribute =3D=3D Page1G); + + ASSERT (AllocatePagesFunc !=3D NULL); + + if (PageAttribute =3D=3D Page2M) { + // + // Split 2M to 4K + // + ASSERT (SplitAttribute =3D=3D Page4K); + if (SplitAttribute =3D=3D Page4K) { + NewPageEntry =3D AllocatePagesFunc (1); + DEBUG ((DEBUG_INFO, "Split - 0x%x\n", NewPageEntry)); + if (NewPageEntry =3D=3D NULL) { + return RETURN_OUT_OF_RESOURCES; + } + BaseAddress =3D *PageEntry & PAGING_2M_ADDRESS_MASK_64; + for (Index =3D 0; Index < SIZE_4KB / sizeof(UINT64); Index++) { + NewPageEntry[Index] =3D BaseAddress + SIZE_4KB * Index + ((*PageEn= try) & PAGE_PROGATE_BITS); + } + (*PageEntry) =3D (UINT64)(UINTN)NewPageEntry + ((*PageEntry) & PAGE_= PROGATE_BITS); + return RETURN_SUCCESS; + } else { + return RETURN_UNSUPPORTED; + } + } else if (PageAttribute =3D=3D Page1G) { + // + // Split 1G to 2M + // No need support 1G->4K directly, we should use 1G->2M, then 2M->4K = to get more compact page table. + // + ASSERT (SplitAttribute =3D=3D Page2M || SplitAttribute =3D=3D Page4K); + if ((SplitAttribute =3D=3D Page2M || SplitAttribute =3D=3D Page4K)) { + NewPageEntry =3D AllocatePagesFunc (1); + DEBUG ((DEBUG_INFO, "Split - 0x%x\n", NewPageEntry)); + if (NewPageEntry =3D=3D NULL) { + return RETURN_OUT_OF_RESOURCES; + } + BaseAddress =3D *PageEntry & PAGING_1G_ADDRESS_MASK_64; + for (Index =3D 0; Index < SIZE_4KB / sizeof(UINT64); Index++) { + NewPageEntry[Index] =3D BaseAddress + SIZE_2MB * Index + IA32_PG_P= S + ((*PageEntry) & PAGE_PROGATE_BITS); + } + (*PageEntry) =3D (UINT64)(UINTN)NewPageEntry + ((*PageEntry) & PAGE_= PROGATE_BITS); + return RETURN_SUCCESS; + } else { + return RETURN_UNSUPPORTED; + } + } else { + return RETURN_UNSUPPORTED; + } +} + +/** + This function modifies the page attributes for the memory region specifi= ed by BaseAddress and + Length from their current attributes to the attributes specified by Attr= ibutes. + + Caller should make sure BaseAddress and Length is at page boundary. + + @param[in] PagingContext The paging context. NULL means get page ta= ble from current CPU context. + @param[in] BaseAddress The physical address that is the start add= ress of a memory region. + @param[in] Length The size in bytes of the memory region. + @param[in] Attributes The bit mask of attributes to modify for t= he memory region. + @param[in] PageAction The page action. + @param[in] AllocatePagesFunc If page split is needed, this function is = used to allocate more pages. + NULL mean page split is unsupported. + @param[out] IsSplitted TRUE means page table splitted. FALSE mean= s page table not splitted. + @param[out] IsModified TRUE means page table modified. FALSE mean= s page table not modified. + + @retval RETURN_SUCCESS The attributes were modified for the me= mory region. + @retval RETURN_ACCESS_DENIED The attributes for the memory resource = range specified by + BaseAddress and Length cannot be modifi= ed. + @retval RETURN_INVALID_PARAMETER Length is zero. + Attributes specified an illegal combina= tion of attributes that + cannot be set together. + @retval RETURN_OUT_OF_RESOURCES There are not enough system resources t= o modify the attributes of + the memory resource range. + @retval RETURN_UNSUPPORTED The processor does not support one or m= ore bytes of the memory + resource range specified by BaseAddress= and Length. + The bit mask of attributes is not suppo= rt for the memory resource + range specified by BaseAddress and Leng= th. +**/ +RETURN_STATUS +ConvertMemoryPageAttributes ( + IN PAGE_TABLE_LIB_PAGING_CONTEXT *PagingContext OPTIONAL, + IN PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + IN UINT64 Attributes, + IN PAGE_ACTION PageAction, + IN PAGE_TABLE_LIB_ALLOCATE_PAGES AllocatePagesFunc OPTIONAL, + OUT BOOLEAN *IsSplitted, OPTIONAL + OUT BOOLEAN *IsModified OPTIONAL + ) +{ + PAGE_TABLE_LIB_PAGING_CONTEXT CurrentPagingContext; + UINT64 *PageEntry; + PAGE_ATTRIBUTE PageAttribute; + UINTN PageEntryLength; + PAGE_ATTRIBUTE SplitAttribute; + RETURN_STATUS Status; + BOOLEAN IsEntryModified; + + if ((BaseAddress & (SIZE_4KB - 1)) !=3D 0) { + DEBUG ((DEBUG_ERROR, "BaseAddress(0x%lx) is not aligned!\n", BaseAddre= ss)); + return EFI_UNSUPPORTED; + } + if ((Length & (SIZE_4KB - 1)) !=3D 0) { + DEBUG ((DEBUG_ERROR, "Length(0x%lx) is not aligned!\n", Length)); + return EFI_UNSUPPORTED; + } + if (Length =3D=3D 0) { + DEBUG ((DEBUG_ERROR, "Length is 0!\n")); + return RETURN_INVALID_PARAMETER; + } + + if ((Attributes & ~(EFI_MEMORY_RP | EFI_MEMORY_RO | EFI_MEMORY_XP)) !=3D= 0) { + DEBUG ((DEBUG_ERROR, "Attributes(0x%lx) has unsupported bit\n", Attrib= utes)); + return EFI_UNSUPPORTED; + } + + if (PagingContext =3D=3D NULL) { + GetCurrentPagingContext (&CurrentPagingContext); + } else { + CopyMem (&CurrentPagingContext, PagingContext, sizeof(CurrentPagingCon= text)); + } + switch(CurrentPagingContext.MachineType) { + case IMAGE_FILE_MACHINE_I386: + if (CurrentPagingContext.ContextData.Ia32.PageTableBase =3D=3D 0) { + DEBUG ((DEBUG_ERROR, "PageTable is 0!\n")); + if (Attributes =3D=3D 0) { + return EFI_SUCCESS; + } else { + return EFI_UNSUPPORTED; + } + } + if ((CurrentPagingContext.ContextData.Ia32.Attributes & PAGE_TABLE_LIB= _PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PAE) =3D=3D 0) { + DEBUG ((DEBUG_ERROR, "Non-PAE Paging!\n")); + return EFI_UNSUPPORTED; + } + break; + case IMAGE_FILE_MACHINE_X64: + ASSERT (CurrentPagingContext.ContextData.X64.PageTableBase !=3D 0); + break; + default: + ASSERT(FALSE); + return EFI_UNSUPPORTED; + break; + } + +// DEBUG ((DEBUG_ERROR, "ConvertMemoryPageAttributes(%x) - %016lx, %016lx= , %02lx\n", IsSet, BaseAddress, Length, Attributes)); + + if (IsSplitted !=3D NULL) { + *IsSplitted =3D FALSE; + } + if (IsModified !=3D NULL) { + *IsModified =3D FALSE; + } + + // + // Below logic is to check 2M/4K page to make sure we donot waist memory. + // + while (Length !=3D 0) { + PageEntry =3D GetPageTableEntry (&CurrentPagingContext, BaseAddress, &= PageAttribute); + if (PageEntry =3D=3D NULL) { + return RETURN_UNSUPPORTED; + } + PageEntryLength =3D PageAttributeToLength (PageAttribute); + SplitAttribute =3D NeedSplitPage (BaseAddress, Length, PageEntry, Page= Attribute); + if (SplitAttribute =3D=3D PageNone) { + ConvertPageEntryAttribute (&CurrentPagingContext, PageEntry, Attribu= tes, PageAction, &IsEntryModified); + if (IsEntryModified) { + if (IsModified !=3D NULL) { + *IsModified =3D TRUE; + } + } + // + // Convert success, move to next + // + BaseAddress +=3D PageEntryLength; + Length -=3D PageEntryLength; + } else { + if (AllocatePagesFunc =3D=3D NULL) { + return RETURN_UNSUPPORTED; + } + Status =3D SplitPage (PageEntry, PageAttribute, SplitAttribute, Allo= catePagesFunc); + if (RETURN_ERROR (Status)) { + return RETURN_UNSUPPORTED; + } + if (IsSplitted !=3D NULL) { + *IsSplitted =3D TRUE; + } + if (IsModified !=3D NULL) { + *IsModified =3D TRUE; + } + // + // Just split current page + // Convert success in next around + // + } + } + + return RETURN_SUCCESS; +} + +/** + This function assigns the page attributes for the memory region specifie= d by BaseAddress and + Length from their current attributes to the attributes specified by Attr= ibutes. + + Caller should make sure BaseAddress and Length is at page boundary. + + Caller need guarentee the TPL <=3D TPL_NOTIFY, if there is split page re= quest. + + @param[in] PagingContext The paging context. NULL means get page ta= ble from current CPU context. + @param[in] BaseAddress The physical address that is the start add= ress of a memory region. + @param[in] Length The size in bytes of the memory region. + @param[in] Attributes The bit mask of attributes to set for the = memory region. + @param[in] AllocatePagesFunc If page split is needed, this function is = used to allocate more pages. + NULL mean page split is unsupported. + + @retval RETURN_SUCCESS The attributes were cleared for the mem= ory region. + @retval RETURN_ACCESS_DENIED The attributes for the memory resource = range specified by + BaseAddress and Length cannot be modifi= ed. + @retval RETURN_INVALID_PARAMETER Length is zero. + Attributes specified an illegal combina= tion of attributes that + cannot be set together. + @retval RETURN_OUT_OF_RESOURCES There are not enough system resources t= o modify the attributes of + the memory resource range. + @retval RETURN_UNSUPPORTED The processor does not support one or m= ore bytes of the memory + resource range specified by BaseAddress= and Length. + The bit mask of attributes is not suppo= rt for the memory resource + range specified by BaseAddress and Leng= th. +**/ +RETURN_STATUS +EFIAPI +AssignMemoryPageAttributes ( + IN PAGE_TABLE_LIB_PAGING_CONTEXT *PagingContext OPTIONAL, + IN PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + IN UINT64 Attributes, + IN PAGE_TABLE_LIB_ALLOCATE_PAGES AllocatePagesFunc OPTIONAL + ) +{ + RETURN_STATUS Status; + BOOLEAN IsModified; + BOOLEAN IsSplitted; + +// DEBUG((DEBUG_INFO, "AssignMemoryPageAttributes: 0x%lx - 0x%lx (0x%lx)\= n", BaseAddress, Length, Attributes)); + Status =3D ConvertMemoryPageAttributes (PagingContext, BaseAddress, Leng= th, Attributes, PageActionAssign, AllocatePagesFunc, &IsSplitted, &IsModifi= ed); + if (!EFI_ERROR(Status)) { + if ((PagingContext =3D=3D NULL) && IsModified) { + // + // Flush TLB as last step + // + CpuFlushTlb(); + SyncMemoryPageAttributesAp (SyncCpuFlushTlb); + } + } + + return Status; +} + +/** + Initialize the Page Table lib. +**/ +VOID +InitializePageTableLib ( + VOID + ) +{ + PAGE_TABLE_LIB_PAGING_CONTEXT CurrentPagingContext; + + GetCurrentPagingContext (&CurrentPagingContext); + DEBUG ((DEBUG_INFO, "CurrentPagingContext:\n", CurrentPagingContext.Mach= ineType)); + DEBUG ((DEBUG_INFO, " MachineType - 0x%x\n", CurrentPagingContext.Mac= hineType)); + DEBUG ((DEBUG_INFO, " PageTableBase - 0x%x\n", CurrentPagingContext.Con= textData.X64.PageTableBase)); + DEBUG ((DEBUG_INFO, " Attributes - 0x%x\n", CurrentPagingContext.Con= textData.X64.Attributes)); + + return ; +} + diff --git a/UefiCpuPkg/CpuDxe/CpuPageTable.h b/UefiCpuPkg/CpuDxe/CpuPageTa= ble.h new file mode 100644 index 0000000..eaff595 --- /dev/null +++ b/UefiCpuPkg/CpuDxe/CpuPageTable.h @@ -0,0 +1,113 @@ +/** @file + Page table management header file. + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#ifndef _PAGE_TABLE_LIB_H_ +#define _PAGE_TABLE_LIB_H_ + +#include + +#define PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PSE = BIT0 +#define PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PAE = BIT1 +#define PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PAGE_1G_SUPPORT = BIT2 +#define PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_WP_ENABLE = BIT30 +#define PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_XD_ACTIVATED = BIT31 +// Other bits are reserved for future use +typedef struct { + UINT32 PageTableBase; + UINT32 Reserved; + UINT32 Attributes; +} PAGE_TABLE_LIB_PAGING_CONTEXT_IA32; + +typedef struct { + UINT64 PageTableBase; + UINT32 Attributes; +} PAGE_TABLE_LIB_PAGING_CONTEXT_X64; + +typedef union { + PAGE_TABLE_LIB_PAGING_CONTEXT_IA32 Ia32; + PAGE_TABLE_LIB_PAGING_CONTEXT_X64 X64; +} PAGE_TABLE_LIB_PAGING_CONTEXT_DATA; + +typedef struct { + // + // PE32+ Machine type for EFI images + // + // #define IMAGE_FILE_MACHINE_I386 0x014c + // #define IMAGE_FILE_MACHINE_X64 0x8664 + // + UINT16 MachineType; + PAGE_TABLE_LIB_PAGING_CONTEXT_DATA ContextData; +} PAGE_TABLE_LIB_PAGING_CONTEXT; + +/** + Allocates one or more 4KB pages for page table. + + @param Pages The number of 4 KB pages to allocate. + + @return A pointer to the allocated buffer or NULL if allocation fails. + +**/ +typedef +VOID * +(EFIAPI *PAGE_TABLE_LIB_ALLOCATE_PAGES) ( + IN UINTN Pages + ); + +/** + This function assigns the page attributes for the memory region specifie= d by BaseAddress and + Length from their current attributes to the attributes specified by Attr= ibutes. + + Caller should make sure BaseAddress and Length is at page boundary. + + Caller need guarentee the TPL <=3D TPL_NOTIFY, if there is split page re= quest. + + @param PagingContext The paging context. NULL means get page table = from current CPU context. + @param BaseAddress The physical address that is the start address= of a memory region. + @param Length The size in bytes of the memory region. + @param Attributes The bit mask of attributes to set for the memo= ry region. + @param AllocatePagesFunc If page split is needed, this function is used= to allocate more pages. + NULL mean page split is unsupported. + + @retval RETURN_SUCCESS The attributes were cleared for the mem= ory region. + @retval RETURN_ACCESS_DENIED The attributes for the memory resource = range specified by + BaseAddress and Length cannot be modifi= ed. + @retval RETURN_INVALID_PARAMETER Length is zero. + Attributes specified an illegal combina= tion of attributes that + cannot be set together. + @retval RETURN_OUT_OF_RESOURCES There are not enough system resources t= o modify the attributes of + the memory resource range. + @retval RETURN_UNSUPPORTED The processor does not support one or m= ore bytes of the memory + resource range specified by BaseAddress= and Length. + The bit mask of attributes is not suppo= rt for the memory resource + range specified by BaseAddress and Leng= th. +**/ +RETURN_STATUS +EFIAPI +AssignMemoryPageAttributes ( + IN PAGE_TABLE_LIB_PAGING_CONTEXT *PagingContext OPTIONAL, + IN PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + IN UINT64 Attributes, + IN PAGE_TABLE_LIB_ALLOCATE_PAGES AllocatePagesFunc OPTIONAL + ); + +/** + Initialize the Page Table lib. +**/ +VOID +InitializePageTableLib ( + VOID + ); + +#endif --=20 2.7.4.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat Nov 2 14:26:21 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zoho.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 148662484227311.049033032710327; Wed, 8 Feb 2017 23:20:42 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 3017482093; Wed, 8 Feb 2017 23:20:38 -0800 (PST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id B443482027 for ; Wed, 8 Feb 2017 23:20:36 -0800 (PST) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga102.jf.intel.com with ESMTP; 08 Feb 2017 23:20:36 -0800 Received: from jyao1-mobl.ccr.corp.intel.com ([10.254.176.87]) by fmsmga002.fm.intel.com with ESMTP; 08 Feb 2017 23:20:36 -0800 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.35,349,1484035200"; d="scan'208";a="1124128247" From: Jiewen Yao To: edk2-devel@lists.01.org Date: Wed, 8 Feb 2017 23:20:30 -0800 Message-Id: <1486624832-15736-3-git-send-email-jiewen.yao@intel.com> X-Mailer: git-send-email 2.7.4.windows.1 In-Reply-To: <1486624832-15736-1-git-send-email-jiewen.yao@intel.com> References: <1486624832-15736-1-git-send-email-jiewen.yao@intel.com> Subject: [edk2] [PATCH V3 2/4] ArmPkg/CpuDxe: Correct EFI_MEMORY_RO usage X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Leif Lindholm , Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Current Arm CpuDxe driver uses EFI_MEMORY_WP for write protection, according to UEFI spec, we should use EFI_MEMORY_RO for write protection. The EFI_MEMORY_WP is the cache attribute instead of memory attribute. Cc: Leif Lindholm Cc: Ard Biesheuvel Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao --- ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c | 3 ++- ArmPkg/Drivers/CpuDxe/Arm/Mmu.c | 14 ++++++-------- ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c | 5 +++-- ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c | 3 ++- 4 files changed, 13 insertions(+), 12 deletions(-) diff --git a/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c b/ArmPkg/Drivers/CpuDxe/AA= rch64/Mmu.c index d8bb419..15d5a81 100644 --- a/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c +++ b/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c @@ -3,6 +3,7 @@ Copyright (c) 2009, Hewlett-Packard Company. All rights reserved.
Portions copyright (c) 2010, Apple Inc. All rights reserved.
Portions copyright (c) 2011-2013, ARM Ltd. All rights reserved.
+Copyright (c) 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License @@ -224,7 +225,7 @@ EfiAttributeToArmAttribute ( ArmAttributes |=3D TT_AF; =20 // Determine protection attributes - if (EfiAttributes & EFI_MEMORY_WP) { + if (EfiAttributes & EFI_MEMORY_RO) { ArmAttributes |=3D TT_AP_RO_RO; } =20 diff --git a/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c b/ArmPkg/Drivers/CpuDxe/Arm/Mm= u.c index 14fc22d..6dcfba6 100644 --- a/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c +++ b/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c @@ -3,6 +3,7 @@ Copyright (c) 2009, Hewlett-Packard Company. All rights reserved.
Portions copyright (c) 2010, Apple Inc. All rights reserved.
Portions copyright (c) 2013, ARM Ltd. All rights reserved.
+Copyright (c) 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License @@ -62,7 +63,7 @@ SectionToGcdAttributes ( // determine protection attributes switch(SectionAttributes & TT_DESCRIPTOR_SECTION_AP_MASK) { case TT_DESCRIPTOR_SECTION_AP_NO_NO: // no read, no write - //*GcdAttributes |=3D EFI_MEMORY_WP | EFI_MEMORY_RP; + //*GcdAttributes |=3D EFI_MEMORY_RO | EFI_MEMORY_RP; break; =20 case TT_DESCRIPTOR_SECTION_AP_RW_NO: @@ -73,7 +74,7 @@ SectionToGcdAttributes ( // read only cases map to write-protect case TT_DESCRIPTOR_SECTION_AP_RO_NO: case TT_DESCRIPTOR_SECTION_AP_RO_RO: - *GcdAttributes |=3D EFI_MEMORY_WP; + *GcdAttributes |=3D EFI_MEMORY_RO; break; =20 default: @@ -126,7 +127,7 @@ PageToGcdAttributes ( // determine protection attributes switch(PageAttributes & TT_DESCRIPTOR_PAGE_AP_MASK) { case TT_DESCRIPTOR_PAGE_AP_NO_NO: // no read, no write - //*GcdAttributes |=3D EFI_MEMORY_WP | EFI_MEMORY_RP; + //*GcdAttributes |=3D EFI_MEMORY_RO | EFI_MEMORY_RP; break; =20 case TT_DESCRIPTOR_PAGE_AP_RW_NO: @@ -137,7 +138,7 @@ PageToGcdAttributes ( // read only cases map to write-protect case TT_DESCRIPTOR_PAGE_AP_RO_NO: case TT_DESCRIPTOR_PAGE_AP_RO_RO: - *GcdAttributes |=3D EFI_MEMORY_WP; + *GcdAttributes |=3D EFI_MEMORY_RO; break; =20 default: @@ -730,9 +731,6 @@ EfiAttributeToArmAttribute ( ArmAttributes =3D TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLO= C; // TEX [2:0] =3D 001, C=3D1, B=3D1 break; =20 - case EFI_MEMORY_WP: - case EFI_MEMORY_XP: - case EFI_MEMORY_RP: case EFI_MEMORY_UCE: default: // Cannot be implemented UEFI definition unclear for ARM @@ -743,7 +741,7 @@ EfiAttributeToArmAttribute ( } =20 // Determine protection attributes - if (EfiAttributes & EFI_MEMORY_WP) { + if (EfiAttributes & EFI_MEMORY_RO) { ArmAttributes |=3D TT_DESCRIPTOR_SECTION_AP_RO_RO; } else { ArmAttributes |=3D TT_DESCRIPTOR_SECTION_AP_RW_RW; diff --git a/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c b/ArmPkg/Drivers/CpuDxe/C= puMmuCommon.c index 723604d..54d9b01 100644 --- a/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c +++ b/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c @@ -1,6 +1,7 @@ /** @file * * Copyright (c) 2013, ARM Limited. All rights reserved. +* Copyright (c) 2017, Intel Corporation. All rights reserved.
* * This program and the accompanying materials * are licensed and made available under the terms and conditions of the B= SD License @@ -236,7 +237,7 @@ CpuConvertPagesToUncachedVirtualAddress ( // be the PCI address. Code should always use the CPU address, and we wi= ll or in VirtualMask // to that address. // - Status =3D SetMemoryAttributes (Address, Length, EFI_MEMORY_WP, 0); + Status =3D SetMemoryAttributes (Address, Length, EFI_MEMORY_RO, 0); if (!EFI_ERROR (Status)) { Status =3D SetMemoryAttributes (Address | VirtualMask, Length, EFI_MEM= ORY_UC, VirtualMask); } @@ -264,7 +265,7 @@ CpuReconvertPages ( // // Unmap the aliased Address // - Status =3D SetMemoryAttributes (Address | VirtualMask, Length, EFI_MEMOR= Y_WP, 0); + Status =3D SetMemoryAttributes (Address | VirtualMask, Length, EFI_MEMOR= Y_RO, 0); if (!EFI_ERROR (Status)) { // // Restore atttributes diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/ArmPkg/Libr= ary/ArmMmuLib/AArch64/ArmMmuLibCore.c index 540069a..6aa970b 100644 --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c @@ -3,6 +3,7 @@ * * Copyright (c) 2011-2014, ARM Limited. All rights reserved. * Copyright (c) 2016, Linaro Limited. All rights reserved. +* Copyright (c) 2017, Intel Corporation. All rights reserved.
* * This program and the accompanying materials * are licensed and made available under the terms and conditions of the B= SD License @@ -89,7 +90,7 @@ PageAttributeToGcdAttribute ( // Determine protection attributes if (((PageAttributes & TT_AP_MASK) =3D=3D TT_AP_NO_RO) || ((PageAttribut= es & TT_AP_MASK) =3D=3D TT_AP_RO_RO)) { // Read only cases map to write-protect - GcdAttributes |=3D EFI_MEMORY_WP; + GcdAttributes |=3D EFI_MEMORY_RO; } =20 // Process eXecute Never attribute --=20 2.7.4.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat Nov 2 14:26:21 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zoho.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1486624844412999.4248314098776; Wed, 8 Feb 2017 23:20:44 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 74B0D82080; Wed, 8 Feb 2017 23:20:40 -0800 (PST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 1458B81FD1 for ; Wed, 8 Feb 2017 23:20:37 -0800 (PST) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga102.jf.intel.com with ESMTP; 08 Feb 2017 23:20:37 -0800 Received: from jyao1-mobl.ccr.corp.intel.com ([10.254.176.87]) by fmsmga002.fm.intel.com with ESMTP; 08 Feb 2017 23:20:36 -0800 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.35,349,1484035200"; d="scan'208";a="1124128252" From: Jiewen Yao To: edk2-devel@lists.01.org Date: Wed, 8 Feb 2017 23:20:31 -0800 Message-Id: <1486624832-15736-4-git-send-email-jiewen.yao@intel.com> X-Mailer: git-send-email 2.7.4.windows.1 In-Reply-To: <1486624832-15736-1-git-send-email-jiewen.yao@intel.com> References: <1486624832-15736-1-git-send-email-jiewen.yao@intel.com> Subject: [edk2] [PATCH V3 3/4] MdeModulePkg/dec: add PcdImageProtectionPolicy. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Kinney , Feng Tian , Star Zeng MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Add PCD for image protection policy. Cc: Star Zeng Cc: Feng Tian Cc: Michael Kinney Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao --- MdeModulePkg/MdeModulePkg.dec | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/MdeModulePkg/MdeModulePkg.dec b/MdeModulePkg/MdeModulePkg.dec index 273cd7e..ab0490f 100644 --- a/MdeModulePkg/MdeModulePkg.dec +++ b/MdeModulePkg/MdeModulePkg.dec @@ -1087,6 +1087,16 @@ # @Prompt Memory profile driver path. gEfiMdeModulePkgTokenSpaceGuid.PcdMemoryProfileDriverPath|{0x0}|VOID*|0x= 00001043 =20 + ## Set image protection policy. The policy is bitwise. + # If a bit is set, the image will be protected by DxeCore if it is alig= ned. + # The code section becomes read-only, and the data section becomes non= -executable. + # If a bit is clear, the image will not be protected.

+ # BIT0 - Image from unknown device.
+ # BIT1 - Image from firmware volume.
+ # @Prompt Set image protection policy. + # @ValidRange 0x80000002 | 0x00000000 - 0x0000001F + gEfiMdeModulePkgTokenSpaceGuid.PcdImageProtectionPolicy|0x00000002|UINT3= 2|0x00001047 + ## PCI Serial Device Info. It is an array of Device, Function, and Power= Management # information that describes the path that contains zero or more PCI to= PCI briges # followed by a PCI serial device. Each array entry is 4-bytes in leng= th. The --=20 2.7.4.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat Nov 2 14:26:21 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zoho.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1486624846690924.9969464251825; Wed, 8 Feb 2017 23:20:46 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id A7633820A9; Wed, 8 Feb 2017 23:20:40 -0800 (PST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 87BBD81FD1 for ; Wed, 8 Feb 2017 23:20:37 -0800 (PST) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga102.jf.intel.com with ESMTP; 08 Feb 2017 23:20:37 -0800 Received: from jyao1-mobl.ccr.corp.intel.com ([10.254.176.87]) by fmsmga002.fm.intel.com with ESMTP; 08 Feb 2017 23:20:36 -0800 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.35,349,1484035200"; d="scan'208";a="1124128256" From: Jiewen Yao To: edk2-devel@lists.01.org Date: Wed, 8 Feb 2017 23:20:32 -0800 Message-Id: <1486624832-15736-5-git-send-email-jiewen.yao@intel.com> X-Mailer: git-send-email 2.7.4.windows.1 In-Reply-To: <1486624832-15736-1-git-send-email-jiewen.yao@intel.com> References: <1486624832-15736-1-git-send-email-jiewen.yao@intel.com> Subject: [edk2] [PATCH V3 4/4] MdeModulePkg/DxeCore: Add UEFI image protection. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Kinney , Feng Tian , Star Zeng MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" If the UEFI image is page aligned, the image code section is set to read only and the image data section is set to non-executable. 1) This policy is applied for all UEFI image including boot service driver, runtime driver or application. 2) This policy is applied only if the UEFI image meets the page alignment requirement. 3) This policy is applied only if the Source UEFI image matches the PcdImageProtectionPolicy definition. 4) This policy is not applied to the non-PE image region. The DxeCore calls CpuArchProtocol->SetMemoryAttributes() to protect the image. If the CpuArch protocol is not installed yet, the DxeCore enqueues the protection request. Once the CpuArch is installed, the DxeCore dequeues the protection request and applies policy. Once the image is unloaded, the protection is removed automatically. NOTE: It is per-requisite that code section and data section should not be not merged. That is same criteria for SMM/runtime driver. We are not able to detect during BIOS boot, because we can only get LINK warning below: "LINK : warning LNK4254: section '.data' (C0000040) merged into '.text' (60000020) with different attributes" But final attribute in PE code section is same. Cc: Star Zeng Cc: Feng Tian Cc: Michael Kinney Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao --- MdeModulePkg/Core/Dxe/DxeMain.h | 53 ++ MdeModulePkg/Core/Dxe/DxeMain.inf | 5 +- MdeModulePkg/Core/Dxe/DxeMain/DxeMain.c | 3 +- MdeModulePkg/Core/Dxe/Image/Image.c | 7 +- MdeModulePkg/Core/Dxe/Misc/MemoryProtection.c | 735 ++++++++++++++++++++ MdeModulePkg/Core/Dxe/Misc/PropertiesTable.c | 24 +- 6 files changed, 801 insertions(+), 26 deletions(-) diff --git a/MdeModulePkg/Core/Dxe/DxeMain.h b/MdeModulePkg/Core/Dxe/DxeMai= n.h index ae35fbb..67b5a5a 100644 --- a/MdeModulePkg/Core/Dxe/DxeMain.h +++ b/MdeModulePkg/Core/Dxe/DxeMain.h @@ -267,6 +267,26 @@ typedef struct { #define LOADED_IMAGE_PRIVATE_DATA_FROM_THIS(a) \ CR(a, LOADED_IMAGE_PRIVATE_DATA, Info, LOADED_IMAGE_PRIVATE_DATA= _SIGNATURE) =20 +#define IMAGE_PROPERTIES_RECORD_CODE_SECTION_SIGNATURE SIGNATURE_32 ('I','= P','R','C') + +typedef struct { + UINT32 Signature; + LIST_ENTRY Link; + EFI_PHYSICAL_ADDRESS CodeSegmentBase; + UINT64 CodeSegmentSize; +} IMAGE_PROPERTIES_RECORD_CODE_SECTION; + +#define IMAGE_PROPERTIES_RECORD_SIGNATURE SIGNATURE_32 ('I','P','R','D') + +typedef struct { + UINT32 Signature; + LIST_ENTRY Link; + EFI_PHYSICAL_ADDRESS ImageBase; + UINT64 ImageSize; + UINTN CodeSegmentCount; + LIST_ENTRY CodeSegmentList; +} IMAGE_PROPERTIES_RECORD; + // // DXE Core Global Variables // @@ -2859,6 +2879,15 @@ CoreInitializeMemoryAttributesTable ( ); =20 /** + Initialize Memory Protection support. +**/ +VOID +EFIAPI +CoreInitializeMemoryProtection ( + VOID + ); + +/** Install MemoryAttributesTable on memory allocation. =20 @param[in] MemoryType EFI memory type. @@ -2888,4 +2917,28 @@ RemoveImageRecord ( IN EFI_RUNTIME_IMAGE_ENTRY *RuntimeImage ); =20 +/** + Protect UEFI image. + + @param[in] LoadedImage The loaded image protocol + @param[in] LoadedImageDevicePath The loaded image device path protoc= ol +**/ +VOID +ProtectUefiImage ( + IN EFI_LOADED_IMAGE_PROTOCOL *LoadedImage, + IN EFI_DEVICE_PATH_PROTOCOL *LoadedImageDevicePath + ); + +/** + Unprotect UEFI image. + + @param[in] LoadedImage The loaded image protocol + @param[in] LoadedImageDevicePath The loaded image device path protoc= ol +**/ +VOID +UnprotectUefiImage ( + IN EFI_LOADED_IMAGE_PROTOCOL *LoadedImage, + IN EFI_DEVICE_PATH_PROTOCOL *LoadedImageDevicePath + ); + #endif diff --git a/MdeModulePkg/Core/Dxe/DxeMain.inf b/MdeModulePkg/Core/Dxe/DxeM= ain.inf index 13a2381..371e91c 100644 --- a/MdeModulePkg/Core/Dxe/DxeMain.inf +++ b/MdeModulePkg/Core/Dxe/DxeMain.inf @@ -3,7 +3,7 @@ # # It provides an implementation of DXE Core that is compliant with DXE CI= S. # =20 -# Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+# Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
# This program and the accompanying materials # are licensed and made available under the terms and conditions of the B= SD License # which accompanies this distribution. The full text of the license may = be found at @@ -42,6 +42,7 @@ Misc/InstallConfigurationTable.c Misc/PropertiesTable.c Misc/MemoryAttributesTable.c + Misc/MemoryProtection.c Library/Library.c Hand/DriverSupport.c Hand/Notify.c @@ -159,6 +160,7 @@ gEfiHiiPackageListProtocolGuid ## SOMETIMES_PRODUCES gEfiEbcProtocolGuid ## SOMETIMES_CONSUMES gEfiSmmBase2ProtocolGuid ## SOMETIMES_CONSUMES + gEfiBlockIoProtocolGuid ## SOMETIMES_CONSUMES =20 # Arch Protocols gEfiBdsArchProtocolGuid ## CONSUMES @@ -188,6 +190,7 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdMemoryProfilePropertyMask = ## CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdMemoryProfileDriverPath = ## CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdPropertiesTableEnable = ## CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdImageProtectionPolicy = ## CONSUMES =20 # [Hob] # RESOURCE_DESCRIPTOR ## CONSUMES diff --git a/MdeModulePkg/Core/Dxe/DxeMain/DxeMain.c b/MdeModulePkg/Core/Dx= e/DxeMain/DxeMain.c index 21cd61a..b133e5e 100644 --- a/MdeModulePkg/Core/Dxe/DxeMain/DxeMain.c +++ b/MdeModulePkg/Core/Dxe/DxeMain/DxeMain.c @@ -1,7 +1,7 @@ /** @file DXE Core Main Entry Point =20 -Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License which accompanies this distribution. The full text of the license may be = found at @@ -398,6 +398,7 @@ DxeMain ( =20 CoreInitializePropertiesTable (); CoreInitializeMemoryAttributesTable (); + CoreInitializeMemoryProtection (); =20 // // Get persisted vector hand-off info from GUIDeed HOB again due to HobS= tart may be updated, diff --git a/MdeModulePkg/Core/Dxe/Image/Image.c b/MdeModulePkg/Core/Dxe/Im= age/Image.c index 4a8a16d..652da8b 100644 --- a/MdeModulePkg/Core/Dxe/Image/Image.c +++ b/MdeModulePkg/Core/Dxe/Image/Image.c @@ -1,7 +1,7 @@ /** @file Core image handling services to load and unload PeImage. =20 -Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License which accompanies this distribution. The full text of the license may be = found at @@ -203,6 +203,8 @@ CoreInitializeImageServices ( ); } =20 + ProtectUefiImage (&Image->Info, Image->LoadedImageDevicePath); + return Status; } =20 @@ -862,6 +864,8 @@ CoreUnloadAndCloseImage ( UnregisterMemoryProfileImage (Image); } =20 + UnprotectUefiImage (&Image->Info, Image->LoadedImageDevicePath); + if (Image->Ebc !=3D NULL) { // // If EBC protocol exists we must perform cleanups for this image. @@ -1341,6 +1345,7 @@ CoreLoadImageCommon ( goto Done; } } + ProtectUefiImage (&Image->Info, Image->LoadedImageDevicePath); =20 // // Success. Return the image handle diff --git a/MdeModulePkg/Core/Dxe/Misc/MemoryProtection.c b/MdeModulePkg/C= ore/Dxe/Misc/MemoryProtection.c new file mode 100644 index 0000000..72b5d95 --- /dev/null +++ b/MdeModulePkg/Core/Dxe/Misc/MemoryProtection.c @@ -0,0 +1,735 @@ +/** @file + UEFI Memory Protection support. + + If the UEFI image is page aligned, the image code section is set to read= only + and the image data section is set to non-executable. + + 1) This policy is applied for all UEFI image including boot service driv= er, + runtime driver or application. + 2) This policy is applied only if the UEFI image meets the page alignment + requirement. + 3) This policy is applied only if the Source UEFI image matches the + PcdImageProtectionPolicy definition. + 4) This policy is not applied to the non-PE image region. + + The DxeCore calls CpuArchProtocol->SetMemoryAttributes() to protect + the image. If the CpuArch protocol is not installed yet, the DxeCore + enqueues the protection request. Once the CpuArch is installed, the + DxeCore dequeues the protection request and applies policy. + + Once the image is unloaded, the protection is removed automatically. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials +are licensed and made available under the terms and conditions of the BSD = License +which accompanies this distribution. The full text of the license may be = found at +http://opensource.org/licenses/bsd-license.php + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLI= ED. + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + +#include "DxeMain.h" + +#define CACHE_ATTRIBUTE_MASK (EFI_MEMORY_UC | EFI_MEMORY_WC | EFI_MEMORY= _WT | EFI_MEMORY_WB | EFI_MEMORY_UCE | EFI_MEMORY_WP) +#define MEMORY_ATTRIBUTE_MASK (EFI_MEMORY_RP | EFI_MEMORY_XP | EFI_MEMORY= _RO) + +// +// Image type definitions +// +#define IMAGE_UNKNOWN 0x00000001 +#define IMAGE_FROM_FV 0x00000002 + +// +// Protection policy bit definition +// +#define DO_NOT_PROTECT 0x00000000 +#define PROTECT_IF_ALIGNED_ELSE_ALLOW 0x00000001 + +UINT32 mImageProtectionPolicy; + +/** + Sort code section in image record, based upon CodeSegmentBase from low t= o high. + + @param ImageRecord image record to be sorted +**/ +VOID +SortImageRecordCodeSection ( + IN IMAGE_PROPERTIES_RECORD *ImageRecord + ); + +/** + Check if code section in image record is valid. + + @param ImageRecord image record to be checked + + @retval TRUE image record is valid + @retval FALSE image record is invalid +**/ +BOOLEAN +IsImageRecordCodeSectionValid ( + IN IMAGE_PROPERTIES_RECORD *ImageRecord + ); + +/** + Get the image type. + + @param[in] File This is a pointer to the device path of the fil= e that is + being dispatched. + + @return UINT32 Image Type +**/ +UINT32 +GetImageType ( + IN CONST EFI_DEVICE_PATH_PROTOCOL *File + ) +{ + EFI_STATUS Status; + EFI_HANDLE DeviceHandle; + EFI_DEVICE_PATH_PROTOCOL *TempDevicePath; + + if (File =3D=3D NULL) { + return IMAGE_UNKNOWN; + } + + // + // First check to see if File is from a Firmware Volume + // + DeviceHandle =3D NULL; + TempDevicePath =3D (EFI_DEVICE_PATH_PROTOCOL *) File; + Status =3D gBS->LocateDevicePath ( + &gEfiFirmwareVolume2ProtocolGuid, + &TempDevicePath, + &DeviceHandle + ); + if (!EFI_ERROR (Status)) { + Status =3D gBS->OpenProtocol ( + DeviceHandle, + &gEfiFirmwareVolume2ProtocolGuid, + NULL, + NULL, + NULL, + EFI_OPEN_PROTOCOL_TEST_PROTOCOL + ); + if (!EFI_ERROR (Status)) { + return IMAGE_FROM_FV; + } + } + return IMAGE_UNKNOWN; +} + +/** + Get UEFI image protection policy based upon image type. + + @param[in] ImageType The UEFI image type + + @return UEFI image protection policy +**/ +UINT32 +GetProtectionPolicyFromImageType ( + IN UINT32 ImageType + ) +{ + if ((ImageType & mImageProtectionPolicy) =3D=3D 0) { + return DO_NOT_PROTECT; + } else { + return PROTECT_IF_ALIGNED_ELSE_ALLOW; + } +} + +/** + Get UEFI image protection policy based upon loaded image device path. + + @param[in] LoadedImage The loaded image protocol + @param[in] LoadedImageDevicePath The loaded image device path protoc= ol + + @return UEFI image protection policy +**/ +UINT32 +GetUefiImageProtectionPolicy ( + IN EFI_LOADED_IMAGE_PROTOCOL *LoadedImage, + IN EFI_DEVICE_PATH_PROTOCOL *LoadedImageDevicePath + ) +{ + BOOLEAN InSmm; + UINT32 ImageType; + UINT32 ProtectionPolicy; + + // + // Check SMM + // + InSmm =3D FALSE; + if (gSmmBase2 !=3D NULL) { + gSmmBase2->InSmm (gSmmBase2, &InSmm); + } + if (InSmm) { + return FALSE; + } + + // + // Check DevicePath + // + if (LoadedImage =3D=3D gDxeCoreLoadedImage) { + ImageType =3D IMAGE_FROM_FV; + } else { + ImageType =3D GetImageType (LoadedImageDevicePath); + } + ProtectionPolicy =3D GetProtectionPolicyFromImageType (ImageType); + return ProtectionPolicy; +} + + +/** + Set UEFI image memory attributes. + + @param[in] BaseAddress Specified start address + @param[in] Length Specified length + @param[in] Attributes Specified attributes +**/ +VOID +SetUefiImageMemoryAttributes ( + IN UINT64 BaseAddress, + IN UINT64 Length, + IN UINT64 Attributes + ) +{ + EFI_STATUS Status; + EFI_GCD_MEMORY_SPACE_DESCRIPTOR Descriptor; + UINT64 FinalAttributes; + + Status =3D CoreGetMemorySpaceDescriptor(BaseAddress, &Descriptor); + ASSERT_EFI_ERROR(Status); + + FinalAttributes =3D (Descriptor.Attributes & CACHE_ATTRIBUTE_MASK) | (At= tributes & MEMORY_ATTRIBUTE_MASK); + + DEBUG ((DEBUG_INFO, "SetUefiImageMemoryAttributes - 0x%016lx - 0x%016lx = (0x%016lx)\n", BaseAddress, Length, FinalAttributes)); + + ASSERT(gCpu !=3D NULL); + gCpu->SetMemoryAttributes (gCpu, BaseAddress, Length, FinalAttributes); +} + +/** + Set UEFI image protection attributes. + + @param[in] ImageRecord A UEFI image record + @param[in] Protect TRUE: Protect the UEFI image. + FALSE: Unprotect the UEFI image. +**/ +VOID +SetUefiImageProtectionAttributes ( + IN IMAGE_PROPERTIES_RECORD *ImageRecord, + IN BOOLEAN Protect + ) +{ + IMAGE_PROPERTIES_RECORD_CODE_SECTION *ImageRecordCodeSection; + LIST_ENTRY *ImageRecordCodeSectionLink; + LIST_ENTRY *ImageRecordCodeSectionEndLink; + LIST_ENTRY *ImageRecordCodeSectionList; + UINT64 CurrentBase; + UINT64 ImageEnd; + UINT64 Attribute; + + ImageRecordCodeSectionList =3D &ImageRecord->CodeSegmentList; + + CurrentBase =3D ImageRecord->ImageBase; + ImageEnd =3D ImageRecord->ImageBase + ImageRecord->ImageSize; + + ImageRecordCodeSectionLink =3D ImageRecordCodeSectionList->ForwardLink; + ImageRecordCodeSectionEndLink =3D ImageRecordCodeSectionList; + while (ImageRecordCodeSectionLink !=3D ImageRecordCodeSectionEndLink) { + ImageRecordCodeSection =3D CR ( + ImageRecordCodeSectionLink, + IMAGE_PROPERTIES_RECORD_CODE_SECTION, + Link, + IMAGE_PROPERTIES_RECORD_CODE_SECTION_SIGNAT= URE + ); + ImageRecordCodeSectionLink =3D ImageRecordCodeSectionLink->ForwardLink; + + ASSERT (CurrentBase <=3D ImageRecordCodeSection->CodeSegmentBase); + if (CurrentBase < ImageRecordCodeSection->CodeSegmentBase) { + // + // DATA + // + if (Protect) { + Attribute =3D EFI_MEMORY_XP; + } else { + Attribute =3D 0; + } + SetUefiImageMemoryAttributes ( + CurrentBase, + ImageRecordCodeSection->CodeSegmentBase - CurrentBase, + Attribute + ); + } + // + // CODE + // + if (Protect) { + Attribute =3D EFI_MEMORY_RO; + } else { + Attribute =3D 0; + } + SetUefiImageMemoryAttributes ( + ImageRecordCodeSection->CodeSegmentBase, + ImageRecordCodeSection->CodeSegmentSize, + Attribute + ); + CurrentBase =3D ImageRecordCodeSection->CodeSegmentBase + ImageRecordC= odeSection->CodeSegmentSize; + } + // + // Last DATA + // + ASSERT (CurrentBase <=3D ImageEnd); + if (CurrentBase < ImageEnd) { + // + // DATA + // + if (Protect) { + Attribute =3D EFI_MEMORY_XP; + } else { + Attribute =3D 0; + } + SetUefiImageMemoryAttributes ( + CurrentBase, + ImageEnd - CurrentBase, + Attribute + ); + } + return ; +} + +/** + Return if the PE image section is aligned. + + @param[in] SectionAlignment PE/COFF section alignment + @param[in] MemoryType PE/COFF image memory type + + @retval TRUE The PE image section is aligned. + @retval FALSE The PE image section is not aligned. +**/ +BOOLEAN +IsMemoryProtectionSectionAligned ( + IN UINT32 SectionAlignment, + IN EFI_MEMORY_TYPE MemoryType + ) +{ + UINT32 PageAlignment; + + switch (MemoryType) { + case EfiRuntimeServicesCode: + case EfiACPIMemoryNVS: + PageAlignment =3D EFI_ACPI_RUNTIME_PAGE_ALLOCATION_ALIGNMENT; + break; + case EfiRuntimeServicesData: + case EfiACPIReclaimMemory: + ASSERT (FALSE); + PageAlignment =3D EFI_ACPI_RUNTIME_PAGE_ALLOCATION_ALIGNMENT; + break; + case EfiBootServicesCode: + case EfiLoaderCode: + case EfiReservedMemoryType: + PageAlignment =3D EFI_PAGE_SIZE; + break; + default: + ASSERT (FALSE); + PageAlignment =3D EFI_PAGE_SIZE; + break; + } + + if ((SectionAlignment & (PageAlignment - 1)) !=3D 0) { + return FALSE; + } else { + return TRUE; + } +} + +/** + Free Image record. + + @param[in] ImageRecord A UEFI image record +**/ +VOID +FreeImageRecord ( + IN IMAGE_PROPERTIES_RECORD *ImageRecord + ) +{ + LIST_ENTRY *CodeSegmentListHead; + IMAGE_PROPERTIES_RECORD_CODE_SECTION *ImageRecordCodeSection; + + CodeSegmentListHead =3D &ImageRecord->CodeSegmentList; + while (!IsListEmpty (CodeSegmentListHead)) { + ImageRecordCodeSection =3D CR ( + CodeSegmentListHead->ForwardLink, + IMAGE_PROPERTIES_RECORD_CODE_SECTION, + Link, + IMAGE_PROPERTIES_RECORD_CODE_SECTION_SIGNAT= URE + ); + RemoveEntryList (&ImageRecordCodeSection->Link); + FreePool (ImageRecordCodeSection); + } + + if (ImageRecord->Link.ForwardLink !=3D NULL) { + RemoveEntryList (&ImageRecord->Link); + } + FreePool (ImageRecord); +} + +/** + Protect or unprotect UEFI image common function. + + @param[in] LoadedImage The loaded image protocol + @param[in] LoadedImageDevicePath The loaded image device path protoc= ol + @param[in] Protect TRUE: Protect the UEFI image. + FALSE: Unprotect the UEFI image. +**/ +VOID +ProtectUefiImageCommon ( + IN EFI_LOADED_IMAGE_PROTOCOL *LoadedImage, + IN EFI_DEVICE_PATH_PROTOCOL *LoadedImageDevicePath, + IN BOOLEAN Protect + ) +{ + VOID *ImageAddress; + EFI_IMAGE_DOS_HEADER *DosHdr; + UINT32 PeCoffHeaderOffset; + UINT32 SectionAlignment; + EFI_IMAGE_SECTION_HEADER *Section; + EFI_IMAGE_OPTIONAL_HEADER_PTR_UNION Hdr; + UINT8 *Name; + UINTN Index; + IMAGE_PROPERTIES_RECORD *ImageRecord; + CHAR8 *PdbPointer; + IMAGE_PROPERTIES_RECORD_CODE_SECTION *ImageRecordCodeSection; + UINT16 Magic; + BOOLEAN IsAligned; + UINT32 ProtectionPolicy; + + DEBUG ((DEBUG_INFO, "ProtectUefiImageCommon - 0x%x\n", LoadedImage)); + DEBUG ((DEBUG_INFO, " - 0x%016lx - 0x%016lx\n", (EFI_PHYSICAL_ADDRESS)(= UINTN)LoadedImage->ImageBase, LoadedImage->ImageSize)); + + if (gCpu =3D=3D NULL) { + return ; + } + + ProtectionPolicy =3D GetUefiImageProtectionPolicy (LoadedImage, LoadedIm= ageDevicePath); + switch (ProtectionPolicy) { + case DO_NOT_PROTECT: + return ; + case PROTECT_IF_ALIGNED_ELSE_ALLOW: + break; + default: + ASSERT(FALSE); + return ; + } + + ImageRecord =3D AllocateZeroPool (sizeof(*ImageRecord)); + if (ImageRecord =3D=3D NULL) { + return ; + } + ImageRecord->Signature =3D IMAGE_PROPERTIES_RECORD_SIGNATURE; + + // + // Step 1: record whole region + // + ImageRecord->ImageBase =3D (EFI_PHYSICAL_ADDRESS)(UINTN)LoadedImage->Ima= geBase; + ImageRecord->ImageSize =3D LoadedImage->ImageSize; + + ImageAddress =3D LoadedImage->ImageBase; + + PdbPointer =3D PeCoffLoaderGetPdbPointer ((VOID*) (UINTN) ImageAddress); + if (PdbPointer !=3D NULL) { + DEBUG ((DEBUG_VERBOSE, " Image - %a\n", PdbPointer)); + } + + // + // Check PE/COFF image + // + DosHdr =3D (EFI_IMAGE_DOS_HEADER *) (UINTN) ImageAddress; + PeCoffHeaderOffset =3D 0; + if (DosHdr->e_magic =3D=3D EFI_IMAGE_DOS_SIGNATURE) { + PeCoffHeaderOffset =3D DosHdr->e_lfanew; + } + + Hdr.Pe32 =3D (EFI_IMAGE_NT_HEADERS32 *)((UINT8 *) (UINTN) ImageAddress += PeCoffHeaderOffset); + if (Hdr.Pe32->Signature !=3D EFI_IMAGE_NT_SIGNATURE) { + DEBUG ((DEBUG_VERBOSE, "Hdr.Pe32->Signature invalid - 0x%x\n", Hdr.Pe3= 2->Signature)); + // It might be image in SMM. + goto Finish; + } + + // + // Get SectionAlignment + // + if (Hdr.Pe32->FileHeader.Machine =3D=3D IMAGE_FILE_MACHINE_IA64 && Hdr.P= e32->OptionalHeader.Magic =3D=3D EFI_IMAGE_NT_OPTIONAL_HDR32_MAGIC) { + // + // NOTE: Some versions of Linux ELILO for Itanium have an incorrect ma= gic value + // in the PE/COFF Header. If the MachineType is Itanium(IA64) an= d the + // Magic value in the OptionalHeader is EFI_IMAGE_NT_OPTIONAL_HD= R32_MAGIC + // then override the magic value to EFI_IMAGE_NT_OPTIONAL_HDR64_= MAGIC + // + Magic =3D EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC; + } else { + // + // Get the magic value from the PE/COFF Optional Header + // + Magic =3D Hdr.Pe32->OptionalHeader.Magic; + } + if (Magic =3D=3D EFI_IMAGE_NT_OPTIONAL_HDR32_MAGIC) { + SectionAlignment =3D Hdr.Pe32->OptionalHeader.SectionAlignment; + } else { + SectionAlignment =3D Hdr.Pe32Plus->OptionalHeader.SectionAlignment; + } + + IsAligned =3D IsMemoryProtectionSectionAligned (SectionAlignment, Loaded= Image->ImageCodeType); + if (!IsAligned) { + DEBUG ((DEBUG_VERBOSE, "!!!!!!!! ProtectUefiImageCommon - Section Ali= gnment(0x%x) is incorrect !!!!!!!!\n", + SectionAlignment)); + PdbPointer =3D PeCoffLoaderGetPdbPointer ((VOID*) (UINTN) ImageAddress= ); + if (PdbPointer !=3D NULL) { + DEBUG ((DEBUG_VERBOSE, "!!!!!!!! Image - %a !!!!!!!!\n", PdbPointe= r)); + } + goto Finish; + } + + Section =3D (EFI_IMAGE_SECTION_HEADER *) ( + (UINT8 *) (UINTN) ImageAddress + + PeCoffHeaderOffset + + sizeof(UINT32) + + sizeof(EFI_IMAGE_FILE_HEADER) + + Hdr.Pe32->FileHeader.SizeOfOptionalHeader + ); + ImageRecord->CodeSegmentCount =3D 0; + InitializeListHead (&ImageRecord->CodeSegmentList); + for (Index =3D 0; Index < Hdr.Pe32->FileHeader.NumberOfSections; Index++= ) { + Name =3D Section[Index].Name; + DEBUG (( + DEBUG_VERBOSE, + " Section - '%c%c%c%c%c%c%c%c'\n", + Name[0], + Name[1], + Name[2], + Name[3], + Name[4], + Name[5], + Name[6], + Name[7] + )); + + if ((Section[Index].Characteristics & EFI_IMAGE_SCN_CNT_CODE) !=3D 0) { + DEBUG ((DEBUG_VERBOSE, " VirtualSize - 0x%08x\n", Section[= Index].Misc.VirtualSize)); + DEBUG ((DEBUG_VERBOSE, " VirtualAddress - 0x%08x\n", Section[= Index].VirtualAddress)); + DEBUG ((DEBUG_VERBOSE, " SizeOfRawData - 0x%08x\n", Section[= Index].SizeOfRawData)); + DEBUG ((DEBUG_VERBOSE, " PointerToRawData - 0x%08x\n", Section[= Index].PointerToRawData)); + DEBUG ((DEBUG_VERBOSE, " PointerToRelocations - 0x%08x\n", Section[= Index].PointerToRelocations)); + DEBUG ((DEBUG_VERBOSE, " PointerToLinenumbers - 0x%08x\n", Section[= Index].PointerToLinenumbers)); + DEBUG ((DEBUG_VERBOSE, " NumberOfRelocations - 0x%08x\n", Section[= Index].NumberOfRelocations)); + DEBUG ((DEBUG_VERBOSE, " NumberOfLinenumbers - 0x%08x\n", Section[= Index].NumberOfLinenumbers)); + DEBUG ((DEBUG_VERBOSE, " Characteristics - 0x%08x\n", Section[= Index].Characteristics)); + + // + // Step 2: record code section + // + ImageRecordCodeSection =3D AllocatePool (sizeof(*ImageRecordCodeSect= ion)); + if (ImageRecordCodeSection =3D=3D NULL) { + return ; + } + ImageRecordCodeSection->Signature =3D IMAGE_PROPERTIES_RECORD_CODE_S= ECTION_SIGNATURE; + + ImageRecordCodeSection->CodeSegmentBase =3D (UINTN)ImageAddress + Se= ction[Index].VirtualAddress; + ImageRecordCodeSection->CodeSegmentSize =3D ALIGN_VALUE(Section[Inde= x].SizeOfRawData, SectionAlignment); + + DEBUG ((DEBUG_VERBOSE, "ImageCode: 0x%016lx - 0x%016lx\n", ImageReco= rdCodeSection->CodeSegmentBase, ImageRecordCodeSection->CodeSegmentSize)); + + InsertTailList (&ImageRecord->CodeSegmentList, &ImageRecordCodeSecti= on->Link); + ImageRecord->CodeSegmentCount++; + } + } + + if (ImageRecord->CodeSegmentCount =3D=3D 0) { + DEBUG ((DEBUG_ERROR, "!!!!!!!! ProtectUefiImageCommon - CodeSegmentCo= unt is 0 !!!!!!!!\n")); + PdbPointer =3D PeCoffLoaderGetPdbPointer ((VOID*) (UINTN) ImageAddress= ); + if (PdbPointer !=3D NULL) { + DEBUG ((DEBUG_ERROR, "!!!!!!!! Image - %a !!!!!!!!\n", PdbPointer)= ); + } + goto Finish; + } + + // + // Final + // + SortImageRecordCodeSection (ImageRecord); + // + // Check overlap all section in ImageBase/Size + // + if (!IsImageRecordCodeSectionValid (ImageRecord)) { + DEBUG ((DEBUG_ERROR, "IsImageRecordCodeSectionValid - FAIL\n")); + goto Finish; + } + + // + // CPU ARCH present. Update memory attribute directly. + // + SetUefiImageProtectionAttributes (ImageRecord, Protect); + + // + // Clean up + // + FreeImageRecord (ImageRecord); + +Finish: + return ; +} + +/** + Protect UEFI image. + + @param[in] LoadedImage The loaded image protocol + @param[in] LoadedImageDevicePath The loaded image device path protoc= ol +**/ +VOID +ProtectUefiImage ( + IN EFI_LOADED_IMAGE_PROTOCOL *LoadedImage, + IN EFI_DEVICE_PATH_PROTOCOL *LoadedImageDevicePath + ) +{ + if (PcdGet32(PcdImageProtectionPolicy) !=3D 0) { + ProtectUefiImageCommon (LoadedImage, LoadedImageDevicePath, TRUE); + } +} + +/** + Unprotect UEFI image. + + @param[in] LoadedImage The loaded image protocol + @param[in] LoadedImageDevicePath The loaded image device path protoc= ol +**/ +VOID +UnprotectUefiImage ( + IN EFI_LOADED_IMAGE_PROTOCOL *LoadedImage, + IN EFI_DEVICE_PATH_PROTOCOL *LoadedImageDevicePath + ) +{ + if (PcdGet32(PcdImageProtectionPolicy) !=3D 0) { + ProtectUefiImageCommon (LoadedImage, LoadedImageDevicePath, FALSE); + } +} + +/** + A notification for CPU_ARCH protocol. + + @param[in] Event Event whose notification function is b= eing invoked. + @param[in] Context Pointer to the notification function's= context, + which is implementation-dependent. + +**/ +VOID +EFIAPI +MemoryProtectionCpuArchProtocolNotify ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + EFI_STATUS Status; + EFI_LOADED_IMAGE_PROTOCOL *LoadedImage; + EFI_DEVICE_PATH_PROTOCOL *LoadedImageDevicePath; + UINTN NoHandles; + EFI_HANDLE *HandleBuffer; + UINTN Index; + + DEBUG ((DEBUG_INFO, "MemoryProtectionCpuArchProtocolNotify:\n")); + Status =3D CoreLocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)= &gCpu); + if (EFI_ERROR (Status)) { + return; + } + + Status =3D gBS->LocateHandleBuffer ( + ByProtocol, + &gEfiLoadedImageProtocolGuid, + NULL, + &NoHandles, + &HandleBuffer + ); + if (EFI_ERROR (Status) && (NoHandles =3D=3D 0)) { + return ; + } + + for (Index =3D 0; Index < NoHandles; Index++) { + Status =3D gBS->HandleProtocol ( + HandleBuffer[Index], + &gEfiLoadedImageProtocolGuid, + (VOID **)&LoadedImage + ); + if (EFI_ERROR(Status)) { + continue; + } + Status =3D gBS->HandleProtocol ( + HandleBuffer[Index], + &gEfiLoadedImageDevicePathProtocolGuid, + (VOID **)&LoadedImageDevicePath + ); + if (EFI_ERROR(Status)) { + LoadedImageDevicePath =3D NULL; + } + + ProtectUefiImage (LoadedImage, LoadedImageDevicePath); + } + + CoreCloseEvent (Event); + return; +} + +/** + Initialize Memory Protection support. +**/ +VOID +EFIAPI +CoreInitializeMemoryProtection ( + VOID + ) +{ + EFI_STATUS Status; + EFI_EVENT Event; + VOID *Registration; + + mImageProtectionPolicy =3D PcdGet32(PcdImageProtectionPolicy); + + if (mImageProtectionPolicy !=3D 0) { + Status =3D CoreCreateEvent ( + EVT_NOTIFY_SIGNAL, + TPL_CALLBACK, + MemoryProtectionCpuArchProtocolNotify, + NULL, + &Event + ); + ASSERT_EFI_ERROR(Status); + + // + // Register for protocol notifactions on this event + // + Status =3D CoreRegisterProtocolNotify ( + &gEfiCpuArchProtocolGuid, + Event, + &Registration + ); + ASSERT_EFI_ERROR(Status); + } + return ; +} diff --git a/MdeModulePkg/Core/Dxe/Misc/PropertiesTable.c b/MdeModulePkg/Co= re/Dxe/Misc/PropertiesTable.c index 7ecad89..5ea20db 100644 --- a/MdeModulePkg/Core/Dxe/Misc/PropertiesTable.c +++ b/MdeModulePkg/Core/Dxe/Misc/PropertiesTable.c @@ -1,7 +1,7 @@ /** @file UEFI PropertiesTable support =20 -Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License which accompanies this distribution. The full text of the license may be = found at @@ -36,26 +36,6 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHE= R EXPRESS OR IMPLIED. #define PREVIOUS_MEMORY_DESCRIPTOR(MemoryDescriptor, Size) \ ((EFI_MEMORY_DESCRIPTOR *)((UINT8 *)(MemoryDescriptor) - (Size))) =20 -#define IMAGE_PROPERTIES_RECORD_CODE_SECTION_SIGNATURE SIGNATURE_32 ('I','= P','R','C') - -typedef struct { - UINT32 Signature; - LIST_ENTRY Link; - EFI_PHYSICAL_ADDRESS CodeSegmentBase; - UINT64 CodeSegmentSize; -} IMAGE_PROPERTIES_RECORD_CODE_SECTION; - -#define IMAGE_PROPERTIES_RECORD_SIGNATURE SIGNATURE_32 ('I','P','R','D') - -typedef struct { - UINT32 Signature; - LIST_ENTRY Link; - EFI_PHYSICAL_ADDRESS ImageBase; - UINT64 ImageSize; - UINTN CodeSegmentCount; - LIST_ENTRY CodeSegmentList; -} IMAGE_PROPERTIES_RECORD; - #define IMAGE_PROPERTIES_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('I','P','P',= 'D') =20 typedef struct { @@ -864,7 +844,6 @@ SwapImageRecordCodeSection ( =20 @param ImageRecord image record to be sorted **/ -STATIC VOID SortImageRecordCodeSection ( IN IMAGE_PROPERTIES_RECORD *ImageRecord @@ -915,7 +894,6 @@ SortImageRecordCodeSection ( @retval TRUE image record is valid @retval FALSE image record is invalid **/ -STATIC BOOLEAN IsImageRecordCodeSectionValid ( IN IMAGE_PROPERTIES_RECORD *ImageRecord --=20 2.7.4.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel