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Tue, 22 Feb 2022 02:42:16 +0000 X-Received: from rnnvmail205.nvidia.com (10.129.68.10) by DRHQMAIL107.nvidia.com (10.27.9.16) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 22 Feb 2022 02:42:15 +0000 X-Received: from rnnvmail201.nvidia.com (10.129.68.8) by rnnvmail205.nvidia.com (10.129.68.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.9; Mon, 21 Feb 2022 18:42:15 -0800 X-Received: from ashishsingha-lnx.nvidia.com (10.127.8.11) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server id 15.2.986.9 via Frontend Transport; Mon, 21 Feb 2022 18:42:14 -0800 From: "Ashish Singhal via groups.io" To: , , , CC: Ashish Singhal Subject: [edk2-devel] [PATCH] ArmPkg: Invalidate Instruction Cache On MMU Enable Date: Mon, 21 Feb 2022 19:42:12 -0700 Message-ID: <122c32bb19ed0730ef166b9f46d3b112bc9ed937.1645497637.git.ashishsingha@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 33472188-4441-412c-7b25-08d9f5acf08b X-MS-TrafficTypeDiagnostic: BY5PR12MB4802:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Message-Info: qP1tLCtjdYvGQMT9iWtjlt46+296hrbjTSUEGVJEf8mB85b0p/ZwTQhWQkhZKzAmvMerq0rwBYQnfsz/E3gLDNOROFdS3yaSBt/JajjVWfOZ+LReSsdyQCsoA4IwnqXR4nEdc/+hv8QbmnXQjX/lnpjW0Q/dRyYb769cx3mELHNmLP8U/iP3a6y40uJUQVcNuix1JLX0S4tENeANrrFOdoJY3tsP/zlBzhFdrL5rbL9qyW2Pp+RpQHuED72/5vWKMm8/zxyyyOPgdBNk6Ex/DuoecTNhbjHbBYv/RRwzmpyiKpQI7fxpuzEegkaMbFuke+++9sj3ZqOG6BB3fE4M7D+OOATPJb9y5/6bkaU8WFD2ATgtKnWkZNyZplNOgO/e3wEKqg/0PCxGgIkh/aKBPiJUHqc3oioey+vtoogEeAXsor/CRWK6AwwT3bXZTek+y5z25/96LAFWisMJ2KqfiDLcZMxu2jLd4H5DQ68UsddBT0TFKC3FYWnaXVr2WmqvvkaQxzwg8VmZ8KhIERHLCPFqQWaV7ZD/ZsCMY7TV+IoUi8OAfdmloGysMEXoydUg2l9hh4k2A7hJvYygzVu4uxbXXrqC7u2MYSnr8kyV3J5mThzBqaMyhS9Sopur7BOYl3IfxegC3qhXQtEHhfyjI6Y7WBSRkLTH1bSvP/ibcplU/0YSWlqKkJPBP+k/aGH032SfJRrDH+niqP2x4t6M9w== X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Feb 2022 02:42:16.6926 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 33472188-4441-412c-7b25-08d9f5acf08b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.235];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT035.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4802 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ashishsingha@nvidia.com X-Gm-Message-State: bNV17VpHW0BdLrI60lUArpwdx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1645497740; bh=1g4MRR4XMYg1ou2snx6NTRloympBbJPNntGfBmqff6c=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=muhJEBU/jXiltNlBTkKssIVpkn7jRDlsbqLLY+xa5fUY5kEpcpSglVrNJ6LYSwsB0nI pf69w5QmCXlbGJqTcPfsQXD2fS2Fys1KzkaM5DtZDJm3CHo2ap1ogHwHb+DK21OE0cgjb ZWCLc2tTpf71cZsKemfldtDX/oRli4FWdc8= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1645497742745100002 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Even with MMU turned off, instruction cache can speculate and fetch instructions. This can cause a crash if region being executed has been modified recently. With this patch, we ensure that instruction cache is invalidated right after MMU has been enabled and any potentially stale instruction fetched earlier has been discarded. This is specially helpful when the memory attributes of a region in MMU are being changed and some instructions operating on the region are prefetched in the instruction cache. Signed-off-by: Ashish Singhal --- ArmPkg/Library/ArmLib/AArch64/AArch64Support.S | 4 +++- ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibReplaceEntry.S | 2 ++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S b/ArmPkg/Librar= y/ArmLib/AArch64/AArch64Support.S index d3cc1e8671..9648245182 100644 --- a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S +++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S @@ -89,7 +89,9 @@ ASM_FUNC(ArmEnableMmu) dsb nsh isb msr sctlr_el3, x0 // Write back -4: isb +4: ic iallu + dsb sy + isb ret =20 =20 diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibReplaceEntry.S b/Arm= Pkg/Library/ArmMmuLib/AArch64/ArmMmuLibReplaceEntry.S index 66ebca571e..56cc2dd73f 100644 --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibReplaceEntry.S +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibReplaceEntry.S @@ -37,6 +37,8 @@ =20 // re-enable the MMU msr sctlr_el\el, x8 + ic iallu + dsb sy isb .endm =20 --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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