This patch is to add the notifier for PLL0 clock and set the PLL0 rate
to 1.5GHz to fix the lower rate of CPUfreq on the JH7110 SoC.

The first patch is to add the notifier for PLL0 clock. Setting the PLL0
rate need the son clock (cpu_root) to switch its parent clock to OSC 
clock and switch it back after setting PLL0 rate. It need to use the 
cpu_root clock from SYSCRG and register the notifier in the SYSCRG
driver.

The second patch is to set cpu_core rate to 500MHz and PLL0 rate to
1.5GHz to fix the problem about the lower rate of CPUfreq on the 
visionfive board. The cpu_core clock rate is set to 500MHz first to
ensure that the cpu frequency will not suddenly become high and the cpu 
voltage is not enough to cause a crash when the PLL0 is set to 1.5GHz.
The cpu voltage and frequency are then adjusted together by CPUfreq.

Changes since v4:
- Fixed the wrong words.
- Added the Fixes tag in first patch.

v4: https://lore.kernel.org/all/20240410033148.213991-1-xingyu.wu@starfivetech.com/

Changes since v3: 
- Added the notifier for PLL0 clock.
- Set cpu_core rate in DTS 

v3: https://lore.kernel.org/all/20240402090920.11627-1-xingyu.wu@starfivetech.com/

Changes since v2: 
- Made the steps into the process into the process of setting PLL0 rate

v2: https://lore.kernel.org/all/20230821152915.208366-1-xingyu.wu@starfivetech.com/

Changes since v1: 
- Added the fixes tag in the commit.

v1: https://lore.kernel.org/all/20230811033631.160912-1-xingyu.wu@starfivetech.com/

Xingyu Wu (2):
  clk: starfive: jh7110-sys: Add notifier for PLL0 clock
  riscv: dts: starfive: visionfive-2: Fix lower rate of CPUfreq by
    setting PLL0 rate to 1.5GHz

 .../jh7110-starfive-visionfive-2.dtsi         |  6 ++++
 .../clk/starfive/clk-starfive-jh7110-sys.c    | 31 ++++++++++++++++++-
 drivers/clk/starfive/clk-starfive-jh71x0.h    |  2 ++
 3 files changed, 38 insertions(+), 1 deletion(-)

-- 
2.25.1

On Tue, May 07, 2024 at 02:53:17PM +0800, Xingyu Wu wrote:
> This patch is to add the notifier for PLL0 clock and set the PLL0 rate
> to 1.5GHz to fix the lower rate of CPUfreq on the JH7110 SoC.
> 
> The first patch is to add the notifier for PLL0 clock. Setting the PLL0
> rate need the son clock (cpu_root) to switch its parent clock to OSC 
> clock and switch it back after setting PLL0 rate. It need to use the 
> cpu_root clock from SYSCRG and register the notifier in the SYSCRG
> driver.
> 
> The second patch is to set cpu_core rate to 500MHz and PLL0 rate to
> 1.5GHz to fix the problem about the lower rate of CPUfreq on the 
> visionfive board. The cpu_core clock rate is set to 500MHz first to
> ensure that the cpu frequency will not suddenly become high and the cpu 
> voltage is not enough to cause a crash when the PLL0 is set to 1.5GHz.
> The cpu voltage and frequency are then adjusted together by CPUfreq.

Hmm, how does sequencing work here? If we split the patches between
trees it sounds like without the dts patch, the clock tree would (or
could) crash, or mainline if the clock changes there before the dts ones
do. Am I misunderstanding that?