From nobody Wed May 15 10:17:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of seabios.org designates 78.46.105.101 as permitted sender) client-ip=78.46.105.101; envelope-from=seabios-bounces@seabios.org; helo=coreboot.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of seabios.org designates 78.46.105.101 as permitted sender) smtp.mailfrom=seabios-bounces@seabios.org Return-Path: Received: from coreboot.org (coreboot.org [78.46.105.101]) by mx.zohomail.com with SMTPS id 1710214042934393.6944055686647; Mon, 11 Mar 2024 20:27:22 -0700 (PDT) Received: from authenticated-user (PRIMARY_HOSTNAME [PUBLIC_IP]) by coreboot.org (Postfix) with ESMTPA id DEE21219A0; Tue, 12 Mar 2024 03:27:17 +0000 (UTC) Received: from authenticated-user (PRIMARY_HOSTNAME [PUBLIC_IP]) by coreboot.org (Postfix) with ESMTP id B4C8D21B27 for ; Tue, 12 Mar 2024 03:27:00 +0000 (UTC) Received: from authenticated-user (PRIMARY_HOSTNAME [PUBLIC_IP]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1) server-digest SHA256) (No client certificate requested) (Authenticated sender: daniel@drv.nu) by oak.drv.nu (Postfix) with ESMTPSA id CACE4103045; Mon, 11 Mar 2024 20:26:58 -0700 (PDT) From: Daniel Verkamp To: seabios@seabios.org Date: Mon, 11 Mar 2024 20:26:18 -0700 Message-ID: <20240312032644.1439715-1-daniel@drv.nu> MIME-Version: 1.0 X-Spam-Level: ** Message-ID-Hash: 7FLVZVGLIL7T47B3YY5DQNFWFJRUG5FM X-Message-ID-Hash: 7FLVZVGLIL7T47B3YY5DQNFWFJRUG5FM X-MailFrom: daniel@drv.nu X-Mailman-Rule-Misses: dmarc-mitigation; no-senders; approved; emergency; loop; banned-address; member-moderation; header-match-seabios.seabios.org-0; header-match-seabios.seabios.org-1; nonmember-moderation; administrivia; implicit-dest; max-recipients; max-size; news-moderation; no-subject; digests; suspicious-header X-Mailman-Version: 3.3.6b1 Precedence: list Subject: [SeaBIOS] [PATCH v2] vbe: implement function 09h (get/set palette data) List-Id: SeaBIOS mailing list Archived-At: List-Archive: List-Help: List-Owner: List-Post: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable Authentication-Results: coreboot.org; auth=pass smtp.auth=mailman@coreboot.org smtp.mailfrom=seabios-bounces@seabios.org X-Spamd-Bar: / X-ZM-MESSAGEID: 1710214043759100001 Content-Type: text/plain; charset="utf-8" Since the VBE mode attributes indicate that all modes are not VGA compatible, applications must use VBE function 09h to manipulate the palette rather than directly accessing the VGA registers. This implementation uses the standard VGA registers for all hardware, which may not be appropriate; I only verified qemu -device VGA. Without this patch, the get/set palette function returns an error code, so programs that use 8-bit indexed color modes fail. For example, Quake (DOS) printed "Error: Unable to load VESA palette" and exited when trying to set a SVGA mode like 640x480, but with the patch it succeeds. This fixes qemu issue #251 and #1862. Signed-off-by: Daniel Verkamp --- V2: use existing stdvga_dac_read/write() functions vgasrc/vbe.c | 61 ++++++++++++++++++++++++++++++++++++++++++++++++++ vgasrc/vgahw.h | 10 +++++++++ 2 files changed, 71 insertions(+) diff --git a/vgasrc/vbe.c b/vgasrc/vbe.c index 91abc9ab..7e4b80bf 100644 --- a/vgasrc/vbe.c +++ b/vgasrc/vbe.c @@ -376,6 +376,66 @@ fail: regs->ax =3D 0x014f; } =20 +static void +vbe_104f09(struct bregs *regs) +{ + struct vgamode_s *vmode_g =3D get_current_mode(); + if (! vmode_g) + goto fail; + u8 memmodel =3D GET_GLOBAL(vmode_g->memmodel); + u8 depth =3D GET_GLOBAL(vmode_g->depth); + if (memmodel =3D=3D MM_DIRECT || memmodel =3D=3D MM_YUV || depth > 8) { + regs->ax =3D 0x034f; + return; + } + if (regs->dh) + goto fail; + u8 start =3D regs->dl; + int count =3D regs->cx; + int max_colors =3D 1 << depth; + if (start + count > max_colors) + goto fail; + u16 seg =3D regs->es; + u8 *data_far =3D (void*)(regs->di+0); + u8 rgb[3]; + int ret =3D 0; + int i; + switch (regs->bl) { + case 0x80: + case 0x00: + for (i =3D 0; i < count; i++) { + SET_SEG(ES, seg); + rgb[0] =3D GET_VAR(ES, data_far[i*4 + 2]); + rgb[1] =3D GET_VAR(ES, data_far[i*4 + 1]); + rgb[2] =3D GET_VAR(ES, data_far[i*4 + 0]); + ret =3D vgahw_dac_write(GET_SEG(SS), rgb, start + i, 1); + if (ret < 0) + goto fail; + } + break; + case 0x01: + for (i =3D 0; i < count; i++) { + ret =3D vgahw_dac_read(GET_SEG(SS), rgb, start + i, 1); + if (ret < 0) + goto fail; + SET_SEG(ES, seg); + SET_VAR(ES, data_far[i*4 + 0], rgb[2]); + SET_VAR(ES, data_far[i*4 + 1], rgb[1]); + SET_VAR(ES, data_far[i*4 + 2], rgb[0]); + SET_VAR(ES, data_far[i*4 + 3], 0); + } + break; + default: + goto fail; + } + if (ret < 0) + goto fail; + regs->ax =3D 0x004f; + return; +fail: + regs->ax =3D 0x014f; +} + static void vbe_104f0a(struct bregs *regs) { @@ -456,6 +516,7 @@ handle_104f(struct bregs *regs) case 0x06: vbe_104f06(regs); break; case 0x07: vbe_104f07(regs); break; case 0x08: vbe_104f08(regs); break; + case 0x09: vbe_104f09(regs); break; case 0x0a: vbe_104f0a(regs); break; case 0x10: vbe_104f10(regs); break; case 0x15: vbe_104f15(regs); break; diff --git a/vgasrc/vgahw.h b/vgasrc/vgahw.h index 8b64660e..b10075ac 100644 --- a/vgasrc/vgahw.h +++ b/vgasrc/vgahw.h @@ -141,6 +141,16 @@ static inline int vgahw_set_dacformat(struct vgamode_s= *vmode_g, int val) { return stdvga_set_dacformat(vmode_g, val); } =20 +static inline int vgahw_dac_write(u16 seg, u8 *data_far, u8 start, int cou= nt) { + stdvga_dac_write(seg, data_far, start, count); + return 0; +} + +static inline int vgahw_dac_read(u16 seg, u8 *data_far, u8 start, int coun= t) { + stdvga_dac_read(seg, data_far, start, count); + return 0; +} + static inline int vgahw_save_restore(int cmd, u16 seg, void *data) { if (CONFIG_VGA_CIRRUS) return clext_save_restore(cmd, seg, data); --=20 2.43.0 _______________________________________________ SeaBIOS mailing list -- seabios@seabios.org To unsubscribe send an email to seabios-leave@seabios.org