From nobody Tue May 14 21:31:26 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of seabios.org designates 78.46.105.101 as permitted sender) client-ip=78.46.105.101; envelope-from=seabios-bounces@seabios.org; helo=coreboot.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of seabios.org designates 78.46.105.101 as permitted sender) smtp.mailfrom=seabios-bounces@seabios.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from coreboot.org (coreboot.org [78.46.105.101]) by mx.zohomail.com with SMTPS id 1699879866132401.75307771249106; Mon, 13 Nov 2023 04:51:06 -0800 (PST) Received: from authenticated-user (PRIMARY_HOSTNAME [PUBLIC_IP]) by coreboot.org (Postfix) with ESMTPA id CAF48219BB; Mon, 13 Nov 2023 12:51:00 +0000 (UTC) Received: from authenticated-user (PRIMARY_HOSTNAME [PUBLIC_IP]) by coreboot.org (Postfix) with ESMTP id 4614423C53 for ; Mon, 13 Nov 2023 12:50:46 +0000 (UTC) Received: from authenticated-user (PRIMARY_HOSTNAME [PUBLIC_IP]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-94-0ZtkwhRDPvi-sEqN8aOC7A-1; Mon, 13 Nov 2023 07:50:41 -0500 Received: from authenticated-user (PRIMARY_HOSTNAME [PUBLIC_IP]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 3DFB13C1AC94; Mon, 13 Nov 2023 12:50:41 +0000 (UTC) Received: from authenticated-user (PRIMARY_HOSTNAME [PUBLIC_IP]) by smtp.corp.redhat.com (Postfix) with ESMTPS id EA8D85031; Mon, 13 Nov 2023 12:50:40 +0000 (UTC) Received: from authenticated-user (PRIMARY_HOSTNAME [PUBLIC_IP]) id 8AB061804A63; Mon, 13 Nov 2023 13:50:39 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1699879844; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding; bh=Onk9QxmyyaXrupbRmx0M+aIO5AGYsMNFSXnY/RPkB2M=; b=XycSumbSiLtkw2oowdUQRYR6BU8Xyo86bDP6UKYZq7PQqcFLCfOKIJiUAnFVRps6JYVXjb X+ykUPHgOO3VdvBFYkcv0iyg3++k2l03m98WPPDUxnOWwwup0xVYkKPVqbndnJO04s2HRW oQCBuHcQGrGHgWqOJqHYcp1gTMV3OHI= X-MC-Unique: 0ZtkwhRDPvi-sEqN8aOC7A-1 From: Gerd Hoffmann To: seabios@seabios.org Date: Mon, 13 Nov 2023 13:50:39 +0100 Message-ID: <20231113125039.57200-1-kraxel@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.4.1 on 10.11.54.5 Message-ID-Hash: PFSGTSQ7OZBIZ6FIKMMKJBMWZCTGBYPB X-Message-ID-Hash: PFSGTSQ7OZBIZ6FIKMMKJBMWZCTGBYPB X-MailFrom: kraxel@redhat.com X-Mailman-Rule-Misses: dmarc-mitigation; no-senders; approved; emergency; loop; banned-address; member-moderation; header-match-seabios.seabios.org-0; header-match-seabios.seabios.org-1; nonmember-moderation; administrivia; implicit-dest; max-recipients; max-size; news-moderation; no-subject; digests; suspicious-header CC: qemu-devel@nongnu.org, Gerd Hoffmann , Claudio Fontana X-Mailman-Version: 3.3.6b1 Precedence: list Subject: [SeaBIOS] [PATCH v6] limit address space used for pci devices. List-Id: SeaBIOS mailing list Archived-At: List-Archive: List-Help: List-Owner: List-Post: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable Authentication-Results: coreboot.org; auth=pass smtp.auth=mailman@coreboot.org smtp.mailfrom=seabios-bounces@seabios.org X-Spamd-Bar: / X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1699879866628100001 Content-Type: text/plain; charset="utf-8" For better compatibility with old linux kernels, see source code comment. Also rename some variables to make the code more readable, following suggestions by Kevin. Related (same problem in ovmf): https://github.com/tianocore/edk2/commit/c1e853769046 Cc: Kevin O'Connor Reported-by: Claudio Fontana Signed-off-by: Gerd Hoffmann --- src/fw/pciinit.c | 38 ++++++++++++++++++++++++++------------ 1 file changed, 26 insertions(+), 12 deletions(-) diff --git a/src/fw/pciinit.c b/src/fw/pciinit.c index c7084f5e397e..6b13cd5b7d1c 100644 --- a/src/fw/pciinit.c +++ b/src/fw/pciinit.c @@ -46,12 +46,16 @@ static const char *region_type_name[] =3D { [ PCI_REGION_TYPE_PREFMEM ] =3D "prefmem", }; =20 +// Memory ranges exported to legacy ACPI type table generation u64 pcimem_start =3D BUILD_PCIMEM_START; u64 pcimem_end =3D BUILD_PCIMEM_END; u64 pcimem64_start =3D BUILD_PCIMEM64_START; u64 pcimem64_end =3D BUILD_PCIMEM64_END; -u64 pci_io_low_end =3D 0xa000; -u32 pci_use_64bit =3D 0; + +// Resource allocation limits +static u64 pci_io_low_end =3D 0xa000; +static u64 pci_mem64_top =3D 0; +static u32 pci_pad_mem64 =3D 0; =20 struct pci_region_entry { struct pci_device *dev; @@ -966,8 +970,9 @@ static int pci_bios_check_devices(struct pci_bus *busse= s) int resource_optional =3D 0; if (hotplug_support =3D=3D HOTPLUG_PCIE) resource_optional =3D pcie_cap && (type =3D=3D PCI_REGION_= TYPE_IO); - if (hotplug_support && pci_use_64bit && is64 && (type =3D=3D P= CI_REGION_TYPE_PREFMEM)) - align =3D (u64)1 << (CPUPhysBits - 11); + if (hotplug_support && pci_pad_mem64 && is64 + && (type =3D=3D PCI_REGION_TYPE_PREFMEM)) + align =3D pci_mem64_top >> 11; if (align > sum && hotplug_support && !resource_optional) sum =3D align; /* reserve min size for hot-plug */ if (size > sum) { @@ -1111,7 +1116,7 @@ static void pci_bios_map_devices(struct pci_bus *buss= es) panic("PCI: out of I/O address space\n"); =20 dprintf(1, "PCI: 32: %016llx - %016llx\n", pcimem_start, pcimem_end); - if (pci_use_64bit || pci_bios_init_root_regions_mem(busses)) { + if (pci_pad_mem64 || pci_bios_init_root_regions_mem(busses)) { struct pci_region r64_mem, r64_pref; r64_mem.list.first =3D NULL; r64_pref.list.first =3D NULL; @@ -1131,14 +1136,13 @@ static void pci_bios_map_devices(struct pci_bus *bu= sses) r64_mem.base =3D le64_to_cpu(romfile_loadint("etc/reserved-memory-= end", 0)); if (r64_mem.base < 0x100000000LL + RamSizeOver4G) r64_mem.base =3D 0x100000000LL + RamSizeOver4G; - if (CPUPhysBits) { - u64 top =3D 1LL << CPUPhysBits; + if (pci_mem64_top) { u64 size =3D (ALIGN(sum_mem, (1LL<<30)) + ALIGN(sum_pref, (1LL<<30))); - if (pci_use_64bit) - size =3D ALIGN(size, (1LL<<(CPUPhysBits-3))); - if (r64_mem.base < top - size) { - r64_mem.base =3D top - size; + if (pci_pad_mem64) + size =3D ALIGN(size, pci_mem64_top >> 3); + if (r64_mem.base < pci_mem64_top - size) { + r64_mem.base =3D pci_mem64_top - size; } if (e820_is_used(r64_mem.base, size)) r64_mem.base -=3D size; @@ -1181,8 +1185,18 @@ pci_setup(void) =20 dprintf(3, "pci setup\n"); =20 + if (CPUPhysBits) { + pci_mem64_top =3D 1LL << CPUPhysBits; + if (CPUPhysBits > 46) { + // Old linux kernels have trouble dealing with more than 46 + // phys-bits, so avoid that for now. Seems to be a bug in the + // virtio-pci driver. Reported: centos-7, ubuntu-18.04 + pci_mem64_top =3D 1LL << 46; + } + } + if (CPUPhysBits >=3D 36 && CPULongMode && RamSizeOver4G) - pci_use_64bit =3D 1; + pci_pad_mem64 =3D 1; =20 dprintf(1, "=3D=3D=3D PCI bus & bridge init =3D=3D=3D\n"); if (pci_probe_host() !=3D 0) { --=20 2.41.0 _______________________________________________ SeaBIOS mailing list -- seabios@seabios.org To unsubscribe send an email to seabios-leave@seabios.org