From nobody Tue May 14 06:00:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of seabios.org designates 78.46.105.101 as permitted sender) client-ip=78.46.105.101; envelope-from=seabios-bounces@seabios.org; helo=coreboot.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of seabios.org designates 78.46.105.101 as permitted sender) smtp.mailfrom=seabios-bounces@seabios.org; dmarc=fail(p=none dis=none) header.from=ilande.co.uk Return-Path: Received: from coreboot.org (coreboot.org [78.46.105.101]) by mx.zohomail.com with SMTPS id 1690635928732358.7557998517601; Sat, 29 Jul 2023 06:05:28 -0700 (PDT) Received: from authenticated-user (PRIMARY_HOSTNAME [PUBLIC_IP]) by coreboot.org (Postfix) with ESMTPA id 3C39132556; Sat, 29 Jul 2023 13:05:24 +0000 (UTC) Received: from authenticated-user (PRIMARY_HOSTNAME [PUBLIC_IP]) by coreboot.org (Postfix) with ESMTP id 7ADDD32533 for ; Sat, 29 Jul 2023 13:04:56 +0000 (UTC) Received: from authenticated-user (PRIMARY_HOSTNAME [PUBLIC_IP]) by mail.ilande.co.uk with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1qPjcW-0002XJ-Mu for seabios@seabios.org; Sat, 29 Jul 2023 14:04:36 +0100 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=ilande.co.uk; s=20220518; h=Subject:Content-Transfer-Encoding:MIME-Version: References:In-Reply-To:Message-Id:Date:To:From:Sender:Reply-To:Cc: Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help: List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=80FZz+4BTQR88Su7z9OsWKHRwO70oFv9ldkMeik+Y/0=; b=qnFsf8J9tQ+xVN0AyjO4jumeet s2Cy/b0NTEU2XWVuQimVRsJUq3EqcmEB3cLWga6+TacQAsT1QTUrlDzRTAZ/8zRQLl6C3SIAomLN0 oQrmdFOPcg7tT9ERmG6aR2XzsdBGfUTj9EJJnAkHbig3F9Uc3K9+xYkxiv/v+/5VTlO2LIzQPskzT yhh3pAKIB+xvEGuZe6aDSCvWbfUGTHE0IDFB193487VHN+iJMRXJQ7WIcYJRp3yvGX3x6TdB4MHgr jf6SzXGZn7KMjkptJowZGrX1WPeDcSAQBjIKo9SweRPBqGA2zlcFODeL5iWnHM4Thm/ibrECKgZcW P0oo96fRfVm70MkSp5mZhh+EuGy+TkZgr0/vGvWZZ3qplRBIPAYxrH/K2pJv/h7HO0MLLZZaKUYsQ w8q0h3o3489ztRsu7xgO4/Ue5Azhr20XwCKktio4EFRwJq+9mzLe22FMwmJ9bw8qrR7jZ1q8A+mqu zro2p5n09WVBV4ZlxyNhAA+ao2L2Np9vF1CJg60+aalBljDvPWuxEjbHRG0lDHfKtsk1Wrx8qR1gF bXIjBwiCP6TWMhEoF+84h6eveNvpm4i+q+jvCDueA7RWaO8JF02jg1w84QSMMmF3dqNZOKYaBSLZx PtOdV8PhADx0ENWqtFCrBQ5Zc+TY8kGHJb1Rmar0U=; From: Mark Cave-Ayland To: seabios@seabios.org Date: Sat, 29 Jul 2023 14:04:40 +0100 Message-Id: <20230729130441.109516-2-mark.cave-ayland@ilande.co.uk> In-Reply-To: <20230729130441.109516-1-mark.cave-ayland@ilande.co.uk> References: <20230729130441.109516-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2a00:23c4:8bae:1c00:dfd7:380:3565:1db7 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on mail.default.ilande.bv.iomart.io X-Spam-Status: No, score=-2.8 required=5.0 tests=ALL_TRUSTED,BAYES_00, URIBL_BLOCKED,URIBL_SBL_A autolearn=no autolearn_force=no version=3.4.2 X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.ilande.co.uk) X-Spam-Level: *** Message-ID-Hash: QKY53KDXCFGQHVPMUATXKDW67SCW3UXU X-Message-ID-Hash: QKY53KDXCFGQHVPMUATXKDW67SCW3UXU X-MailFrom: mark.cave-ayland@ilande.co.uk X-Mailman-Rule-Misses: dmarc-mitigation; no-senders; approved; emergency; loop; banned-address; member-moderation; header-match-seabios.seabios.org-0; header-match-seabios.seabios.org-1; nonmember-moderation; administrivia; implicit-dest; max-recipients; max-size; news-moderation; no-subject; digests; suspicious-header X-Mailman-Version: 3.3.6b1 Precedence: list Subject: [SeaBIOS] [PATCH 1/2] esp-scsi: flush FIFO before sending SCSI command List-Id: SeaBIOS mailing list Archived-At: List-Archive: List-Help: List-Owner: List-Post: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable Authentication-Results: coreboot.org; auth=pass smtp.auth=mailman@coreboot.org smtp.mailfrom=seabios-bounces@seabios.org X-Spamd-Bar: --- X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1690635931001100001 Content-Type: text/plain; charset="utf-8" The ESP FIFO is used as a buffer for DMA requests and so isn't guaranteed to be empty in the case of SCSI errors or a mixed DMA/non-DMA request. Flush t= he FIFO before sending a SCSI command to guarantee that it is correctly positioned at the start of the FIFO. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- src/hw/esp-scsi.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/hw/esp-scsi.c b/src/hw/esp-scsi.c index cc25f22..e4815aa 100644 --- a/src/hw/esp-scsi.c +++ b/src/hw/esp-scsi.c @@ -46,6 +46,7 @@ #define ESP_DMA_WMAC 0x58c =20 #define ESP_CMD_DMA 0x80 +#define ESP_CMD_FLUSH 0x01 #define ESP_CMD_RESET 0x02 #define ESP_CMD_TI 0x10 #define ESP_CMD_ICCS 0x11 @@ -96,6 +97,9 @@ esp_scsi_process_op(struct disk_op_s *op) =20 outb(target, iobase + ESP_WBUSID); =20 + /* Clear FIFO before sending command. */ + outb(ESP_CMD_FLUSH, iobase + ESP_CMD); + /* * We need to pass the LUN at the beginning of the command, and the FI= FO * is only 16 bytes, so we cannot support 16-byte CDBs. The alternati= ve --=20 2.30.2 _______________________________________________ SeaBIOS mailing list -- seabios@seabios.org To unsubscribe send an email to seabios-leave@seabios.org From nobody Tue May 14 06:00:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of seabios.org designates 78.46.105.101 as permitted sender) client-ip=78.46.105.101; envelope-from=seabios-bounces@seabios.org; helo=coreboot.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of seabios.org designates 78.46.105.101 as permitted sender) smtp.mailfrom=seabios-bounces@seabios.org; dmarc=fail(p=none dis=none) header.from=ilande.co.uk Return-Path: Received: from coreboot.org (coreboot.org [78.46.105.101]) by mx.zohomail.com with SMTPS id 169063594214832.47829893685355; Sat, 29 Jul 2023 06:05:42 -0700 (PDT) Received: from authenticated-user (PRIMARY_HOSTNAME [PUBLIC_IP]) by coreboot.org (Postfix) with ESMTPA id 2A63122D45; Sat, 29 Jul 2023 13:05:38 +0000 (UTC) Received: from authenticated-user (PRIMARY_HOSTNAME [PUBLIC_IP]) by coreboot.org (Postfix) with ESMTP id A0FCC32533 for ; Sat, 29 Jul 2023 13:05:00 +0000 (UTC) Received: from authenticated-user (PRIMARY_HOSTNAME [PUBLIC_IP]) by mail.ilande.co.uk with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1qPjca-0002XJ-TA for seabios@seabios.org; Sat, 29 Jul 2023 14:04:41 +0100 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=ilande.co.uk; s=20220518; h=Subject:Content-Transfer-Encoding:MIME-Version: References:In-Reply-To:Message-Id:Date:To:From:Sender:Reply-To:Cc: Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help: List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=pW+zwAZZRMFtr7perWdS8FrJiXXixK6zxiEo7QoPdtI=; b=ow0fPSt30Zd+hif9P21s7U5U4A 2oQ7aWY7Z/TNAqGgi+00LCFufcDqAUkKicji2ePTM8i/vbvHGeUtvtGNQKY88TnxUNXoZ7a1pCsn4 Gbg+FA40IEqbXtHDZoiz5NF7uKOsQyIYuiRdbsQ4D/9IGtr+Fl8ztP9jdLhhXCWHjkMnAEs7lvN8M xnRrijVe379oefqbDRVxOkONJaKmNDY/AyYos872u7vusihXT767Rw80lXVCxLE/VuHccddX5msCd 7NHcrZReQ7kWmSN6DW+k44fuXO0LtXZB3UyHsH9Gydsa7+Gbcd8CAfJ0554q2WxsauL2wbvDvve5H nGInsV6EQiAVqb+IYPbsp5Z9K7YtXNSACZE+hVlBXsb4ip8SQrtLmec5jhlse3pq/B3yXTcRIkYdy NjhqjP91IjrEErkr42VmSgU3FMIrEpnUJGLu/IsDfeErWR66CvwUBcP+e2wHFMG/FiV3vMXi9dX27 HqiPTL5WGP2aV10TjggQumj1qqJu3mqPhHTfa/14jAUvhBYrDm8GODY/nPChVAcGW8z5FZmRaXg71 isN1XtcDtZUVVPyNNli1rlQlKGWegp3E6+4M8u7VRUdNW6oD4UmMMG4edBiX+V6LqhINBUlq6aMbj LdmqrEqzWEeZ6F1pdB0n1EenmYcunDDm7ug3qFJYk=; From: Mark Cave-Ayland To: seabios@seabios.org Date: Sat, 29 Jul 2023 14:04:41 +0100 Message-Id: <20230729130441.109516-3-mark.cave-ayland@ilande.co.uk> In-Reply-To: <20230729130441.109516-1-mark.cave-ayland@ilande.co.uk> References: <20230729130441.109516-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2a00:23c4:8bae:1c00:dfd7:380:3565:1db7 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on mail.default.ilande.bv.iomart.io X-Spam-Status: No, score=-2.8 required=5.0 tests=ALL_TRUSTED,BAYES_00, URIBL_BLOCKED,URIBL_SBL_A autolearn=no autolearn_force=no version=3.4.2 X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.ilande.co.uk) X-Spam-Level: *** Message-ID-Hash: G6BSL4MJXJ2ZQEABU5HKBMU2ZA4YLV3M X-Message-ID-Hash: G6BSL4MJXJ2ZQEABU5HKBMU2ZA4YLV3M X-MailFrom: mark.cave-ayland@ilande.co.uk X-Mailman-Rule-Misses: dmarc-mitigation; no-senders; approved; emergency; loop; banned-address; member-moderation; header-match-seabios.seabios.org-0; header-match-seabios.seabios.org-1; nonmember-moderation; administrivia; implicit-dest; max-recipients; max-size; news-moderation; no-subject; digests; suspicious-header X-Mailman-Version: 3.3.6b1 Precedence: list Subject: [SeaBIOS] [PATCH 2/2] esp-scsi: check for INTR_BS/INTR_FC instead of STAT_TC for command completion List-Id: SeaBIOS mailing list Archived-At: List-Archive: List-Help: List-Owner: List-Post: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable Authentication-Results: coreboot.org; auth=pass smtp.auth=mailman@coreboot.org smtp.mailfrom=seabios-bounces@seabios.org X-Spamd-Bar: --- X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1690635944279100001 Content-Type: text/plain; charset="utf-8" The ESP SELATN command used to send SCSI commands from the ESP to thes SCSI= bus is not a DMA command and therefore does not affect the STAT_TC bit. The only reason this works at all is due to a bug in QEMU which (currently) always updates the STAT_TC bit in ESP_RSTAT regardless of the state of the ESP_CMD= _DMA bit. According to the NCR datasheet the INTR_BS/INTR_FC bits are set when the SE= LATN command has completed, so update the existing logic to check for these bits= in ESP_RINTR instead. Note that the read of ESP_RINTR needs to be restricted to state =3D=3D 0 as reading ESP_RINTR resets the ESP_RSTAT register which bre= aks the STAT_TC check when state =3D=3D 1. This commit also includes an extra read of ESP_INTR to clear all the interr= upt bits before submitting the SELATN command to ensure that we don't accidenta= lly immediately progress to the data phase handling logic where ESP_RINTR bits = have already been set by a previous ESP command. Signed-off-by: Mark Cave-Ayland Reviewed-by: Paul Menzel --- src/hw/esp-scsi.c | 36 ++++++++++++++++++++++-------------- 1 file changed, 22 insertions(+), 14 deletions(-) diff --git a/src/hw/esp-scsi.c b/src/hw/esp-scsi.c index e4815aa..2d2d915 100644 --- a/src/hw/esp-scsi.c +++ b/src/hw/esp-scsi.c @@ -57,6 +57,8 @@ #define ESP_STAT_MSG 0x04 #define ESP_STAT_TC 0x10 =20 +#define ESP_INTR_FC 0x08 +#define ESP_INTR_BS 0x10 #define ESP_INTR_DC 0x20 =20 struct esp_lun_s { @@ -97,8 +99,9 @@ esp_scsi_process_op(struct disk_op_s *op) =20 outb(target, iobase + ESP_WBUSID); =20 - /* Clear FIFO before sending command. */ + /* Clear FIFO and interrupts before sending command. */ outb(ESP_CMD_FLUSH, iobase + ESP_CMD); + inb(iobase + ESP_RINTR); =20 /* * We need to pass the LUN at the beginning of the command, and the FI= FO @@ -115,22 +118,27 @@ esp_scsi_process_op(struct disk_op_s *op) =20 for (state =3D 0;;) { u8 stat =3D inb(iobase + ESP_RSTAT); + u8 intr; =20 - /* Detect disconnected device. */ - if (state =3D=3D 0 && (inb(iobase + ESP_RINTR) & ESP_INTR_DC)) { - return DISK_RET_ENOTREADY; - } + if (state =3D=3D 0) { + intr =3D inb(iobase + ESP_RINTR); =20 - /* HBA reads command, clears CD, sets TC -> do DMA if needed. */ - if (state =3D=3D 0 && (stat & ESP_STAT_TC)) { - state++; - if (op->count && blocksize) { - /* Data phase. */ - u32 count =3D (u32)op->count * blocksize; - esp_scsi_dma(iobase, (u32)op->buf_fl, count, scsi_is_read(= op)); - outb(ESP_CMD_TI | ESP_CMD_DMA, iobase + ESP_CMD); - continue; + /* Detect disconnected device. */ + if (intr & ESP_INTR_DC) { + return DISK_RET_ENOTREADY; } + + /* HBA reads command, executes it, sets BS/FC -> do DMA if nee= ded. */ + if (intr & (ESP_INTR_BS | ESP_INTR_FC)) { + state++; + if (op->count && blocksize) { + /* Data phase. */ + u32 count =3D (u32)op->count * blocksize; + esp_scsi_dma(iobase, (u32)op->buf_fl, count, scsi_is_r= ead(op)); + outb(ESP_CMD_TI | ESP_CMD_DMA, iobase + ESP_CMD); + continue; + } + } } =20 /* At end of DMA TC is set again -> complete command. */ --=20 2.30.2 _______________________________________________ SeaBIOS mailing list -- seabios@seabios.org To unsubscribe send an email to seabios-leave@seabios.org