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[95.84.133.8]) by smtp.gmail.com with ESMTPSA id v126sm732360lfa.21.2017.07.28.16.37.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 28 Jul 2017 16:37:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=j21YQc98FbWq62rIoNGvcMApcBNsN+myQp4+JRq9P8I=; b=ip1+toFAQhHBseSjn90u6dDYdK40bCCpWd1bgXIBNWRgk//qIDpyVSSdEUjp+8TWG2 Fke2mFeFKRFvgPyDyge/Sygzfm0M0zKN28i58szflmUuCGXNBGM2KIpLdIAlluKKNBwe rLe6IzAL/EpVMyndEj7CxlI6olsHKNt/3lu8G1csahRzQrZ3Bt/GzfEkufJHThbihzEq 9/PE9E1V2OaKDvFdZ+0NEkjAD4cfX9JjsKzdr65OnTrdhgmn0lDbXcHRE11Ax9Vdo1z9 QiTyOPMIxEYkH03iT5F/QUsKg8XAU4RuSuoaAxr9UrfuVjTt+VSE0qnvYWnyifXEZfCG Ey+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=j21YQc98FbWq62rIoNGvcMApcBNsN+myQp4+JRq9P8I=; b=r4OISG8GymWJFIW7ulSqT0qXn7ED7n/XCc5DmN9Aw4O4IF4Xx/vOEX3/xUO8IDu8zE ltHi4MZZubOwMy3QHV/ksIu2b93uwNNvCuyouHrWIW2cpfSTqhKWmEvNE0bz03eDb30p /VctcbWe7v+B7JoO0e6kyId483c5Yrystj1NziyrjOsdXEGqYBOoSt8BNS18RP1scIin UKwJrIn7O/glEKJ7Vda6hnb46oQNGCDYpLSltLCPDcm5YNzkVbaotvqE/6ORvESP30+6 lsPrY5GbbCimUtXbJGX9bV8hst5KPE9+mYN2GDz+Z93fTktlrNC4nQ6rQ6lZh/PWzOfT MlLA== X-Gm-Message-State: AIVw110m3D9W6QheLTmWozt8SqC70GCPu6UXVXbx/ANMnBgJX64IpCq2 bCd46+RhbcNRb9fy2v0= X-Received: by 10.46.71.136 with SMTP id u130mr3383489lja.70.1501285078448; Fri, 28 Jul 2017 16:37:58 -0700 (PDT) From: Aleksandr Bezzubikov To: qemu-devel@nongnu.org Date: Sat, 29 Jul 2017 02:37:49 +0300 Message-Id: <1501285073-2215-2-git-send-email-zuban32s@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501285073-2215-1-git-send-email-zuban32s@gmail.com> References: <1501285073-2215-1-git-send-email-zuban32s@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::244 Subject: [Qemu-devel] [PATCH v3 1/5] hw/i386: allow SHPC for Q35 machine X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ehabkost@redhat.com, mst@redhat.com, seabios@seabios.org, Aleksandr Bezzubikov , kevin@koconnor.net, kraxel@redhat.com, pbonzini@redhat.com, marcel@redhat.com, imammedo@redhat.com, lersek@redhat.com, rth@twiddle.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Unmask previously masked SHPC feature in _OSC method. Signed-off-by: Aleksandr Bezzubikov Reviewed-by: Marcel Apfelbaum --- hw/i386/acpi-build.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 6b7bade..2ab32f9 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -1848,9 +1848,9 @@ static Aml *build_q35_osc_method(void) =20 /* * Always allow native PME, AER (no dependencies) - * Never allow SHPC (no SHPC controller in this system) + * Allow SHPC (PCI bridges can have SHPC controller) */ - aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1D), a_ctrl)); + aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1F), a_ctrl)); =20 if_ctx2 =3D aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1)))); /* Unknown revision */ --=20 2.7.4 From nobody Wed May 1 15:02:41 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) client-ip=80.81.252.135; envelope-from=seabios-bounces@seabios.org; helo=mail.coreboot.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) smtp.mailfrom=seabios-bounces@seabios.org Return-Path: Received: from mail.coreboot.org (mail.coreboot.org [80.81.252.135]) by mx.zohomail.com with SMTPS id 1501285108934757.9717444560275; Fri, 28 Jul 2017 16:38:28 -0700 (PDT) Received: from [127.0.0.1] (helo=ra.coresystems.de) by mail.coreboot.org with esmtp (Exim 4.86_2) (envelope-from ) id 1dbEnd-00073i-4B; Sat, 29 Jul 2017 01:36:05 +0200 Received: from mail-lf0-f66.google.com ([209.85.215.66]) by mail.coreboot.org with esmtps (TLSv1.2:ECDHE-RSA-AES128-GCM-SHA256:128) (Exim 4.86_2) (envelope-from ) id 1dbEnP-0006y8-Ls for seabios@seabios.org; Sat, 29 Jul 2017 01:36:02 +0200 Received: by mail-lf0-f66.google.com with SMTP id x16so10948839lfb.4 for ; Fri, 28 Jul 2017 16:38:01 -0700 (PDT) Received: from localhost.localdomain (broadband-95-84-133-8.moscow.rt.ru. [95.84.133.8]) by smtp.gmail.com with ESMTPSA id v126sm732360lfa.21.2017.07.28.16.37.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 28 Jul 2017 16:37:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=8iWWSJZnoTjd9iMC6srOJtFO88A8XmSzYbMCO8o/baY=; b=fJ2L7wNfkR+65EBwUF1UuKvzsn8tTAux8iIPcV8kECqLjZ+6VG/yY9hWna9LFVGF3r hxYCyRuOLMAhY/agkQAxcqm2V2DUTzCbc/2rPEH7FROck6LU/LCJhA5aOeHOXcsYLvbr beVD5b8xxLmvLw2PSNjywpjMb2RBNPvxeTzlex1EFZpHkNF16YzblECtg6VvLciVingP tf7LQ6qHNb9lw2cGv7chVBbMJv0i4trtHdUoHEelMIXxXXdzV1ykvCjtLYMOo2//a37T xNTHrlDBeH7Yg6ARtEDG6z0OD2GehDDeZzTrJllutXg1AwVnZwLKoOcqjch9cNfJwkgZ C9tw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=8iWWSJZnoTjd9iMC6srOJtFO88A8XmSzYbMCO8o/baY=; b=W1E4v6MVzGv1nEoGgSkXhqoo901GgqnTeP1NdlZN7LSP0XtpR2J+WJUk44O19kqRkq dN4h79wqeiLLq9fjnuWyjQe6wFsKQ3+2CTMGi1WBozbpf5YiF69RTkRCpFiFY8KSQShL u9XF6uVnN0tXGXuMJI1pQ19EJAmO8OwXe2w7jxTo3Z9zKO/VL8LTzdxS/J8dV4cjLxyC 8MJf7JhRti2Ku17Vondqs0//5mNO6Ee6CQZ2lIPh4/CDgGyb4CmGGA27V8A3iHZJ8DGr jtBrO6pcwSQw68PN0EHzsjih1iYDbr/CYeE7IKhpycTYKMD8c+PsbvsJkOgr5eeNpVUd GI4Q== X-Gm-Message-State: AIVw112z7fs0XV+Rdb6VmdEaRzDLbNrTiA2DMdxBPBG9QcjI2xmiDgEc ip3rT9Qa5ObuYQ== X-Received: by 10.46.87.74 with SMTP id r10mr3660113ljd.42.1501285079943; Fri, 28 Jul 2017 16:37:59 -0700 (PDT) From: Aleksandr Bezzubikov To: qemu-devel@nongnu.org Date: Sat, 29 Jul 2017 02:37:50 +0300 Message-Id: <1501285073-2215-3-git-send-email-zuban32s@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501285073-2215-1-git-send-email-zuban32s@gmail.com> References: <1501285073-2215-1-git-send-email-zuban32s@gmail.com> X-Spam-Score: -3.5 (---) Subject: [SeaBIOS] [PATCH v3 2/5] hw/pci: introduce pcie-pci-bridge device X-BeenThere: seabios@seabios.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: SeaBIOS mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mst@redhat.com, seabios@seabios.org, kraxel@redhat.com, pbonzini@redhat.com, marcel@redhat.com, lersek@redhat.com, rth@twiddle.net MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: seabios-bounces@seabios.org Sender: "SeaBIOS" X-Duff: Orig. Duff, Duff Lite, Duff Dry, Duff Dark, Raspberry Duff, Lady Duff, Red Duff, Tartar Control Duff X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Introduce a new PCIExpress-to-PCI Bridge device, which is a hot-pluggable PCI Express device and supports devices hot-plug with SHPC. This device is intended to replace the DMI-to-PCI Bridge in an overwhelming majority of use-cases. Signed-off-by: Aleksandr Bezzubikov --- hw/pci-bridge/Makefile.objs | 2 +- hw/pci-bridge/pcie_pci_bridge.c | 220 ++++++++++++++++++++++++++++++++++++= ++++ include/hw/pci/pci.h | 1 + 3 files changed, 222 insertions(+), 1 deletion(-) create mode 100644 hw/pci-bridge/pcie_pci_bridge.c diff --git a/hw/pci-bridge/Makefile.objs b/hw/pci-bridge/Makefile.objs index c4683cf..666db37 100644 --- a/hw/pci-bridge/Makefile.objs +++ b/hw/pci-bridge/Makefile.objs @@ -1,4 +1,4 @@ -common-obj-y +=3D pci_bridge_dev.o +common-obj-y +=3D pci_bridge_dev.o pcie_pci_bridge.o common-obj-$(CONFIG_PCIE_PORT) +=3D pcie_root_port.o gen_pcie_root_port.o common-obj-$(CONFIG_PXB) +=3D pci_expander_bridge.o common-obj-$(CONFIG_XIO3130) +=3D xio3130_upstream.o xio3130_downstream.o diff --git a/hw/pci-bridge/pcie_pci_bridge.c b/hw/pci-bridge/pcie_pci_bridg= e.c new file mode 100644 index 0000000..c28f820 --- /dev/null +++ b/hw/pci-bridge/pcie_pci_bridge.c @@ -0,0 +1,220 @@ +/* + * QEMU Generic PCIE-PCI Bridge + * + * Copyright (c) 2017 Aleksandr Bezzubikov + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/pci/pci.h" +#include "hw/pci/pci_bus.h" +#include "hw/pci/pci_bridge.h" +#include "hw/pci/msi.h" +#include "hw/pci/shpc.h" +#include "hw/pci/slotid_cap.h" + +typedef struct PCIEPCIBridge { + /*< private >*/ + PCIBridge parent_obj; + + bool msi_enable; + MemoryRegion bar; + /*< public >*/ +} PCIEPCIBridge; + +#define TYPE_PCIE_PCI_BRIDGE_DEV "pcie-pci-bridge" +#define PCIE_PCI_BRIDGE_DEV(obj) \ + OBJECT_CHECK(PCIEPCIBridge, (obj), TYPE_PCIE_PCI_BRIDGE_DEV) + +static void pciepci_bridge_realize(PCIDevice *d, Error **errp) +{ + PCIBridge *br =3D PCI_BRIDGE(d); + PCIEPCIBridge *pcie_br =3D PCIE_PCI_BRIDGE_DEV(d); + int rc, pos; + Error *local_err =3D NULL; + + pci_bridge_initfn(d, TYPE_PCI_BUS); + + d->config[PCI_INTERRUPT_PIN] =3D 0x1; + memory_region_init(&pcie_br->bar, OBJECT(d), "shpc-bar", + shpc_bar_size(d)); + rc =3D shpc_init(d, &br->sec_bus, &pcie_br->bar, 0, &local_err); + if (rc) { + error_propagate(errp, local_err); + goto error; + } + + rc =3D pcie_cap_init(d, 0, PCI_EXP_TYPE_PCI_BRIDGE, 0, &local_err); + if (rc < 0) { + error_propagate(errp, local_err); + goto cap_error; + } + + pos =3D pci_add_capability(d, PCI_CAP_ID_PM, 0, PCI_PM_SIZEOF, &local_= err); + if (pos < 0) { + error_propagate(errp, local_err); + goto pm_error; + } + d->exp.pm_cap =3D pos; + pci_set_word(d->config + pos + PCI_PM_PMC, 0x3); + + pcie_cap_arifwd_init(d); + pcie_cap_deverr_init(d); + + rc =3D pcie_aer_init(d, PCI_ERR_VER, 0x100, PCI_ERR_SIZEOF, &local_err= ); + if (rc < 0) { + error_propagate(errp, local_err); + goto aer_error; + } + + if (pcie_br->msi_enable) { + rc =3D msi_init(d, 0, 1, true, true, &local_err); + if (rc < 0) { + error_propagate(errp, local_err); + goto msi_error; + } + } + pci_register_bar(d, 0, PCI_BASE_ADDRESS_SPACE_MEMORY | + PCI_BASE_ADDRESS_MEM_TYPE_64, &pcie_br->bar); + return; + +msi_error: + pcie_aer_exit(d); +aer_error: +pm_error: + pcie_cap_exit(d); +cap_error: + shpc_free(d); +error: + pci_bridge_exitfn(d); +} + +static void pciepci_bridge_exit(PCIDevice *d) +{ + PCIEPCIBridge *bridge_dev =3D PCIE_PCI_BRIDGE_DEV(d); + pcie_cap_exit(d); + shpc_cleanup(d, &bridge_dev->bar); + pci_bridge_exitfn(d); +} + +static void pciepci_bridge_reset(DeviceState *qdev) +{ + PCIDevice *d =3D PCI_DEVICE(qdev); + pci_bridge_reset(qdev); + msi_reset(d); + shpc_reset(d); +} + +static void pcie_pci_bridge_write_config(PCIDevice *d, + uint32_t address, uint32_t val, int len) +{ + pci_bridge_write_config(d, address, val, len); + msi_write_config(d, address, val, len); + shpc_cap_write_config(d, address, val, len); +} + +static bool pci_device_shpc_present(void *opaque, int version_id) +{ + PCIDevice *dev =3D opaque; + + return shpc_present(dev); +} + +static Property pcie_pci_bridge_dev_properties[] =3D { + DEFINE_PROP_BOOL("msi_enable", PCIEPCIBridge, msi_enable, true), + DEFINE_PROP_END_OF_LIST(), +}; + +static const VMStateDescription pciepci_bridge_dev_vmstate =3D { + .name =3D TYPE_PCIE_PCI_BRIDGE_DEV, + .fields =3D (VMStateField[]) { + VMSTATE_PCI_DEVICE(parent_obj, PCIBridge), + SHPC_VMSTATE(shpc, PCIDevice, pci_device_shpc_present), + VMSTATE_END_OF_LIST() + } +}; + +static void pcie_pci_bridge_hotplug_cb(HotplugHandler *hotplug_dev, + DeviceState *dev, Error **errp) +{ + PCIDevice *pci_hotplug_dev =3D PCI_DEVICE(hotplug_dev); + + if (!shpc_present(pci_hotplug_dev)) { + error_setg(errp, "standard hotplug controller has been disabled fo= r " + "this %s", TYPE_PCIE_PCI_BRIDGE_DEV); + return; + } + shpc_device_hotplug_cb(hotplug_dev, dev, errp); +} + +static void pcie_pci_bridge_hot_unplug_request_cb(HotplugHandler *hotplug_= dev, + DeviceState *dev, + Error **errp) +{ + PCIDevice *pci_hotplug_dev =3D PCI_DEVICE(hotplug_dev); + + if (!shpc_present(pci_hotplug_dev)) { + error_setg(errp, "standard hotplug controller has been disabled fo= r " + "this %s", TYPE_PCIE_PCI_BRIDGE_DEV); + return; + } + shpc_device_hot_unplug_request_cb(hotplug_dev, dev, errp); +} + +static void pciepci_bridge_class_init(ObjectClass *klass, void *data) +{ + PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); + DeviceClass *dc =3D DEVICE_CLASS(klass); + HotplugHandlerClass *hc =3D HOTPLUG_HANDLER_CLASS(klass); + + k->is_express =3D 1; + k->is_bridge =3D 1; + k->vendor_id =3D PCI_VENDOR_ID_REDHAT; + k->device_id =3D PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE; + k->realize =3D pciepci_bridge_realize; + k->exit =3D pciepci_bridge_exit; + k->config_write =3D pcie_pci_bridge_write_config; + dc->vmsd =3D &pciepci_bridge_dev_vmstate; + dc->props =3D pcie_pci_bridge_dev_properties; + dc->vmsd =3D &pciepci_bridge_dev_vmstate; + dc->reset =3D &pciepci_bridge_reset; + set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); + hc->plug =3D pcie_pci_bridge_hotplug_cb; + hc->unplug_request =3D pcie_pci_bridge_hot_unplug_request_cb; +} + +static const TypeInfo pciepci_bridge_info =3D { + .name =3D TYPE_PCIE_PCI_BRIDGE_DEV, + .parent =3D TYPE_PCI_BRIDGE, + .instance_size =3D sizeof(PCIEPCIBridge), + .class_init =3D pciepci_bridge_class_init, + .interfaces =3D (InterfaceInfo[]) { + { TYPE_HOTPLUG_HANDLER }, + { }, + } +}; + +static void pciepci_register(void) +{ + type_register_static(&pciepci_bridge_info); +} + +type_init(pciepci_register); diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index e598b09..b33a34f 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -98,6 +98,7 @@ #define PCI_DEVICE_ID_REDHAT_PXB_PCIE 0x000b #define PCI_DEVICE_ID_REDHAT_PCIE_RP 0x000c #define PCI_DEVICE_ID_REDHAT_XHCI 0x000d +#define PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE 0x000e #define PCI_DEVICE_ID_REDHAT_QXL 0x0100 =20 #define FMT_PCIBUS PRIx64 --=20 2.7.4 _______________________________________________ SeaBIOS mailing list SeaBIOS@seabios.org https://mail.coreboot.org/mailman/listinfo/seabios From nobody Wed May 1 15:02:41 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) client-ip=80.81.252.135; envelope-from=seabios-bounces@seabios.org; helo=mail.coreboot.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) smtp.mailfrom=seabios-bounces@seabios.org Return-Path: Received: from mail.coreboot.org (mail.coreboot.org [80.81.252.135]) by mx.zohomail.com with SMTPS id 1501285122413367.2565971424573; Fri, 28 Jul 2017 16:38:42 -0700 (PDT) Received: from [127.0.0.1] (helo=ra.coresystems.de) by mail.coreboot.org with esmtp (Exim 4.86_2) (envelope-from ) id 1dbEnm-00075d-3J; Sat, 29 Jul 2017 01:36:14 +0200 Received: from mail-lf0-f65.google.com ([209.85.215.65]) by mail.coreboot.org with esmtps (TLSv1.2:ECDHE-RSA-AES128-GCM-SHA256:128) (Exim 4.86_2) (envelope-from ) id 1dbEnR-0006yP-7U for seabios@seabios.org; Sat, 29 Jul 2017 01:36:05 +0200 Received: by mail-lf0-f65.google.com with SMTP id y15so11401023lfd.5 for ; Fri, 28 Jul 2017 16:38:03 -0700 (PDT) Received: from localhost.localdomain (broadband-95-84-133-8.moscow.rt.ru. [95.84.133.8]) by smtp.gmail.com with ESMTPSA id v126sm732360lfa.21.2017.07.28.16.38.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 28 Jul 2017 16:38:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Bw3NM/OhB/t10s8w4nv7tzL1p8wu17CGVQKoWKt5CC8=; b=MjErMsHUEIJ06CvtgzM17zUaGbf3tRy6qNfxwpGVY8plMTUqjmENApYucIUWygUHnt lelGHVmgEnTfJg4pHRtO5dway5rZvEw1fqlJ6Nr1pQTE9q9qLq2H2FFNwVP0GLtigzoZ XSQ9EuB2Tdiwr0/WmplmBvDv30smwXv9PAmwojfo2bvxtwoHFeVxyssnUqDpIzEllYEF I70eJhHdj0kcLOD4vdK/fOxcDU7gNGrSWiCOMZ0tAfUq0/6pKXQFEt2EXOeBLZXRW7MC J61GiWfgJPOWE8RNNZRr0vZKBZDIuxTAdRZHgUDiEmJBRy0GV9n5x78jRoqg6+mjtMjb vZkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Bw3NM/OhB/t10s8w4nv7tzL1p8wu17CGVQKoWKt5CC8=; b=EtSYY4QuMh6j0bZWUPUEsszHTDyKMWFxQ2/VW++OJOSyIx1hu2/EFMAlOyMgCMwrSh D5b1k0w4w3M2OgiyPap2JfSEB2hHmfqDRk3xnOivRxBmMfLlxDhKHz08DijsrwRAsKgp HuqjkQDt+WXSW6/KSxKLqhQjcc6wxr3qzUJZWD3VpOfpo3ujUiqwlMrKEVrwrscpbbGO suEE49E1pQrNcvMIfGZFVnCNa9BYkBTZ68OHkTJS24GIrCDx3hRTnCI0NBEMvZZP/R/q HqFCsmtmSf9SB0xv0h03CpofTQ1xWyft0IxolUb2m7nggbCzpEzr8Tx3XlIV8RfcPwsv bK7w== X-Gm-Message-State: AIVw110jFT/iJWZ+hGVDYr6TbKy2U2WS1KuxlPCYG68eFoscEEAIpn1h ySrZy32EO867AACQzGQ= X-Received: by 10.46.83.17 with SMTP id h17mr1961116ljb.186.1501285081534; Fri, 28 Jul 2017 16:38:01 -0700 (PDT) From: Aleksandr Bezzubikov To: qemu-devel@nongnu.org Date: Sat, 29 Jul 2017 02:37:51 +0300 Message-Id: <1501285073-2215-4-git-send-email-zuban32s@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501285073-2215-1-git-send-email-zuban32s@gmail.com> References: <1501285073-2215-1-git-send-email-zuban32s@gmail.com> X-Spam-Score: -1.1 (-) Subject: [SeaBIOS] [PATCH v3 3/5] hw/pci: introduce bridge-only vendor-specific capability to provide some hints to firmware X-BeenThere: seabios@seabios.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: SeaBIOS mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mst@redhat.com, seabios@seabios.org, kraxel@redhat.com, pbonzini@redhat.com, marcel@redhat.com, lersek@redhat.com, rth@twiddle.net MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: seabios-bounces@seabios.org Sender: "SeaBIOS" X-Duff: Orig. Duff, Duff Lite, Duff Dry, Duff Dark, Raspberry Duff, Lady Duff, Red Duff, Tartar Control Duff X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" On PCI init PCI bridges may need some extra info about bus number to reserve, IO, memory and prefetchable memory limits. QEMU can provide this with a special vendor-specific PCI capability. Signed-off-by: Aleksandr Bezzubikov --- hw/pci/pci_bridge.c | 37 +++++++++++++++++++++++++++++++++++++ include/hw/pci/pci_bridge.h | 28 ++++++++++++++++++++++++++++ 2 files changed, 65 insertions(+) diff --git a/hw/pci/pci_bridge.c b/hw/pci/pci_bridge.c index 720119b..e9f12d6 100644 --- a/hw/pci/pci_bridge.c +++ b/hw/pci/pci_bridge.c @@ -408,6 +408,43 @@ void pci_bridge_map_irq(PCIBridge *br, const char* bus= _name, br->bus_name =3D bus_name; } =20 + +int pci_bridge_qemu_cap_init(PCIDevice *dev, int cap_offset, + uint8_t bus_reserve, uint32_t io_reserve, + uint16_t non_pref_reserve, uint64_t pref_res= erve, + Error **errp) +{ + size_t cap_len =3D sizeof(PCIBridgeQemuCap); + PCIBridgeQemuCap cap =3D { + .len =3D cap_len, + .type =3D REDHAT_PCI_CAP_QEMU, + .bus_res =3D bus_reserve, + .non_pref_16 =3D non_pref_reserve + }; + + if ((uint8_t)io_reserve =3D=3D io_reserve) { + cap.io_8 =3D io_reserve; + } else { + cap.io_32 =3D io_reserve; + } + if ((uint16_t)pref_reserve =3D=3D pref_reserve) { + cap.pref_32 =3D pref_reserve; + } else { + cap.pref_64 =3D pref_reserve; + } + + int offset =3D pci_add_capability(dev, PCI_CAP_ID_VNDR, + cap_offset, cap_len, errp); + if (offset < 0) { + return offset; + } + + memcpy(dev->config + offset + PCI_CAP_FLAGS, + (char *)&cap + PCI_CAP_FLAGS, + cap_len - PCI_CAP_FLAGS); + return 0; +} + static const TypeInfo pci_bridge_type_info =3D { .name =3D TYPE_PCI_BRIDGE, .parent =3D TYPE_PCI_DEVICE, diff --git a/include/hw/pci/pci_bridge.h b/include/hw/pci/pci_bridge.h index ff7cbaa..e9b7cf4 100644 --- a/include/hw/pci/pci_bridge.h +++ b/include/hw/pci/pci_bridge.h @@ -67,4 +67,32 @@ void pci_bridge_map_irq(PCIBridge *br, const char* bus_n= ame, #define PCI_BRIDGE_CTL_DISCARD_STATUS 0x400 /* Discard timer status */ #define PCI_BRIDGE_CTL_DISCARD_SERR 0x800 /* Discard timer SERR# enable */ =20 +typedef struct PCIBridgeQemuCap { + uint8_t id; /* Standard PCI capability header field */ + uint8_t next; /* Standard PCI capability header field */ + uint8_t len; /* Standard PCI vendor-specific capability header fiel= d */ + uint8_t type; /* Red Hat vendor-specific capability type. + Types are defined with REDHAT_PCI_CAP_ prefix */ + + uint16_t non_pref_16; /* Non-prefetchable memory limit */ + uint8_t bus_res; /* Minimum number of buses to reserve */ + uint8_t io_8; /* IO space limit in case of 8-bit value */ + uint32_t io_32; /* IO space limit in case of 32-bit value + This 2 values are mutually exclusive, + i.e. they can't be >0 both*/ + uint32_t pref_32; /* Prefetchable memory limit + in case of 32-bit value */ + uint64_t pref_64; /* Prefetchable memory limit + in case of 64-bit value + This 2 values are mutually exclusive (just = as + IO limit), i.e. they can't be >0 both */ +} PCIBridgeQemuCap; + +#define REDHAT_PCI_CAP_QEMU 1 + +int pci_bridge_qemu_cap_init(PCIDevice *dev, int cap_offset, + uint8_t bus_reserve, uint32_t io_reserve, + uint16_t mem_reserve, uint64_t pref_reserve, + Error **errp); + #endif /* QEMU_PCI_BRIDGE_H */ --=20 2.7.4 _______________________________________________ SeaBIOS mailing list SeaBIOS@seabios.org https://mail.coreboot.org/mailman/listinfo/seabios From nobody Wed May 1 15:02:41 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) client-ip=80.81.252.135; envelope-from=seabios-bounces@seabios.org; helo=mail.coreboot.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) smtp.mailfrom=seabios-bounces@seabios.org Return-Path: Received: from mail.coreboot.org (mail.coreboot.org [80.81.252.135]) by mx.zohomail.com with SMTPS id 1501285106460830.5971065811267; Fri, 28 Jul 2017 16:38:26 -0700 (PDT) Received: from [127.0.0.1] (helo=ra.coresystems.de) by mail.coreboot.org with esmtp (Exim 4.86_2) (envelope-from ) id 1dbEnc-00073T-CD; Sat, 29 Jul 2017 01:36:04 +0200 Received: from mail-lf0-f68.google.com ([209.85.215.68]) by mail.coreboot.org with esmtps (TLSv1.2:ECDHE-RSA-AES128-GCM-SHA256:128) (Exim 4.86_2) (envelope-from ) id 1dbEnS-0006yS-UK for seabios@seabios.org; Sat, 29 Jul 2017 01:36:02 +0200 Received: by mail-lf0-f68.google.com with SMTP id x16so10948915lfb.4 for ; Fri, 28 Jul 2017 16:38:04 -0700 (PDT) Received: from localhost.localdomain (broadband-95-84-133-8.moscow.rt.ru. [95.84.133.8]) by smtp.gmail.com with ESMTPSA id v126sm732360lfa.21.2017.07.28.16.38.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 28 Jul 2017 16:38:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=FsDtWyqa/xakCn61nt8oC6F7aIZuYYb4JbsTAXKAQdI=; b=AbWHBpxiuCciS3dQVAuYujQjs/iCj7ffaiosPs/X2nIp2VY3vQSjSmFJMnXTNzvske OK5y4NTmel615O8vm8do95lLAsKlc8ztTjmbwabREA1n6a1G6mo+X80FwD+LCCbP90Ex Xwn8rrUOlojPc3PkRK7IMZufpUrFl4Z3oJ+eSpjP0PgxVzZgcoKYQhI3xs8IzDOwLwg/ GEO0LH7WqZsZocnRNAfpo92wkJZC6lGuppK3sDjTgfJJd8Ld18HWEaVw7ThCvuGsWptn 9mmEryVsusJQdmKUYJ/yI+GLhbRkBu6Ss+lvYb5SVS4JfNNFPNn9yPCTZfMOP6NAXJBB 3DPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=FsDtWyqa/xakCn61nt8oC6F7aIZuYYb4JbsTAXKAQdI=; b=MQ0fF0RjeNc7MrFw7jwkOTp55fGI/28+CqHPbawe9anjHarrdl/EYvTOA4NHXhA8Mb /vwVlnHuY/3ETDfoGN7Rd0e6oZtM/9Yjo/pERxkcKzvo/eDATMtmafBkXyFxTkl6VA6D r4T4rz7sDHTBgfkLS6SAvf9xjB2MJg1KYXtw1Y0xKiX5SxlQDq1F4lmhDoy7RtY2ObW7 e/sH/7euEzO4yrE3P4x9P71rRqXeRlrOhMIWNqt3mW6C6ImB9cENCAuqOo7HNa0j2K67 L1hFlIFByxnw3VFnlTCItppQ0qZA8xHiLXMyOmAG1d9Vp3sCi5BV2LSWj1Gbqc82ajd+ mr8Q== X-Gm-Message-State: AIVw111ikrxP+uKIzKDtz2/Ef/c3HsQCZYb5Mw44RUhiHYN5cKN7+KbB UMVT2mqfg4YLEA== X-Received: by 10.46.84.81 with SMTP id y17mr607674ljd.133.1501285083245; Fri, 28 Jul 2017 16:38:03 -0700 (PDT) From: Aleksandr Bezzubikov To: qemu-devel@nongnu.org Date: Sat, 29 Jul 2017 02:37:52 +0300 Message-Id: <1501285073-2215-5-git-send-email-zuban32s@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501285073-2215-1-git-send-email-zuban32s@gmail.com> References: <1501285073-2215-1-git-send-email-zuban32s@gmail.com> X-Spam-Score: 2.4 (++) Subject: [SeaBIOS] [PATCH v3 4/5] hw/pci: add QEMU-specific PCI capability to Generic PCI Express Root Port X-BeenThere: seabios@seabios.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: SeaBIOS mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mst@redhat.com, seabios@seabios.org, kraxel@redhat.com, Aleksandr Bezzubikov , pbonzini@redhat.com, marcel@redhat.com, lersek@redhat.com, rth@twiddle.net MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: seabios-bounces@seabios.org Sender: "SeaBIOS" X-Duff: Orig. Duff, Duff Lite, Duff Dry, Duff Dark, Raspberry Duff, Lady Duff, Red Duff, Tartar Control Duff X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Aleksandr Bezzubikov To enable hotplugging of a newly created pcie-pci-bridge, we need to tell firmware (SeaBIOS in this case) to reserve additional buses for pcie-root-port, that allows us to hotplug pcie-pci-bridge into this root port. The number of buses to reserve is provided to the device via a corresponding property, and to the firmware via new PCI capability. The property's default value is 0 to keep default behavior unchanged. Signed-off-by: Aleksandr Bezzubikov --- hw/pci-bridge/gen_pcie_root_port.c | 23 +++++++++++++++++++++++ hw/pci-bridge/pcie_root_port.c | 2 +- include/hw/pci/pcie_port.h | 2 ++ 3 files changed, 26 insertions(+), 1 deletion(-) diff --git a/hw/pci-bridge/gen_pcie_root_port.c b/hw/pci-bridge/gen_pcie_ro= ot_port.c index cb694d6..da3caa1 100644 --- a/hw/pci-bridge/gen_pcie_root_port.c +++ b/hw/pci-bridge/gen_pcie_root_port.c @@ -16,6 +16,8 @@ #include "hw/pci/pcie_port.h" =20 #define TYPE_GEN_PCIE_ROOT_PORT "pcie-root-port" +#define GEN_PCIE_ROOT_PORT(obj) \ + OBJECT_CHECK(GenPCIERootPort, (obj), TYPE_GEN_PCIE_ROOT_PORT) =20 #define GEN_PCIE_ROOT_PORT_AER_OFFSET 0x100 #define GEN_PCIE_ROOT_PORT_MSIX_NR_VECTOR 1 @@ -26,6 +28,9 @@ typedef struct GenPCIERootPort { /*< public >*/ =20 bool migrate_msix; + + /* additional buses to reserve on firmware init */ + uint8_t bus_reserve; } GenPCIERootPort; =20 static uint8_t gen_rp_aer_vector(const PCIDevice *d) @@ -60,6 +65,21 @@ static bool gen_rp_test_migrate_msix(void *opaque, int v= ersion_id) return rp->migrate_msix; } =20 +static void gen_rp_realize(PCIDevice *d, Error **errp) +{ + rp_realize(d, errp); + PCIESlot *s =3D PCIE_SLOT(d); + GenPCIERootPort *grp =3D GEN_PCIE_ROOT_PORT(d); + + int rc =3D pci_bridge_qemu_cap_init(d, 0, grp->bus_reserve, 0, 0, 0, e= rrp); + if (rc < 0) { + pcie_chassis_del_slot(s); + pcie_cap_exit(d); + gen_rp_interrupts_uninit(d); + pci_bridge_exitfn(d); + } +} + static const VMStateDescription vmstate_rp_dev =3D { .name =3D "pcie-root-port", .version_id =3D 1, @@ -78,6 +98,7 @@ static const VMStateDescription vmstate_rp_dev =3D { =20 static Property gen_rp_props[] =3D { DEFINE_PROP_BOOL("x-migrate-msix", GenPCIERootPort, migrate_msix, true= ), + DEFINE_PROP_UINT8("bus-reserve", GenPCIERootPort, bus_reserve, 0), DEFINE_PROP_END_OF_LIST() }; =20 @@ -89,6 +110,8 @@ static void gen_rp_dev_class_init(ObjectClass *klass, vo= id *data) =20 k->vendor_id =3D PCI_VENDOR_ID_REDHAT; k->device_id =3D PCI_DEVICE_ID_REDHAT_PCIE_RP; + k->realize =3D gen_rp_realize; + dc->desc =3D "PCI Express Root Port"; dc->vmsd =3D &vmstate_rp_dev; dc->props =3D gen_rp_props; diff --git a/hw/pci-bridge/pcie_root_port.c b/hw/pci-bridge/pcie_root_port.c index 4d588cb..2f3bcb1 100644 --- a/hw/pci-bridge/pcie_root_port.c +++ b/hw/pci-bridge/pcie_root_port.c @@ -52,7 +52,7 @@ static void rp_reset(DeviceState *qdev) pci_bridge_disable_base_limit(d); } =20 -static void rp_realize(PCIDevice *d, Error **errp) +void rp_realize(PCIDevice *d, Error **errp) { PCIEPort *p =3D PCIE_PORT(d); PCIESlot *s =3D PCIE_SLOT(d); diff --git a/include/hw/pci/pcie_port.h b/include/hw/pci/pcie_port.h index 1333266..febd96a 100644 --- a/include/hw/pci/pcie_port.h +++ b/include/hw/pci/pcie_port.h @@ -63,6 +63,8 @@ void pcie_chassis_del_slot(PCIESlot *s); #define PCIE_ROOT_PORT_GET_CLASS(obj) \ OBJECT_GET_CLASS(PCIERootPortClass, (obj), TYPE_PCIE_ROOT_PORT) =20 +void rp_realize(PCIDevice *d, Error **errp); + typedef struct PCIERootPortClass { PCIDeviceClass parent_class; =20 --=20 2.7.4 _______________________________________________ SeaBIOS mailing list SeaBIOS@seabios.org https://mail.coreboot.org/mailman/listinfo/seabios From nobody Wed May 1 15:02:41 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) client-ip=80.81.252.135; envelope-from=seabios-bounces@seabios.org; helo=mail.coreboot.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) smtp.mailfrom=seabios-bounces@seabios.org Return-Path: Received: from mail.coreboot.org (mail.coreboot.org [80.81.252.135]) by mx.zohomail.com with SMTPS id 1501285110729107.86312469100199; Fri, 28 Jul 2017 16:38:30 -0700 (PDT) Received: from [127.0.0.1] (helo=ra.coresystems.de) by mail.coreboot.org with esmtp (Exim 4.86_2) (envelope-from ) id 1dbEng-00075B-Ab; Sat, 29 Jul 2017 01:36:08 +0200 Received: from mail-lf0-f67.google.com ([209.85.215.67]) by mail.coreboot.org with esmtps (TLSv1.2:ECDHE-RSA-AES128-GCM-SHA256:128) (Exim 4.86_2) (envelope-from ) id 1dbEnU-0006z4-If for seabios@seabios.org; Sat, 29 Jul 2017 01:36:04 +0200 Received: by mail-lf0-f67.google.com with SMTP id x16so10948933lfb.4 for ; Fri, 28 Jul 2017 16:38:06 -0700 (PDT) Received: from localhost.localdomain (broadband-95-84-133-8.moscow.rt.ru. [95.84.133.8]) by smtp.gmail.com with ESMTPSA id v126sm732360lfa.21.2017.07.28.16.38.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 28 Jul 2017 16:38:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=6ALfQPUCiVBD6k089Bp19056usjd/Kp1yklsbECxo2E=; b=iRxin/9Ve1JZUl4kV7LEP7i1bS+yky9u/nBm92srJph6JWkc4kMIkJ1S+tpZ7hVx6X GUZsL51NaN5JQbUOm9s2bfMOjkZj5uoArlq4H6SvA81cJuCLc2Msa1tRyGQJEv4/m5G8 lLbgqdyY/QDRClbstwwqFE1wm05No1hbJRR+SAt75gvINhJU8aOcbbcUtwSQQtQ/cMOB yEdxnEZ7jaCwZ7Sfj4F1WVoYhhpLTPeZ/PQyceuJKDd+y/GxlgB/A0TCjk94dZxZqI0/ u1pYr4AAKr2vMgUPDkAXIz5nl5I7qNIwnXPz1UwsCgbQU8HJX9B27RcwEusZiAMVXVsx nyGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=6ALfQPUCiVBD6k089Bp19056usjd/Kp1yklsbECxo2E=; b=NKLRTCubZqQ36oDmvDwo+RppxTYcg5GnE/wGv5Wrj3k8KW1SSUOF+XM7c1Px9eWeV2 W15nl0tBRV2ig7uyTVZlQmn7woLAV9MbcSJnnBUb/MwjKpsYpNDVxwL5LqUyQ2obhRMQ PWw2wJarMsEfDLxsdLMCSX+Ux5WEfpeqQXpKrWuqqqVR5g0xYWZy6qU4KFYmil9f+2Fx sHwHzA/sGTfLOyFORP7Cy4Rz4NStpsCxn2OFcdJ/Um6LmZlvnc9fd6WClAvZTdOEdVlf +xsVgbQSP6H2J50O4Q1LZ/NUsgGBDMijT/N2U1DLkPxK/600kdBBv92g4ExoVAib2m8P 4Iig== X-Gm-Message-State: AIVw111tkxT3zb6xdcCjOXn0BWsZnh+iaC8CN02A7iOSefV840LQP7cR FS1aOHd9nRgapw== X-Received: by 10.46.71.198 with SMTP id u189mr3633922lja.110.1501285084723; Fri, 28 Jul 2017 16:38:04 -0700 (PDT) From: Aleksandr Bezzubikov To: qemu-devel@nongnu.org Date: Sat, 29 Jul 2017 02:37:53 +0300 Message-Id: <1501285073-2215-6-git-send-email-zuban32s@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501285073-2215-1-git-send-email-zuban32s@gmail.com> References: <1501285073-2215-1-git-send-email-zuban32s@gmail.com> X-Spam-Score: 0.9 (/) Subject: [SeaBIOS] [PATCH v3 5/5] docs: update documentation considering PCIE-PCI bridge X-BeenThere: seabios@seabios.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: SeaBIOS mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mst@redhat.com, seabios@seabios.org, kraxel@redhat.com, pbonzini@redhat.com, marcel@redhat.com, lersek@redhat.com, rth@twiddle.net MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: seabios-bounces@seabios.org Sender: "SeaBIOS" X-Duff: Orig. Duff, Duff Lite, Duff Dry, Duff Dark, Raspberry Duff, Lady Duff, Red Duff, Tartar Control Duff X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Aleksandr Bezzubikov --- docs/pcie.txt | 46 ++++++++++-------- docs/pcie_pci_bridge.txt | 121 +++++++++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 147 insertions(+), 20 deletions(-) create mode 100644 docs/pcie_pci_bridge.txt diff --git a/docs/pcie.txt b/docs/pcie.txt index 5bada24..338b50e 100644 --- a/docs/pcie.txt +++ b/docs/pcie.txt @@ -46,7 +46,7 @@ Place only the following kinds of devices directly on the= Root Complex: (2) PCI Express Root Ports (ioh3420), for starting exclusively PCI Exp= ress hierarchies. =20 - (3) DMI-PCI Bridges (i82801b11-bridge), for starting legacy PCI + (3) PCIE-PCI Bridge (pcie-pci-bridge), for starting legacy PCI hierarchies. =20 (4) Extra Root Complexes (pxb-pcie), if multiple PCI Express Root Buses @@ -55,18 +55,18 @@ Place only the following kinds of devices directly on t= he Root Complex: pcie.0 bus -----------------------------------------------------------------------= ----- | | | | - ----------- ------------------ ------------------ -------------- - | PCI Dev | | PCIe Root Port | | DMI-PCI Bridge | | pxb-pcie | - ----------- ------------------ ------------------ -------------- + ----------- ------------------ ------------------- -------------- + | PCI Dev | | PCIe Root Port | | PCIE-PCI Bridge | | pxb-pcie | + ----------- ------------------ ------------------- -------------- =20 2.1.1 To plug a device into pcie.0 as a Root Complex Integrated Endpoint u= se: -device [,bus=3Dpcie.0] 2.1.2 To expose a new PCI Express Root Bus use: -device pxb-pcie,id=3Dpcie.1,bus_nr=3Dx[,numa_node=3Dy][,addr=3D= z] - Only PCI Express Root Ports and DMI-PCI bridges can be connected + Only PCI Express Root Ports, PCIE-PCI bridges and DMI-PCI bridges ca= n be connected to the pcie.1 bus: -device ioh3420,id=3Droot_port1[,bus=3Dpcie.1][,chassis=3Dx][,sl= ot=3Dy][,addr=3Dz] \ - -device i82801b11-bridge,id=3Ddmi_pci_bridge1,bus=3Dpcie.1 + -device pcie-pci-bridge,id=3Dpcie_pci_bridge1,bus=3Dpcie.1 =20 =20 2.2 PCI Express only hierarchy @@ -130,21 +130,25 @@ Notes: Legacy PCI devices can be plugged into pcie.0 as Integrated Endpoints, but, as mentioned in section 5, doing so means the legacy PCI device in question will be incapable of hot-unplugging. -Besides that use DMI-PCI Bridges (i82801b11-bridge) in combination +Besides that use PCIE-PCI Bridges (pcie-pci-bridge) in combination with PCI-PCI Bridges (pci-bridge) to start PCI hierarchies. +Instead of the PCIE-PCI Bridge DMI-PCI one can be used, +but it doens't support hot-plug, is not crossplatform and since that +is obsolete and deprecated. Use the PCIE-PCI Bridge if you're not=20 +absolutely sure you need the DMI-PCI Bridge. =20 -Prefer flat hierarchies. For most scenarios a single DMI-PCI Bridge +Prefer flat hierarchies. For most scenarios a single PCIE-PCI Bridge (having 32 slots) and several PCI-PCI Bridges attached to it (each supporting also 32 slots) will support hundreds of legacy devices. -The recommendation is to populate one PCI-PCI Bridge under the DMI-PCI Bri= dge +The recommendation is to populate one PCI-PCI Bridge under the PCIE-PCI Br= idge until is full and then plug a new PCI-PCI Bridge... =20 pcie.0 bus ---------------------------------------------- | | - ----------- ------------------ - | PCI Dev | | DMI-PCI BRIDGE | - ---------- ------------------ + ----------- ------------------- + | PCI Dev | | PCIE-PCI BRIDGE | + ---------- ------------------- | | ------------------ ------------------ | PCI-PCI Bridge | | PCI-PCI Bridge | ... @@ -157,11 +161,11 @@ until is full and then plug a new PCI-PCI Bridge... 2.3.1 To plug a PCI device into pcie.0 as an Integrated Endpoint use: -device [,bus=3Dpcie.0] 2.3.2 Plugging a PCI device into a PCI-PCI Bridge: - -device i82801b11-bridge,id=3Ddmi_pci_bridge1[,bus=3Dpcie.0] = \ - -device pci-bridge,id=3Dpci_bridge1,bus=3Ddmi_pci_bridge1[,chassis_n= r=3Dx][,addr=3Dy] \ + -device pcie-pci-bridge,id=3Dpcie_pci_bridge1[,bus=3Dpcie.0] = \ + -device pci-bridge,id=3Dpci_bridge1,bus=3Dpcie_pci_bridge1[,chassis_= nr=3Dx][,addr=3Dy] \ -device ,bus=3Dpci_bridge1[,addr=3Dx] Note that 'addr' cannot be 0 unless shpc=3Doff parameter is passed to - the PCI Bridge. + the PCI Bridge, and can never be 0 when plugging into the PCIE-PCI B= ridge. =20 3. IO space issues =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D @@ -219,25 +223,27 @@ do not support hot-plug, so any devices plugged into = Root Complexes cannot be hot-plugged/hot-unplugged: (1) PCI Express Integrated Endpoints (2) PCI Express Root Ports - (3) DMI-PCI Bridges + (3) PCIE-PCI Bridges (4) pxb-pcie =20 Be aware that PCI Express Downstream Ports can't be hot-plugged into an existing PCI Express Upstream Port. =20 -PCI devices can be hot-plugged into PCI-PCI Bridges. The PCI hot-plug is A= CPI -based and can work side by side with the PCI Express native hot-plug. +PCI devices can be hot-plugged into PCIE-PCI and PCI-PCI Bridges. +The PCI hot-plug into PCI-PCI bridge is ACPI based, whereas hot-plug into +PCIE-PCI bridges is SHPC-base. They both can work side by side with the PC= I Express native hot-plug. =20 PCI Express devices can be natively hot-plugged/hot-unplugged into/from -PCI Express Root Ports (and PCI Express Downstream Ports). +PCI Express Root Ports (and PCI Express Downstream Ports) and PCIExpress-t= o-PCI Bridges. =20 5.1 Planning for hot-plug: (1) PCI hierarchy Leave enough PCI-PCI Bridge slots empty or add one - or more empty PCI-PCI Bridges to the DMI-PCI Bridge. + or more empty PCI-PCI Bridges to the PCIE-PCI Bridge. =20 For each such PCI-PCI Bridge the Guest Firmware is expected to res= erve 4K IO space and 2M MMIO range to be used for all devices behind it. + Appropriate PCI capability is designed, see pcie_pci_bridge.txt. =20 Because of the hard IO limit of around 10 PCI Bridges (~ 40K space) per system don't use more than 9 PCI-PCI Bridges, leaving 4K for t= he diff --git a/docs/pcie_pci_bridge.txt b/docs/pcie_pci_bridge.txt new file mode 100644 index 0000000..ad392ad --- /dev/null +++ b/docs/pcie_pci_bridge.txt @@ -0,0 +1,121 @@ +Generic PCIExpress-to-PCI Bridge +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D + +Description +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +PCIE-to-PCI bridge is a new method for legacy PCI +hierarchies creation on Q35 machines. + +Previously Intel DMI-to-PCI bridge was used for this purpose. +But due to its strict limitations - no support of hot-plug, +no cross-platform and cross-architecture support - a new generic +PCIE-to-PCI bridge should now be used for any legacy PCI device usage +with PCI Express machine. + +This generic PCIE-PCI bridge is a cross-platform device, +can be hot-plugged into appropriate root port (requires additional actions= ,=20 +see 'PCIE-PCI bridge hot-plug' section), +and supports devices hot-plug into the bridge itself=20 +(with some limitations, see below). + +Hot-plug of legacy PCI devices into the bridge +is provided by bridge's built-in Standard hot-plug Controller. +Though it still has some limitations, see 'Limitations' below. + +PCIE-PCI bridge hot-plug +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +As opposed to Windows, Linux guest requires extra efforts to +enable PCIE-PCI bridge hot-plug. +Motivation - now on init any PCI Express root port which doesn't have +any device plugged in, has no free buses reserved to provide any of them +to a hot-plugged devices in future. + +To solve this problem we reserve additional buses on a firmware level.=20 +Currently only SeaBIOS is supported. +The way of bus number to reserve delivery is special +Red Hat vendor-specific PCI capability, added to the root port +that is planned to have PCIE-PCI bridge hot-plugged in. + +Capability layout (defined in include/hw/pci/pci_bridge.h): + + uint8_t id; Standard PCI capability header field + uint8_t next; Standard PCI capability header field + uint8_t len; Standard PCI vendor-specific capability header field + =20 + uint8_t type; Red Hat vendor-specific capability type + List of currently existing types: + QEMU =3D 1 + =20 + uint16_t non_pref_16; Non-prefetchable memory limit + + uint8_t bus_res; Minimum number of buses to reserve + =20 + uint8_t io_8; IO space limit in case of 8-bit value + uint32_t io_32; IO space limit in case of 32-bit value + This two values are mutually exclusive, + i.e. they can't both be >0. + + uint32_t pref_32; Prefetchable memory limit in case of 32-bit value + uint64_t pref_64; Prefetchable memory limit in case of 64-bit value + This two values are mutually exclusive (just as IO= limit), + i.e. they can't both be >0. + +Memory limits are unused now, in future they are planned +to be used for providing similar hints to the firmware. + +At the moment this capability is used only in +QEMU generic PCIE root port (-device pcie-root-port). +Capability construction function takes bus range value +from root ports' common property 'bus_reserve'. +By default it is set to 0 to leave root port's default +behavior unchanged. + +Usage +=3D=3D=3D=3D=3D +A detailed command line would be: + +[qemu-bin + storage options] +-m 2G +-device ioh3420,bus=3Dpcie.0,id=3Drp1 +-device ioh3420,bus=3Dpcie.0,id=3Drp2 +-device pcie-root-port,bus=3Dpcie.0,id=3Drp3,bus-reserve=3D1 +-device pcie-pci-bridge,id=3Dbr1,bus=3Drp1 +-device pcie-pci-bridge,id=3Dbr2,bus=3Drp2 +-device e1000,bus=3Dbr1,addr=3D8 + +Then in monitor it's OK to do: +device_add pcie-pci-bridge,id=3Dbr3,bus=3Drp3 +device_add e1000,bus=3Dbr2,addr=3D1 +device_add e1000,bus=3Dbr3,addr=3D1 + +Here you have: + (1) Cold-plugged: + - Root ports: 1 QEMU generic root port with the capability mentioned a= bove,=20 + 2 ioh3420 root ports; + - 2 PCIE-PCI bridges plugged into 2 different root ports; + - e1000 plugged into the first bridge. + (2) Hot-plugged: + - PCIE-PCI bridge, plugged into QEMU generic root port; + - 2 e1000 cards, one plugged into the cold-plugged PCIE-PCI bridge,=20 + another plugged into the hot-plugged bridge. + +Limitations +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +The PCIE-PCI bridge can be hot-plugged only into pcie-root-port that +has proper 'bus_reserve' property value to provide secondary bus for the h= ot-plugged bridge. + +Windows 7 and older versions don't support hot-plug devices into the PCIE-= PCI bridge. +To enable device hot-plug into the bridge on Linux there're 3 ways: +1) Build shpchp module with this patch http://www.spinics.net/lists/linux-= pci/msg63052.html +2) Wait until the kernel patch mentioned above get merged into upstream -=20 + it's expected to happen in 4.14. +3) set 'msi_enable' property to false - this forced the bridge to use lega= cy INTx, + which allows the bridge to notify the OS about hot-plug event without = having + BUSMASTER set. + +Implementation +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +The PCIE-PCI bridge is based on PCI-PCI bridge, +but also accumulates PCI Express features=20 +as a PCI Express device (is_express=3D1). + --=20 2.7.4 _______________________________________________ SeaBIOS mailing list SeaBIOS@seabios.org https://mail.coreboot.org/mailman/listinfo/seabios