From nobody Mon Apr 29 07:41:50 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) client-ip=80.81.252.135; envelope-from=seabios-bounces@seabios.org; helo=mail.coreboot.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) smtp.mailfrom=seabios-bounces@seabios.org Return-Path: Received: from mail.coreboot.org (mail.coreboot.org [80.81.252.135]) by mx.zohomail.com with SMTPS id 1501284954509292.5714888054132; Fri, 28 Jul 2017 16:35:54 -0700 (PDT) Received: from [127.0.0.1] (helo=ra.coresystems.de) by mail.coreboot.org with esmtp (Exim 4.86_2) (envelope-from ) id 1dbEkR-0006BC-7S; Sat, 29 Jul 2017 01:32:47 +0200 Received: from mail-lf0-f67.google.com ([209.85.215.67]) by mail.coreboot.org with esmtps (TLSv1.2:ECDHE-RSA-AES128-GCM-SHA256:128) (Exim 4.86_2) (envelope-from ) id 1dbEkI-00069J-EI for seabios@seabios.org; Sat, 29 Jul 2017 01:32:45 +0200 Received: by mail-lf0-f67.google.com with SMTP id w199so8821341lff.2 for ; Fri, 28 Jul 2017 16:34:48 -0700 (PDT) Received: from localhost.localdomain (broadband-95-84-133-8.moscow.rt.ru. [95.84.133.8]) by smtp.gmail.com with ESMTPSA id s133sm2579116lfs.4.2017.07.28.16.34.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 28 Jul 2017 16:34:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ZTN0NL/akWiOhGSpYM9KjBCTrE2Al0/0aDFRfSoxGdU=; b=Ieok8ONoq1IAYcTuGOVDRXd0oaIaAId+MNbzmrvYZQ6WrBeju1oQeTq0azb+CAeOEd BpV/gj3OxogzN/m8PodFbS35w1+5VKy1jnEAK63BXKNvsGCFNVtxRln99TeQ8iMtPdmU KHVAWgPVClsI0DCdoMo3d5f56jLXSAFpnXn1Qijq1KTcwF0PcaUhQ5qz48kw9iGdD7mS ecsdmwzZXTu7/BFwH91INTaFsU2uftO+UdwbskUCq37mfIekNR9LGy+j6htZ1gv37s5q awZwIc8ngVfwMa7R9WMHF0OlLTxvcde+5t1G8mJg4kl65JACGoSRSWe/uRiVNkUtAMSx JZIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ZTN0NL/akWiOhGSpYM9KjBCTrE2Al0/0aDFRfSoxGdU=; b=bxRyRJtY6ZaUt2ou3P1whOg7fsnTa3wb3KBzdKY0h3cuuB5+PUj45/6TO+JsASxrId sMgop1+1oh+U5x9dugayw6HurFPMIpL6HG+qUpJfFlj2KNwA2lAtxonePtz7s72eGYMm LQdGR+Wpfx/1WTZcIwsgiARq//jsFEF14peNzcGUfUc+3vFtOmYTwyiYG0x3ia/0VxT+ L88ZR7zSYb+WzTR+lsGmhKkCzVIi2AgGZ7VoIrWzH9o80wxOFdd+nNKh6kKz2uMvXv43 mRRHUKRQ4l6LzzXnQWSVJR6wjaWozmAS8EjFtT+9o0y38ViqMGojuFP+BhqPeAMCMUZn tnww== X-Gm-Message-State: AIVw111ZQ3NkbgTMzgFKUfW1fX25wCwWuCCO/OsEARmDNQ60aDpGLX7G E0Mnn4Uj+yYde7WJ X-Received: by 10.46.9.202 with SMTP id 193mr3654922ljj.137.1501284886401; Fri, 28 Jul 2017 16:34:46 -0700 (PDT) From: Aleksandr Bezzubikov To: seabios@seabios.org Date: Sat, 29 Jul 2017 02:34:30 +0300 Message-Id: <1501284872-2078-2-git-send-email-zuban32s@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501284872-2078-1-git-send-email-zuban32s@gmail.com> References: <1501284872-2078-1-git-send-email-zuban32s@gmail.com> X-Spam-Score: -2.6 (--) Subject: [SeaBIOS] [PATCH v3 1/3] pci: refactor pci_find_capapibilty to get bdf as the first argument instead of the whole pci_device X-BeenThere: seabios@seabios.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: SeaBIOS mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mst@redhat.com, qemu-devel@nongnu.org, kraxel@redhat.com, marcel@redhat.com, lersek@redhat.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: seabios-bounces@seabios.org Sender: "SeaBIOS" X-Duff: Orig. Duff, Duff Lite, Duff Dry, Duff Dark, Raspberry Duff, Lady Duff, Red Duff, Tartar Control Duff X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Refactor pci_find_capability function to get bdf instead of a whole pci_device* as the only necessary field for this function is still bdf. Reviewed-by: Marcel Apfelbaum Signed-off-by: Aleksandr Bezzubikov --- src/fw/pciinit.c | 4 ++-- src/hw/pci.c | 25 +++++++++++++++++++++++++ src/hw/pci.h | 1 + src/hw/pcidevice.c | 24 ------------------------ src/hw/pcidevice.h | 1 - src/hw/virtio-pci.c | 6 +++--- 6 files changed, 31 insertions(+), 30 deletions(-) diff --git a/src/fw/pciinit.c b/src/fw/pciinit.c index 08221e6..864954f 100644 --- a/src/fw/pciinit.c +++ b/src/fw/pciinit.c @@ -762,7 +762,7 @@ static int pci_bus_hotplug_support(struct pci_bus *bus,= u8 pcie_cap) return downstream_port && slot_implemented; } =20 - shpc_cap =3D pci_find_capability(bus->bus_dev, PCI_CAP_ID_SHPC, 0); + shpc_cap =3D pci_find_capability(bus->bus_dev->bdf, PCI_CAP_ID_SHPC, 0= ); return !!shpc_cap; } =20 @@ -844,7 +844,7 @@ static int pci_bios_check_devices(struct pci_bus *busse= s) */ parent =3D &busses[0]; int type; - u8 pcie_cap =3D pci_find_capability(s->bus_dev, PCI_CAP_ID_EXP, 0); + u8 pcie_cap =3D pci_find_capability(s->bus_dev->bdf, PCI_CAP_ID_EX= P, 0); int hotplug_support =3D pci_bus_hotplug_support(s, pcie_cap); for (type =3D 0; type < PCI_REGION_TYPE_COUNT; type++) { u64 align =3D (type =3D=3D PCI_REGION_TYPE_IO) ? diff --git a/src/hw/pci.c b/src/hw/pci.c index 8e3d617..50d9d2d 100644 --- a/src/hw/pci.c +++ b/src/hw/pci.c @@ -58,6 +58,30 @@ pci_config_maskw(u16 bdf, u32 addr, u16 off, u16 on) pci_config_writew(bdf, addr, val); } =20 +u8 pci_find_capability(u16 bdf, u8 cap_id, u8 cap) +{ + int i; + u16 status =3D pci_config_readw(bdf, PCI_STATUS); + + if (!(status & PCI_STATUS_CAP_LIST)) + return 0; + + if (cap =3D=3D 0) { + /* find first */ + cap =3D pci_config_readb(bdf, PCI_CAPABILITY_LIST); + } else { + /* find next */ + cap =3D pci_config_readb(bdf, cap + PCI_CAP_LIST_NEXT); + } + for (i =3D 0; cap && i <=3D 0xff; i++) { + if (pci_config_readb(bdf, cap + PCI_CAP_LIST_ID) =3D=3D cap_id) + return cap; + cap =3D pci_config_readb(bdf, cap + PCI_CAP_LIST_NEXT); + } + + return 0; +} + // Helper function for foreachbdf() macro - return next device int pci_next(int bdf, int bus) @@ -107,3 +131,4 @@ pci_reboot(void) outb(v|6, PORT_PCI_REBOOT); /* Actually do the reset */ udelay(50); } + diff --git a/src/hw/pci.h b/src/hw/pci.h index ee6e196..2e30e28 100644 --- a/src/hw/pci.h +++ b/src/hw/pci.h @@ -39,6 +39,7 @@ u32 pci_config_readl(u16 bdf, u32 addr); u16 pci_config_readw(u16 bdf, u32 addr); u8 pci_config_readb(u16 bdf, u32 addr); void pci_config_maskw(u16 bdf, u32 addr, u16 off, u16 on); +u8 pci_find_capability(u16 bdf, u8 cap_id, u8 cap); int pci_next(int bdf, int bus); int pci_probe_host(void); void pci_reboot(void); diff --git a/src/hw/pcidevice.c b/src/hw/pcidevice.c index cfebf66..8853cf7 100644 --- a/src/hw/pcidevice.c +++ b/src/hw/pcidevice.c @@ -134,30 +134,6 @@ pci_find_init_device(const struct pci_device_id *ids, = void *arg) return NULL; } =20 -u8 pci_find_capability(struct pci_device *pci, u8 cap_id, u8 cap) -{ - int i; - u16 status =3D pci_config_readw(pci->bdf, PCI_STATUS); - - if (!(status & PCI_STATUS_CAP_LIST)) - return 0; - - if (cap =3D=3D 0) { - /* find first */ - cap =3D pci_config_readb(pci->bdf, PCI_CAPABILITY_LIST); - } else { - /* find next */ - cap =3D pci_config_readb(pci->bdf, cap + PCI_CAP_LIST_NEXT); - } - for (i =3D 0; cap && i <=3D 0xff; i++) { - if (pci_config_readb(pci->bdf, cap + PCI_CAP_LIST_ID) =3D=3D cap_i= d) - return cap; - cap =3D pci_config_readb(pci->bdf, cap + PCI_CAP_LIST_NEXT); - } - - return 0; -} - // Enable PCI bus-mastering (ie, DMA) support on a pci device void pci_enable_busmaster(struct pci_device *pci) diff --git a/src/hw/pcidevice.h b/src/hw/pcidevice.h index 354b549..225d545 100644 --- a/src/hw/pcidevice.h +++ b/src/hw/pcidevice.h @@ -69,7 +69,6 @@ int pci_init_device(const struct pci_device_id *ids , struct pci_device *pci, void *arg); struct pci_device *pci_find_init_device(const struct pci_device_id *ids , void *arg); -u8 pci_find_capability(struct pci_device *pci, u8 cap_id, u8 cap); void pci_enable_busmaster(struct pci_device *pci); u16 pci_enable_iobar(struct pci_device *pci, u32 addr); void *pci_enable_membar(struct pci_device *pci, u32 addr); diff --git a/src/hw/virtio-pci.c b/src/hw/virtio-pci.c index e5c2c33..96f9c6b 100644 --- a/src/hw/virtio-pci.c +++ b/src/hw/virtio-pci.c @@ -19,7 +19,7 @@ #include "malloc.h" // free #include "output.h" // dprintf #include "pci.h" // pci_config_readl -#include "pcidevice.h" // pci_find_capability +#include "pcidevice.h" // struct pci_device #include "pci_regs.h" // PCI_BASE_ADDRESS_0 #include "string.h" // memset #include "virtio-pci.h" @@ -381,7 +381,7 @@ fail: =20 void vp_init_simple(struct vp_device *vp, struct pci_device *pci) { - u8 cap =3D pci_find_capability(pci, PCI_CAP_ID_VNDR, 0); + u8 cap =3D pci_find_capability(pci->bdf, PCI_CAP_ID_VNDR, 0); struct vp_cap *vp_cap; const char *mode; u32 offset, base, mul; @@ -479,7 +479,7 @@ void vp_init_simple(struct vp_device *vp, struct pci_de= vice *pci) vp_cap->cap, type, vp_cap->bar, addr, offset, mode); } =20 - cap =3D pci_find_capability(pci, PCI_CAP_ID_VNDR, cap); + cap =3D pci_find_capability(pci->bdf, PCI_CAP_ID_VNDR, cap); } =20 if (vp->common.cap && vp->notify.cap && vp->isr.cap && vp->device.cap)= { --=20 2.7.4 _______________________________________________ SeaBIOS mailing list SeaBIOS@seabios.org https://mail.coreboot.org/mailman/listinfo/seabios From nobody Mon Apr 29 07:41:50 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) client-ip=80.81.252.135; envelope-from=seabios-bounces@seabios.org; helo=mail.coreboot.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) smtp.mailfrom=seabios-bounces@seabios.org Return-Path: Received: from mail.coreboot.org (mail.coreboot.org [80.81.252.135]) by mx.zohomail.com with SMTPS id 1501284917976452.6195846401548; Fri, 28 Jul 2017 16:35:17 -0700 (PDT) Received: from [127.0.0.1] (helo=ra.coresystems.de) by mail.coreboot.org with esmtp (Exim 4.86_2) (envelope-from ) id 1dbEka-0006Ei-7o; Sat, 29 Jul 2017 01:32:56 +0200 Received: from mail-lf0-f68.google.com ([209.85.215.68]) by mail.coreboot.org with esmtps (TLSv1.2:ECDHE-RSA-AES128-GCM-SHA256:128) (Exim 4.86_2) (envelope-from ) id 1dbEkJ-00069i-Pc for seabios@seabios.org; Sat, 29 Jul 2017 01:32:55 +0200 Received: by mail-lf0-f68.google.com with SMTP id d80so9434305lfg.1 for ; Fri, 28 Jul 2017 16:34:49 -0700 (PDT) Received: from localhost.localdomain (broadband-95-84-133-8.moscow.rt.ru. [95.84.133.8]) by smtp.gmail.com with ESMTPSA id s133sm2579116lfs.4.2017.07.28.16.34.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 28 Jul 2017 16:34:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=1vO4FxwTEHDhowPCQrmcc8dCS7kl3aSjIIdcQq23MLs=; b=UhC6imfW5lNDmvh3/hRV+G+Ypk1q8Y9ZAd2k6pSGLMI+R8P1WzJ+ArNQ/A8b/I9gXB tZnzWQ9RnYAwFi0hTgCM63QgEHpSW+X2y7x4/4L4rxtHR7hFRwLm3cQ802Uad274BqO+ uS+4EpQYvYuJEKiaHl2U1/WDxOdFdnYHyomn+WWps4OUltOzKTqIuz/yFFfaGEmrqbBj TEo4JRctNIPdBlriRIDvX8PPWFqssylmSRt+6xeWuaX/IBnDuyZjlV8/kN4JEJUy9OMI K/KjbGgSr7SPsSOgTBOeg7sl573NuMRa9a7X8lN3FWQ2s/lXwE5Wr60MJM8/gMhbX5HU yynA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1vO4FxwTEHDhowPCQrmcc8dCS7kl3aSjIIdcQq23MLs=; b=e5REFXAQ68DUcAxcj6wC2A5Rd8byJ0fnIVi2dWlcxrNUYC0bvHqYzwc0HwKjAFhGIv xizBKaFeJFx20OTtf4BItefswqkk84SKsioO0zuewlyTdyl7NARCqJKCzyCnRKXWFqux 1Rz4MZK7DbOSKl7myBvq99Up/wm/vAs+1/+tM0frJ7c0YOaYtvPZJX5QdkCBfaYAk4Bo Lc8xScUdHuQQbL6wmeYjq86THowgEyHroLEmsAEDubwo/HsUotV+PS6MzokQ89U0K1Q2 bnJf7xJ9q5M5iJh35UGZ79/sZO+bwRNYw0UcKUJtdSL1BP97mzWtUWTyzN7Z3Nka9VsK cccw== X-Gm-Message-State: AIVw11370Nqo0frJY9Z4QMlKoCUfe35xst8mk5Ic1ZGfjNwhOBzuelVl Ojq7/n4gPif5qFqg X-Received: by 10.46.84.21 with SMTP id i21mr760514ljb.150.1501284887797; Fri, 28 Jul 2017 16:34:47 -0700 (PDT) From: Aleksandr Bezzubikov To: seabios@seabios.org Date: Sat, 29 Jul 2017 02:34:31 +0300 Message-Id: <1501284872-2078-3-git-send-email-zuban32s@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501284872-2078-1-git-send-email-zuban32s@gmail.com> References: <1501284872-2078-1-git-send-email-zuban32s@gmail.com> X-Spam-Score: -2.1 (--) Subject: [SeaBIOS] [PATCH v3 2/3] pci: add QEMU-specific PCI capability structure X-BeenThere: seabios@seabios.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: SeaBIOS mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mst@redhat.com, qemu-devel@nongnu.org, kraxel@redhat.com, marcel@redhat.com, lersek@redhat.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: seabios-bounces@seabios.org Sender: "SeaBIOS" X-Duff: Orig. Duff, Duff Lite, Duff Dry, Duff Dark, Raspberry Duff, Lady Duff, Red Duff, Tartar Control Duff X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" On PCI init PCI bridge devices may need some extra info about bus number to reserve, IO, memory and prefetchable memory limits. QEMU can provide this with special vendor-specific PCI capability. This capability is intended to be used only for Red Hat PCI bridges, i.e. QEMU cooperation. Signed-off-by: Aleksandr Bezzubikov --- src/fw/dev-pci.h | 62 ++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 62 insertions(+) create mode 100644 src/fw/dev-pci.h diff --git a/src/fw/dev-pci.h b/src/fw/dev-pci.h new file mode 100644 index 0000000..fbd49ed --- /dev/null +++ b/src/fw/dev-pci.h @@ -0,0 +1,62 @@ +#ifndef _PCI_CAP_H +#define _PCI_CAP_H + +#include "types.h" + +/* + +QEMU-specific vendor(Red Hat)-specific capability. +It's intended to provide some hints for firmware to init PCI devices. + +Its is shown below: + +Header: + +u8 id; Standard PCI Capability Header field +u8 next; Standard PCI Capability Header field +u8 len; Standard PCI Capability Header field +u8 type; Red Hat vendor-specific capability type: + now only REDHAT_QEMU_CAP 1 exists +Data: + +u16 non_prefetchable_16; non-prefetchable memory limit + +u8 bus_res; minimum bus number to reserve; + this is necessary for PCI Express Root Ports + to support PCIE-to-PCI bridge hotplug + +u8 io_8; IO limit in case of 8-bit limit value +u32 io_32; IO limit in case of 16-bit limit value + io_8 and io_16 are mutually exclusive, in other words, + they can't be non-zero simultaneously + +u32 prefetchable_32; non-prefetchable memory limit + in case of 32-bit limit value +u64 prefetchable_64; non-prefetchable memory limit + in case of 64-bit limit value + prefetachable_32 and prefetchable_64 are + mutually exclusive, in other words, + they can't be non-zero simultaneously +If any field in Data section is 0, +it means that such kind of reservation +is not needed. + +*/ + +/* Offset of vendor-specific capability type field */ +#define PCI_CAP_VNDR_SPEC_TYPE 3 + +/* List of valid Red Hat vendor-specific capability types */ +#define REDHAT_CAP_TYPE_QEMU 1 + + +/* Offsets of QEMU capability fields */ +#define QEMU_PCI_CAP_NON_PREF 4 +#define QEMU_PCI_CAP_BUS_RES 6 +#define QEMU_PCI_CAP_IO_8 7 +#define QEMU_PCI_CAP_IO_32 8 +#define QEMU_PCI_CAP_PREF_32 12 +#define QEMU_PCI_CAP_PREF_64 16 +#define QEMU_PCI_CAP_SIZE 24 + +#endif /* _PCI_CAP_H */ --=20 2.7.4 _______________________________________________ SeaBIOS mailing list SeaBIOS@seabios.org https://mail.coreboot.org/mailman/listinfo/seabios From nobody Mon Apr 29 07:41:50 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) client-ip=80.81.252.135; envelope-from=seabios-bounces@seabios.org; helo=mail.coreboot.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) smtp.mailfrom=seabios-bounces@seabios.org Return-Path: Received: from mail.coreboot.org (mail.coreboot.org [80.81.252.135]) by mx.zohomail.com with SMTPS id 1501284920875181.42351655390848; Fri, 28 Jul 2017 16:35:20 -0700 (PDT) Received: from [127.0.0.1] (helo=ra.coresystems.de) by mail.coreboot.org with esmtp (Exim 4.86_2) (envelope-from ) id 1dbEkd-0006FR-1p; Sat, 29 Jul 2017 01:32:59 +0200 Received: from mail-lf0-f67.google.com ([209.85.215.67]) by mail.coreboot.org with esmtps (TLSv1.2:ECDHE-RSA-AES128-GCM-SHA256:128) (Exim 4.86_2) (envelope-from ) id 1dbEkL-00069k-2t for seabios@seabios.org; Sat, 29 Jul 2017 01:32:56 +0200 Received: by mail-lf0-f67.google.com with SMTP id x16so10946717lfb.4 for ; Fri, 28 Jul 2017 16:34:50 -0700 (PDT) Received: from localhost.localdomain (broadband-95-84-133-8.moscow.rt.ru. [95.84.133.8]) by smtp.gmail.com with ESMTPSA id s133sm2579116lfs.4.2017.07.28.16.34.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 28 Jul 2017 16:34:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=hZyvRCjiiIf2F6dVBk5hTdB46qGz36P2+wsR3JrZudA=; b=tRrYGXrtUQ7nrWvMmmDbIRyN4Nj2hCY9XgGRSYVq9VRAoVypidsiUlpO4km0crC4Zv puG0B9zMGy2TPd4ndYATunJ2+VdKOqCB9rr356zIurhi+T5UYdZNd7T4/VHxt+L3lRsC 3lzNwVU/3A+gl1/echOCgV8kcVYlgiKkYYds3weazGp/la9/YGRKGGUtYyhB6VCwQpAm 20yi4Mi5sw2HbddpE99tdWB8EjzorrVdpDiPWIvL6HQz/ZDz6R2J3vPFTtfgBwgvwkwx 5kbnlyMW95ElDgtVa6tXedlHaFNvqPramJvdsIM4XwtQFXiFKWidZMyNooM1oLAA1ZlY 7RTw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=hZyvRCjiiIf2F6dVBk5hTdB46qGz36P2+wsR3JrZudA=; b=ez8rTpKVqU5BT6K2kOlEsrmtUnYDF+Z27/i2Hv4DOUr2CBskBuTHqhSCIaaDlkTf+L E95I9NEUtO5I3YhPQ1HIIKxWMd18P8heHt9vNWi869nCvN+h3+5nzR1pbWujLOWEVgNN Zu9QpQlhQ95YGgmfilGYls3b87fdOaJcOEavKPFDBbnklCYN3UFuNItRa05OeciW2MRg +b2vPktNoBWQMhCJ9nc0l4jUaoKFyzDAHRe8VJmj5cxMAcpel5FhveM69ULcJg5CazRM Z/ApMeEwc5pIG2tJdNbBUJFL+YQL2rqsF8MXGmmZeppXuKpa6pw1t/6ZS7ruKBt0FAjH vaGw== X-Gm-Message-State: AIVw112CsibKGZ79ByxFVDRFP4dqIKGOCf49EzL1H0qnIt6XZIMXRfis Gl6eE8j6Ttly18k7 X-Received: by 10.46.92.137 with SMTP id q131mr3379209ljb.102.1501284889112; Fri, 28 Jul 2017 16:34:49 -0700 (PDT) From: Aleksandr Bezzubikov To: seabios@seabios.org Date: Sat, 29 Jul 2017 02:34:32 +0300 Message-Id: <1501284872-2078-4-git-send-email-zuban32s@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501284872-2078-1-git-send-email-zuban32s@gmail.com> References: <1501284872-2078-1-git-send-email-zuban32s@gmail.com> X-Spam-Score: -6.4 (------) Subject: [SeaBIOS] [PATCH v3 3/3] pci: enable RedHat PCI bridges to reserve additional buses on PCI init X-BeenThere: seabios@seabios.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: SeaBIOS mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mst@redhat.com, qemu-devel@nongnu.org, kraxel@redhat.com, marcel@redhat.com, lersek@redhat.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: seabios-bounces@seabios.org Sender: "SeaBIOS" X-Duff: Orig. Duff, Duff Lite, Duff Dry, Duff Dark, Raspberry Duff, Lady Duff, Red Duff, Tartar Control Duff X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" In case of Red Hat Generic PCIE Root Port reserve additional buses, which number is provided in a vendor-specific capability. Signed-off-by: Aleksandr Bezzubikov --- src/fw/pciinit.c | 37 +++++++++++++++++++++++++++++++++++-- src/hw/pci_ids.h | 3 +++ src/types.h | 2 ++ 3 files changed, 40 insertions(+), 2 deletions(-) diff --git a/src/fw/pciinit.c b/src/fw/pciinit.c index 864954f..a302a85 100644 --- a/src/fw/pciinit.c +++ b/src/fw/pciinit.c @@ -15,6 +15,7 @@ #include "hw/pcidevice.h" // pci_probe_devices #include "hw/pci_ids.h" // PCI_VENDOR_ID_INTEL #include "hw/pci_regs.h" // PCI_COMMAND +#include "fw/dev-pci.h" // qemu_pci_cap #include "list.h" // struct hlist_node #include "malloc.h" // free #include "output.h" // dprintf @@ -578,9 +579,41 @@ pci_bios_init_bus_rec(int bus, u8 *pci_bus) pci_bios_init_bus_rec(secbus, pci_bus); =20 if (subbus !=3D *pci_bus) { + u8 res_bus =3D 0; + if (pci_config_readw(bdf, PCI_VENDOR_ID) =3D=3D PCI_VENDOR_ID_= REDHAT && + pci_config_readw(bdf, PCI_DEVICE_ID) =3D=3D + PCI_DEVICE_ID_REDHAT_ROOT_PORT) { + u8 cap; + do { + cap =3D pci_find_capability(bdf, PCI_CAP_ID_VNDR, 0); + } while (cap && + pci_config_readb(bdf, cap + PCI_CAP_VNDR_SPEC_TYP= E) !=3D + REDHAT_CAP_TYPE_QEMU); + if (cap) { + u8 cap_len =3D pci_config_readb(bdf, cap + PCI_CAP_FLA= GS); + if (cap_len !=3D QEMU_PCI_CAP_SIZE) { + dprintf(1, "PCI: QEMU cap length %d is invalid\n", + cap_len); + } else { + res_bus =3D pci_config_readb(bdf, + cap + QEMU_PCI_CAP_BUS_= RES); + if ((u8)(res_bus + secbus) < secbus || + (u8)(res_bus + secbus) < res_bus) { + dprintf(1, "PCI: bus_reserve value %d is inval= id\n", + res_bus); + res_bus =3D 0; + } else { + dprintf(1, "PCI: QEMU cap is found, value =3D = %u\n", + res_bus); + } + } + } + res_bus =3D MAX(*pci_bus, secbus + res_bus); + } dprintf(1, "PCI: subordinate bus =3D 0x%x -> 0x%x\n", - subbus, *pci_bus); - subbus =3D *pci_bus; + subbus, res_bus); + subbus =3D res_bus; + *pci_bus =3D res_bus; } else { dprintf(1, "PCI: subordinate bus =3D 0x%x\n", subbus); } diff --git a/src/hw/pci_ids.h b/src/hw/pci_ids.h index 4ac73b4..38fa2ca 100644 --- a/src/hw/pci_ids.h +++ b/src/hw/pci_ids.h @@ -2263,6 +2263,9 @@ #define PCI_DEVICE_ID_KORENIX_JETCARDF0 0x1600 #define PCI_DEVICE_ID_KORENIX_JETCARDF1 0x16ff =20 +#define PCI_VENDOR_ID_REDHAT 0x1b36 +#define PCI_DEVICE_ID_REDHAT_ROOT_PORT 0x000C + #define PCI_VENDOR_ID_TEKRAM 0x1de1 #define PCI_DEVICE_ID_TEKRAM_DC290 0xdc29 =20 diff --git a/src/types.h b/src/types.h index 19d9f6c..75d9108 100644 --- a/src/types.h +++ b/src/types.h @@ -122,6 +122,8 @@ extern void __force_link_error__only_in_16bit(void) __n= oreturn; typeof(divisor) __divisor =3D divisor; \ (((x) + ((__divisor) / 2)) / (__divisor)); \ }) +#define MIN(a, b) (((a) < (b)) ? (a) : (b)) +#define MAX(a, b) (((a) > (b)) ? (a) : (b)) #define ALIGN(x,a) __ALIGN_MASK(x,(typeof(x))(a)-1) #define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask)) #define ALIGN_DOWN(x,a) ((x) & ~((typeof(x))(a)-1)) --=20 2.7.4 _______________________________________________ SeaBIOS mailing list SeaBIOS@seabios.org https://mail.coreboot.org/mailman/listinfo/seabios