From nobody Sat May 4 22:45:36 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) client-ip=80.81.252.135; envelope-from=seabios-bounces@seabios.org; helo=mail.coreboot.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) smtp.mailfrom=seabios-bounces@seabios.org Return-Path: Received: from mail.coreboot.org (mail.coreboot.org [80.81.252.135]) by mx.zohomail.com with SMTPS id 1500761786645639.5226218749044; Sat, 22 Jul 2017 15:16:26 -0700 (PDT) Received: from [127.0.0.1] (helo=ra.coresystems.de) by mail.coreboot.org with esmtp (Exim 4.86_2) (envelope-from ) id 1dZ2f7-0000BF-BR; Sun, 23 Jul 2017 00:14:13 +0200 Received: from mail-lf0-f65.google.com ([209.85.215.65]) by mail.coreboot.org with esmtps (TLSv1.2:ECDHE-RSA-AES128-GCM-SHA256:128) (Exim 4.86_2) (envelope-from ) id 1dZ2eu-000097-U1 for seabios@seabios.org; Sun, 23 Jul 2017 00:14:11 +0200 Received: by mail-lf0-f65.google.com with SMTP id t128so760707lff.3 for ; Sat, 22 Jul 2017 15:16:00 -0700 (PDT) Received: from localhost.localdomain (broadband-178-140-16-138.moscow.rt.ru. [178.140.16.138]) by smtp.gmail.com with ESMTPSA id t10sm757832lja.47.2017.07.22.15.15.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 22 Jul 2017 15:15:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=f8IkrGKfYhX6PXQLqhusFjW7aqNP9b5IupzzagSkz20=; b=lCQGgOM1xb6o+G+Y/vK3oRbotGr/gS0+sw39HIuU4bkpMNAQeW6ugOwls+vcXPx9Bs +dV526gXm2XivcgUrdkj+VVBpnHBMwfGIyZ9VX0H97W9JFhQPIIW1VBvcydLOw3H8qDF vOpXC4z1R1Pq3mJJ8/To/5Z8vj1LZx+8ptjoEpdMagyMoY5oQ+NlaUCtpV3Giuz1zBXd vowzePk97t8tp6Xr1U6LePZcpdk0yfmUwhv+zJvTpxXiFJ2C8CghP9EFqKxQt0m3r0Zm +TCV9vEvAN65/2BhdQgSI3sYfGTQkEZwIkJbudx4d0RNtavcuj8zjOdNILsIurHwRl7h 258w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=f8IkrGKfYhX6PXQLqhusFjW7aqNP9b5IupzzagSkz20=; b=O72vO8nC7m0XOAhnGrqAHTr88H//qKbwYwa+bRM603p91nxVCYpwa4ccjMFVb2utbE 5JrMFw6lPN5j9fmPg047wlqHxMxamVVZUqyHW9Lck6FsZ4KMlgCw3F4bVgH7XavVIw7I g8qHf0WHytOItRxqgKGfXllo7ixo1onequ7epwbjExpleI3qPDriDNZNHsrlWhvajOWo m1VRfHWLAdDVKeQTVoWZc9aDDgkOQa5ybrX8nhMv3DkrmKJ1lTjmtnTxUUR5CkOUhZYg JPOhDwVsaaSFTFqpB6N3lBCUB8HhyjyTeM3j3WzW+2zQc9ukLfgwnYcCh/pFMX+klWec KvSQ== X-Gm-Message-State: AIVw110i6oroD3b8PBToHq7RiRM/8JYfXrF54yjTA2LRl7/8+tx/9xMN qHjUCwEVOm2O/g== X-Received: by 10.46.32.10 with SMTP id g10mr3316760ljg.176.1500761759352; Sat, 22 Jul 2017 15:15:59 -0700 (PDT) From: Aleksandr Bezzubikov To: qemu-devel@nongnu.org Date: Sun, 23 Jul 2017 01:15:38 +0300 Message-Id: <1500761743-1669-2-git-send-email-zuban32s@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500761743-1669-1-git-send-email-zuban32s@gmail.com> References: <1500761743-1669-1-git-send-email-zuban32s@gmail.com> X-Spam-Score: -4.5 (----) Subject: [SeaBIOS] [RFC PATCH v2 1/6] hw/pci: introduce pcie-pci-bridge device X-BeenThere: seabios@seabios.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: SeaBIOS mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mst@redhat.com, seabios@seabios.org, kraxel@redhat.com, pbonzini@redhat.com, marcel@redhat.com, rth@twiddle.net MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: seabios-bounces@seabios.org Sender: "SeaBIOS" X-Duff: Orig. Duff, Duff Lite, Duff Dry, Duff Dark, Raspberry Duff, Lady Duff, Red Duff, Tartar Control Duff X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Aleksandr Bezzubikov --- hw/pci-bridge/Makefile.objs | 2 +- hw/pci-bridge/pcie_pci_bridge.c | 151 ++++++++++++++++++++++++++++++++++++= ++++ include/hw/pci/pci.h | 1 + 3 files changed, 153 insertions(+), 1 deletion(-) create mode 100644 hw/pci-bridge/pcie_pci_bridge.c diff --git a/hw/pci-bridge/Makefile.objs b/hw/pci-bridge/Makefile.objs index c4683cf..666db37 100644 --- a/hw/pci-bridge/Makefile.objs +++ b/hw/pci-bridge/Makefile.objs @@ -1,4 +1,4 @@ -common-obj-y +=3D pci_bridge_dev.o +common-obj-y +=3D pci_bridge_dev.o pcie_pci_bridge.o common-obj-$(CONFIG_PCIE_PORT) +=3D pcie_root_port.o gen_pcie_root_port.o common-obj-$(CONFIG_PXB) +=3D pci_expander_bridge.o common-obj-$(CONFIG_XIO3130) +=3D xio3130_upstream.o xio3130_downstream.o diff --git a/hw/pci-bridge/pcie_pci_bridge.c b/hw/pci-bridge/pcie_pci_bridg= e.c new file mode 100644 index 0000000..0991a7b --- /dev/null +++ b/hw/pci-bridge/pcie_pci_bridge.c @@ -0,0 +1,151 @@ +/* + * QEMU Generic PCIE-PCI Bridge + * + * Copyright (c) 2017 Aleksandr Bezzubikov + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/pci/pci.h" +#include "hw/pci/pci_bus.h" +#include "hw/pci/pci_bridge.h" +#include "hw/pci/msi.h" +#include "hw/pci/slotid_cap.h" + +typedef struct PCIEPCIBridge { + /*< private >*/ + PCIBridge parent_obj; + uint32_t flags; + + /*< public >*/ +} PCIEPCIBridge; + +#define TYPE_PCIE_PCI_BRIDGE_DEV "pcie-pci-bridge" +#define PCIE_PCI_BRIDGE_DEV(obj) \ + OBJECT_CHECK(PCIEPCIBridge, (obj), TYPE_PCIE_PCI_BRIDGE_DEV) + +static void pciepci_bridge_realize(PCIDevice *d, Error **errp) +{ + int rc, pos; + Error *local_err =3D NULL; + + pci_bridge_initfn(d, TYPE_PCI_BUS); + + rc =3D pcie_cap_init(d, 0, PCI_EXP_TYPE_PCI_BRIDGE, 0, &local_err); + if (rc < 0) { + error_propagate(errp, local_err); + goto error; + } + + pos =3D pci_add_capability(d, PCI_CAP_ID_PM, 0, PCI_PM_SIZEOF, &local_= err); + if (pos < 0) { + error_propagate(errp, local_err); + goto error; + } + d->exp.pm_cap =3D pos; + pci_set_word(d->config + pos + PCI_PM_PMC, 0x3); + + pcie_cap_arifwd_init(d); + pcie_cap_deverr_init(d); + + rc =3D pcie_aer_init(d, PCI_ERR_VER, 0x100, PCI_ERR_SIZEOF, &local_err= ); + if (rc < 0) { + error_propagate(errp, local_err); + goto error; + } + + rc =3D msi_init(d, 0, 1, true, true, &local_err); + if (rc < 0) { + error_propagate(errp, local_err); + goto error; + } + + return; + + error: + pci_bridge_exitfn(d); +} + +static void pciepci_bridge_exit(PCIDevice *d) +{ + pcie_cap_exit(d); + pci_bridge_exitfn(d); +} + +static void pciepci_bridge_reset(DeviceState *qdev) +{ + PCIDevice *d =3D PCI_DEVICE(qdev); + pci_bridge_reset(qdev); + msi_reset(d); +} + +static void pcie_pci_bridge_write_config(PCIDevice *d, + uint32_t address, uint32_t val, int len) +{ + pci_bridge_write_config(d, address, val, len); + msi_write_config(d, address, val, len); +} + + +static Property pcie_pci_bridge_dev_properties[] =3D { + DEFINE_PROP_END_OF_LIST(), +}; + +static const VMStateDescription pciepci_bridge_dev_vmstate =3D { + .name =3D TYPE_PCIE_PCI_BRIDGE_DEV, + .fields =3D (VMStateField[]) { + VMSTATE_PCI_DEVICE(parent_obj, PCIBridge), + VMSTATE_END_OF_LIST() + } +}; + +static void pciepci_bridge_class_init(ObjectClass *klass, void *data) +{ + PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); + DeviceClass *dc =3D DEVICE_CLASS(klass); + + k->is_express =3D 1; + k->is_bridge =3D 1; + k->vendor_id =3D PCI_VENDOR_ID_REDHAT; + k->device_id =3D PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE; + k->realize =3D pciepci_bridge_realize; + k->exit =3D pciepci_bridge_exit; + k->config_write =3D pcie_pci_bridge_write_config; + dc->vmsd =3D &pciepci_bridge_dev_vmstate; + dc->props =3D pcie_pci_bridge_dev_properties; + dc->vmsd =3D &pciepci_bridge_dev_vmstate; + dc->reset =3D &pciepci_bridge_reset; + set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); +} + +static const TypeInfo pciepci_bridge_info =3D { + .name =3D TYPE_PCIE_PCI_BRIDGE_DEV, + .parent =3D TYPE_PCI_BRIDGE, + .instance_size =3D sizeof(PCIEPCIBridge), + .class_init =3D pciepci_bridge_class_init +}; + +static void pciepci_register(void) +{ + type_register_static(&pciepci_bridge_info); +} + +type_init(pciepci_register); diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index e598b09..b33a34f 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -98,6 +98,7 @@ #define PCI_DEVICE_ID_REDHAT_PXB_PCIE 0x000b #define PCI_DEVICE_ID_REDHAT_PCIE_RP 0x000c #define PCI_DEVICE_ID_REDHAT_XHCI 0x000d +#define PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE 0x000e #define PCI_DEVICE_ID_REDHAT_QXL 0x0100 =20 #define FMT_PCIBUS PRIx64 --=20 2.7.4 _______________________________________________ SeaBIOS mailing list SeaBIOS@seabios.org https://mail.coreboot.org/mailman/listinfo/seabios From nobody Sat May 4 22:45:36 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) client-ip=80.81.252.135; envelope-from=seabios-bounces@seabios.org; helo=mail.coreboot.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) smtp.mailfrom=seabios-bounces@seabios.org Return-Path: Received: from mail.coreboot.org (mail.coreboot.org [80.81.252.135]) by mx.zohomail.com with SMTPS id 15007617922151019.680804872558; Sat, 22 Jul 2017 15:16:32 -0700 (PDT) Received: from [127.0.0.1] (helo=ra.coresystems.de) by mail.coreboot.org with esmtp (Exim 4.86_2) (envelope-from ) id 1dZ2f8-0000CY-OL; Sun, 23 Jul 2017 00:14:14 +0200 Received: from mail-lf0-f68.google.com ([209.85.215.68]) by mail.coreboot.org with esmtps (TLSv1.2:ECDHE-RSA-AES128-GCM-SHA256:128) (Exim 4.86_2) (envelope-from ) id 1dZ2ew-00009G-J9 for seabios@seabios.org; Sun, 23 Jul 2017 00:14:13 +0200 Received: by mail-lf0-f68.google.com with SMTP id p11so5151559lfd.1 for ; Sat, 22 Jul 2017 15:16:02 -0700 (PDT) Received: from localhost.localdomain (broadband-178-140-16-138.moscow.rt.ru. [178.140.16.138]) by smtp.gmail.com with ESMTPSA id t10sm757832lja.47.2017.07.22.15.15.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 22 Jul 2017 15:15:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=2bRwt42umk3O6XUw3b5SeZTeFb+VcGvPlqA9XMOlT0c=; b=d4jLizSQu9Lk7NWnw+zx9Czb0WUcG4tlC9X6IEeNp85ZXdcXwfaXWoMgIYnsAyeFNi 05sYV7w6IpeDcNEXwCjRL0JA9izo8c9aGWX1/lSXSfhcSBqK+j/N7i+3cE7+hLkgToBn R7LH8iOY2mgvGOv6JiMnC7htaXGR7KyTMu3LySP/EBNpH9Gu9RWVRDgFDI2A0toJONcY 5HGum6CpO7JwIc7Wn+RrjAAbh0ODn/1tj4hm7iBx7A8sz7AyB80xWaxzkUbB6eJX24lG x87r36bKAILDzl6FGkdHUzBslhH6vOKNa+B7W/Qu+M2cOFtkCvaiM7q9NzN+2VmjR1UD tk7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=2bRwt42umk3O6XUw3b5SeZTeFb+VcGvPlqA9XMOlT0c=; b=tr9q+ppY3soP/OtQpIAjvsST+Ulo/lrg7CJMnbmOjlsnrE291h0YhzMWAA6XeuCfzI +8H1OV1iyqu0gaZbhUE387GTRnFJXLOc4k3R/cJ64C0HlbUAa2Zz1lwgUz7apCNyYekM MmVCQbbVYn2J16tDHzxPdLT9/TsmRcPa+LJIorgFqNdEd+PT/Geocf3nYe4tr3TK29WG y5O7EHzSvZEEzFarszZMAoIA8RKIjY1Jvei+MgTEFUGTbu5rHTX8OwEKXat7wRwDY4uw ZFcKOZfj3eD1l0+68D5/PdQPlxnNu+kFqGcb8arzaTG/0IIHzGzoIAUFblftHeAJCcWH GPew== X-Gm-Message-State: AIVw111des7niLP0j1mCyEhvMTMjwYEJlt8+GBXtWIt4pRKBnALaiQkr O372POSt4G+cXA== X-Received: by 10.46.0.20 with SMTP id 20mr1106988lja.68.1500761761080; Sat, 22 Jul 2017 15:16:01 -0700 (PDT) From: Aleksandr Bezzubikov To: qemu-devel@nongnu.org Date: Sun, 23 Jul 2017 01:15:39 +0300 Message-Id: <1500761743-1669-3-git-send-email-zuban32s@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500761743-1669-1-git-send-email-zuban32s@gmail.com> References: <1500761743-1669-1-git-send-email-zuban32s@gmail.com> X-Spam-Score: -2.6 (--) Subject: [SeaBIOS] [RFC PATCH v2 2/6] hw/i386: allow SHPC for Q35 machine X-BeenThere: seabios@seabios.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: SeaBIOS mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mst@redhat.com, seabios@seabios.org, kraxel@redhat.com, pbonzini@redhat.com, marcel@redhat.com, rth@twiddle.net MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: seabios-bounces@seabios.org Sender: "SeaBIOS" X-Duff: Orig. Duff, Duff Lite, Duff Dry, Duff Dark, Raspberry Duff, Lady Duff, Red Duff, Tartar Control Duff X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Unmask previously masked SHPC feature in _OSC method. Signed-off-by: Aleksandr Bezzubikov --- hw/i386/acpi-build.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 6b7bade..0d99585 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -1850,7 +1850,7 @@ static Aml *build_q35_osc_method(void) * Always allow native PME, AER (no dependencies) * Never allow SHPC (no SHPC controller in this system) */ - aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1D), a_ctrl)); + aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1F), a_ctrl)); =20 if_ctx2 =3D aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1)))); /* Unknown revision */ --=20 2.7.4 _______________________________________________ SeaBIOS mailing list SeaBIOS@seabios.org https://mail.coreboot.org/mailman/listinfo/seabios From nobody Sat May 4 22:45:36 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) client-ip=80.81.252.135; envelope-from=seabios-bounces@seabios.org; helo=mail.coreboot.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) smtp.mailfrom=seabios-bounces@seabios.org Return-Path: Received: from mail.coreboot.org (mail.coreboot.org [80.81.252.135]) by mx.zohomail.com with SMTPS id 15007617898741010.8133958165715; Sat, 22 Jul 2017 15:16:29 -0700 (PDT) Received: from [127.0.0.1] (helo=ra.coresystems.de) by mail.coreboot.org with esmtp (Exim 4.86_2) (envelope-from ) id 1dZ2fA-0000Do-H5; Sun, 23 Jul 2017 00:14:16 +0200 Received: from mail-lf0-f65.google.com ([209.85.215.65]) by mail.coreboot.org with esmtps (TLSv1.2:ECDHE-RSA-AES128-GCM-SHA256:128) (Exim 4.86_2) (envelope-from ) id 1dZ2ey-00009N-G2 for seabios@seabios.org; Sun, 23 Jul 2017 00:14:14 +0200 Received: by mail-lf0-f65.google.com with SMTP id t128so760735lff.3 for ; Sat, 22 Jul 2017 15:16:04 -0700 (PDT) Received: from localhost.localdomain (broadband-178-140-16-138.moscow.rt.ru. [178.140.16.138]) by smtp.gmail.com with ESMTPSA id t10sm757832lja.47.2017.07.22.15.16.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 22 Jul 2017 15:16:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=rIBS7YdoDjtW2bJ3l1aFA9YuYSMk+NiXjDEoUSvWLyE=; b=nPDUIfnp8uZMflSIXaMWM3IMUOsDM+Lk+9csoI17WOQ6DRJq8rHbTN+YH9DXU+mYQE iDiuzacX/pXIVq0x+NVY5uXm4G9K5tdqYfVcQLmarF00qU5AaIOrXBdb+1/fGU1WwdIr qQNlZ+7e0Ou91Fh0pcM6QFTo7TzeZa6mDLsYxPvqzPrfktCVlc5iDeqfI3TE6n00r8e/ 6gQaJtWDTV4P00mER/QaU4gFDrwNVca3/Pk4KHs4mTB0J9T9fNGepUqja9Q4enG7CJcp KzNxflLdBuqoiK0fSj77n9pFHVlzD54UU8+1cMt5UJYsP97W6otWBhaJl/buWbgO34Vm YYtg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=rIBS7YdoDjtW2bJ3l1aFA9YuYSMk+NiXjDEoUSvWLyE=; b=cY9Bh09qWSfhkOcyviagEFAMzZ0Q/2eS2AIZoTvooMTncdtoX/c5V46RIXRyKdHz17 LHUgsJiUhU8yBAKcwEAJ/06MFoccUyoqCQ7jVGVz3gj0EJALTv4RbpckP7cIMf6AGwcN eq4781nsoagNplM+zBKkLEnuAvF22Eg1liMfzKAKO2pmrdhFUkaDRuDMszfF5hJ9CdW/ uHziCFz90zLEClMIit6WPsquMOOjl5e+CwvYtw3EiFilXWbxpith5bjqQneJhQrPb/A1 4WnMySBcoPHL25SIgut9TvhuLuz6oS4AcRZQHjorWbNIRjfi/vLnzAEO3EgxDka9n0L/ Gh0A== X-Gm-Message-State: AIVw110h3/7/AYZaciYdTLk8sNPIjv3n8S+MuQBacgDPOV1VJxR2l99L ibtvna8dmQJt1Q== X-Received: by 10.25.151.19 with SMTP id z19mr101822lfd.134.1500761762557; Sat, 22 Jul 2017 15:16:02 -0700 (PDT) From: Aleksandr Bezzubikov To: qemu-devel@nongnu.org Date: Sun, 23 Jul 2017 01:15:40 +0300 Message-Id: <1500761743-1669-4-git-send-email-zuban32s@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500761743-1669-1-git-send-email-zuban32s@gmail.com> References: <1500761743-1669-1-git-send-email-zuban32s@gmail.com> X-Spam-Score: -5.8 (-----) Subject: [SeaBIOS] [RFC PATCH v2 3/6] hw/pci: enable SHPC for PCIE-PCI bridge X-BeenThere: seabios@seabios.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: SeaBIOS mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mst@redhat.com, seabios@seabios.org, kraxel@redhat.com, pbonzini@redhat.com, marcel@redhat.com, rth@twiddle.net MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: seabios-bounces@seabios.org Sender: "SeaBIOS" X-Duff: Orig. Duff, Duff Lite, Duff Dry, Duff Dark, Raspberry Duff, Lady Duff, Red Duff, Tartar Control Duff X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Aleksandr Bezzubikov --- hw/pci-bridge/pcie_pci_bridge.c | 63 +++++++++++++++++++++++++++++++++++++= +++- 1 file changed, 62 insertions(+), 1 deletion(-) diff --git a/hw/pci-bridge/pcie_pci_bridge.c b/hw/pci-bridge/pcie_pci_bridg= e.c index 0991a7b..38f665f 100644 --- a/hw/pci-bridge/pcie_pci_bridge.c +++ b/hw/pci-bridge/pcie_pci_bridge.c @@ -28,6 +28,7 @@ #include "hw/pci/pci_bus.h" #include "hw/pci/pci_bridge.h" #include "hw/pci/msi.h" +#include "hw/pci/shpc.h" #include "hw/pci/slotid_cap.h" =20 typedef struct PCIEPCIBridge { @@ -35,6 +36,7 @@ typedef struct PCIEPCIBridge { PCIBridge parent_obj; uint32_t flags; =20 + MemoryRegion bar; /*< public >*/ } PCIEPCIBridge; =20 @@ -44,11 +46,22 @@ typedef struct PCIEPCIBridge { =20 static void pciepci_bridge_realize(PCIDevice *d, Error **errp) { + PCIBridge *br =3D PCI_BRIDGE(d); + PCIEPCIBridge *bridge_dev =3D PCIE_PCI_BRIDGE_DEV(d); int rc, pos; Error *local_err =3D NULL; =20 pci_bridge_initfn(d, TYPE_PCI_BUS); =20 + d->config[PCI_INTERRUPT_PIN] =3D 0x1; + memory_region_init(&bridge_dev->bar, OBJECT(d), "shpc-bar", + shpc_bar_size(d)); + rc =3D shpc_init(d, &br->sec_bus, &bridge_dev->bar, 0, &local_err); + if (rc) { + error_propagate(errp, local_err); + goto error; + } + rc =3D pcie_cap_init(d, 0, PCI_EXP_TYPE_PCI_BRIDGE, 0, &local_err); if (rc < 0) { error_propagate(errp, local_err); @@ -78,6 +91,9 @@ static void pciepci_bridge_realize(PCIDevice *d, Error **= errp) goto error; } =20 + pci_register_bar(d, 0, PCI_BASE_ADDRESS_SPACE_MEMORY | + PCI_BASE_ADDRESS_MEM_TYPE_64, &bridge_dev->bar); + return; =20 error: @@ -86,7 +102,9 @@ static void pciepci_bridge_realize(PCIDevice *d, Error *= *errp) =20 static void pciepci_bridge_exit(PCIDevice *d) { + PCIEPCIBridge *bridge_dev =3D PCIE_PCI_BRIDGE_DEV(d); pcie_cap_exit(d); + shpc_cleanup(d, &bridge_dev->bar); pci_bridge_exitfn(d); } =20 @@ -95,6 +113,7 @@ static void pciepci_bridge_reset(DeviceState *qdev) PCIDevice *d =3D PCI_DEVICE(qdev); pci_bridge_reset(qdev); msi_reset(d); + shpc_reset(d); } =20 static void pcie_pci_bridge_write_config(PCIDevice *d, @@ -102,8 +121,15 @@ static void pcie_pci_bridge_write_config(PCIDevice *d, { pci_bridge_write_config(d, address, val, len); msi_write_config(d, address, val, len); + shpc_cap_write_config(d, address, val, len); } =20 +static bool pci_device_shpc_present(void *opaque, int version_id) +{ + PCIDevice *dev =3D opaque; + + return shpc_present(dev); +} =20 static Property pcie_pci_bridge_dev_properties[] =3D { DEFINE_PROP_END_OF_LIST(), @@ -113,14 +139,43 @@ static const VMStateDescription pciepci_bridge_dev_vm= state =3D { .name =3D TYPE_PCIE_PCI_BRIDGE_DEV, .fields =3D (VMStateField[]) { VMSTATE_PCI_DEVICE(parent_obj, PCIBridge), + SHPC_VMSTATE(shpc, PCIDevice, pci_device_shpc_present), VMSTATE_END_OF_LIST() } }; =20 +static void pcie_pci_bridge_hotplug_cb(HotplugHandler *hotplug_dev, + DeviceState *dev, Error **errp) +{ + PCIDevice *pci_hotplug_dev =3D PCI_DEVICE(hotplug_dev); + + if (!shpc_present(pci_hotplug_dev)) { + error_setg(errp, "standard hotplug controller has been disabled fo= r " + "this %s", TYPE_PCIE_PCI_BRIDGE_DEV); + return; + } + shpc_device_hotplug_cb(hotplug_dev, dev, errp); +} + +static void pcie_pci_bridge_hot_unplug_request_cb(HotplugHandler *hotplug_= dev, + DeviceState *dev, + Error **errp) +{ + PCIDevice *pci_hotplug_dev =3D PCI_DEVICE(hotplug_dev); + + if (!shpc_present(pci_hotplug_dev)) { + error_setg(errp, "standard hotplug controller has been disabled fo= r " + "this %s", TYPE_PCIE_PCI_BRIDGE_DEV); + return; + } + shpc_device_hot_unplug_request_cb(hotplug_dev, dev, errp); +} + static void pciepci_bridge_class_init(ObjectClass *klass, void *data) { PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); DeviceClass *dc =3D DEVICE_CLASS(klass); + HotplugHandlerClass *hc =3D HOTPLUG_HANDLER_CLASS(klass); =20 k->is_express =3D 1; k->is_bridge =3D 1; @@ -134,13 +189,19 @@ static void pciepci_bridge_class_init(ObjectClass *kl= ass, void *data) dc->vmsd =3D &pciepci_bridge_dev_vmstate; dc->reset =3D &pciepci_bridge_reset; set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); + hc->plug =3D pcie_pci_bridge_hotplug_cb; + hc->unplug_request =3D pcie_pci_bridge_hot_unplug_request_cb; } =20 static const TypeInfo pciepci_bridge_info =3D { .name =3D TYPE_PCIE_PCI_BRIDGE_DEV, .parent =3D TYPE_PCI_BRIDGE, .instance_size =3D sizeof(PCIEPCIBridge), - .class_init =3D pciepci_bridge_class_init + .class_init =3D pciepci_bridge_class_init, + .interfaces =3D (InterfaceInfo[]) { + { TYPE_HOTPLUG_HANDLER }, + { }, + } }; =20 static void pciepci_register(void) --=20 2.7.4 _______________________________________________ SeaBIOS mailing list SeaBIOS@seabios.org https://mail.coreboot.org/mailman/listinfo/seabios From nobody Sat May 4 22:45:36 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) client-ip=80.81.252.135; envelope-from=seabios-bounces@seabios.org; helo=mail.coreboot.org; Authentication-Results: mx.zohomail.com; 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[178.140.16.138]) by smtp.gmail.com with ESMTPSA id t10sm757832lja.47.2017.07.22.15.16.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 22 Jul 2017 15:16:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=uJODcaUN2fghYTMSE/DiWYdzbEjrlez4PlO02Mw1RLU=; b=gLMDeLv6UEtRqsru6GnlLZF+JGy6WU2EjlHvPtd9gnLFnHDtGe+4kTWP6c4Msb8SAj SkBHOTrqY3+N2YGjU+omGk2ayDHzTR4rp82OXQgxVDyzDemfoETOgJFpdOb3duSAWYdj UXz7vjRIcWDTr7XHD7tQIjv1hq9x/+5bu6phicMLXJg/srVjQTepALXo2lkzU8xlTlrP RCkJNTv0C7DB1GI13wxrZDjkbVhoU01jZ2DOUQLoDE/MCIME+CK23rhP4RyLYilFwUhP ErbTAJqaNTvokhQUbuxnvUqg2tho/johJt+zqBrnCUxb4lUlbq/TYsNPYzdnEL9thrv4 IrLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=uJODcaUN2fghYTMSE/DiWYdzbEjrlez4PlO02Mw1RLU=; b=Zkb3BcigMNC8/In5HOxucdVV1rM/njpnD9xD9CL83EDC4lrgIzVoYyM3AcBzJOSAJy wNB1JXBBkdKNMmNNyHqf5+nnw03lMY+va6P8iEv6vVX01Cb9VlMPTeMbpV93To/N0rOm pPx7BrHCiUEnz3PSX2JM5S0rSslLZB5DQRQsToIrgrPJsrar4IrC4kn02dG4MEUixe0h p13Md78m1aE0OFm3kJCmTrBtHHFUFxSz4nPjviSzmJ+KK4MVJDs1+rK9ROcbqOvcjXFE x2GXGN7c1OLXdUbsMcMetUcP0X3rHRWEbV3k1frd/hLNz/vJ0g2En5fnhocWKEHfi+6t OdnQ== X-Gm-Message-State: AIVw110u826jRGUDQy4Tcff3dfG2Lw/r/N9bpDrL2Y4nNns56p2GGLeg CzlUzW1WXHRtJQ== X-Received: by 10.25.210.3 with SMTP id j3mr2108228lfg.86.1500761764188; Sat, 22 Jul 2017 15:16:04 -0700 (PDT) From: Aleksandr Bezzubikov To: qemu-devel@nongnu.org Date: Sun, 23 Jul 2017 01:15:41 +0300 Message-Id: <1500761743-1669-5-git-send-email-zuban32s@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500761743-1669-1-git-send-email-zuban32s@gmail.com> References: <1500761743-1669-1-git-send-email-zuban32s@gmail.com> X-Spam-Score: -4.5 (----) Subject: [SeaBIOS] [RFC PATCH v2 4/6] hw/pci: introduce bridge-only vendor-specific capability to provide some hints to firmware X-BeenThere: seabios@seabios.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: SeaBIOS mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mst@redhat.com, seabios@seabios.org, kraxel@redhat.com, pbonzini@redhat.com, marcel@redhat.com, rth@twiddle.net MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: seabios-bounces@seabios.org Sender: "SeaBIOS" X-Duff: Orig. Duff, Duff Lite, Duff Dry, Duff Dark, Raspberry Duff, Lady Duff, Red Duff, Tartar Control Duff X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" On PCI init PCI bridges may need some extra info about bus number to reserve, IO, memory and prefetchable memory limits. QEMU can provide this with special vendor-specific PCI capability. Sizes of limits match ones from PCI Type 1 Configuration Space Header, number of buses to reserve occupies only 1 byte=20 since it is the size of Subordinate Bus Number register. Signed-off-by: Aleksandr Bezzubikov --- hw/pci/pci_bridge.c | 27 +++++++++++++++++++++++++++ include/hw/pci/pci_bridge.h | 18 ++++++++++++++++++ 2 files changed, 45 insertions(+) diff --git a/hw/pci/pci_bridge.c b/hw/pci/pci_bridge.c index 720119b..8ec6c2c 100644 --- a/hw/pci/pci_bridge.c +++ b/hw/pci/pci_bridge.c @@ -408,6 +408,33 @@ void pci_bridge_map_irq(PCIBridge *br, const char* bus= _name, br->bus_name =3D bus_name; } =20 + +int pci_bridge_help_cap_init(PCIDevice *dev, int cap_offset, + uint8_t bus_reserve, uint32_t io_limit, + uint16_t mem_limit, uint64_t pref_limit, + Error **errp) +{ + size_t cap_len =3D sizeof(PCIBridgeQemuCap); + PCIBridgeQemuCap cap; + + cap.len =3D cap_len; + cap.bus_res =3D bus_reserve; + cap.io_lim =3D io_limit & 0xFF; + cap.io_lim_upper =3D io_limit >> 8 & 0xFFFF; + cap.mem_lim =3D mem_limit; + cap.pref_lim =3D pref_limit & 0xFFFF; + cap.pref_lim_upper =3D pref_limit >> 16 & 0xFFFFFFFF; + + int offset =3D pci_add_capability(dev, PCI_CAP_ID_VNDR, + cap_offset, cap_len, errp); + if (offset < 0) { + return offset; + } + + memcpy(dev->config + offset + 2, (char *)&cap + 2, cap_len - 2); + return 0; +} + static const TypeInfo pci_bridge_type_info =3D { .name =3D TYPE_PCI_BRIDGE, .parent =3D TYPE_PCI_DEVICE, diff --git a/include/hw/pci/pci_bridge.h b/include/hw/pci/pci_bridge.h index ff7cbaa..c9f642c 100644 --- a/include/hw/pci/pci_bridge.h +++ b/include/hw/pci/pci_bridge.h @@ -67,4 +67,22 @@ void pci_bridge_map_irq(PCIBridge *br, const char* bus_n= ame, #define PCI_BRIDGE_CTL_DISCARD_STATUS 0x400 /* Discard timer status */ #define PCI_BRIDGE_CTL_DISCARD_SERR 0x800 /* Discard timer SERR# enable */ =20 +typedef struct PCIBridgeQemuCap { + uint8_t id; /* Standard PCI capability header field */ + uint8_t next; /* Standard PCI capability header field */ + uint8_t len; /* Standard PCI vendor-specific capability header fiel= d */ + uint8_t bus_res; + uint32_t pref_lim_upper; + uint16_t pref_lim; + uint16_t mem_lim; + uint16_t io_lim_upper; + uint8_t io_lim; + uint8_t padding; +} PCIBridgeQemuCap; + +int pci_bridge_help_cap_init(PCIDevice *dev, int cap_offset, + uint8_t bus_reserve, uint32_t io_limit, + uint16_t mem_limit, uint64_t pref_limit, + Error **errp); + #endif /* QEMU_PCI_BRIDGE_H */ --=20 2.7.4 _______________________________________________ SeaBIOS mailing list SeaBIOS@seabios.org https://mail.coreboot.org/mailman/listinfo/seabios From nobody Sat May 4 22:45:36 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) client-ip=80.81.252.135; envelope-from=seabios-bounces@seabios.org; helo=mail.coreboot.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) smtp.mailfrom=seabios-bounces@seabios.org Return-Path: Received: from mail.coreboot.org (mail.coreboot.org [80.81.252.135]) by mx.zohomail.com with SMTPS id 150076180355754.670459834376175; Sat, 22 Jul 2017 15:16:43 -0700 (PDT) Received: from [127.0.0.1] (helo=ra.coresystems.de) by mail.coreboot.org with esmtp (Exim 4.86_2) (envelope-from ) id 1dZ2fE-0000FV-Pa; Sun, 23 Jul 2017 00:14:20 +0200 Received: from mail-lf0-f68.google.com ([209.85.215.68]) by mail.coreboot.org with esmtps (TLSv1.2:ECDHE-RSA-AES128-GCM-SHA256:128) (Exim 4.86_2) (envelope-from ) id 1dZ2f6-0000A4-CV for seabios@seabios.org; Sun, 23 Jul 2017 00:14:19 +0200 Received: by mail-lf0-f68.google.com with SMTP id t128so760769lff.3 for ; Sat, 22 Jul 2017 15:16:07 -0700 (PDT) Received: from localhost.localdomain (broadband-178-140-16-138.moscow.rt.ru. [178.140.16.138]) by smtp.gmail.com with ESMTPSA id t10sm757832lja.47.2017.07.22.15.16.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 22 Jul 2017 15:16:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=CmC0ZrzbdJ6lPaeasTTJvLBJ0ACZREUz5pMUAmIHDtg=; b=E7d/Flxr3VYf4kSKrTBtRuq9xLMQI7ZECmdXy1wHP4SBqgl8MwNxSwOXFlzQde2iga u3Z0G0fV9KBzNdDsW5ptIYXP4QrlJHOfpsRNDZlepHMUh4Vxou7gyhb16JjR0vQZKVVs StV26ZpSv9woKy1mjR0O9/tHxTFvSZ5eLsvg2g4IP+NVpbzJsp1mVSVnh0BqdwrvOpwB MEx+hGajaVoNW8fgvl01vW/SJuWG6EI172VkquI8jLjcdp1h7gKaWWVrsjU7EQWi/xZQ SMllf6BNiggvFafup7xJgBxU4QCfl+odP89HBpDHO/Xv+AUz7czxOAh5gu1H2D6U8aKN KqtQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=CmC0ZrzbdJ6lPaeasTTJvLBJ0ACZREUz5pMUAmIHDtg=; b=Apj17gDHgeFPDfxLWTlhSQbN0H+AH8zLU/oYLACWE0CAYVcQXDuKh5KYoXVvPE1+TD eKMTcq7vwGX3sHIww3a6/D5UnVaSnbP46ATTdLv3L/GWG/d5fIgw0SmAScpTH/UB6ECV VVWSUY1oSTy2lXrASkoB9pQLcecx/JNwV9sCSjNZ9Z1obmxxhZ4S91TQ7R6KwjXO9Fus /xZTm1a2qSCVsmwlndHov9Fr1fQN41gobhbd1kXgoKpQ8rKlRPlqu1WxhWSuxEdvyoiF Aj7Y2Xj1E4zjX2PEpbMpW0cPUihe/kFVdHB8uWyOsqEieV4rW5pAwvKhkdt/okkrCAHd 8KSQ== X-Gm-Message-State: AIVw1105ZA1IckImgIDUhkEf7wAb5tz5RjJPPQvvfSU4ZlmCHFLYk+s2 XinnARqOnDRw5A== X-Received: by 10.25.190.83 with SMTP id o80mr3204656lff.87.1500761765859; Sat, 22 Jul 2017 15:16:05 -0700 (PDT) From: Aleksandr Bezzubikov To: qemu-devel@nongnu.org Date: Sun, 23 Jul 2017 01:15:42 +0300 Message-Id: <1500761743-1669-6-git-send-email-zuban32s@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500761743-1669-1-git-send-email-zuban32s@gmail.com> References: <1500761743-1669-1-git-send-email-zuban32s@gmail.com> X-Spam-Score: -2.6 (--) Subject: [SeaBIOS] [RFC PATCH v2 5/6] hw/pci: add bus_reserve property to pcie-root-port X-BeenThere: seabios@seabios.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: SeaBIOS mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mst@redhat.com, seabios@seabios.org, kraxel@redhat.com, pbonzini@redhat.com, marcel@redhat.com, rth@twiddle.net MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: seabios-bounces@seabios.org Sender: "SeaBIOS" X-Duff: Orig. Duff, Duff Lite, Duff Dry, Duff Dark, Raspberry Duff, Lady Duff, Red Duff, Tartar Control Duff X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" To enable hotplugging of a newly created pcie-pci-bridge, we need to tell firmware (SeaBIOS in this case) to reserve additional buses for pcie-root-port, that allows us to=20 hotplug pcie-pci-bridge into this root port. The number of buses to reserve is provided to the device via a corresponding property, and to the firmware via new PCI capability (next patch). The property's default value is 1 as we want to hotplug at least 1 bridge. Signed-off-by: Aleksandr Bezzubikov --- hw/pci-bridge/pcie_root_port.c | 1 + include/hw/pci/pcie_port.h | 3 +++ 2 files changed, 4 insertions(+) diff --git a/hw/pci-bridge/pcie_root_port.c b/hw/pci-bridge/pcie_root_port.c index 4d588cb..b0e49e1 100644 --- a/hw/pci-bridge/pcie_root_port.c +++ b/hw/pci-bridge/pcie_root_port.c @@ -137,6 +137,7 @@ static void rp_exit(PCIDevice *d) static Property rp_props[] =3D { DEFINE_PROP_BIT(COMPAT_PROP_PCP, PCIDevice, cap_present, QEMU_PCIE_SLTCAP_PCP_BITNR, true), + DEFINE_PROP_UINT8("bus_reserve", PCIEPort, bus_reserve, 1), DEFINE_PROP_END_OF_LIST() }; =20 diff --git a/include/hw/pci/pcie_port.h b/include/hw/pci/pcie_port.h index 1333266..1b2dd1f 100644 --- a/include/hw/pci/pcie_port.h +++ b/include/hw/pci/pcie_port.h @@ -34,6 +34,9 @@ struct PCIEPort { =20 /* pci express switch port */ uint8_t port; + + /* additional buses to reserve on firmware init */ + uint8_t bus_reserve; }; =20 void pcie_port_init_reg(PCIDevice *d); --=20 2.7.4 _______________________________________________ SeaBIOS mailing list SeaBIOS@seabios.org https://mail.coreboot.org/mailman/listinfo/seabios From nobody Sat May 4 22:45:36 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) client-ip=80.81.252.135; envelope-from=seabios-bounces@seabios.org; helo=mail.coreboot.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) smtp.mailfrom=seabios-bounces@seabios.org Return-Path: Received: from mail.coreboot.org (mail.coreboot.org [80.81.252.135]) by mx.zohomail.com with SMTPS id 1500761795912669.3974494767627; Sat, 22 Jul 2017 15:16:35 -0700 (PDT) Received: from [127.0.0.1] (helo=ra.coresystems.de) by mail.coreboot.org with esmtp (Exim 4.86_2) (envelope-from ) id 1dZ2fC-0000Ej-4B; Sun, 23 Jul 2017 00:14:18 +0200 Received: from mail-lf0-f67.google.com ([209.85.215.67]) by mail.coreboot.org with esmtps (TLSv1.2:ECDHE-RSA-AES128-GCM-SHA256:128) (Exim 4.86_2) (envelope-from ) id 1dZ2f2-0000AI-PN for seabios@seabios.org; Sun, 23 Jul 2017 00:14:15 +0200 Received: by mail-lf0-f67.google.com with SMTP id t128so760781lff.3 for ; Sat, 22 Jul 2017 15:16:08 -0700 (PDT) Received: from localhost.localdomain (broadband-178-140-16-138.moscow.rt.ru. [178.140.16.138]) by smtp.gmail.com with ESMTPSA id t10sm757832lja.47.2017.07.22.15.16.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 22 Jul 2017 15:16:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=KSaFQzNV0QFdrzwoAK/epXxc95Td8lwlHfcY3kBhmBw=; b=N9Bf3z/6Q2XNPYtglk+kttwJqmkCAZuie1QSwxrmk+uoX6UnQINSVqZYkvNHjycPAz V0lLlrmwyLJ9H7W1vQV8+zksEEF3Rdqyo/MwXUGOw0K1n5tEeIz3Oduhjad4A4hGaZ0u bdxZDqlf6h2FTVPH9pwTbnsRu6S+q/E+MwZ/L/Jth93HTV7519puX10NBxdjyW915AfE Yjb7zoAH3Rs5IaGPCSTQWKCyzvBiNCQN5bfGAVoT49e435PEfql2jND9YD3Ia+cnItGi HAQbo+vNQU2gecBrq2c4CIde6wMsW3maxepwOaco/XJDtr6yj53xmcGMv8g6YddS73Q0 1GXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=KSaFQzNV0QFdrzwoAK/epXxc95Td8lwlHfcY3kBhmBw=; b=gZSXWQtAr3iRta3JWrF9kJVYe85jd7WPHxL5oIxRGxuOqphHL6NzsmWF3DwYnm3DWm wrkE36/CGjR3z+05Xz8VbTU+tveD1ThjAIxnh+3ypPrEpags2jwKv0k8E+uacfQy5/1w zH4GnG5vtbBm7O03OK799pS6K6zvbDrytO3eT4a/FF/GKH0yHv0+pToJ97hXFq9MGCDY l/P2ECpuD9/pxJWpCrR6dzzpHa2uD0oIzb1Jlk61u1l1cjX5NQSc/RuALOE0pdn894fz I2BtORblQ+5I0LYZTdxgnX2ACngZqD2Wx7uNlvKzFXkUlg8Le+UwUsmbaKCcaVrdnUkz wOeA== X-Gm-Message-State: AIVw110LuvGOWDI575FdUVHyRZT3jBhy5V2UkRYFIS4n9Mogthjr0Fgw sg4XK5RF+s6CLQ== X-Received: by 10.46.70.17 with SMTP id t17mr1391930lja.128.1500761767256; Sat, 22 Jul 2017 15:16:07 -0700 (PDT) From: Aleksandr Bezzubikov To: qemu-devel@nongnu.org Date: Sun, 23 Jul 2017 01:15:43 +0300 Message-Id: <1500761743-1669-7-git-send-email-zuban32s@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500761743-1669-1-git-send-email-zuban32s@gmail.com> References: <1500761743-1669-1-git-send-email-zuban32s@gmail.com> X-Spam-Score: -2.6 (--) Subject: [SeaBIOS] [RFC PATCH v2 6/6] hw/pci: add hint capabilty for additional bus reservation to pcie-root-port X-BeenThere: seabios@seabios.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: SeaBIOS mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mst@redhat.com, seabios@seabios.org, kraxel@redhat.com, pbonzini@redhat.com, marcel@redhat.com, rth@twiddle.net MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: seabios-bounces@seabios.org Sender: "SeaBIOS" X-Duff: Orig. Duff, Duff Lite, Duff Dry, Duff Dark, Raspberry Duff, Lady Duff, Red Duff, Tartar Control Duff X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Aleksandr Bezzubikov --- hw/pci-bridge/pcie_root_port.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/hw/pci-bridge/pcie_root_port.c b/hw/pci-bridge/pcie_root_port.c index b0e49e1..ca92d85 100644 --- a/hw/pci-bridge/pcie_root_port.c +++ b/hw/pci-bridge/pcie_root_port.c @@ -106,6 +106,11 @@ static void rp_realize(PCIDevice *d, Error **errp) pcie_aer_root_init(d); rp_aer_vector_update(d); =20 + rc =3D pci_bridge_help_cap_init(d, 0, p->bus_reserve, 0, 0, 0, errp); + if (rc < 0) { + goto err; + } + return; =20 err: --=20 2.7.4 _______________________________________________ SeaBIOS mailing list SeaBIOS@seabios.org https://mail.coreboot.org/mailman/listinfo/seabios