From nobody Mon Apr 29 08:23:41 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) client-ip=80.81.252.135; envelope-from=seabios-bounces@seabios.org; helo=mail.coreboot.org; Authentication-Results: mx.zoho.com; spf=none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) smtp.mailfrom=seabios-bounces@seabios.org; Return-Path: Received: from mail.coreboot.org (mail.coreboot.org [80.81.252.135]) by mx.zohomail.com with SMTPS id 1488557613958548.7756556919612; Fri, 3 Mar 2017 08:13:33 -0800 (PST) Received: from [127.0.0.1] (helo=ra.coresystems.de) by mail.coreboot.org with esmtp (Exim 4.86_2) (envelope-from ) id 1cjppY-0008MK-Lg; Fri, 03 Mar 2017 17:13:20 +0100 Received: from mail-qk0-f196.google.com ([209.85.220.196]) by mail.coreboot.org with esmtps (TLSv1.2:ECDHE-RSA-AES128-GCM-SHA256:128) (Exim 4.86_2) (envelope-from ) id 1cjppP-0008Lh-08 for seabios@seabios.org; Fri, 03 Mar 2017 17:13:18 +0100 Received: by mail-qk0-f196.google.com with SMTP id n127so28199792qkf.2 for ; Fri, 03 Mar 2017 08:13:10 -0800 (PST) Received: from localhost ([64.9.249.1]) by smtp.gmail.com with ESMTPSA id w41sm7876447qtw.34.2017.03.03.08.13.08 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 03 Mar 2017 08:13:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=koconnor-net.20150623.gappssmtp.com; s=20150623; h=from:to:subject:date:message-id; bh=R1FNZuNsoFQ19+KSosWBo0tIiK+1xMhLcym0A9xu94g=; b=tPnzn0gMzLplz7H1Fg7FPNx9wfm/ZJHPv7mRZA1UmVgPIj1tkwYDYE2XqqJIhex6K8 Ih8gCAwoTi+YhiXofKjwyeLBcN5HPlSUdMm8yKquEkY/3PJ9S4w5RfI8cIy1w0DppxOx daPqRECbGbQYft9be1hIaT7rn1dSpdHVvMrBF1nNKgND8vmCbcAko/Vj+sWvffSxzYkR y+azbVvUo3rhWXJlIV/pWpBbl/Y+zmxJlrhONGIsq3N7Yef939p5v+9xrYN7IkCvQ40G GdLWwfZSH/BA/K5dGYEgRHrzIontz5u0E5N9uA9IIzNg16pwZikqESe3O5QqZ6/UJEVD Wi6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id; bh=R1FNZuNsoFQ19+KSosWBo0tIiK+1xMhLcym0A9xu94g=; b=O0ivatQwOsiB0KHCXRTdhVj6rJFSIRrGNRyJ9ZSJLkYW0RHy+kyJE4n7kGqBjJr4DA Gl5p4pRIY5BN47PGSbTKYDtJWSPcd6FU27A9mF5l79AyF/gOgPECDECWdlYiBhf6i0kK XzKJEuP386V+nhts35bMIah8GSe1o2dK/KcU3mwoftanASr8/BA3RL8VQSpkR/K6BL/7 YYaAJQg8WnLKnNKMoDGIJmcLl5cOUVAKshthq33j6+CtR8jqTYTGNhXJUGYqItnJV5Od 4tEHmFZ4CW1bIpdZHQzYlEak8Tf4AJoLYiVIEZGjLN6TvCW0K+aWl1TNfAdCAvslMtXQ 7u1Q== X-Gm-Message-State: AMke39kehq0DNBikVqj49CsbrZTzNM5UlSv1xmnrtAoNH6otR/Ok/xhjZEFCxnVbhF0kNw== X-Received: by 10.237.41.7 with SMTP id s7mr3304974qtd.64.1488557588594; Fri, 03 Mar 2017 08:13:08 -0800 (PST) From: Kevin O'Connor To: seabios@seabios.org, Laszlo Ersek , Paolo Bonzini , kraxel@redhat.com, "Dr. David Alan Gilbert" Date: Fri, 3 Mar 2017 11:13:05 -0500 Message-Id: <1488557585-916-1-git-send-email-kevin@koconnor.net> X-Mailer: git-send-email 2.5.5 X-Spam-Score: -2.3 (--) Subject: [SeaBIOS] [PATCH] resume: Don't attempt to use generic reboot mechanisms on QEMU X-BeenThere: seabios@seabios.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: SeaBIOS mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: seabios-bounces@seabios.org Sender: "SeaBIOS" X-Duff: Orig. Duff, Duff Lite, Duff Dry, Duff Dark, Raspberry Duff, Lady Duff, Red Duff, Tartar Control Duff X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" On QEMU it's necessary to manually reset the BIOS memory region between 0xc0000-0x100000 on a reboot. After this manual memory reset is completed, it's not valid to use the generic reset mechanisms. Rename qemu_prep_reset() to qemu_reboot() and change the function to immediately reboot after the code memcpy. This fixes a bug that could cause code corruption on reboots - calling the udelay() function (as invoked by i8042_reboot and/or pci_reboot) was not valid after the BIOS was memcpy'd. Reported-by: "Dr. David Alan Gilbert" Signed-off-by: Kevin O'Connor Tested-by: Dr. David Alan Gilbert --- This patch is based on Paolo's recommendation of first attempting a PCI style reboot on QEMU. However, instead of next attempting a keyboard reset, this patch attempts to signal an "INIT" via a triple fault (as I think that's a bit simpler and less likely to fail). --- src/fw/shadow.c | 14 +++++++++++++- src/hw/pci.c | 1 - src/hw/pci.h | 2 ++ src/resume.c | 4 ++-- src/util.h | 2 +- 5 files changed, 18 insertions(+), 5 deletions(-) diff --git a/src/fw/shadow.c b/src/fw/shadow.c index cd02d3a..c80b266 100644 --- a/src/fw/shadow.c +++ b/src/fw/shadow.c @@ -167,7 +167,7 @@ make_bios_readonly(void) } =20 void -qemu_prep_reset(void) +qemu_reboot(void) { if (!CONFIG_QEMU || runningOnXen()) return; @@ -187,4 +187,16 @@ qemu_prep_reset(void) memcpy(hrp + 4, hrp + 4 + BIOS_SRC_OFFSET, cend - (hrp + 4)); barrier(); HaveRunPost =3D 0; + barrier(); + + // Request a QEMU system reset. Do the reset in this function as + // the BIOS code was overwritten above and not all BIOS + // functionality may be available. + + // Attempt PCI style reset + outb(0x02, PORT_PCI_REBOOT); + outb(0x06, PORT_PCI_REBOOT); + + // Next try triple faulting the CPU to force a reset + asm volatile("int3"); } diff --git a/src/hw/pci.c b/src/hw/pci.c index 506ee56..8e3d617 100644 --- a/src/hw/pci.c +++ b/src/hw/pci.c @@ -12,7 +12,6 @@ #include "x86.h" // outl =20 #define PORT_PCI_CMD 0x0cf8 -#define PORT_PCI_REBOOT 0x0cf9 #define PORT_PCI_DATA 0x0cfc =20 void pci_config_writel(u16 bdf, u32 addr, u32 val) diff --git a/src/hw/pci.h b/src/hw/pci.h index bf50430..ee6e196 100644 --- a/src/hw/pci.h +++ b/src/hw/pci.h @@ -3,6 +3,8 @@ =20 #include "types.h" // u32 =20 +#define PORT_PCI_REBOOT 0x0cf9 + static inline u8 pci_bdf_to_bus(u16 bdf) { return bdf >> 8; } diff --git a/src/resume.c b/src/resume.c index 99fa34f..fb0b8a8 100644 --- a/src/resume.c +++ b/src/resume.c @@ -125,8 +125,8 @@ tryReboot(void) { dprintf(1, "Attempting a hard reboot\n"); =20 - // Setup for reset on qemu. - qemu_prep_reset(); + // Use a QEMU specific reboot on QEMU + qemu_reboot(); =20 // Reboot using ACPI RESET_REG acpi_reboot(); diff --git a/src/util.h b/src/util.h index 336eaaf..8269057 100644 --- a/src/util.h +++ b/src/util.h @@ -123,7 +123,7 @@ void pirtable_setup(void); // fw/shadow.c void make_bios_writable(void); void make_bios_readonly(void); -void qemu_prep_reset(void); +void qemu_reboot(void); =20 // fw/smbios.c void smbios_legacy_setup(void); --=20 2.5.5 _______________________________________________ SeaBIOS mailing list SeaBIOS@seabios.org https://www.coreboot.org/mailman/listinfo/seabios