This patch adds a few unimplemented TZ devices (TZASC and CSU) to
i.MX6UL and i.MX7 processors to avoid bare metal application to
experiment "bus error" when acccessing these devices.

It also adds some internal memory segments (OCRAM) to the i.MX7 to
allow bare metal application to use them.

Last, it adds the SRC device to the i.MX7 processor to allow bare
metal application to start the secondary Cortex-A7 core.

Note: When running Linux inside Qemu, the secondary core is started
by calling PSCI API and Qemu is emulating PSCI without needing access
to the SRC device. This is why Linux is using the 2 cores in Qemu
even if the SRC is not implemented. This is not the case when running
bare metal application (like u-boot itself) that do not rely on the
PSCI service being available.

Changes since v3:
* Add a specific patch to remove IOMUXC GPR device from i.MX6UL
* remove unimplemented IOMUXC GPR device frome i.MX7D
* move the initialisation of PWM devices 5 to 8 to 3rd patch
* put the init of i.MX7d devices in previous order to ease review
* Remove device memory size from header file when the device is actually
  implemented in QEMU (the device implementation defines the memory
  size it manages).

Changes since v2:
* use GiB, MiB, KiB constant defined in qemu/units.h after code review

Changes since v1:
* split the i.MX6UL patch into a refactor patch and an addon patch.
* Split the i.MX7 patch into a refactor patch and an addon patch.
* Fix SRC code after few comments in code review.

Jean-Christophe Dubois (6):
  Remove i.MX7 IOMUX GPR device from i.MX6UL
  Refactor i.MX6UL processor code
  Add i.MX6UL missing devices.
  Refactor i.MX7 processor code
  Add i.MX7 missing TZ devices and memory regions
  Add i.MX7 SRC device implementation

 hw/arm/fsl-imx6ul.c         | 174 ++++++++++++-------
 hw/arm/fsl-imx7.c           | 201 +++++++++++++++++-----
 hw/misc/imx7_src.c          | 276 +++++++++++++++++++++++++++++
 hw/misc/meson.build         |   1 +
 hw/misc/trace-events        |   4 +
 include/hw/arm/fsl-imx6ul.h | 136 +++++++++++++--
 include/hw/arm/fsl-imx7.h   | 334 +++++++++++++++++++++++++++---------
 include/hw/misc/imx7_src.h  |  66 +++++++
 8 files changed, 995 insertions(+), 197 deletions(-)
 create mode 100644 hw/misc/imx7_src.c
 create mode 100644 include/hw/misc/imx7_src.h

-- 
2.34.1

On Fri, 25 Aug 2023 at 13:21, Jean-Christophe Dubois
<jcd@tribudubois.net> wrote:
>
> This patch adds a few unimplemented TZ devices (TZASC and CSU) to
> i.MX6UL and i.MX7 processors to avoid bare metal application to
> experiment "bus error" when acccessing these devices.
>
> It also adds some internal memory segments (OCRAM) to the i.MX7 to
> allow bare metal application to use them.
>
> Last, it adds the SRC device to the i.MX7 processor to allow bare
> metal application to start the secondary Cortex-A7 core.
>
> Note: When running Linux inside Qemu, the secondary core is started
> by calling PSCI API and Qemu is emulating PSCI without needing access
> to the SRC device. This is why Linux is using the 2 cores in Qemu
> even if the SRC is not implemented. This is not the case when running
> bare metal application (like u-boot itself) that do not rely on the
> PSCI service being available.



Applied to target-arm.next, thanks.

-- PMM