risc-v: Add ISA extension smcntrpmf support

[PATCH 0/3] risc-v: Add ISA extension smcntrpmf support

Kaiwen Xue posted 3 patches 9 months, 2 weeks ago

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Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/cover.1689631639.git.kaiwenx@rivosinc.com

Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Bin Meng <bin.meng@windriver.com>, Weiwei Li <liweiwei@iscas.ac.cn>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>

target/riscv/cpu.c      |  2 ++
target/riscv/cpu.h      |  6 ++++
target/riscv/cpu_bits.h | 29 ++++++++++++++++
target/riscv/cpu_cfg.h  |  1 +
target/riscv/csr.c      | 73 +++++++++++++++++++++++++++++++++++++++++
5 files changed, 111 insertions(+)

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[PATCH 0/3] risc-v: Add ISA extension smcntrpmf support

Posted by Kaiwen Xue 9 months, 2 weeks ago

This patch series adds the support for RISC-V ISA extension smcntrpmf (cycle and
privilege mode filtering) [1]. QEMU only calculates dummy cycles and
instructions, so there is no actual means to stop the icount in QEMU. Therefore,
this series only add the read/write behavior of the relevant CSRs such that the
implemented firmware support [2] can work without causing unnecessary illegal
instruction exceptions.

[1] https://github.com/riscv/riscv-smcntrpmf
[2] https://github.com/rivosinc/opensbi/tree/dev/kaiwenx/smcntrpmf_upstream

Kaiwen Xue (3):
  target/riscv: Add cycle & instret privilege mode filtering properties
  target/riscv: Add cycle & instret privilege mode filtering definitions
  target/riscv: Add cycle & instret privilege mode filtering support

 target/riscv/cpu.c      |  2 ++
 target/riscv/cpu.h      |  6 ++++
 target/riscv/cpu_bits.h | 29 ++++++++++++++++
 target/riscv/cpu_cfg.h  |  1 +
 target/riscv/csr.c      | 73 +++++++++++++++++++++++++++++++++++++++++
 5 files changed, 111 insertions(+)

-- 
2.34.1