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charset="utf-8" From: Yifei Jiang mstatus/mstatush and vsstatus/vsstatush are two halved for RISCV32. This patch expands mstatus and vsstatus to uint64_t instead of target_ulong so that it can be saved as one unit and reduce some ifdefs in the code. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin Signed-off-by: Alistair Francis Reviewed-by: Alistair Francis Message-id: 20201026115530.304-2-jiangyifei@huawei.com Reviewed-by: Richard Henderson --- target/riscv/cpu.h | 24 +++++++++++------------- target/riscv/cpu_bits.h | 19 ++++--------------- target/riscv/cpu.c | 8 +++++--- target/riscv/cpu_helper.c | 35 +++++++---------------------------- target/riscv/csr.c | 18 ++++++++++-------- target/riscv/op_helper.c | 11 ++++------- 6 files changed, 41 insertions(+), 74 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index de4705bb57..87b68affa8 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -144,14 +144,14 @@ struct CPURISCVState { target_ulong resetvec; =20 target_ulong mhartid; - target_ulong mstatus; + /* + * For RV32 this is 32-bit mstatus and 32-bit mstatush. + * For RV64 this is a 64-bit mstatus. + */ + uint64_t mstatus; =20 target_ulong mip; =20 -#ifdef TARGET_RISCV32 - target_ulong mstatush; -#endif - uint32_t miclaim; =20 target_ulong mie; @@ -183,16 +183,17 @@ struct CPURISCVState { uint64_t htimedelta; =20 /* Virtual CSRs */ - target_ulong vsstatus; + /* + * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. + * For RV64 this is a 64-bit vsstatus. + */ + uint64_t vsstatus; target_ulong vstvec; target_ulong vsscratch; target_ulong vsepc; target_ulong vscause; target_ulong vstval; target_ulong vsatp; -#ifdef TARGET_RISCV32 - target_ulong vsstatush; -#endif =20 target_ulong mtval2; target_ulong mtinst; @@ -204,10 +205,7 @@ struct CPURISCVState { target_ulong scause_hs; target_ulong stval_hs; target_ulong satp_hs; - target_ulong mstatus_hs; -#ifdef TARGET_RISCV32 - target_ulong mstatush_hs; -#endif + uint64_t mstatus_hs; =20 target_ulong scounteren; target_ulong mcounteren; diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index bd36062877..daedad8691 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -4,10 +4,10 @@ #define TARGET_RISCV_CPU_BITS_H =20 #define get_field(reg, mask) (((reg) & \ - (target_ulong)(mask)) / ((mask) & ~((mask) << 1))) -#define set_field(reg, mask, val) (((reg) & ~(target_ulong)(mask)) | \ - (((target_ulong)(val) * ((mask) & ~((mask) << 1))) & \ - (target_ulong)(mask))) + (uint64_t)(mask)) / ((mask) & ~((mask) << 1))) +#define set_field(reg, mask, val) (((reg) & ~(uint64_t)(mask)) | \ + (((uint64_t)(val) * ((mask) & ~((mask) << 1))) & \ + (uint64_t)(mask))) =20 /* Floating point round mode */ #define FSR_RD_SHIFT 5 @@ -381,19 +381,8 @@ #define MSTATUS_TVM 0x00100000 /* since: priv-1.10 */ #define MSTATUS_TW 0x20000000 /* since: priv-1.10 */ #define MSTATUS_TSR 0x40000000 /* since: priv-1.10 */ -#if defined(TARGET_RISCV64) #define MSTATUS_GVA 0x4000000000ULL #define MSTATUS_MPV 0x8000000000ULL -#elif defined(TARGET_RISCV32) -#define MSTATUS_GVA 0x00000040 -#define MSTATUS_MPV 0x00000080 -#endif - -#ifdef TARGET_RISCV32 -# define MSTATUS_MPV_ISSET(env) get_field(env->mstatush, MSTATUS_MPV) -#else -# define MSTATUS_MPV_ISSET(env) get_field(env->mstatus, MSTATUS_MPV) -#endif =20 #define MSTATUS64_UXL 0x0000000300000000ULL #define MSTATUS64_SXL 0x0000000C00000000ULL diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0bbfd7f457..dd05a220c7 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -216,13 +216,15 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *= f, int flags) qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); #ifndef CONFIG_USER_ONLY qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", env->mstatus); + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", (target_ulong)e= nv->mstatus); #ifdef TARGET_RISCV32 - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ", env->mstatush); + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ", + (target_ulong)(env->mstatus >> 32)); #endif if (riscv_has_ext(env, RVH)) { qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatu= s); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus ", env->vssta= tus); + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus ", + (target_ulong)env->vsstatus); } qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip ", env->mip); qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie ", env->mie); diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 4652082df1..3eb3a034db 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -110,27 +110,19 @@ bool riscv_cpu_fp_enabled(CPURISCVState *env) =20 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) { - target_ulong mstatus_mask =3D MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS | - MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE; + uint64_t mstatus_mask =3D MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS | + MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE | + MSTATUS64_UXL; bool current_virt =3D riscv_cpu_virt_enabled(env); =20 g_assert(riscv_has_ext(env, RVH)); =20 -#if defined(TARGET_RISCV64) - mstatus_mask |=3D MSTATUS64_UXL; -#endif - if (current_virt) { /* Current V=3D1 and we are about to change to V=3D0 */ env->vsstatus =3D env->mstatus & mstatus_mask; env->mstatus &=3D ~mstatus_mask; env->mstatus |=3D env->mstatus_hs; =20 -#if defined(TARGET_RISCV32) - env->vsstatush =3D env->mstatush; - env->mstatush |=3D env->mstatush_hs; -#endif - env->vstvec =3D env->stvec; env->stvec =3D env->stvec_hs; =20 @@ -154,11 +146,6 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) env->mstatus &=3D ~mstatus_mask; env->mstatus |=3D env->vsstatus; =20 -#if defined(TARGET_RISCV32) - env->mstatush_hs =3D env->mstatush; - env->mstatush |=3D env->vsstatush; -#endif - env->stvec_hs =3D env->stvec; env->stvec =3D env->vstvec; =20 @@ -727,7 +714,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, if (riscv_has_ext(env, RVH) && env->priv =3D=3D PRV_M && access_type !=3D MMU_INST_FETCH && get_field(env->mstatus, MSTATUS_MPRV) && - MSTATUS_MPV_ISSET(env)) { + get_field(env->mstatus, MSTATUS_MPV)) { riscv_cpu_set_two_stage_lookup(env, true); } =20 @@ -799,7 +786,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, if (riscv_has_ext(env, RVH) && env->priv =3D=3D PRV_M && access_type !=3D MMU_INST_FETCH && get_field(env->mstatus, MSTATUS_MPRV) && - MSTATUS_MPV_ISSET(env)) { + get_field(env->mstatus, MSTATUS_MPV)) { riscv_cpu_set_two_stage_lookup(env, false); } =20 @@ -862,7 +849,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; bool force_hs_execp =3D riscv_cpu_force_hs_excep_enabled(env); - target_ulong s; + uint64_t s; =20 /* cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide * so we mask off the MSB and separate into trap type and cause. @@ -995,19 +982,11 @@ void riscv_cpu_do_interrupt(CPUState *cs) if (riscv_cpu_virt_enabled(env)) { riscv_cpu_swap_hypervisor_regs(env); } -#ifdef TARGET_RISCV32 - env->mstatush =3D set_field(env->mstatush, MSTATUS_MPV, - riscv_cpu_virt_enabled(env)); - if (riscv_cpu_virt_enabled(env) && tval) { - env->mstatush =3D set_field(env->mstatush, MSTATUS_GVA, 1); - } -#else env->mstatus =3D set_field(env->mstatus, MSTATUS_MPV, - riscv_cpu_virt_enabled(env)); + riscv_cpu_virt_enabled(env)); if (riscv_cpu_virt_enabled(env) && tval) { env->mstatus =3D set_field(env->mstatus, MSTATUS_GVA, 1); } -#endif =20 mtval2 =3D env->guest_phys_fault_addr; =20 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index aaef6c6f20..e33f6cdc11 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -446,8 +446,8 @@ static int validate_vm(CPURISCVState *env, target_ulong= vm) =20 static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val) { - target_ulong mstatus =3D env->mstatus; - target_ulong mask =3D 0; + uint64_t mstatus =3D env->mstatus; + uint64_t mask =3D 0; int dirty; =20 /* flush tlb on mstatus fields that affect VM */ @@ -480,19 +480,20 @@ static int write_mstatus(CPURISCVState *env, int csrn= o, target_ulong val) #ifdef TARGET_RISCV32 static int read_mstatush(CPURISCVState *env, int csrno, target_ulong *val) { - *val =3D env->mstatush; + *val =3D env->mstatus >> 32; return 0; } =20 static int write_mstatush(CPURISCVState *env, int csrno, target_ulong val) { - if ((val ^ env->mstatush) & (MSTATUS_MPV)) { + uint64_t valh =3D (uint64_t)val << 32; + uint64_t mask =3D MSTATUS_MPV | MSTATUS_GVA; + + if ((valh ^ env->mstatus) & (MSTATUS_MPV)) { tlb_flush(env_cpu(env)); } =20 - val &=3D MSTATUS_MPV | MSTATUS_GVA; - - env->mstatush =3D val; + env->mstatus =3D (env->mstatus & ~mask) | (valh & mask); =20 return 0; } @@ -1105,7 +1106,8 @@ static int read_vsstatus(CPURISCVState *env, int csrn= o, target_ulong *val) =20 static int write_vsstatus(CPURISCVState *env, int csrno, target_ulong val) { - env->vsstatus =3D val; + uint64_t mask =3D (target_ulong)-1; + env->vsstatus =3D (env->vsstatus & ~mask) | (uint64_t)val; return 0; } =20 diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 4ce73575a7..e20d56dcb8 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -78,7 +78,8 @@ target_ulong helper_csrrc(CPURISCVState *env, target_ulon= g src, =20 target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb) { - target_ulong prev_priv, prev_virt, mstatus; + uint64_t mstatus; + target_ulong prev_priv, prev_virt; =20 if (!(env->priv >=3D PRV_S)) { riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); @@ -147,18 +148,14 @@ target_ulong helper_mret(CPURISCVState *env, target_u= long cpu_pc_deb) riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC()); } =20 - target_ulong mstatus =3D env->mstatus; + uint64_t mstatus =3D env->mstatus; target_ulong prev_priv =3D get_field(mstatus, MSTATUS_MPP); - target_ulong prev_virt =3D MSTATUS_MPV_ISSET(env); + target_ulong prev_virt =3D get_field(env->mstatus, MSTATUS_MPV); mstatus =3D set_field(mstatus, MSTATUS_MIE, get_field(mstatus, MSTATUS_MPIE)); mstatus =3D set_field(mstatus, MSTATUS_MPIE, 1); mstatus =3D set_field(mstatus, MSTATUS_MPP, PRV_U); -#ifdef TARGET_RISCV32 - env->mstatush =3D set_field(env->mstatush, MSTATUS_MPV, 0); -#else mstatus =3D set_field(mstatus, MSTATUS_MPV, 0); -#endif env->mstatus =3D mstatus; riscv_cpu_set_mode(env, prev_priv); =20 --=20 2.28.0 From nobody Sun May 19 16:58:43 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Add a new MMU mode that includes the current virt mode. Signed-off-by: Alistair Francis --- target/riscv/cpu-param.h | 10 +++++++++- target/riscv/cpu.h | 4 +++- target/riscv/cpu_helper.c | 6 +++++- 3 files changed, 17 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu-param.h b/target/riscv/cpu-param.h index 664fc1d371..0db6e23140 100644 --- a/target/riscv/cpu-param.h +++ b/target/riscv/cpu-param.h @@ -18,6 +18,14 @@ # define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */ #endif #define TARGET_PAGE_BITS 12 /* 4 KiB Pages */ -#define NB_MMU_MODES 4 +/* + * The current MMU Modes are: + * - U mode 0b000 + * - S mode 0b001 + * - M mode 0b011 + * - HU mode 0b100 + * - HS mode 0b101 + */ +#define NB_MMU_MODES 6 =20 #endif diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 87b68affa8..5d8e54c426 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -363,7 +363,9 @@ void QEMU_NORETURN riscv_raise_exception(CPURISCVState = *env, target_ulong riscv_cpu_get_fflags(CPURISCVState *env); void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); =20 -#define TB_FLAGS_MMU_MASK 3 +#define TB_FLAGS_MMU_MASK 7 +#define TB_FLAGS_PRIV_MMU_MASK 3 +#define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2) #define TB_FLAGS_MSTATUS_FS MSTATUS_FS =20 typedef CPURISCVState CPUArchState; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 3eb3a034db..453e4c6d8a 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -30,6 +30,10 @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) #ifdef CONFIG_USER_ONLY return 0; #else + if (riscv_cpu_virt_enabled(env)) { + return env->priv | TB_FLAGS_PRIV_HYP_ACCESS_MASK; + } + return env->priv; #endif } @@ -323,7 +327,7 @@ static int get_physical_address(CPURISCVState *env, hwa= ddr *physical, * (riscv_cpu_do_interrupt) is correct */ MemTxResult res; MemTxAttrs attrs =3D MEMTXATTRS_UNSPECIFIED; - int mode =3D mmu_idx; + int mode =3D mmu_idx & TB_FLAGS_PRIV_MMU_MASK; bool use_background =3D false; =20 /* --=20 2.28.0 From nobody Sun May 19 16:58:43 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" When performing the hypervisor load/store operations set the MMU mode to indicate that we are virtualised. Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/op_helper.c | 30 +++++++++++++++++------------- 1 file changed, 17 insertions(+), 13 deletions(-) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index e20d56dcb8..548c5851ec 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -235,30 +235,31 @@ target_ulong helper_hyp_load(CPURISCVState *env, targ= et_ulong address, (env->priv =3D=3D PRV_U && !riscv_cpu_virt_enabled(env) && get_field(env->hstatus, HSTATUS_HU))) { target_ulong pte; + int mmu_idx =3D cpu_mmu_index(env, false) | TB_FLAGS_PRIV_HYP_ACCE= SS_MASK; =20 riscv_cpu_set_two_stage_lookup(env, true); =20 switch (memop) { case MO_SB: - pte =3D cpu_ldsb_data_ra(env, address, GETPC()); + pte =3D cpu_ldsb_mmuidx_ra(env, address, mmu_idx, GETPC()); break; case MO_UB: - pte =3D cpu_ldub_data_ra(env, address, GETPC()); + pte =3D cpu_ldub_mmuidx_ra(env, address, mmu_idx, GETPC()); break; case MO_TESW: - pte =3D cpu_ldsw_data_ra(env, address, GETPC()); + pte =3D cpu_ldsw_mmuidx_ra(env, address, mmu_idx, GETPC()); break; case MO_TEUW: - pte =3D cpu_lduw_data_ra(env, address, GETPC()); + pte =3D cpu_lduw_mmuidx_ra(env, address, mmu_idx, GETPC()); break; case MO_TESL: - pte =3D cpu_ldl_data_ra(env, address, GETPC()); + pte =3D cpu_ldl_mmuidx_ra(env, address, mmu_idx, GETPC()); break; case MO_TEUL: - pte =3D cpu_ldl_data_ra(env, address, GETPC()); + pte =3D cpu_ldl_mmuidx_ra(env, address, mmu_idx, GETPC()); break; case MO_TEQ: - pte =3D cpu_ldq_data_ra(env, address, GETPC()); + pte =3D cpu_ldq_mmuidx_ra(env, address, mmu_idx, GETPC()); break; default: g_assert_not_reached(); @@ -284,23 +285,25 @@ void helper_hyp_store(CPURISCVState *env, target_ulon= g address, (env->priv =3D=3D PRV_S && !riscv_cpu_virt_enabled(env)) || (env->priv =3D=3D PRV_U && !riscv_cpu_virt_enabled(env) && get_field(env->hstatus, HSTATUS_HU))) { + int mmu_idx =3D cpu_mmu_index(env, false) | TB_FLAGS_PRIV_HYP_ACCE= SS_MASK; + riscv_cpu_set_two_stage_lookup(env, true); =20 switch (memop) { case MO_SB: case MO_UB: - cpu_stb_data_ra(env, address, val, GETPC()); + cpu_stb_mmuidx_ra(env, address, val, mmu_idx, GETPC()); break; case MO_TESW: case MO_TEUW: - cpu_stw_data_ra(env, address, val, GETPC()); + cpu_stw_mmuidx_ra(env, address, val, mmu_idx, GETPC()); break; case MO_TESL: case MO_TEUL: - cpu_stl_data_ra(env, address, val, GETPC()); + cpu_stl_mmuidx_ra(env, address, val, mmu_idx, GETPC()); break; case MO_TEQ: - cpu_stq_data_ra(env, address, val, GETPC()); + cpu_stq_mmuidx_ra(env, address, val, mmu_idx, GETPC()); break; default: g_assert_not_reached(); @@ -326,15 +329,16 @@ target_ulong helper_hyp_x_load(CPURISCVState *env, ta= rget_ulong address, (env->priv =3D=3D PRV_U && !riscv_cpu_virt_enabled(env) && get_field(env->hstatus, HSTATUS_HU))) { target_ulong pte; + int mmu_idx =3D cpu_mmu_index(env, false) | TB_FLAGS_PRIV_HYP_ACCE= SS_MASK; =20 riscv_cpu_set_two_stage_lookup(env, true); =20 switch (memop) { case MO_TEUW: - pte =3D cpu_lduw_data_ra(env, address, GETPC()); + pte =3D cpu_lduw_mmuidx_ra(env, address, mmu_idx, GETPC()); break; case MO_TEUL: - pte =3D cpu_ldl_data_ra(env, address, GETPC()); + pte =3D cpu_ldl_mmuidx_ra(env, address, mmu_idx, GETPC()); break; default: g_assert_not_reached(); --=20 2.28.0 From nobody Sun May 19 16:58:43 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1604434007; cv=none; d=zohomail.com; s=zohoarc; b=IRVO+ozf42yIwbibj4LmcBUS2xwcrYtk9iaJokJ5LdpNmnU22012bot2CwVmF/KDBKk769QAU1/l6cy8HqfiZM8uza0jsB+QFLYkZ+U+yVm6hxwy7i/7Up8yBWItIBe/jc5weeGx2xKjRiXl7JH0yaiPGmno7S210oYqjSlOXUU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1604434007; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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IronPort-SDR: ss/RoGQ0IksMXT9BrYQse30sG8qwMCMyolgJrs12+94naT5BXR6VhjQEyM2a4Ww93EGSrbunDQ vVXiLJZbFCInVsuhEY2mN6V3dW0m47h/3ag3h0Tr7efO9S5FaeALQZK2c0d0g88UbIYGZnQ3Cj VB7pXTg+zvVQWdKO3HEmLBuvpaI0UwMk8x8MQXAV8JyT+/ukfJXKepIDsGwdl6jkEgSO9E2ms/ 3TxvenGjpKUH4hDhmT6dtbe83agGWLA986t6nYvjHil0u4jO01WiEt3zd3nUmBeketPSl/za/S KHg= X-IronPort-AV: E=Sophos;i="5.77,448,1596470400"; d="scan'208";a="151793192" IronPort-SDR: c8jcz1KkRZYsHSuLDhJf+v2F09+/Mx1cGmZGdy9iiwf5AvQEGeOujeMEBeKrX/GuUecQ+hAIJc hhndHKVbcdUF4OVOlKCfzSMHG4WAes05HCqwywPNMGlZCBI528e4mYyeffuGq04ur6P+egy2Ed YYXMqMQ1LgZKHiNal+quTm9rixQWK2kQvUnANprVBwgu3yQmN0vJjZ8VlQPpsPL/xhNic4JuNb ciU0+yonRxmxqvkEi9EMmk7kk3QRxFSvcG64gDZRFhN0dT3XcbuH5YgWdLc7hrNQDvF3VoDKhl M3wHIfrapek9TCZAKzjyInEj IronPort-SDR: AmIoc+3ASJZQKwtRCAbKE5vvULFnd7vow3E3nprgY3UeJnJdb6zbMSl5tt9tPrydUOxwdoHNx+ eSCJU7GKLYiqWjX2fBFQvcNkn3uEduyRegCcIioipLFWSAieGVcwtYM4xPN8Lc+eMzEbe0ATNU 79Lojt0PqkwV2HREEvrDOQh0Z4iAfjmy2OXRawPYF0/T2R5OM9ExqxnkpMKb1tS5hbA76gKAHQ hIHLhrH+3EnckXec2iZEeoaqAtoaEMR5mi0t8i3Z+hI3brapAmauJ7zObZ9tEBp++7rpBIHtJS Xy4= WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 4/7] target/riscv: Remove the HS_TWO_STAGE flag Date: Tue, 3 Nov 2020 11:51:03 -0800 Message-Id: <0f672ebbc70670711ef0d8dcf8fe51d39cbf2095.1604432950.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" The HS_TWO_STAGE flag is no longer required as the MMU index contains the information if we are performing a two stage access. Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/cpu.h | 3 +- target/riscv/cpu_bits.h | 1 - target/riscv/cpu_helper.c | 60 ++++++++++++++++----------------------- target/riscv/op_helper.c | 12 -------- 4 files changed, 25 insertions(+), 51 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 5d8e54c426..0cf48a1521 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -323,8 +323,7 @@ bool riscv_cpu_virt_enabled(CPURISCVState *env); void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env); void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable); -bool riscv_cpu_two_stage_lookup(CPURISCVState *env); -void riscv_cpu_set_two_stage_lookup(CPURISCVState *env, bool enable); +bool riscv_cpu_two_stage_lookup(int mmu_idx); int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index daedad8691..24b24c69c5 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -469,7 +469,6 @@ * page table fault. */ #define FORCE_HS_EXCEP 2 -#define HS_TWO_STAGE 4 =20 /* RV32 satp CSR field masks */ #define SATP32_MODE 0x80000000 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 453e4c6d8a..dd891264c2 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -211,22 +211,9 @@ void riscv_cpu_set_force_hs_excep(CPURISCVState *env, = bool enable) env->virt =3D set_field(env->virt, FORCE_HS_EXCEP, enable); } =20 -bool riscv_cpu_two_stage_lookup(CPURISCVState *env) +bool riscv_cpu_two_stage_lookup(int mmu_idx) { - if (!riscv_has_ext(env, RVH)) { - return false; - } - - return get_field(env->virt, HS_TWO_STAGE); -} - -void riscv_cpu_set_two_stage_lookup(CPURISCVState *env, bool enable) -{ - if (!riscv_has_ext(env, RVH)) { - return; - } - - env->virt =3D set_field(env->virt, HS_TWO_STAGE, enable); + return mmu_idx & TB_FLAGS_PRIV_HYP_ACCESS_MASK; } =20 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts) @@ -337,7 +324,7 @@ static int get_physical_address(CPURISCVState *env, hwa= ddr *physical, * was called. Background registers will be used if the guest has * forced a two stage translation to be on (in HS or M mode). */ - if (riscv_cpu_two_stage_lookup(env) && access_type !=3D MMU_INST_FETCH= ) { + if (!riscv_cpu_virt_enabled(env) && riscv_cpu_two_stage_lookup(mmu_idx= )) { use_background =3D true; } =20 @@ -576,7 +563,7 @@ restart: =20 static void raise_mmu_exception(CPURISCVState *env, target_ulong address, MMUAccessType access_type, bool pmp_violat= ion, - bool first_stage) + bool first_stage, bool two_stage) { CPUState *cs =3D env_cpu(env); int page_fault_exceptions; @@ -599,8 +586,7 @@ static void raise_mmu_exception(CPURISCVState *env, tar= get_ulong address, } break; case MMU_DATA_LOAD: - if ((riscv_cpu_virt_enabled(env) || riscv_cpu_two_stage_lookup(env= )) && - !first_stage) { + if (two_stage && !first_stage) { cs->exception_index =3D RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT; } else { cs->exception_index =3D page_fault_exceptions ? @@ -608,8 +594,7 @@ static void raise_mmu_exception(CPURISCVState *env, tar= get_ulong address, } break; case MMU_DATA_STORE: - if ((riscv_cpu_virt_enabled(env) || riscv_cpu_two_stage_lookup(env= )) && - !first_stage) { + if (two_stage && !first_stage) { cs->exception_index =3D RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAUL= T; } else { cs->exception_index =3D page_fault_exceptions ? @@ -700,6 +685,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, int prot, prot2; bool pmp_violation =3D false; bool first_stage_error =3D true; + bool two_stage_lookup =3D false; int ret =3D TRANSLATE_FAIL; int mode =3D mmu_idx; target_ulong tlb_size =3D 0; @@ -719,11 +705,12 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, access_type !=3D MMU_INST_FETCH && get_field(env->mstatus, MSTATUS_MPRV) && get_field(env->mstatus, MSTATUS_MPV)) { - riscv_cpu_set_two_stage_lookup(env, true); + two_stage_lookup =3D true; } =20 if (riscv_cpu_virt_enabled(env) || - (riscv_cpu_two_stage_lookup(env) && access_type !=3D MMU_INST_FETC= H)) { + ((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) && + access_type !=3D MMU_INST_FETCH)) { /* Two stage lookup */ ret =3D get_physical_address(env, &pa, &prot, address, &env->guest_phys_fault_addr, access_typ= e, @@ -786,14 +773,6 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, __func__, address, ret, pa, prot); } =20 - /* We did the two stage lookup based on MPRV, unset the lookup */ - if (riscv_has_ext(env, RVH) && env->priv =3D=3D PRV_M && - access_type !=3D MMU_INST_FETCH && - get_field(env->mstatus, MSTATUS_MPRV) && - get_field(env->mstatus, MSTATUS_MPV)) { - riscv_cpu_set_two_stage_lookup(env, false); - } - if (riscv_feature(env, RISCV_FEATURE_PMP) && (ret =3D=3D TRANSLATE_SUCCESS) && !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) { @@ -815,7 +794,10 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, } else if (probe) { return false; } else { - raise_mmu_exception(env, address, access_type, pmp_violation, firs= t_stage_error); + raise_mmu_exception(env, address, access_type, pmp_violation, + first_stage_error, + riscv_cpu_virt_enabled(env) || + riscv_cpu_two_stage_lookup(mmu_idx)); riscv_raise_exception(env, cs->exception_index, retaddr); } =20 @@ -919,9 +901,16 @@ void riscv_cpu_do_interrupt(CPUState *cs) /* handle the trap in S-mode */ if (riscv_has_ext(env, RVH)) { target_ulong hdeleg =3D async ? env->hideleg : env->hedeleg; + bool two_stage_lookup =3D false; + + if (env->priv =3D=3D PRV_M || + (env->priv =3D=3D PRV_S && !riscv_cpu_virt_enabled(env)) || + (env->priv =3D=3D PRV_U && !riscv_cpu_virt_enabled(env) && + get_field(env->hstatus, HSTATUS_HU))) { + two_stage_lookup =3D true; + } =20 - if ((riscv_cpu_virt_enabled(env) || - riscv_cpu_two_stage_lookup(env)) && write_tval) { + if ((riscv_cpu_virt_enabled(env) || two_stage_lookup) && write= _tval) { /* * If we are writing a guest virtual address to stval, set * this to 1. If we are trapping to VS we will set this to= 0 @@ -959,11 +948,10 @@ void riscv_cpu_do_interrupt(CPUState *cs) riscv_cpu_set_force_hs_excep(env, 0); } else { /* Trap into HS mode */ - if (!riscv_cpu_two_stage_lookup(env)) { + if (!two_stage_lookup) { env->hstatus =3D set_field(env->hstatus, HSTATUS_SPV, riscv_cpu_virt_enabled(env)); } - riscv_cpu_set_two_stage_lookup(env, false); htval =3D env->guest_phys_fault_addr; } } diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 548c5851ec..5759850e69 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -237,8 +237,6 @@ target_ulong helper_hyp_load(CPURISCVState *env, target= _ulong address, target_ulong pte; int mmu_idx =3D cpu_mmu_index(env, false) | TB_FLAGS_PRIV_HYP_ACCE= SS_MASK; =20 - riscv_cpu_set_two_stage_lookup(env, true); - switch (memop) { case MO_SB: pte =3D cpu_ldsb_mmuidx_ra(env, address, mmu_idx, GETPC()); @@ -265,8 +263,6 @@ target_ulong helper_hyp_load(CPURISCVState *env, target= _ulong address, g_assert_not_reached(); } =20 - riscv_cpu_set_two_stage_lookup(env, false); - return pte; } =20 @@ -287,8 +283,6 @@ void helper_hyp_store(CPURISCVState *env, target_ulong = address, get_field(env->hstatus, HSTATUS_HU))) { int mmu_idx =3D cpu_mmu_index(env, false) | TB_FLAGS_PRIV_HYP_ACCE= SS_MASK; =20 - riscv_cpu_set_two_stage_lookup(env, true); - switch (memop) { case MO_SB: case MO_UB: @@ -309,8 +303,6 @@ void helper_hyp_store(CPURISCVState *env, target_ulong = address, g_assert_not_reached(); } =20 - riscv_cpu_set_two_stage_lookup(env, false); - return; } =20 @@ -331,8 +323,6 @@ target_ulong helper_hyp_x_load(CPURISCVState *env, targ= et_ulong address, target_ulong pte; int mmu_idx =3D cpu_mmu_index(env, false) | TB_FLAGS_PRIV_HYP_ACCE= SS_MASK; =20 - riscv_cpu_set_two_stage_lookup(env, true); - switch (memop) { case MO_TEUW: pte =3D cpu_lduw_mmuidx_ra(env, address, mmu_idx, GETPC()); @@ -344,8 +334,6 @@ target_ulong helper_hyp_x_load(CPURISCVState *env, targ= et_ulong address, g_assert_not_reached(); } =20 - riscv_cpu_set_two_stage_lookup(env, false); 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charset="utf-8" Remove the special Virtulisation load and store functions and just use the standard tcg tcg_gen_qemu_ld_tl() and tcg_gen_qemu_st_tl() functions instead. As part of this change we ensure we still run an access check to make sure we can perform the operations. Signed-off-by: Alistair Francis --- target/riscv/helper.h | 3 +- target/riscv/op_helper.c | 72 +-------------- target/riscv/insn_trans/trans_rvh.c.inc | 111 +++++++----------------- 3 files changed, 35 insertions(+), 151 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 4b690147fb..7dbdd117d2 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -81,8 +81,7 @@ DEF_HELPER_1(tlb_flush, void, env) #ifndef CONFIG_USER_ONLY DEF_HELPER_1(hyp_tlb_flush, void, env) DEF_HELPER_1(hyp_gvma_tlb_flush, void, env) -DEF_HELPER_4(hyp_load, tl, env, tl, tl, tl) -DEF_HELPER_5(hyp_store, void, env, tl, tl, tl, tl) +DEF_HELPER_1(hyp_access_check, void, env) DEF_HELPER_4(hyp_x_load, tl, env, tl, tl, tl) #endif =20 diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 5759850e69..d81d8282cc 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -227,82 +227,12 @@ void helper_hyp_gvma_tlb_flush(CPURISCVState *env) helper_hyp_tlb_flush(env); } =20 -target_ulong helper_hyp_load(CPURISCVState *env, target_ulong address, - target_ulong attrs, target_ulong memop) +void helper_hyp_access_check(CPURISCVState *env) { if (env->priv =3D=3D PRV_M || (env->priv =3D=3D PRV_S && !riscv_cpu_virt_enabled(env)) || (env->priv =3D=3D PRV_U && !riscv_cpu_virt_enabled(env) && get_field(env->hstatus, HSTATUS_HU))) { - target_ulong pte; - int mmu_idx =3D cpu_mmu_index(env, false) | TB_FLAGS_PRIV_HYP_ACCE= SS_MASK; - - switch (memop) { - case MO_SB: - pte =3D cpu_ldsb_mmuidx_ra(env, address, mmu_idx, GETPC()); - break; - case MO_UB: - pte =3D cpu_ldub_mmuidx_ra(env, address, mmu_idx, GETPC()); - break; - case MO_TESW: - pte =3D cpu_ldsw_mmuidx_ra(env, address, mmu_idx, GETPC()); - break; - case MO_TEUW: - pte =3D cpu_lduw_mmuidx_ra(env, address, mmu_idx, GETPC()); - break; - case MO_TESL: - pte =3D cpu_ldl_mmuidx_ra(env, address, mmu_idx, GETPC()); - break; - case MO_TEUL: - pte =3D cpu_ldl_mmuidx_ra(env, address, mmu_idx, GETPC()); - break; - case MO_TEQ: - pte =3D cpu_ldq_mmuidx_ra(env, address, mmu_idx, GETPC()); - break; - default: - g_assert_not_reached(); - } - - return pte; - } - - if (riscv_cpu_virt_enabled(env)) { - riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETP= C()); - } else { - riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); - } - return 0; -} - -void helper_hyp_store(CPURISCVState *env, target_ulong address, - target_ulong val, target_ulong attrs, target_ulong m= emop) -{ - if (env->priv =3D=3D PRV_M || - (env->priv =3D=3D PRV_S && !riscv_cpu_virt_enabled(env)) || - (env->priv =3D=3D PRV_U && !riscv_cpu_virt_enabled(env) && - get_field(env->hstatus, HSTATUS_HU))) { - int mmu_idx =3D cpu_mmu_index(env, false) | TB_FLAGS_PRIV_HYP_ACCE= SS_MASK; - - switch (memop) { - case MO_SB: - case MO_UB: - cpu_stb_mmuidx_ra(env, address, val, mmu_idx, GETPC()); - break; - case MO_TESW: - case MO_TEUW: - cpu_stw_mmuidx_ra(env, address, val, mmu_idx, GETPC()); - break; - case MO_TESL: - case MO_TEUL: - cpu_stl_mmuidx_ra(env, address, val, mmu_idx, GETPC()); - break; - case MO_TEQ: - cpu_stq_mmuidx_ra(env, address, val, mmu_idx, GETPC()); - break; - default: - g_assert_not_reached(); - } - return; } =20 diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_tr= ans/trans_rvh.c.inc index 881c9ef4d2..79968701e9 100644 --- a/target/riscv/insn_trans/trans_rvh.c.inc +++ b/target/riscv/insn_trans/trans_rvh.c.inc @@ -22,20 +22,16 @@ static bool trans_hlv_b(DisasContext *ctx, arg_hlv_b *a) #ifndef CONFIG_USER_ONLY TCGv t0 =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_new(); - TCGv mem_idx =3D tcg_temp_new(); - TCGv memop =3D tcg_temp_new(); + + gen_helper_hyp_access_check(cpu_env); =20 gen_get_gpr(t0, a->rs1); - tcg_gen_movi_tl(mem_idx, ctx->mem_idx); - tcg_gen_movi_tl(memop, MO_SB); =20 - gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop); + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MAS= K, MO_SB); gen_set_gpr(a->rd, t1); =20 tcg_temp_free(t0); tcg_temp_free(t1); - tcg_temp_free(mem_idx); - tcg_temp_free(memop); return true; #else return false; @@ -48,20 +44,16 @@ static bool trans_hlv_h(DisasContext *ctx, arg_hlv_h *a) #ifndef CONFIG_USER_ONLY TCGv t0 =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_new(); - TCGv mem_idx =3D tcg_temp_new(); - TCGv memop =3D tcg_temp_new(); + + gen_helper_hyp_access_check(cpu_env); =20 gen_get_gpr(t0, a->rs1); - tcg_gen_movi_tl(mem_idx, ctx->mem_idx); - tcg_gen_movi_tl(memop, MO_TESW); =20 - gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop); + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MAS= K, MO_TESW); gen_set_gpr(a->rd, t1); =20 tcg_temp_free(t0); tcg_temp_free(t1); - tcg_temp_free(mem_idx); - tcg_temp_free(memop); return true; #else return false; @@ -74,20 +66,16 @@ static bool trans_hlv_w(DisasContext *ctx, arg_hlv_w *a) #ifndef CONFIG_USER_ONLY TCGv t0 =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_new(); - TCGv mem_idx =3D tcg_temp_new(); - TCGv memop =3D tcg_temp_new(); + + gen_helper_hyp_access_check(cpu_env); =20 gen_get_gpr(t0, a->rs1); - tcg_gen_movi_tl(mem_idx, ctx->mem_idx); - tcg_gen_movi_tl(memop, MO_TESL); =20 - gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop); + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MAS= K, MO_TESL); gen_set_gpr(a->rd, t1); =20 tcg_temp_free(t0); tcg_temp_free(t1); - tcg_temp_free(mem_idx); - tcg_temp_free(memop); return true; #else return false; @@ -100,20 +88,16 @@ static bool trans_hlv_bu(DisasContext *ctx, arg_hlv_bu= *a) #ifndef CONFIG_USER_ONLY TCGv t0 =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_new(); - TCGv mem_idx =3D tcg_temp_new(); - TCGv memop =3D tcg_temp_new(); + + gen_helper_hyp_access_check(cpu_env); =20 gen_get_gpr(t0, a->rs1); - tcg_gen_movi_tl(mem_idx, ctx->mem_idx); - tcg_gen_movi_tl(memop, MO_UB); =20 - gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop); + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MAS= K, MO_UB); gen_set_gpr(a->rd, t1); =20 tcg_temp_free(t0); tcg_temp_free(t1); - tcg_temp_free(mem_idx); - tcg_temp_free(memop); return true; #else return false; @@ -126,20 +110,15 @@ static bool trans_hlv_hu(DisasContext *ctx, arg_hlv_h= u *a) #ifndef CONFIG_USER_ONLY TCGv t0 =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_new(); - TCGv mem_idx =3D tcg_temp_new(); - TCGv memop =3D tcg_temp_new(); =20 - gen_get_gpr(t0, a->rs1); - tcg_gen_movi_tl(mem_idx, ctx->mem_idx); - tcg_gen_movi_tl(memop, MO_TEUW); + gen_helper_hyp_access_check(cpu_env); =20 - gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop); + gen_get_gpr(t0, a->rs1); + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MAS= K, MO_TEUW); gen_set_gpr(a->rd, t1); =20 tcg_temp_free(t0); tcg_temp_free(t1); - tcg_temp_free(mem_idx); - tcg_temp_free(memop); return true; #else return false; @@ -152,20 +131,16 @@ static bool trans_hsv_b(DisasContext *ctx, arg_hsv_b = *a) #ifndef CONFIG_USER_ONLY TCGv t0 =3D tcg_temp_new(); TCGv dat =3D tcg_temp_new(); - TCGv mem_idx =3D tcg_temp_new(); - TCGv memop =3D tcg_temp_new(); + + gen_helper_hyp_access_check(cpu_env); =20 gen_get_gpr(t0, a->rs1); gen_get_gpr(dat, a->rs2); - tcg_gen_movi_tl(mem_idx, ctx->mem_idx); - tcg_gen_movi_tl(memop, MO_SB); =20 - gen_helper_hyp_store(cpu_env, t0, dat, mem_idx, memop); + tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MA= SK, MO_SB); =20 tcg_temp_free(t0); tcg_temp_free(dat); - tcg_temp_free(mem_idx); - tcg_temp_free(memop); return true; #else return false; @@ -178,20 +153,16 @@ static bool trans_hsv_h(DisasContext *ctx, arg_hsv_h = *a) #ifndef CONFIG_USER_ONLY TCGv t0 =3D tcg_temp_new(); TCGv dat =3D tcg_temp_new(); - TCGv mem_idx =3D tcg_temp_new(); - TCGv memop =3D tcg_temp_new(); + + gen_helper_hyp_access_check(cpu_env); =20 gen_get_gpr(t0, a->rs1); gen_get_gpr(dat, a->rs2); - tcg_gen_movi_tl(mem_idx, ctx->mem_idx); - tcg_gen_movi_tl(memop, MO_TESW); =20 - gen_helper_hyp_store(cpu_env, t0, dat, mem_idx, memop); + tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MA= SK, MO_TESW); =20 tcg_temp_free(t0); tcg_temp_free(dat); - tcg_temp_free(mem_idx); - tcg_temp_free(memop); return true; #else return false; @@ -204,20 +175,16 @@ static bool trans_hsv_w(DisasContext *ctx, arg_hsv_w = *a) #ifndef CONFIG_USER_ONLY TCGv t0 =3D tcg_temp_new(); TCGv dat =3D tcg_temp_new(); - TCGv mem_idx =3D tcg_temp_new(); - TCGv memop =3D tcg_temp_new(); + + gen_helper_hyp_access_check(cpu_env); =20 gen_get_gpr(t0, a->rs1); gen_get_gpr(dat, a->rs2); - tcg_gen_movi_tl(mem_idx, ctx->mem_idx); - tcg_gen_movi_tl(memop, MO_TESL); =20 - gen_helper_hyp_store(cpu_env, t0, dat, mem_idx, memop); + tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MA= SK, MO_TESL); =20 tcg_temp_free(t0); tcg_temp_free(dat); - tcg_temp_free(mem_idx); - tcg_temp_free(memop); return true; #else return false; @@ -231,20 +198,16 @@ static bool trans_hlv_wu(DisasContext *ctx, arg_hlv_w= u *a) #ifndef CONFIG_USER_ONLY TCGv t0 =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_new(); - TCGv mem_idx =3D tcg_temp_new(); - TCGv memop =3D tcg_temp_new(); + + gen_helper_hyp_access_check(cpu_env); =20 gen_get_gpr(t0, a->rs1); - tcg_gen_movi_tl(mem_idx, ctx->mem_idx); - tcg_gen_movi_tl(memop, MO_TEUL); =20 - gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop); + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MAS= K, MO_TEUL); gen_set_gpr(a->rd, t1); =20 tcg_temp_free(t0); tcg_temp_free(t1); - tcg_temp_free(mem_idx); - tcg_temp_free(memop); return true; #else return false; @@ -257,20 +220,16 @@ static bool trans_hlv_d(DisasContext *ctx, arg_hlv_d = *a) #ifndef CONFIG_USER_ONLY TCGv t0 =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_new(); - TCGv mem_idx =3D tcg_temp_new(); - TCGv memop =3D tcg_temp_new(); + + gen_helper_hyp_access_check(cpu_env); =20 gen_get_gpr(t0, a->rs1); - tcg_gen_movi_tl(mem_idx, ctx->mem_idx); - tcg_gen_movi_tl(memop, MO_TEQ); =20 - gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop); + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MAS= K, MO_TEQ); gen_set_gpr(a->rd, t1); =20 tcg_temp_free(t0); tcg_temp_free(t1); - tcg_temp_free(mem_idx); - tcg_temp_free(memop); return true; #else return false; @@ -283,20 +242,16 @@ static bool trans_hsv_d(DisasContext *ctx, arg_hsv_d = *a) #ifndef CONFIG_USER_ONLY TCGv t0 =3D tcg_temp_new(); TCGv dat =3D tcg_temp_new(); - TCGv mem_idx =3D tcg_temp_new(); - TCGv memop =3D tcg_temp_new(); + + gen_helper_hyp_access_check(cpu_env); =20 gen_get_gpr(t0, a->rs1); gen_get_gpr(dat, a->rs2); - tcg_gen_movi_tl(mem_idx, ctx->mem_idx); - tcg_gen_movi_tl(memop, MO_TEQ); =20 - gen_helper_hyp_store(cpu_env, t0, dat, mem_idx, memop); + tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MA= SK, MO_TEQ); =20 tcg_temp_free(t0); tcg_temp_free(dat); - tcg_temp_free(mem_idx); - tcg_temp_free(memop); return true; #else return false; --=20 2.28.0 From nobody Sun May 19 16:58:43 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" Instead of using an external helper to ensure we can perform the Hypervisor load/store instructions let's do it inline using TB_FLAGS. Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 12 +++ target/riscv/helper.h | 1 - target/riscv/op_helper.c | 16 ---- target/riscv/translate.c | 2 + target/riscv/insn_trans/trans_rvh.c.inc | 121 +++++++++++++++++++++--- 5 files changed, 124 insertions(+), 28 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 0cf48a1521..c0a326c843 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -375,6 +375,8 @@ FIELD(TB_FLAGS, VL_EQ_VLMAX, 2, 1) FIELD(TB_FLAGS, LMUL, 3, 2) FIELD(TB_FLAGS, SEW, 5, 3) FIELD(TB_FLAGS, VILL, 8, 1) +/* Is a Hypervisor instruction load/store allowed? */ +FIELD(TB_FLAGS, HLSX, 9, 1) =20 /* * A simplification for VLMAX @@ -421,7 +423,17 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState = *env, target_ulong *pc, if (riscv_cpu_fp_enabled(env)) { flags |=3D env->mstatus & MSTATUS_FS; } + + if (riscv_has_ext(env, RVH)) { + if (env->priv =3D=3D PRV_M || + (env->priv =3D=3D PRV_S && !riscv_cpu_virt_enabled(env)) || + (env->priv =3D=3D PRV_U && !riscv_cpu_virt_enabled(env) && + get_field(env->hstatus, HSTATUS_HU))) { + flags =3D FIELD_DP32(flags, TB_FLAGS, HLSX, 1); + } + } #endif + *pflags =3D flags; } =20 diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 7dbdd117d2..ee35311052 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -81,7 +81,6 @@ DEF_HELPER_1(tlb_flush, void, env) #ifndef CONFIG_USER_ONLY DEF_HELPER_1(hyp_tlb_flush, void, env) DEF_HELPER_1(hyp_gvma_tlb_flush, void, env) -DEF_HELPER_1(hyp_access_check, void, env) DEF_HELPER_4(hyp_x_load, tl, env, tl, tl, tl) #endif =20 diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index d81d8282cc..980d4f39e1 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -227,22 +227,6 @@ void helper_hyp_gvma_tlb_flush(CPURISCVState *env) helper_hyp_tlb_flush(env); } =20 -void helper_hyp_access_check(CPURISCVState *env) -{ - if (env->priv =3D=3D PRV_M || - (env->priv =3D=3D PRV_S && !riscv_cpu_virt_enabled(env)) || - (env->priv =3D=3D PRV_U && !riscv_cpu_virt_enabled(env) && - get_field(env->hstatus, HSTATUS_HU))) { - return; - } - - if (riscv_cpu_virt_enabled(env)) { - riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETP= C()); - } else { - riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); - } -} - target_ulong helper_hyp_x_load(CPURISCVState *env, target_ulong address, target_ulong attrs, target_ulong memop) { diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 79dca2291b..554d52a4be 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -56,6 +56,7 @@ typedef struct DisasContext { to reset this known value. */ int frm; bool ext_ifencei; + bool hlsx; /* vector extension */ bool vill; uint8_t lmul; @@ -807,6 +808,7 @@ static void riscv_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) ctx->frm =3D -1; /* unknown rounding mode */ ctx->ext_ifencei =3D cpu->cfg.ext_ifencei; ctx->vlen =3D cpu->cfg.vlen; + ctx->hlsx =3D FIELD_EX32(tb_flags, TB_FLAGS, HLSX); ctx->vill =3D FIELD_EX32(tb_flags, TB_FLAGS, VILL); ctx->sew =3D FIELD_EX32(tb_flags, TB_FLAGS, SEW); ctx->lmul =3D FIELD_EX32(tb_flags, TB_FLAGS, LMUL); diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_tr= ans/trans_rvh.c.inc index 79968701e9..b780ec8bc4 100644 --- a/target/riscv/insn_trans/trans_rvh.c.inc +++ b/target/riscv/insn_trans/trans_rvh.c.inc @@ -23,7 +23,16 @@ static bool trans_hlv_b(DisasContext *ctx, arg_hlv_b *a) TCGv t0 =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_new(); =20 - gen_helper_hyp_access_check(cpu_env); + if (!ctx->hlsx) { + if (ctx->virt_enabled) { + generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT); + } else { + generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); + } + exit_tb(ctx); /* no chaining */ + ctx->base.is_jmp =3D DISAS_NORETURN; + return false; + } =20 gen_get_gpr(t0, a->rs1); =20 @@ -45,7 +54,16 @@ static bool trans_hlv_h(DisasContext *ctx, arg_hlv_h *a) TCGv t0 =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_new(); =20 - gen_helper_hyp_access_check(cpu_env); + if (!ctx->hlsx) { + if (ctx->virt_enabled) { + generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT); + } else { + generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); + } + exit_tb(ctx); /* no chaining */ + ctx->base.is_jmp =3D DISAS_NORETURN; + return false; + } =20 gen_get_gpr(t0, a->rs1); =20 @@ -67,7 +85,16 @@ static bool trans_hlv_w(DisasContext *ctx, arg_hlv_w *a) TCGv t0 =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_new(); =20 - gen_helper_hyp_access_check(cpu_env); + if (!ctx->hlsx) { + if (ctx->virt_enabled) { + generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT); + } else { + generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); + } + exit_tb(ctx); /* no chaining */ + ctx->base.is_jmp =3D DISAS_NORETURN; + return false; + } =20 gen_get_gpr(t0, a->rs1); =20 @@ -89,7 +116,16 @@ static bool trans_hlv_bu(DisasContext *ctx, arg_hlv_bu = *a) TCGv t0 =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_new(); =20 - gen_helper_hyp_access_check(cpu_env); + if (!ctx->hlsx) { + if (ctx->virt_enabled) { + generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT); + } else { + generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); + } + exit_tb(ctx); /* no chaining */ + ctx->base.is_jmp =3D DISAS_NORETURN; + return false; + } =20 gen_get_gpr(t0, a->rs1); =20 @@ -111,7 +147,16 @@ static bool trans_hlv_hu(DisasContext *ctx, arg_hlv_hu= *a) TCGv t0 =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_new(); =20 - gen_helper_hyp_access_check(cpu_env); + if (!ctx->hlsx) { + if (ctx->virt_enabled) { + generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT); + } else { + generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); + } + exit_tb(ctx); /* no chaining */ + ctx->base.is_jmp =3D DISAS_NORETURN; + return false; + } =20 gen_get_gpr(t0, a->rs1); tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MAS= K, MO_TEUW); @@ -132,7 +177,16 @@ static bool trans_hsv_b(DisasContext *ctx, arg_hsv_b *= a) TCGv t0 =3D tcg_temp_new(); TCGv dat =3D tcg_temp_new(); =20 - gen_helper_hyp_access_check(cpu_env); + if (!ctx->hlsx) { + if (ctx->virt_enabled) { + generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT); + } else { + generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); + } + exit_tb(ctx); /* no chaining */ + ctx->base.is_jmp =3D DISAS_NORETURN; + return false; + } =20 gen_get_gpr(t0, a->rs1); gen_get_gpr(dat, a->rs2); @@ -154,7 +208,16 @@ static bool trans_hsv_h(DisasContext *ctx, arg_hsv_h *= a) TCGv t0 =3D tcg_temp_new(); TCGv dat =3D tcg_temp_new(); =20 - gen_helper_hyp_access_check(cpu_env); + if (!ctx->hlsx) { + if (ctx->virt_enabled) { + generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT); + } else { + generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); + } + exit_tb(ctx); /* no chaining */ + ctx->base.is_jmp =3D DISAS_NORETURN; + return false; + } =20 gen_get_gpr(t0, a->rs1); gen_get_gpr(dat, a->rs2); @@ -176,7 +239,16 @@ static bool trans_hsv_w(DisasContext *ctx, arg_hsv_w *= a) TCGv t0 =3D tcg_temp_new(); TCGv dat =3D tcg_temp_new(); =20 - gen_helper_hyp_access_check(cpu_env); + if (!ctx->hlsx) { + if (ctx->virt_enabled) { + generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT); + } else { + generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); + } + exit_tb(ctx); /* no chaining */ + ctx->base.is_jmp =3D DISAS_NORETURN; + return false; + } =20 gen_get_gpr(t0, a->rs1); gen_get_gpr(dat, a->rs2); @@ -199,7 +271,16 @@ static bool trans_hlv_wu(DisasContext *ctx, arg_hlv_wu= *a) TCGv t0 =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_new(); =20 - gen_helper_hyp_access_check(cpu_env); + if (!ctx->hlsx) { + if (ctx->virt_enabled) { + generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT); + } else { + generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); + } + exit_tb(ctx); /* no chaining */ + ctx->base.is_jmp =3D DISAS_NORETURN; + return false; + } =20 gen_get_gpr(t0, a->rs1); =20 @@ -221,7 +302,16 @@ static bool trans_hlv_d(DisasContext *ctx, arg_hlv_d *= a) TCGv t0 =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_new(); =20 - gen_helper_hyp_access_check(cpu_env); + if (!ctx->hlsx) { + if (ctx->virt_enabled) { + generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT); + } else { + generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); + } + exit_tb(ctx); /* no chaining */ + ctx->base.is_jmp =3D DISAS_NORETURN; + return false; + } =20 gen_get_gpr(t0, a->rs1); =20 @@ -243,7 +333,16 @@ static bool trans_hsv_d(DisasContext *ctx, arg_hsv_d *= a) TCGv t0 =3D tcg_temp_new(); TCGv dat =3D tcg_temp_new(); =20 - gen_helper_hyp_access_check(cpu_env); + if (!ctx->hlsx) { + if (ctx->virt_enabled) { + generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT); + } else { + generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); + } + exit_tb(ctx); /* no chaining */ + ctx->base.is_jmp =3D DISAS_NORETURN; + return false; + } =20 gen_get_gpr(t0, a->rs1); gen_get_gpr(dat, a->rs2); --=20 2.28.0 From nobody Sun May 19 16:58:43 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1604434139; cv=none; d=zohomail.com; s=zohoarc; b=RiRjeWZjzbOjk3G45OYJwWbv5Uwfc3rldqwShlRNMeNETDeAo7YQjf9GYteTpF6Th8XYRaN8WtHGl9+ZCVFTxZ61dliqWZXTGpeqzJ7ITPKkd13SIoA/Ym5RuucF3QcqKP8zCnxdBIpT3V8YV5ZSt2E1ypnxpN08fUetxa3g7WM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1604434139; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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IronPort-SDR: gMjpRD+76INuIGxc35ypaRfqsw/XSosgl1BLT/xfARoCvPiWEZyAUcZq1l+sQ2uBO0U+UazcwF 3GV+rsgPGELNJQo4BnapV4s9KzFJ61FsRW7XjefRiPTSfCwSgObhQjr3FRS3sAEp/LQZd06VPt dBJlowA5CG68d1c/h38hCOO/+NRxwMJQQ5fby41wGxlLLP3wcjWLUuz+sG/603IDGzdJioP2A+ 2FdcWu7w1py55iT0/wrq2gRthwJREI3cCZ5hX2V53yP+pq4GrIltZ4SInaaQGyWDsbBf1+Lwmz J/0= X-IronPort-AV: E=Sophos;i="5.77,448,1596470400"; d="scan'208";a="152912259" IronPort-SDR: ggG30akx2UbE/uMV+b34UmTM8bBPa98hvMfPBphpUIzU4CNar0R4Zf97zjQTxSZpkqNJ96W3l/ VgfNkw+2mVXPENhpOWpkdskddbv8gyUWh2T/eQcfD7Ma2uj+LfBqt291np4BgjXgvg1k6tRRdz gP6VfO6hYAlk2BAb9mYj56xMnRH0XEbbArs8sdAj6DjtkUFHBuuvlBeHmWjOTxvQSTaZQFRoW5 2JFYHjWAvSqRJTHsXCptdT8eyfUy1L/hge9W6MZtRd4bEdsPnzAoeqtcs/mHlva4AecK/m0Rna 7OBr7WEVh2f6zg12jMKC58cq IronPort-SDR: 53VUA+eiwg3RLhloJeoIfRuDLCVWsO2RLajY2DxTd04eMbxLeyN5F8mQhf4l94VM9tS+2ivlvt a3qJTUtkAps4oimDayXLqaJ/99yw8A46XNeAx2oKhkEH8EqBwQ+jIdym/wngr2r6Z/hNvfXGF6 HOUjBQkpl24xELfqZRzo1jfGyE8HHAekyOkwRS7JCJsb7LGWZkiEwlmEGR7ZPwHwkCpjPpQJ3G xPFoigbw1GDcbdo7YTVM3zuxigRyld1CKmPC/arI/WTS/Km4V6dE+hAWZkn6YROrVa699tqwhr hwg= WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 7/7] target/riscv: Split the Hypervisor execute load helpers Date: Tue, 3 Nov 2020 11:51:12 -0800 Message-Id: <078c49d9759ef845affe35ee690cb4242e511429.1604432950.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=569a91e0c=alistair.francis@wdc.com; helo=esa6.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/11/03 15:02:42 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Split the hypervisor execute load functions into two seperate functions. This avoids us having to pass the memop to the C helper functions. Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/helper.h | 3 +- target/riscv/op_helper.c | 36 ++++++----------------- target/riscv/insn_trans/trans_rvh.c.inc | 38 ++++++++++++++++--------- 3 files changed, 35 insertions(+), 42 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index ee35311052..939731c345 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -81,7 +81,8 @@ DEF_HELPER_1(tlb_flush, void, env) #ifndef CONFIG_USER_ONLY DEF_HELPER_1(hyp_tlb_flush, void, env) DEF_HELPER_1(hyp_gvma_tlb_flush, void, env) -DEF_HELPER_4(hyp_x_load, tl, env, tl, tl, tl) +DEF_HELPER_2(hyp_hlvx_hu, tl, env, tl) +DEF_HELPER_2(hyp_hlvx_wu, tl, env, tl) #endif =20 /* Vector functions */ diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 980d4f39e1..d55def76cf 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -227,36 +227,18 @@ void helper_hyp_gvma_tlb_flush(CPURISCVState *env) helper_hyp_tlb_flush(env); } =20 -target_ulong helper_hyp_x_load(CPURISCVState *env, target_ulong address, - target_ulong attrs, target_ulong memop) +target_ulong helper_hyp_hlvx_hu(CPURISCVState *env, target_ulong address) { - if (env->priv =3D=3D PRV_M || - (env->priv =3D=3D PRV_S && !riscv_cpu_virt_enabled(env)) || - (env->priv =3D=3D PRV_U && !riscv_cpu_virt_enabled(env) && - get_field(env->hstatus, HSTATUS_HU))) { - target_ulong pte; - int mmu_idx =3D cpu_mmu_index(env, false) | TB_FLAGS_PRIV_HYP_ACCE= SS_MASK; - - switch (memop) { - case MO_TEUW: - pte =3D cpu_lduw_mmuidx_ra(env, address, mmu_idx, GETPC()); - break; - case MO_TEUL: - pte =3D cpu_ldl_mmuidx_ra(env, address, mmu_idx, GETPC()); - break; - default: - g_assert_not_reached(); - } + int mmu_idx =3D cpu_mmu_index(env, true) | TB_FLAGS_PRIV_HYP_ACCESS_MA= SK; =20 - return pte; - } + return cpu_lduw_mmuidx_ra(env, address, mmu_idx, GETPC()); +} =20 - if (riscv_cpu_virt_enabled(env)) { - riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETP= C()); - } else { - riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); - } - return 0; +target_ulong helper_hyp_hlvx_wu(CPURISCVState *env, target_ulong address) +{ + int mmu_idx =3D cpu_mmu_index(env, true) | TB_FLAGS_PRIV_HYP_ACCESS_MA= SK; + + return cpu_ldl_mmuidx_ra(env, address, mmu_idx, GETPC()); } =20 #endif /* !CONFIG_USER_ONLY */ diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_tr= ans/trans_rvh.c.inc index b780ec8bc4..7c49562d6a 100644 --- a/target/riscv/insn_trans/trans_rvh.c.inc +++ b/target/riscv/insn_trans/trans_rvh.c.inc @@ -364,20 +364,25 @@ static bool trans_hlvx_hu(DisasContext *ctx, arg_hlvx= _hu *a) #ifndef CONFIG_USER_ONLY TCGv t0 =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_new(); - TCGv mem_idx =3D tcg_temp_new(); - TCGv memop =3D tcg_temp_new(); + + if (!ctx->hlsx) { + if (ctx->virt_enabled) { + generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT); + } else { + generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); + } + exit_tb(ctx); /* no chaining */ + ctx->base.is_jmp =3D DISAS_NORETURN; + return false; + } =20 gen_get_gpr(t0, a->rs1); - tcg_gen_movi_tl(mem_idx, ctx->mem_idx); - tcg_gen_movi_tl(memop, MO_TEUW); =20 - gen_helper_hyp_x_load(t1, cpu_env, t0, mem_idx, memop); + gen_helper_hyp_hlvx_hu(t1, cpu_env, t0); gen_set_gpr(a->rd, t1); =20 tcg_temp_free(t0); tcg_temp_free(t1); - tcg_temp_free(mem_idx); - tcg_temp_free(memop); return true; #else return false; @@ -390,20 +395,25 @@ static bool trans_hlvx_wu(DisasContext *ctx, arg_hlvx= _wu *a) #ifndef CONFIG_USER_ONLY TCGv t0 =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_new(); - TCGv mem_idx =3D tcg_temp_new(); - TCGv memop =3D tcg_temp_new(); + + if (!ctx->hlsx) { + if (ctx->virt_enabled) { + generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT); + } else { + generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); + } + exit_tb(ctx); /* no chaining */ + ctx->base.is_jmp =3D DISAS_NORETURN; + return false; + } =20 gen_get_gpr(t0, a->rs1); - tcg_gen_movi_tl(mem_idx, ctx->mem_idx); - tcg_gen_movi_tl(memop, MO_TEUL); =20 - gen_helper_hyp_x_load(t1, cpu_env, t0, mem_idx, memop); + gen_helper_hyp_hlvx_wu(t1, cpu_env, t0); gen_set_gpr(a->rd, t1); =20 tcg_temp_free(t0); tcg_temp_free(t1); - tcg_temp_free(mem_idx); - tcg_temp_free(memop); return true; #else return false; --=20 2.28.0