From nobody Sat May 4 19:43:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 152829358490625.726200956852608; Wed, 6 Jun 2018 06:59:44 -0700 (PDT) Received: from localhost ([::1]:52599 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fQYyO-0001Bc-4L for importer@patchew.org; Wed, 06 Jun 2018 09:59:36 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40178) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fQYwW-0008Q8-5B for qemu-devel@nongnu.org; Wed, 06 Jun 2018 09:57:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fQYwU-0000Wy-DW for qemu-devel@nongnu.org; Wed, 06 Jun 2018 09:57:40 -0400 Received: from zero.eik.bme.hu ([152.66.115.2]:44633) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fQYwU-0000Vk-0D; Wed, 06 Jun 2018 09:57:38 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 9C4CE7456B4; Wed, 6 Jun 2018 15:57:28 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 013807456B5; Wed, 6 Jun 2018 15:57:28 +0200 (CEST) Message-Id: <53f9d0b04374a3f4449af65ce01bd68dbe757ab5.1528291908.git.balaton@eik.bme.hu> In-Reply-To: References: From: BALATON Zoltan Date: Wed, 06 Jun 2018 15:31:48 +0200 To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 152.66.115.2 Subject: [Qemu-devel] [PATCH v2 1/8] ppc4xx_i2c: Clean up and improve error logging X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alexander Graf , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Make it more readable by converting register indexes to decimal (avoids lot of superfluous 0x0) and distinguish errors caused by accessing non-existent vs. unimplemented registers. No functional change. Signed-off-by: BALATON Zoltan --- hw/i2c/ppc4xx_i2c.c | 94 +++++++++++++++++++++++++++++--------------------= ---- 1 file changed, 51 insertions(+), 43 deletions(-) diff --git a/hw/i2c/ppc4xx_i2c.c b/hw/i2c/ppc4xx_i2c.c index ab64d19..d1936db 100644 --- a/hw/i2c/ppc4xx_i2c.c +++ b/hw/i2c/ppc4xx_i2c.c @@ -31,7 +31,7 @@ #include "hw/hw.h" #include "hw/i2c/ppc4xx_i2c.h" =20 -#define PPC4xx_I2C_MEM_SIZE 0x12 +#define PPC4xx_I2C_MEM_SIZE 18 =20 #define IIC_CNTL_PT (1 << 0) #define IIC_CNTL_READ (1 << 1) @@ -70,7 +70,7 @@ static void ppc4xx_i2c_reset(DeviceState *s) i2c->intrmsk =3D 0; i2c->xfrcnt =3D 0; i2c->xtcntlss =3D 0; - i2c->directcntl =3D 0x0f; + i2c->directcntl =3D 0xf; i2c->intr =3D 0; } =20 @@ -85,7 +85,7 @@ static uint64_t ppc4xx_i2c_readb(void *opaque, hwaddr add= r, unsigned int size) uint64_t ret; =20 switch (addr) { - case 0x00: + case 0: ret =3D i2c->mdata; if (ppc4xx_i2c_is_master(i2c)) { ret =3D 0xff; @@ -139,58 +139,62 @@ static uint64_t ppc4xx_i2c_readb(void *opaque, hwaddr= addr, unsigned int size) TYPE_PPC4xx_I2C, __func__); } break; - case 0x02: + case 2: ret =3D i2c->sdata; break; - case 0x04: + case 4: ret =3D i2c->lmadr; break; - case 0x05: + case 5: ret =3D i2c->hmadr; break; - case 0x06: + case 6: ret =3D i2c->cntl; break; - case 0x07: + case 7: ret =3D i2c->mdcntl; break; - case 0x08: + case 8: ret =3D i2c->sts; break; - case 0x09: + case 9: ret =3D i2c->extsts; break; - case 0x0A: + case 10: ret =3D i2c->lsadr; break; - case 0x0B: + case 11: ret =3D i2c->hsadr; break; - case 0x0C: + case 12: ret =3D i2c->clkdiv; break; - case 0x0D: + case 13: ret =3D i2c->intrmsk; break; - case 0x0E: + case 14: ret =3D i2c->xfrcnt; break; - case 0x0F: + case 15: ret =3D i2c->xtcntlss; break; - case 0x10: + case 16: ret =3D i2c->directcntl; break; - case 0x11: + case 17: ret =3D i2c->intr; break; default: - qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad address at offset 0x%" - HWADDR_PRIx "\n", TYPE_PPC4xx_I2C, __func__, addr); + if (addr < PPC4xx_I2C_MEM_SIZE) { + qemu_log_mask(LOG_UNIMP, "%s: Unimplemented register 0x%" + HWADDR_PRIx "\n", __func__, addr); + } else { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address 0x%" + HWADDR_PRIx "\n", __func__, addr); + } ret =3D 0; break; } - return ret; } =20 @@ -200,7 +204,7 @@ static void ppc4xx_i2c_writeb(void *opaque, hwaddr addr= , uint64_t value, PPC4xxI2CState *i2c =3D opaque; =20 switch (addr) { - case 0x00: + case 0: i2c->mdata =3D value; if (!i2c_bus_busy(i2c->bus)) { /* assume we start a write transfer */ @@ -225,19 +229,19 @@ static void ppc4xx_i2c_writeb(void *opaque, hwaddr ad= dr, uint64_t value, } } break; - case 0x02: + case 2: i2c->sdata =3D value; break; - case 0x04: + case 4: i2c->lmadr =3D value; if (i2c_bus_busy(i2c->bus)) { i2c_end_transfer(i2c->bus); } break; - case 0x05: + case 5: i2c->hmadr =3D value; break; - case 0x06: + case 6: i2c->cntl =3D value; if (i2c->cntl & IIC_CNTL_PT) { if (i2c->cntl & IIC_CNTL_READ) { @@ -263,32 +267,31 @@ static void ppc4xx_i2c_writeb(void *opaque, hwaddr ad= dr, uint64_t value, } } break; - case 0x07: - i2c->mdcntl =3D value & 0xDF; + case 7: + i2c->mdcntl =3D value & 0xdf; break; - case 0x08: - i2c->sts &=3D ~(value & 0x0A); + case 8: + i2c->sts &=3D ~(value & 0xa); break; - case 0x09: - i2c->extsts &=3D ~(value & 0x8F); + case 9: + i2c->extsts &=3D ~(value & 0x8f); break; - case 0x0A: + case 10: i2c->lsadr =3D value; - /*i2c_set_slave_address(i2c->bus, i2c->lsadr);*/ break; - case 0x0B: + case 11: i2c->hsadr =3D value; break; - case 0x0C: + case 12: i2c->clkdiv =3D value; break; - case 0x0D: + case 13: i2c->intrmsk =3D value; break; - case 0x0E: + case 14: i2c->xfrcnt =3D value & 0x77; break; - case 0x0F: + case 15: if (value & IIC_XTCNTLSS_SRST) { /* Is it actually a full reset? U-Boot sets some regs before */ ppc4xx_i2c_reset(DEVICE(i2c)); @@ -296,15 +299,20 @@ static void ppc4xx_i2c_writeb(void *opaque, hwaddr ad= dr, uint64_t value, } i2c->xtcntlss =3D value; break; - case 0x10: + case 16: i2c->directcntl =3D value & 0x7; break; - case 0x11: + case 17: i2c->intr =3D value; break; default: - qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad address at offset 0x%" - HWADDR_PRIx "\n", TYPE_PPC4xx_I2C, __func__, addr); + if (addr < PPC4xx_I2C_MEM_SIZE) { + qemu_log_mask(LOG_UNIMP, "%s: Unimplemented register 0x%" + HWADDR_PRIx "\n", __func__, addr); + } else { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address 0x%" + HWADDR_PRIx "\n", __func__, addr); + } break; } } --=20 2.7.6 From nobody Sat May 4 19:43:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1528293922749201.136561737124; Wed, 6 Jun 2018 07:05:22 -0700 (PDT) Received: from localhost ([::1]:52638 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fQZ3o-0006dE-LL for importer@patchew.org; Wed, 06 Jun 2018 10:05:12 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40211) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fQYwX-0008QL-LZ for qemu-devel@nongnu.org; Wed, 06 Jun 2018 09:57:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fQYwT-0000Vv-4k for qemu-devel@nongnu.org; Wed, 06 Jun 2018 09:57:41 -0400 Received: from zero.eik.bme.hu ([152.66.115.2]:44613) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fQYwS-0000Od-N5; Wed, 06 Jun 2018 09:57:37 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 97AA37456B8; Wed, 6 Jun 2018 15:57:28 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 05D507456A0; Wed, 6 Jun 2018 15:57:28 +0200 (CEST) Message-Id: <7017cb3e0ed918bc3a9df823175d91a24692e2ef.1528291908.git.balaton@eik.bme.hu> In-Reply-To: References: From: BALATON Zoltan Date: Wed, 06 Jun 2018 15:31:48 +0200 To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 152.66.115.2 Subject: [Qemu-devel] [PATCH v2 2/8] ppc4xx_i2c: Move register state to private struct and remove unimplemented sdata and intr registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alexander Graf , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: BALATON Zoltan --- hw/i2c/ppc4xx_i2c.c | 75 +++++++++++++++++++++++++----------------= ---- include/hw/i2c/ppc4xx_i2c.h | 19 ++---------- 2 files changed, 43 insertions(+), 51 deletions(-) diff --git a/hw/i2c/ppc4xx_i2c.c b/hw/i2c/ppc4xx_i2c.c index d1936db..a68b5f7 100644 --- a/hw/i2c/ppc4xx_i2c.c +++ b/hw/i2c/ppc4xx_i2c.c @@ -3,7 +3,7 @@ * * Copyright (c) 2007 Jocelyn Mayer * Copyright (c) 2012 Fran\ufffd\ufffdois Revol - * Copyright (c) 2016 BALATON Zoltan + * Copyright (c) 2016-2018 BALATON Zoltan * * Permission is hereby granted, free of charge, to any person obtaining a= copy * of this software and associated documentation files (the "Software"), t= o deal @@ -46,9 +46,26 @@ =20 #define IIC_XTCNTLSS_SRST (1 << 0) =20 +typedef struct { + uint8_t mdata; + uint8_t lmadr; + uint8_t hmadr; + uint8_t cntl; + uint8_t mdcntl; + uint8_t sts; + uint8_t extsts; + uint8_t lsadr; + uint8_t hsadr; + uint8_t clkdiv; + uint8_t intrmsk; + uint8_t xfrcnt; + uint8_t xtcntlss; + uint8_t directcntl; +} PPC4xxI2CRegs; + static void ppc4xx_i2c_reset(DeviceState *s) { - PPC4xxI2CState *i2c =3D PPC4xx_I2C(s); + PPC4xxI2CRegs *i2c =3D PPC4xx_I2C(s)->regs; =20 /* FIXME: Should also reset bus? *if (s->address !=3D ADDR_RESET) { @@ -63,7 +80,6 @@ static void ppc4xx_i2c_reset(DeviceState *s) i2c->mdcntl =3D 0; i2c->sts =3D 0; i2c->extsts =3D 0x8f; - i2c->sdata =3D 0; i2c->lsadr =3D 0; i2c->hsadr =3D 0; i2c->clkdiv =3D 0; @@ -71,7 +87,6 @@ static void ppc4xx_i2c_reset(DeviceState *s) i2c->xfrcnt =3D 0; i2c->xtcntlss =3D 0; i2c->directcntl =3D 0xf; - i2c->intr =3D 0; } =20 static inline bool ppc4xx_i2c_is_master(PPC4xxI2CState *i2c) @@ -81,13 +96,14 @@ static inline bool ppc4xx_i2c_is_master(PPC4xxI2CState = *i2c) =20 static uint64_t ppc4xx_i2c_readb(void *opaque, hwaddr addr, unsigned int s= ize) { - PPC4xxI2CState *i2c =3D PPC4xx_I2C(opaque); + PPC4xxI2CState *s =3D PPC4xx_I2C(opaque); + PPC4xxI2CRegs *i2c =3D s->regs; uint64_t ret; =20 switch (addr) { case 0: ret =3D i2c->mdata; - if (ppc4xx_i2c_is_master(i2c)) { + if (ppc4xx_i2c_is_master(s)) { ret =3D 0xff; =20 if (!(i2c->sts & IIC_STS_MDBS)) { @@ -98,7 +114,7 @@ static uint64_t ppc4xx_i2c_readb(void *opaque, hwaddr ad= dr, unsigned int size) int pending =3D (i2c->cntl >> 4) & 3; =20 /* get the next byte */ - int byte =3D i2c_recv(i2c->bus); + int byte =3D i2c_recv(s->bus); =20 if (byte < 0) { qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: read failed " @@ -113,13 +129,13 @@ static uint64_t ppc4xx_i2c_readb(void *opaque, hwaddr= addr, unsigned int size) =20 if (!pending) { i2c->sts &=3D ~IIC_STS_MDBS; - /*i2c_end_transfer(i2c->bus);*/ + /*i2c_end_transfer(s->bus);*/ /*} else if (i2c->cntl & (IIC_CNTL_RPST | IIC_CNTL_CHT)) {= */ } else if (pending) { /* current smbus implementation doesn't like multibyte xfer repeated start */ - i2c_end_transfer(i2c->bus); - if (i2c_start_transfer(i2c->bus, i2c->lmadr >> 1, 1)) { + i2c_end_transfer(s->bus); + if (i2c_start_transfer(s->bus, i2c->lmadr >> 1, 1)) { /* if non zero is returned, the adress is not vali= d */ i2c->sts &=3D ~IIC_STS_PT; i2c->sts |=3D IIC_STS_ERR; @@ -139,9 +155,6 @@ static uint64_t ppc4xx_i2c_readb(void *opaque, hwaddr a= ddr, unsigned int size) TYPE_PPC4xx_I2C, __func__); } break; - case 2: - ret =3D i2c->sdata; - break; case 4: ret =3D i2c->lmadr; break; @@ -181,9 +194,6 @@ static uint64_t ppc4xx_i2c_readb(void *opaque, hwaddr a= ddr, unsigned int size) case 16: ret =3D i2c->directcntl; break; - case 17: - ret =3D i2c->intr; - break; default: if (addr < PPC4xx_I2C_MEM_SIZE) { qemu_log_mask(LOG_UNIMP, "%s: Unimplemented register 0x%" @@ -201,14 +211,15 @@ static uint64_t ppc4xx_i2c_readb(void *opaque, hwaddr= addr, unsigned int size) static void ppc4xx_i2c_writeb(void *opaque, hwaddr addr, uint64_t value, unsigned int size) { - PPC4xxI2CState *i2c =3D opaque; + PPC4xxI2CState *s =3D PPC4xx_I2C(opaque); + PPC4xxI2CRegs *i2c =3D s->regs; =20 switch (addr) { case 0: i2c->mdata =3D value; - if (!i2c_bus_busy(i2c->bus)) { + if (!i2c_bus_busy(s->bus)) { /* assume we start a write transfer */ - if (i2c_start_transfer(i2c->bus, i2c->lmadr >> 1, 0)) { + if (i2c_start_transfer(s->bus, i2c->lmadr >> 1, 0)) { /* if non zero is returned, the adress is not valid */ i2c->sts &=3D ~IIC_STS_PT; i2c->sts |=3D IIC_STS_ERR; @@ -219,23 +230,20 @@ static void ppc4xx_i2c_writeb(void *opaque, hwaddr ad= dr, uint64_t value, i2c->extsts =3D 0; } } - if (i2c_bus_busy(i2c->bus)) { - if (i2c_send(i2c->bus, i2c->mdata)) { + if (i2c_bus_busy(s->bus)) { + if (i2c_send(s->bus, i2c->mdata)) { /* if the target return non zero then end the transfer */ i2c->sts &=3D ~IIC_STS_PT; i2c->sts |=3D IIC_STS_ERR; i2c->extsts |=3D IIC_EXTSTS_XFRA; - i2c_end_transfer(i2c->bus); + i2c_end_transfer(s->bus); } } break; - case 2: - i2c->sdata =3D value; - break; case 4: i2c->lmadr =3D value; - if (i2c_bus_busy(i2c->bus)) { - i2c_end_transfer(i2c->bus); + if (i2c_bus_busy(s->bus)) { + i2c_end_transfer(s->bus); } break; case 5: @@ -245,12 +253,12 @@ static void ppc4xx_i2c_writeb(void *opaque, hwaddr ad= dr, uint64_t value, i2c->cntl =3D value; if (i2c->cntl & IIC_CNTL_PT) { if (i2c->cntl & IIC_CNTL_READ) { - if (i2c_bus_busy(i2c->bus)) { + if (i2c_bus_busy(s->bus)) { /* end previous transfer */ i2c->sts &=3D ~IIC_STS_PT; - i2c_end_transfer(i2c->bus); + i2c_end_transfer(s->bus); } - if (i2c_start_transfer(i2c->bus, i2c->lmadr >> 1, 1)) { + if (i2c_start_transfer(s->bus, i2c->lmadr >> 1, 1)) { /* if non zero is returned, the adress is not valid */ i2c->sts &=3D ~IIC_STS_PT; i2c->sts |=3D IIC_STS_ERR; @@ -294,7 +302,7 @@ static void ppc4xx_i2c_writeb(void *opaque, hwaddr addr= , uint64_t value, case 15: if (value & IIC_XTCNTLSS_SRST) { /* Is it actually a full reset? U-Boot sets some regs before */ - ppc4xx_i2c_reset(DEVICE(i2c)); + ppc4xx_i2c_reset(DEVICE(s)); break; } i2c->xtcntlss =3D value; @@ -302,9 +310,6 @@ static void ppc4xx_i2c_writeb(void *opaque, hwaddr addr= , uint64_t value, case 16: i2c->directcntl =3D value & 0x7; break; - case 17: - i2c->intr =3D value; - break; default: if (addr < PPC4xx_I2C_MEM_SIZE) { qemu_log_mask(LOG_UNIMP, "%s: Unimplemented register 0x%" @@ -330,7 +335,9 @@ static const MemoryRegionOps ppc4xx_i2c_ops =3D { static void ppc4xx_i2c_init(Object *o) { PPC4xxI2CState *s =3D PPC4xx_I2C(o); + PPC4xxI2CRegs *r =3D g_malloc0(sizeof(PPC4xxI2CRegs)); =20 + s->regs =3D r; memory_region_init_io(&s->iomem, OBJECT(s), &ppc4xx_i2c_ops, s, TYPE_PPC4xx_I2C, PPC4xx_I2C_MEM_SIZE); sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); diff --git a/include/hw/i2c/ppc4xx_i2c.h b/include/hw/i2c/ppc4xx_i2c.h index 3c60307..1d5ba0c 100644 --- a/include/hw/i2c/ppc4xx_i2c.h +++ b/include/hw/i2c/ppc4xx_i2c.h @@ -3,7 +3,7 @@ * * Copyright (c) 2007 Jocelyn Mayer * Copyright (c) 2012 Fran\ufffd\ufffdois Revol - * Copyright (c) 2016 BALATON Zoltan + * Copyright (c) 2016-2018 BALATON Zoltan * * Permission is hereby granted, free of charge, to any person obtaining a= copy * of this software and associated documentation files (the "Software"), t= o deal @@ -37,27 +37,12 @@ typedef struct PPC4xxI2CState { /*< private >*/ SysBusDevice parent_obj; + void *regs; =20 /*< public >*/ I2CBus *bus; qemu_irq irq; MemoryRegion iomem; - uint8_t mdata; - uint8_t lmadr; - uint8_t hmadr; - uint8_t cntl; - uint8_t mdcntl; - uint8_t sts; - uint8_t extsts; - uint8_t sdata; - uint8_t lsadr; - uint8_t hsadr; - uint8_t clkdiv; - uint8_t intrmsk; - uint8_t xfrcnt; - uint8_t xtcntlss; - uint8_t directcntl; - uint8_t intr; } PPC4xxI2CState; =20 #endif /* PPC4XX_I2C_H */ --=20 2.7.6 From nobody Sat May 4 19:43:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1528293584478961.910330763888; Wed, 6 Jun 2018 06:59:44 -0700 (PDT) Received: from localhost ([::1]:52596 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fQYyL-00019G-Fr for importer@patchew.org; Wed, 06 Jun 2018 09:59:33 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40171) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fQYwW-0008Q4-0Y for qemu-devel@nongnu.org; Wed, 06 Jun 2018 09:57:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fQYwT-0000VU-1I for qemu-devel@nongnu.org; Wed, 06 Jun 2018 09:57:40 -0400 Received: from zero.eik.bme.hu ([2001:738:2001:2001::2001]:44612) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fQYwS-0000Ob-NN; Wed, 06 Jun 2018 09:57:36 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 95F017456B7; Wed, 6 Jun 2018 15:57:28 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 0909A7456B4; Wed, 6 Jun 2018 15:57:28 +0200 (CEST) Message-Id: In-Reply-To: References: From: BALATON Zoltan Date: Wed, 06 Jun 2018 15:31:48 +0200 To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:738:2001:2001::2001 Subject: [Qemu-devel] [PATCH v2 3/8] ppc4xx_i2c: Implement directcntl register X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alexander Graf , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: BALATON Zoltan --- default-configs/ppc-softmmu.mak | 1 + default-configs/ppcemb-softmmu.mak | 1 + hw/i2c/ppc4xx_i2c.c | 14 +++++++++++++- 3 files changed, 15 insertions(+), 1 deletion(-) diff --git a/default-configs/ppc-softmmu.mak b/default-configs/ppc-softmmu.= mak index 4d7be45..7d0dc2f 100644 --- a/default-configs/ppc-softmmu.mak +++ b/default-configs/ppc-softmmu.mak @@ -26,6 +26,7 @@ CONFIG_USB_EHCI_SYSBUS=3Dy CONFIG_SM501=3Dy CONFIG_IDE_SII3112=3Dy CONFIG_I2C=3Dy +CONFIG_BITBANG_I2C=3Dy =20 # For Macs CONFIG_MAC=3Dy diff --git a/default-configs/ppcemb-softmmu.mak b/default-configs/ppcemb-so= ftmmu.mak index 67d18b2..37af193 100644 --- a/default-configs/ppcemb-softmmu.mak +++ b/default-configs/ppcemb-softmmu.mak @@ -19,3 +19,4 @@ CONFIG_USB_EHCI_SYSBUS=3Dy CONFIG_SM501=3Dy CONFIG_IDE_SII3112=3Dy CONFIG_I2C=3Dy +CONFIG_BITBANG_I2C=3Dy diff --git a/hw/i2c/ppc4xx_i2c.c b/hw/i2c/ppc4xx_i2c.c index a68b5f7..5806209 100644 --- a/hw/i2c/ppc4xx_i2c.c +++ b/hw/i2c/ppc4xx_i2c.c @@ -30,6 +30,7 @@ #include "cpu.h" #include "hw/hw.h" #include "hw/i2c/ppc4xx_i2c.h" +#include "bitbang_i2c.h" =20 #define PPC4xx_I2C_MEM_SIZE 18 =20 @@ -46,7 +47,13 @@ =20 #define IIC_XTCNTLSS_SRST (1 << 0) =20 +#define IIC_DIRECTCNTL_SDAC (1 << 3) +#define IIC_DIRECTCNTL_SCLC (1 << 2) +#define IIC_DIRECTCNTL_MSDA (1 << 1) +#define IIC_DIRECTCNTL_MSCL (1 << 0) + typedef struct { + bitbang_i2c_interface *bitbang; uint8_t mdata; uint8_t lmadr; uint8_t hmadr; @@ -308,7 +315,11 @@ static void ppc4xx_i2c_writeb(void *opaque, hwaddr add= r, uint64_t value, i2c->xtcntlss =3D value; break; case 16: - i2c->directcntl =3D value & 0x7; + i2c->directcntl =3D value & (IIC_DIRECTCNTL_SDAC & IIC_DIRECTCNTL_= SCLC); + i2c->directcntl |=3D (value & IIC_DIRECTCNTL_SCLC ? 1 : 0); + bitbang_i2c_set(i2c->bitbang, BITBANG_I2C_SCL, i2c->directcntl & 1= ); + i2c->directcntl |=3D bitbang_i2c_set(i2c->bitbang, BITBANG_I2C_SDA, + (value & IIC_DIRECTCNTL_SDAC) !=3D 0) << 1; break; default: if (addr < PPC4xx_I2C_MEM_SIZE) { @@ -343,6 +354,7 @@ static void ppc4xx_i2c_init(Object *o) sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); sysbus_init_irq(SYS_BUS_DEVICE(s), &s->irq); s->bus =3D i2c_init_bus(DEVICE(s), "i2c"); + r->bitbang =3D bitbang_i2c_init(s->bus); } =20 static void ppc4xx_i2c_class_init(ObjectClass *klass, void *data) --=20 2.7.6 From nobody Sat May 4 19:43:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1528293757302410.96540439864293; Wed, 6 Jun 2018 07:02:37 -0700 (PDT) Received: from localhost ([::1]:52620 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fQZ1D-0004MJ-Vi for importer@patchew.org; Wed, 06 Jun 2018 10:02:32 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40170) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fQYwW-0008Q3-0J for qemu-devel@nongnu.org; Wed, 06 Jun 2018 09:57:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fQYwT-0000Vo-4a for qemu-devel@nongnu.org; Wed, 06 Jun 2018 09:57:40 -0400 Received: from zero.eik.bme.hu ([2001:738:2001:2001::2001]:44608) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fQYwS-0000OU-NV; Wed, 06 Jun 2018 09:57:37 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 6B71A7456BC; Wed, 6 Jun 2018 15:57:28 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 0C78D7456B7; Wed, 6 Jun 2018 15:57:28 +0200 (CEST) Message-Id: In-Reply-To: References: From: BALATON Zoltan Date: Wed, 06 Jun 2018 15:31:48 +0200 To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:738:2001:2001::2001 Subject: [Qemu-devel] [PATCH v2 4/8] ppc4xx_i2c: Rewrite to model hardware more closely X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alexander Graf , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Rewrite to make it closer to how real device works so that guest OS drivers can access I2C devices. Previously this was only a hack to allow U-Boot to get past accessing SPD EEPROMs but to support other I2C devices and allow guests to access them we need to model real device more properly. Signed-off-by: BALATON Zoltan --- Can't split this up more but since previous version really only worked with U-Boot and this version still works with that what else could break? This version however also works with AROS, Linux and AmigaOS. So it's an improvement and if something else breaks due to this then that's a bug that should be fixed separately instead of this patch being dropped. hw/i2c/ppc4xx_i2c.c | 223 +++++++++++++++++++++++++------------------------= --- 1 file changed, 109 insertions(+), 114 deletions(-) diff --git a/hw/i2c/ppc4xx_i2c.c b/hw/i2c/ppc4xx_i2c.c index 5806209..8c381ec 100644 --- a/hw/i2c/ppc4xx_i2c.c +++ b/hw/i2c/ppc4xx_i2c.c @@ -38,13 +38,26 @@ #define IIC_CNTL_READ (1 << 1) #define IIC_CNTL_CHT (1 << 2) #define IIC_CNTL_RPST (1 << 3) +#define IIC_CNTL_AMD (1 << 6) +#define IIC_CNTL_HMT (1 << 7) + +#define IIC_MDCNTL_EINT (1 << 2) +#define IIC_MDCNTL_ESM (1 << 3) +#define IIC_MDCNTL_FMDB (1 << 6) =20 #define IIC_STS_PT (1 << 0) +#define IIC_STS_IRQA (1 << 1) #define IIC_STS_ERR (1 << 2) +#define IIC_STS_MDBF (1 << 4) #define IIC_STS_MDBS (1 << 5) =20 #define IIC_EXTSTS_XFRA (1 << 0) =20 +#define IIC_INTRMSK_EIMTC (1 << 0) +#define IIC_INTRMSK_EITA (1 << 1) +#define IIC_INTRMSK_EIIC (1 << 2) +#define IIC_INTRMSK_EIHE (1 << 3) + #define IIC_XTCNTLSS_SRST (1 << 0) =20 #define IIC_DIRECTCNTL_SDAC (1 << 3) @@ -54,7 +67,8 @@ =20 typedef struct { bitbang_i2c_interface *bitbang; - uint8_t mdata; + int mdidx; + uint8_t mdata[4]; uint8_t lmadr; uint8_t hmadr; uint8_t cntl; @@ -74,21 +88,13 @@ static void ppc4xx_i2c_reset(DeviceState *s) { PPC4xxI2CRegs *i2c =3D PPC4xx_I2C(s)->regs; =20 - /* FIXME: Should also reset bus? - *if (s->address !=3D ADDR_RESET) { - * i2c_end_transfer(s->bus); - *} - */ - - i2c->mdata =3D 0; - i2c->lmadr =3D 0; - i2c->hmadr =3D 0; + i2c->mdidx =3D -1; + memset(i2c->mdata, 0, ARRAY_SIZE(i2c->mdata)); + /* [hl][ms]addr are not affected by reset */ i2c->cntl =3D 0; i2c->mdcntl =3D 0; i2c->sts =3D 0; - i2c->extsts =3D 0x8f; - i2c->lsadr =3D 0; - i2c->hsadr =3D 0; + i2c->extsts =3D (1 << 6); i2c->clkdiv =3D 0; i2c->intrmsk =3D 0; i2c->xfrcnt =3D 0; @@ -96,70 +102,30 @@ static void ppc4xx_i2c_reset(DeviceState *s) i2c->directcntl =3D 0xf; } =20 -static inline bool ppc4xx_i2c_is_master(PPC4xxI2CState *i2c) -{ - return true; -} - static uint64_t ppc4xx_i2c_readb(void *opaque, hwaddr addr, unsigned int s= ize) { PPC4xxI2CState *s =3D PPC4xx_I2C(opaque); PPC4xxI2CRegs *i2c =3D s->regs; uint64_t ret; + int i; =20 switch (addr) { case 0: - ret =3D i2c->mdata; - if (ppc4xx_i2c_is_master(s)) { + if (i2c->mdidx < 0) { ret =3D 0xff; - - if (!(i2c->sts & IIC_STS_MDBS)) { - qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to read " - "without starting transfer\n", - TYPE_PPC4xx_I2C, __func__); - } else { - int pending =3D (i2c->cntl >> 4) & 3; - - /* get the next byte */ - int byte =3D i2c_recv(s->bus); - - if (byte < 0) { - qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: read failed " - "for device 0x%02x\n", TYPE_PPC4xx_I2C, - __func__, i2c->lmadr); - ret =3D 0xff; - } else { - ret =3D byte; - /* Raise interrupt if enabled */ - /*ppc4xx_i2c_raise_interrupt(i2c)*/; - } - - if (!pending) { - i2c->sts &=3D ~IIC_STS_MDBS; - /*i2c_end_transfer(s->bus);*/ - /*} else if (i2c->cntl & (IIC_CNTL_RPST | IIC_CNTL_CHT)) {= */ - } else if (pending) { - /* current smbus implementation doesn't like - multibyte xfer repeated start */ - i2c_end_transfer(s->bus); - if (i2c_start_transfer(s->bus, i2c->lmadr >> 1, 1)) { - /* if non zero is returned, the adress is not vali= d */ - i2c->sts &=3D ~IIC_STS_PT; - i2c->sts |=3D IIC_STS_ERR; - i2c->extsts |=3D IIC_EXTSTS_XFRA; - } else { - /*i2c->sts |=3D IIC_STS_PT;*/ - i2c->sts |=3D IIC_STS_MDBS; - i2c->sts &=3D ~IIC_STS_ERR; - i2c->extsts =3D 0; - } - } - pending--; - i2c->cntl =3D (i2c->cntl & 0xcf) | (pending << 4); - } - } else { - qemu_log_mask(LOG_UNIMP, "[%s]%s: slave mode not implemented\n= ", - TYPE_PPC4xx_I2C, __func__); + break; + } + ret =3D i2c->mdata[0]; + if (i2c->mdidx =3D=3D 3) { + i2c->sts &=3D ~IIC_STS_MDBF; + } else if (i2c->mdidx =3D=3D 0) { + i2c->sts &=3D ~IIC_STS_MDBS; + } + for (i =3D 0; i < i2c->mdidx; i++) { + i2c->mdata[i] =3D i2c->mdata[i + 1]; + } + if (i2c->mdidx >=3D 0) { + i2c->mdidx--; } break; case 4: @@ -179,6 +145,7 @@ static uint64_t ppc4xx_i2c_readb(void *opaque, hwaddr a= ddr, unsigned int size) break; case 9: ret =3D i2c->extsts; + ret |=3D !!i2c_bus_busy(s->bus) << 4; break; case 10: ret =3D i2c->lsadr; @@ -223,70 +190,98 @@ static void ppc4xx_i2c_writeb(void *opaque, hwaddr ad= dr, uint64_t value, =20 switch (addr) { case 0: - i2c->mdata =3D value; - if (!i2c_bus_busy(s->bus)) { - /* assume we start a write transfer */ - if (i2c_start_transfer(s->bus, i2c->lmadr >> 1, 0)) { - /* if non zero is returned, the adress is not valid */ - i2c->sts &=3D ~IIC_STS_PT; - i2c->sts |=3D IIC_STS_ERR; - i2c->extsts |=3D IIC_EXTSTS_XFRA; - } else { - i2c->sts |=3D IIC_STS_PT; - i2c->sts &=3D ~IIC_STS_ERR; - i2c->extsts =3D 0; - } + if (i2c->mdidx >=3D 3) { + break; } - if (i2c_bus_busy(s->bus)) { - if (i2c_send(s->bus, i2c->mdata)) { - /* if the target return non zero then end the transfer */ - i2c->sts &=3D ~IIC_STS_PT; - i2c->sts |=3D IIC_STS_ERR; - i2c->extsts |=3D IIC_EXTSTS_XFRA; - i2c_end_transfer(s->bus); - } + i2c->mdata[++i2c->mdidx] =3D value; + if (i2c->mdidx =3D=3D 3) { + i2c->sts |=3D IIC_STS_MDBF; + } else if (i2c->mdidx =3D=3D 0) { + i2c->sts |=3D IIC_STS_MDBS; } break; case 4: i2c->lmadr =3D value; - if (i2c_bus_busy(s->bus)) { - i2c_end_transfer(s->bus); - } break; case 5: i2c->hmadr =3D value; break; case 6: - i2c->cntl =3D value; - if (i2c->cntl & IIC_CNTL_PT) { - if (i2c->cntl & IIC_CNTL_READ) { - if (i2c_bus_busy(s->bus)) { - /* end previous transfer */ - i2c->sts &=3D ~IIC_STS_PT; - i2c_end_transfer(s->bus); + i2c->cntl =3D value & 0xfe; + if (value & IIC_CNTL_AMD) { + qemu_log_mask(LOG_UNIMP, "%s: only 7 bit addresses supported\n= ", + __func__); + } + if (value & IIC_CNTL_HMT && i2c_bus_busy(s->bus)) { + i2c_end_transfer(s->bus); + if (i2c->mdcntl & IIC_MDCNTL_EINT && + i2c->intrmsk & IIC_INTRMSK_EIHE) { + i2c->sts |=3D IIC_STS_IRQA; + qemu_irq_raise(s->irq); + } + } else if (value & IIC_CNTL_PT) { + int recv =3D (value & IIC_CNTL_READ) >> 1; + int tct =3D value >> 4 & 3; + int i; + + if (recv && (i2c->lmadr >> 1) >=3D 0x50 && (i2c->lmadr >> 1) <= 0x58) { + /* smbus emulation does not like multi byte reads w/o rest= art */ + value |=3D IIC_CNTL_RPST; + } + + for (i =3D 0; i <=3D tct; i++) { + if (!i2c_bus_busy(s->bus)) { + i2c->extsts =3D (1 << 6); + if (i2c_start_transfer(s->bus, i2c->lmadr >> 1, recv))= { + i2c->sts |=3D IIC_STS_ERR; + i2c->extsts |=3D IIC_EXTSTS_XFRA; + break; + } else { + i2c->sts &=3D ~IIC_STS_ERR; + } + } + if (!(i2c->sts & IIC_STS_ERR) && + i2c_send_recv(s->bus, &i2c->mdata[i], !recv)) { + i2c->sts |=3D IIC_STS_ERR; + i2c->extsts |=3D IIC_EXTSTS_XFRA; + break; } - if (i2c_start_transfer(s->bus, i2c->lmadr >> 1, 1)) { - /* if non zero is returned, the adress is not valid */ - i2c->sts &=3D ~IIC_STS_PT; - i2c->sts |=3D IIC_STS_ERR; - i2c->extsts |=3D IIC_EXTSTS_XFRA; - } else { - /*i2c->sts |=3D IIC_STS_PT;*/ - i2c->sts |=3D IIC_STS_MDBS; - i2c->sts &=3D ~IIC_STS_ERR; - i2c->extsts =3D 0; + if (value & IIC_CNTL_RPST || !(value & IIC_CNTL_CHT)) { + i2c_end_transfer(s->bus); } - } else { - /* we actually already did the write transfer... */ - i2c->sts &=3D ~IIC_STS_PT; + } + i2c->xfrcnt =3D i; + i2c->mdidx =3D i - 1; + if (recv && i2c->mdidx >=3D 0) { + i2c->sts |=3D IIC_STS_MDBS; + } + if (recv && i2c->mdidx =3D=3D 3) { + i2c->sts |=3D IIC_STS_MDBF; + } + if (i && i2c->mdcntl & IIC_MDCNTL_EINT && + i2c->intrmsk & IIC_INTRMSK_EIMTC) { + i2c->sts |=3D IIC_STS_IRQA; + qemu_irq_raise(s->irq); } } break; case 7: - i2c->mdcntl =3D value & 0xdf; + i2c->mdcntl =3D value & 0x3d; + if (value & IIC_MDCNTL_ESM) { + qemu_log_mask(LOG_UNIMP, "%s: slave mode not implemented\n", + __func__); + } + if (value & IIC_MDCNTL_FMDB) { + i2c->mdidx =3D -1; + memset(i2c->mdata, 0, ARRAY_SIZE(i2c->mdata)); + i2c->sts &=3D ~(IIC_STS_MDBF | IIC_STS_MDBS); + } break; case 8: i2c->sts &=3D ~(value & 0xa); + if (value & IIC_STS_IRQA && i2c->mdcntl & IIC_MDCNTL_EINT) { + qemu_irq_lower(s->irq); + } break; case 9: i2c->extsts &=3D ~(value & 0x8f); @@ -307,12 +302,12 @@ static void ppc4xx_i2c_writeb(void *opaque, hwaddr ad= dr, uint64_t value, i2c->xfrcnt =3D value & 0x77; break; case 15: + i2c->xtcntlss &=3D ~(value & 0xf0); if (value & IIC_XTCNTLSS_SRST) { /* Is it actually a full reset? U-Boot sets some regs before */ ppc4xx_i2c_reset(DEVICE(s)); break; } - i2c->xtcntlss =3D value; break; case 16: i2c->directcntl =3D value & (IIC_DIRECTCNTL_SDAC & IIC_DIRECTCNTL_= SCLC); --=20 2.7.6 From nobody Sat May 4 19:43:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1528293583721724.6100550602647; Wed, 6 Jun 2018 06:59:43 -0700 (PDT) Received: from localhost ([::1]:52598 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fQYyN-0001BR-SH for importer@patchew.org; Wed, 06 Jun 2018 09:59:35 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40177) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fQYwW-0008Q7-59 for qemu-devel@nongnu.org; Wed, 06 Jun 2018 09:57:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fQYwT-0000Vc-2l for qemu-devel@nongnu.org; Wed, 06 Jun 2018 09:57:40 -0400 Received: from zero.eik.bme.hu ([152.66.115.2]:44610) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fQYwS-0000Oa-Mh; Wed, 06 Jun 2018 09:57:37 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 91C8E7456B3; Wed, 6 Jun 2018 15:57:28 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 102887456B8; Wed, 6 Jun 2018 15:57:28 +0200 (CEST) Message-Id: <8c404c8c4ee1bfd2e4d079877d481094f797df8f.1528291908.git.balaton@eik.bme.hu> In-Reply-To: References: From: BALATON Zoltan Date: Wed, 06 Jun 2018 15:31:48 +0200 To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 152.66.115.2 Subject: [Qemu-devel] [PATCH v2 5/8] hw/timer: Add basic M41T80 emulation X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alexander Graf , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Basic emulation of the M41T80 serial (I2C) RTC chip. Only getting time of day is implemented. Setting time and RTC alarm are not supported. Signed-off-by: BALATON Zoltan --- MAINTAINERS | 1 + default-configs/ppc-softmmu.mak | 1 + hw/timer/Makefile.objs | 1 + hw/timer/m41t80.c | 117 ++++++++++++++++++++++++++++++++++++= ++++ 4 files changed, 120 insertions(+) create mode 100644 hw/timer/m41t80.c diff --git a/MAINTAINERS b/MAINTAINERS index 41cd373..9e13bc1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -826,6 +826,7 @@ M: BALATON Zoltan L: qemu-ppc@nongnu.org S: Maintained F: hw/ide/sii3112.c +F: hw/timer/m41t80.c =20 SH4 Machines ------------ diff --git a/default-configs/ppc-softmmu.mak b/default-configs/ppc-softmmu.= mak index 7d0dc2f..9fbaadc 100644 --- a/default-configs/ppc-softmmu.mak +++ b/default-configs/ppc-softmmu.mak @@ -27,6 +27,7 @@ CONFIG_SM501=3Dy CONFIG_IDE_SII3112=3Dy CONFIG_I2C=3Dy CONFIG_BITBANG_I2C=3Dy +CONFIG_M41T80=3Dy =20 # For Macs CONFIG_MAC=3Dy diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs index 8b27a4b..e16b2b9 100644 --- a/hw/timer/Makefile.objs +++ b/hw/timer/Makefile.objs @@ -6,6 +6,7 @@ common-obj-$(CONFIG_CADENCE) +=3D cadence_ttc.o common-obj-$(CONFIG_DS1338) +=3D ds1338.o common-obj-$(CONFIG_HPET) +=3D hpet.o common-obj-$(CONFIG_I8254) +=3D i8254_common.o i8254.o +common-obj-$(CONFIG_M41T80) +=3D m41t80.o common-obj-$(CONFIG_M48T59) +=3D m48t59.o ifeq ($(CONFIG_ISA_BUS),y) common-obj-$(CONFIG_M48T59) +=3D m48t59-isa.o diff --git a/hw/timer/m41t80.c b/hw/timer/m41t80.c new file mode 100644 index 0000000..9dbdb1b --- /dev/null +++ b/hw/timer/m41t80.c @@ -0,0 +1,117 @@ +/* + * M41T80 serial rtc emulation + * + * Copyright (c) 2018 BALATON Zoltan + * + * This work is licensed under the GNU GPL license version 2 or later. + * + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/timer.h" +#include "qemu/bcd.h" +#include "hw/i2c/i2c.h" + +#define TYPE_M41T80 "m41t80" +#define M41T80(obj) OBJECT_CHECK(M41t80State, (obj), TYPE_M41T80) + +typedef struct M41t80State { + I2CSlave parent_obj; + int8_t addr; +} M41t80State; + +static void m41t80_realize(DeviceState *dev, Error **errp) +{ + M41t80State *s =3D M41T80(dev); + + s->addr =3D -1; +} + +static int m41t80_send(I2CSlave *i2c, uint8_t data) +{ + M41t80State *s =3D M41T80(i2c); + + if (s->addr < 0) { + s->addr =3D data; + } else { + s->addr++; + } + return 0; +} + +static int m41t80_recv(I2CSlave *i2c) +{ + M41t80State *s =3D M41T80(i2c); + struct tm now; + qemu_timeval tv; + + if (s->addr < 0) { + s->addr =3D 0; + } + if (s->addr >=3D 1 && s->addr <=3D 7) { + qemu_get_timedate(&now, -1); + } + switch (s->addr++) { + case 0: + qemu_gettimeofday(&tv); + return to_bcd(tv.tv_usec / 10000); + case 1: + return to_bcd(now.tm_sec); + case 2: + return to_bcd(now.tm_min); + case 3: + return to_bcd(now.tm_hour); + case 4: + return to_bcd(now.tm_wday); + case 5: + return to_bcd(now.tm_mday); + case 6: + return to_bcd(now.tm_mon + 1); + case 7: + return to_bcd(now.tm_year % 100); + case 8 ... 19: + qemu_log_mask(LOG_UNIMP, "\n%s: unimplemented register: %d\n", + __func__, s->addr - 1); + return 0; + default: + qemu_log_mask(LOG_GUEST_ERROR, "\n%s: invalid register: %d", + __func__, s->addr - 1); + return 0; + } +} + +static int m41t80_event(I2CSlave *i2c, enum i2c_event event) +{ + M41t80State *s =3D M41T80(i2c); + + if (event =3D=3D I2C_START_SEND) { + s->addr =3D -1; + } + return 0; +} + +static void m41t80_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + I2CSlaveClass *sc =3D I2C_SLAVE_CLASS(klass); + + dc->realize =3D m41t80_realize; + sc->send =3D m41t80_send; + sc->recv =3D m41t80_recv; + sc->event =3D m41t80_event; +} + +static const TypeInfo m41t80_info =3D { + .name =3D TYPE_M41T80, + .parent =3D TYPE_I2C_SLAVE, + .instance_size =3D sizeof(M41t80State), + .class_init =3D m41t80_class_init, +}; + +static void m41t80_register_types(void) +{ + type_register_static(&m41t80_info); +} + +type_init(m41t80_register_types) --=20 2.7.6 From nobody Sat May 4 19:43:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1528293757185350.4582468734976; Wed, 6 Jun 2018 07:02:37 -0700 (PDT) Received: from localhost ([::1]:52622 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fQZ1E-0004NH-AW for importer@patchew.org; Wed, 06 Jun 2018 10:02:32 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40216) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fQYwX-0008QY-Tc for qemu-devel@nongnu.org; Wed, 06 Jun 2018 09:57:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fQYwU-0000Wd-3y for qemu-devel@nongnu.org; Wed, 06 Jun 2018 09:57:41 -0400 Received: from zero.eik.bme.hu ([2001:738:2001:2001::2001]:44634) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fQYwT-0000Vh-TD; Wed, 06 Jun 2018 09:57:38 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id A98257456A0; Wed, 6 Jun 2018 15:57:28 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 13B397456B9; Wed, 6 Jun 2018 15:57:28 +0200 (CEST) Message-Id: <79ec5d3a052aa8380f57a1f0778b0a0584192e49.1528291908.git.balaton@eik.bme.hu> In-Reply-To: References: From: BALATON Zoltan Date: Wed, 06 Jun 2018 15:31:48 +0200 To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:738:2001:2001::2001 Subject: [Qemu-devel] [PATCH v2 6/8] sam460ex: Add RTC device X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alexander Graf , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The Sam460ex has an M41T80 serial RTC chip on I2C bus 0 at address 0x68. Signed-off-by: BALATON Zoltan --- hw/ppc/sam460ex.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c index bdc53d2..dc730cc 100644 --- a/hw/ppc/sam460ex.c +++ b/hw/ppc/sam460ex.c @@ -457,6 +457,7 @@ static void sam460ex_init(MachineState *machine) object_property_set_bool(OBJECT(dev), true, "realized", NULL); smbus_eeprom_init(i2c[0]->bus, 8, smbus_eeprom_buf, smbus_eeprom_size); g_free(smbus_eeprom_buf); + i2c_create_slave(i2c[0]->bus, "m41t80", 0x68); =20 dev =3D sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600800, uic[0][3]); i2c[1] =3D PPC4xx_I2C(dev); --=20 2.7.6 From nobody Sat May 4 19:43:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1528294050752378.2562059290052; Wed, 6 Jun 2018 07:07:30 -0700 (PDT) Received: from localhost ([::1]:52656 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fQZ61-0000J8-SD for importer@patchew.org; Wed, 06 Jun 2018 10:07:29 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40284) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fQYwZ-0008Sc-VR for qemu-devel@nongnu.org; Wed, 06 Jun 2018 09:57:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fQYwU-0000Wp-7h for qemu-devel@nongnu.org; Wed, 06 Jun 2018 09:57:44 -0400 Received: from zero.eik.bme.hu ([2001:738:2001:2001::2001]:44635) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fQYwU-0000W0-0U; Wed, 06 Jun 2018 09:57:38 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id AEDCB7456B5; Wed, 6 Jun 2018 15:57:28 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 17C497456BA; Wed, 6 Jun 2018 15:57:28 +0200 (CEST) Message-Id: In-Reply-To: References: From: BALATON Zoltan Date: Wed, 06 Jun 2018 15:31:48 +0200 To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:738:2001:2001::2001 Subject: [Qemu-devel] [PATCH v2 7/8] sm501: Do not clear read only bits when writing register X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Alexander Graf , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" When writing a register that has read only bits besides reserved bits we have to avoid changing read only bits that may have non zero default values. Signed-off-by: BALATON Zoltan --- hw/display/sm501.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/display/sm501.c b/hw/display/sm501.c index e47be99..7ec1434 100644 --- a/hw/display/sm501.c +++ b/hw/display/sm501.c @@ -836,10 +836,10 @@ static void sm501_system_config_write(void *opaque, h= waddr addr, =20 switch (addr) { case SM501_SYSTEM_CONTROL: - s->system_control =3D value & 0xE300B8F7; + s->system_control |=3D value & 0xEF00B8F7; break; case SM501_MISC_CONTROL: - s->misc_control =3D value & 0xFF7FFF20; + s->misc_control |=3D value & 0xFF7FFF10; break; case SM501_GPIO31_0_CONTROL: s->gpio_31_0_control =3D value; @@ -853,7 +853,7 @@ static void sm501_system_config_write(void *opaque, hwa= ddr addr, s->dram_control |=3D value & 0x7FFFFFC3; break; case SM501_ARBTRTN_CONTROL: - s->arbitration_control =3D value & 0x37777777; + s->arbitration_control =3D value & 0x37777777; break; case SM501_IRQ_MASK: s->irq_mask =3D value; --=20 2.7.6 From nobody Sat May 4 19:43:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 152829375723240.701587454933815; Wed, 6 Jun 2018 07:02:37 -0700 (PDT) Received: from localhost ([::1]:52623 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fQZ1E-0004Og-HJ for importer@patchew.org; Wed, 06 Jun 2018 10:02:32 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40176) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fQYwW-0008Q6-4i for qemu-devel@nongnu.org; Wed, 06 Jun 2018 09:57:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fQYwU-0000X5-Er for qemu-devel@nongnu.org; Wed, 06 Jun 2018 09:57:40 -0400 Received: from zero.eik.bme.hu ([2001:738:2001:2001::2001]:44636) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fQYwU-0000W1-0g; Wed, 06 Jun 2018 09:57:38 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id D0C4A7456B9; Wed, 6 Jun 2018 15:57:28 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 1CBD37456BB; Wed, 6 Jun 2018 15:57:28 +0200 (CEST) Message-Id: <49bd881dc323dfd61cbb0773ac248a32c441d4c2.1528291908.git.balaton@eik.bme.hu> In-Reply-To: References: From: BALATON Zoltan Date: Wed, 06 Jun 2018 15:31:48 +0200 To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:738:2001:2001::2001 Subject: [Qemu-devel] [PATCH v2 8/8] sm501: Implement i2c part for reading monitor EDID X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Alexander Graf , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: BALATON Zoltan --- default-configs/ppc-softmmu.mak | 1 + default-configs/ppcemb-softmmu.mak | 1 + default-configs/sh4-softmmu.mak | 1 + default-configs/sh4eb-softmmu.mak | 1 + hw/display/sm501.c | 136 +++++++++++++++++++++++++++++++++= ++-- 5 files changed, 136 insertions(+), 4 deletions(-) diff --git a/default-configs/ppc-softmmu.mak b/default-configs/ppc-softmmu.= mak index 9fbaadc..860de80 100644 --- a/default-configs/ppc-softmmu.mak +++ b/default-configs/ppc-softmmu.mak @@ -24,6 +24,7 @@ CONFIG_ETSEC=3Dy # For Sam460ex CONFIG_USB_EHCI_SYSBUS=3Dy CONFIG_SM501=3Dy +CONFIG_DDC=3Dy CONFIG_IDE_SII3112=3Dy CONFIG_I2C=3Dy CONFIG_BITBANG_I2C=3Dy diff --git a/default-configs/ppcemb-softmmu.mak b/default-configs/ppcemb-so= ftmmu.mak index 37af193..ac44f15 100644 --- a/default-configs/ppcemb-softmmu.mak +++ b/default-configs/ppcemb-softmmu.mak @@ -17,6 +17,7 @@ CONFIG_XILINX=3Dy CONFIG_XILINX_ETHLITE=3Dy CONFIG_USB_EHCI_SYSBUS=3Dy CONFIG_SM501=3Dy +CONFIG_DDC=3Dy CONFIG_IDE_SII3112=3Dy CONFIG_I2C=3Dy CONFIG_BITBANG_I2C=3Dy diff --git a/default-configs/sh4-softmmu.mak b/default-configs/sh4-softmmu.= mak index 546d855..72d8fca 100644 --- a/default-configs/sh4-softmmu.mak +++ b/default-configs/sh4-softmmu.mak @@ -9,6 +9,7 @@ CONFIG_PFLASH_CFI02=3Dy CONFIG_SH4=3Dy CONFIG_IDE_MMIO=3Dy CONFIG_SM501=3Dy +CONFIG_DDC=3Dy CONFIG_ISA_TESTDEV=3Dy CONFIG_I82378=3Dy CONFIG_I8259=3Dy diff --git a/default-configs/sh4eb-softmmu.mak b/default-configs/sh4eb-soft= mmu.mak index 2d3fd49..c686637 100644 --- a/default-configs/sh4eb-softmmu.mak +++ b/default-configs/sh4eb-softmmu.mak @@ -9,6 +9,7 @@ CONFIG_PFLASH_CFI02=3Dy CONFIG_SH4=3Dy CONFIG_IDE_MMIO=3Dy CONFIG_SM501=3Dy +CONFIG_DDC=3Dy CONFIG_ISA_TESTDEV=3Dy CONFIG_I82378=3Dy CONFIG_I8259=3Dy diff --git a/hw/display/sm501.c b/hw/display/sm501.c index 7ec1434..d357583 100644 --- a/hw/display/sm501.c +++ b/hw/display/sm501.c @@ -26,6 +26,7 @@ #include "qemu/osdep.h" #include "qemu/cutils.h" #include "qapi/error.h" +#include "qemu/log.h" #include "qemu-common.h" #include "cpu.h" #include "hw/hw.h" @@ -34,6 +35,8 @@ #include "hw/devices.h" #include "hw/sysbus.h" #include "hw/pci/pci.h" +#include "hw/i2c/i2c.h" +#include "hw/i2c/i2c-ddc.h" #include "qemu/range.h" #include "ui/pixel_ops.h" =20 @@ -471,10 +474,12 @@ typedef struct SM501State { MemoryRegion local_mem_region; MemoryRegion mmio_region; MemoryRegion system_config_region; + MemoryRegion i2c_region; MemoryRegion disp_ctrl_region; MemoryRegion twoD_engine_region; uint32_t last_width; uint32_t last_height; + I2CBus *i2c_bus; =20 /* mmio registers */ uint32_t system_control; @@ -487,6 +492,11 @@ typedef struct SM501State { uint32_t misc_timing; uint32_t power_mode_control; =20 + uint8_t i2c_byte_count; + uint8_t i2c_status; + uint8_t i2c_addr; + uint8_t i2c_data[16]; + uint32_t uart0_ier; uint32_t uart0_lcr; uint32_t uart0_mcr; @@ -894,6 +904,107 @@ static const MemoryRegionOps sm501_system_config_ops = =3D { .endianness =3D DEVICE_LITTLE_ENDIAN, }; =20 +static uint64_t sm501_i2c_read(void *opaque, hwaddr addr, unsigned size) +{ + SM501State *s =3D (SM501State *)opaque; + uint8_t ret =3D 0; + + switch (addr) { + case SM501_I2C_BYTE_COUNT: + ret =3D s->i2c_byte_count; + break; + case SM501_I2C_STATUS: + ret =3D s->i2c_status; + break; + case SM501_I2C_SLAVE_ADDRESS: + ret =3D s->i2c_addr; + break; + case SM501_I2C_DATA ... SM501_I2C_DATA + 15: + ret =3D s->i2c_data[addr - SM501_I2C_DATA]; + break; + default: + qemu_log_mask(LOG_UNIMP, "sm501 i2c : not implemented register rea= d." + " addr=3D0x%" HWADDR_PRIx "\n", addr); + } + + SM501_DPRINTF("sm501 i2c regs : read addr=3D%" HWADDR_PRIx " val=3D%x\= n", + addr, ret); + return ret; +} + +static void sm501_i2c_write(void *opaque, hwaddr addr, uint64_t value, + unsigned size) +{ + SM501State *s =3D (SM501State *)opaque; + SM501_DPRINTF("sm501 i2c regs : write addr=3D%" HWADDR_PRIx + " val=3D%" PRIx64 "\n", addr, value); + + switch (addr) { + case SM501_I2C_BYTE_COUNT: + s->i2c_byte_count =3D value & 0xf; + break; + case SM501_I2C_CONTROL: + if (value & 1) { + if (value & 4) { + int res =3D i2c_start_transfer(s->i2c_bus, + s->i2c_addr >> 1, + s->i2c_addr & 1); + s->i2c_status |=3D (res ? 1 << 2 : 0); + if (!res) { + int i; + SM501_DPRINTF("sm501 i2c : transferring %d bytes to 0x= %x\n", + s->i2c_byte_count + 1, s->i2c_addr >> 1); + for (i =3D 0; i <=3D s->i2c_byte_count; i++) { + res =3D i2c_send_recv(s->i2c_bus, &s->i2c_data[i], + !(s->i2c_addr & 1)); + if (res) { + SM501_DPRINTF("sm501 i2c : transfer failed" + " i=3D%d, res=3D%d\n", i, res); + s->i2c_status |=3D (res ? 1 << 2 : 0); + return; + } + } + if (i) { + SM501_DPRINTF("sm501 i2c : transferred %d bytes\n"= , i); + s->i2c_status =3D 8; + } + } + } else { + SM501_DPRINTF("sm501 i2c : end transfer\n"); + i2c_end_transfer(s->i2c_bus); + s->i2c_status &=3D ~4; + } + } + break; + case SM501_I2C_RESET: + s->i2c_status &=3D ~4; + break; + case SM501_I2C_SLAVE_ADDRESS: + s->i2c_addr =3D value & 0xff; + break; + case SM501_I2C_DATA ... SM501_I2C_DATA + 15: + s->i2c_data[addr - SM501_I2C_DATA] =3D value & 0xff; + break; + default: + qemu_log_mask(LOG_UNIMP, "sm501 i2c : not implemented register wri= te. " + "addr=3D0x%" HWADDR_PRIx " val=3D%" PRIx64 "\n", add= r, value); + } +} + +static const MemoryRegionOps sm501_i2c_ops =3D { + .read =3D sm501_i2c_read, + .write =3D sm501_i2c_write, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 4, + }, + .impl =3D { + .min_access_size =3D 1, + .max_access_size =3D 1, + }, + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; + static uint32_t sm501_palette_read(void *opaque, hwaddr addr) { SM501State *s =3D (SM501State *)opaque; @@ -1574,6 +1685,10 @@ static void sm501_reset(SM501State *s) s->irq_mask =3D 0; s->misc_timing =3D 0; s->power_mode_control =3D 0; + s->i2c_byte_count =3D 0; + s->i2c_status =3D 0; + s->i2c_addr =3D 0; + memset(s->i2c_data, 0, 16); s->dc_panel_control =3D 0x00010000; /* FIFO level 3 */ s->dc_video_control =3D 0; s->dc_crt_control =3D 0x00010000; @@ -1612,6 +1727,11 @@ static void sm501_init(SM501State *s, DeviceState *d= ev, memory_region_set_log(&s->local_mem_region, true, DIRTY_MEMORY_VGA); s->local_mem =3D memory_region_get_ram_ptr(&s->local_mem_region); =20 + /* i2c */ + s->i2c_bus =3D i2c_init_bus(dev, "sm501.i2c"); + I2CDDCState *ddc =3D I2CDDC(qdev_create(BUS(s->i2c_bus), TYPE_I2CDDC)); + i2c_set_slave_address(I2C_SLAVE(ddc), 0x50); + /* mmio */ memory_region_init(&s->mmio_region, OBJECT(dev), "sm501.mmio", MMIO_SI= ZE); memory_region_init_io(&s->system_config_region, OBJECT(dev), @@ -1619,6 +1739,9 @@ static void sm501_init(SM501State *s, DeviceState *de= v, "sm501-system-config", 0x6c); memory_region_add_subregion(&s->mmio_region, SM501_SYS_CONFIG, &s->system_config_region); + memory_region_init_io(&s->i2c_region, OBJECT(dev), &sm501_i2c_ops, s, + "sm501-i2c", 0x14); + memory_region_add_subregion(&s->mmio_region, SM501_I2C, &s->i2c_region= ); memory_region_init_io(&s->disp_ctrl_region, OBJECT(dev), &sm501_disp_ctrl_ops, s, "sm501-disp-ctrl", 0x1000); @@ -1702,6 +1825,11 @@ static const VMStateDescription vmstate_sm501_state = =3D { VMSTATE_UINT32(twoD_destination_base, SM501State), VMSTATE_UINT32(twoD_alpha, SM501State), VMSTATE_UINT32(twoD_wrap, SM501State), + /* Added in version 2 */ + VMSTATE_UINT8(i2c_byte_count, SM501State), + VMSTATE_UINT8(i2c_status, SM501State), + VMSTATE_UINT8(i2c_addr, SM501State), + VMSTATE_UINT8_ARRAY(i2c_data, SM501State, 16), VMSTATE_END_OF_LIST() } }; @@ -1767,8 +1895,8 @@ static void sm501_reset_sysbus(DeviceState *dev) =20 static const VMStateDescription vmstate_sm501_sysbus =3D { .name =3D TYPE_SYSBUS_SM501, - .version_id =3D 1, - .minimum_version_id =3D 1, + .version_id =3D 2, + .minimum_version_id =3D 2, .fields =3D (VMStateField[]) { VMSTATE_STRUCT(state, SM501SysBusState, 1, vmstate_sm501_state, SM501State), @@ -1840,8 +1968,8 @@ static void sm501_reset_pci(DeviceState *dev) =20 static const VMStateDescription vmstate_sm501_pci =3D { .name =3D TYPE_PCI_SM501, - .version_id =3D 1, - .minimum_version_id =3D 1, + .version_id =3D 2, + .minimum_version_id =3D 2, .fields =3D (VMStateField[]) { VMSTATE_PCI_DEVICE(parent_obj, SM501PCIState), VMSTATE_STRUCT(state, SM501PCIState, 1, --=20 2.7.6