From nobody Sat May 4 20:54:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1515960992627856.6271023069855; Sun, 14 Jan 2018 12:16:32 -0800 (PST) Received: from localhost ([::1]:33584 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eaohj-0007l4-II for importer@patchew.org; Sun, 14 Jan 2018 15:16:31 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42012) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eaog6-0006s5-EF for qemu-devel@nongnu.org; Sun, 14 Jan 2018 15:14:52 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eaog3-0005Hc-6E for qemu-devel@nongnu.org; Sun, 14 Jan 2018 15:14:50 -0500 Received: from smtp8.web4u.cz ([81.91.87.88]:45453 helo=mx-8.mail.web4u.cz) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eaog2-0005HI-Rr for qemu-devel@nongnu.org; Sun, 14 Jan 2018 15:14:47 -0500 Received: from mx-8.mail.web4u.cz (localhost [127.0.0.1]) by mx-8.mail.web4u.cz (Postfix) with ESMTP id B44D71FFED4; Sun, 14 Jan 2018 21:14:43 +0100 (CET) Received: from baree.pikron.com (unknown [89.102.4.32]) (Authenticated sender: ppisa@pikron.com) by mx-8.mail.web4u.cz (Postfix) with ESMTPA id 75D7F1FF62C; Sun, 14 Jan 2018 21:14:43 +0100 (CET) From: pisa@cmp.felk.cvut.cz To: qemu-devel@nongnu.org Date: Sun, 14 Jan 2018 21:14:07 +0100 Message-Id: X-Mailer: git-send-email 2.11.0 In-Reply-To: References: In-Reply-To: References: X-W4U-Auth: 5fac0e038ae823ca29dc9391af048e17e700afab X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 81.91.87.88 Subject: [Qemu-devel] [PATCH V4 1/7] CAN bus simple messages transport implementation for QEMU X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marek Vasut , Oliver Hartkopp , Stefan Hajnoczi , Deniz Eren , Oleksij Rempel , Konrad Frederic , Jan Kiszka , Pavel Pisa Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Pavel Pisa The CanBusState state structure is created for each emulated CAN channel. Individual clients/emulated CAN interfaces or host interface connection registers to the bus by CanBusClientState structure. The CAN core is prepared to support connection to the real host CAN bus network. The commit with such support for Linux SocketCAN follows. Implementation is as simple as possible, no migration, messages prioritization and queuing considered for now. But it is intended to be extended when need arises. Development repository and more documentation at https://gitlab.fel.cvut.cz/canbus/qemu-canbus The work is based on Jin Yang GSoC 2013 work funded by Google and mentored in frame of RTEMS project GSoC slot donated to QEMU. Rewritten for QEMU-2.0+ versions and architecture cleanup by Pavel Pisa (Czech Technical University in Prague). Signed-off-by: Pavel Pisa --- default-configs/pci.mak | 1 + hw/Makefile.objs | 1 + hw/can/Makefile.objs | 6 +++ hw/can/can_core.c | 136 ++++++++++++++++++++++++++++++++++++++++++++= ++++ hw/can/can_host_stub.c | 36 +++++++++++++ include/can/can_emu.h | 131 ++++++++++++++++++++++++++++++++++++++++++++= ++ 6 files changed, 311 insertions(+) create mode 100644 hw/can/Makefile.objs create mode 100644 hw/can/can_core.c create mode 100644 hw/can/can_host_stub.c create mode 100644 include/can/can_emu.h diff --git a/default-configs/pci.mak b/default-configs/pci.mak index e514bdef42..bbe11887a1 100644 --- a/default-configs/pci.mak +++ b/default-configs/pci.mak @@ -31,6 +31,7 @@ CONFIG_ESP_PCI=3Dy CONFIG_SERIAL=3Dy CONFIG_SERIAL_ISA=3Dy CONFIG_SERIAL_PCI=3Dy +CONFIG_CAN_CORE=3Dy CONFIG_IPACK=3Dy CONFIG_WDT_IB6300ESB=3Dy CONFIG_PCI_TESTDEV=3Dy diff --git a/hw/Makefile.objs b/hw/Makefile.objs index cf4cb2010b..9d84b8faaa 100644 --- a/hw/Makefile.objs +++ b/hw/Makefile.objs @@ -6,6 +6,7 @@ devices-dirs-$(CONFIG_SOFTMMU) +=3D block/ devices-dirs-$(CONFIG_SOFTMMU) +=3D bt/ devices-dirs-$(CONFIG_SOFTMMU) +=3D char/ devices-dirs-$(CONFIG_SOFTMMU) +=3D cpu/ +devices-dirs-$(CONFIG_SOFTMMU) +=3D can/ devices-dirs-$(CONFIG_SOFTMMU) +=3D display/ devices-dirs-$(CONFIG_SOFTMMU) +=3D dma/ devices-dirs-$(CONFIG_SOFTMMU) +=3D gpio/ diff --git a/hw/can/Makefile.objs b/hw/can/Makefile.objs new file mode 100644 index 0000000000..1028d7c455 --- /dev/null +++ b/hw/can/Makefile.objs @@ -0,0 +1,6 @@ +# CAN bus interfaces emulation and infrastructure + +ifeq ($(CONFIG_CAN_CORE),y) +common-obj-y +=3D can_core.o +common-obj-y +=3D can_host_stub.o +endif diff --git a/hw/can/can_core.c b/hw/can/can_core.c new file mode 100644 index 0000000000..41c458c792 --- /dev/null +++ b/hw/can/can_core.c @@ -0,0 +1,136 @@ +/* + * CAN common CAN bus emulation support + * + * Copyright (c) 2013-2014 Jin Yang + * Copyright (c) 2014-2018 Pavel Pisa + * + * Initial development supported by Google GSoC 2013 from RTEMS project sl= ot + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ +#include "qemu/osdep.h" +#include "chardev/char.h" +#include "qemu/sockets.h" +#include "qemu/error-report.h" +#include "hw/hw.h" +#include "can/can_emu.h" + +static QTAILQ_HEAD(, CanBusState) can_buses =3D + QTAILQ_HEAD_INITIALIZER(can_buses); + +CanBusState *can_bus_find_by_name(const char *name, bool create_missing) +{ + CanBusState *bus; + + if (name =3D=3D NULL) { + name =3D "canbus0"; + } + + QTAILQ_FOREACH(bus, &can_buses, next) { + if (!strcmp(bus->name, name)) { + return bus; + } + } + + if (!create_missing) { + return 0; + } + + bus =3D g_malloc0(sizeof(*bus)); + if (bus =3D=3D NULL) { + return NULL; + } + + QTAILQ_INIT(&bus->clients); + + bus->name =3D g_strdup(name); + + QTAILQ_INSERT_TAIL(&can_buses, bus, next); + return bus; +} + +int can_bus_insert_client(CanBusState *bus, CanBusClientState *client) +{ + client->bus =3D bus; + QTAILQ_INSERT_TAIL(&bus->clients, client, next); + return 0; +} + +int can_bus_remove_client(CanBusClientState *client) +{ + CanBusState *bus =3D client->bus; + if (bus =3D=3D NULL) { + return 0; + } + + QTAILQ_REMOVE(&bus->clients, client, next); + client->bus =3D NULL; + return 1; +} + +ssize_t can_bus_client_send(CanBusClientState *client, + const struct qemu_can_frame *frames, size_t frames_cnt) +{ + int ret =3D 0; + CanBusState *bus =3D client->bus; + CanBusClientState *peer; + if (bus =3D=3D NULL) { + return -1; + } + + QTAILQ_FOREACH(peer, &bus->clients, next) { + if (peer->info->can_receive(peer)) { + if (peer =3D=3D client) { + /* No loopback support for now */ + continue; + } + if (peer->info->receive(peer, frames, frames_cnt) > 0) { + ret =3D 1; + } + } + } + + return ret; +} + +int can_bus_filter_match(struct qemu_can_filter *filter, qemu_canid_t can_= id) +{ + int m; + if (((can_id | filter->can_mask) & QEMU_CAN_ERR_FLAG)) { + return (filter->can_mask & QEMU_CAN_ERR_FLAG) !=3D 0; + } + m =3D (can_id & filter->can_mask) =3D=3D (filter->can_id & filter->can= _mask); + return filter->can_id & QEMU_CAN_INV_FILTER ? !m : m; +} + +int can_bus_client_set_filters(CanBusClientState *client, + const struct qemu_can_filter *filters, size_t filters_cnt) +{ + return 0; +} + +int can_bus_connect_to_host_device(CanBusState *bus, const char *name) +{ + if (can_bus_connect_to_host_variant =3D=3D NULL) { + error_report("CAN bus connect to host device is not " + "supported on this system"); + exit(1); + } + return can_bus_connect_to_host_variant(bus, name); +} diff --git a/hw/can/can_host_stub.c b/hw/can/can_host_stub.c new file mode 100644 index 0000000000..748d25f995 --- /dev/null +++ b/hw/can/can_host_stub.c @@ -0,0 +1,36 @@ +/* + * CAN stub to connect to host system CAN interface + * + * Copyright (c) 2013-2014 Jin Yang + * Copyright (c) 2014-2018 Pavel Pisa + * + * Initial development supported by Google GSoC 2013 from RTEMS project sl= ot + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ +#include "qemu/osdep.h" +#include "chardev/char.h" +#include "qemu/sockets.h" +#include "qemu/error-report.h" +#include "hw/hw.h" +#include "can/can_emu.h" + + +int (*can_bus_connect_to_host_variant)(CanBusState *bus, const char *name)= =3D + NULL; diff --git a/include/can/can_emu.h b/include/can/can_emu.h new file mode 100644 index 0000000000..85237ee3c9 --- /dev/null +++ b/include/can/can_emu.h @@ -0,0 +1,131 @@ +/* + * CAN common CAN bus emulation support + * + * Copyright (c) 2013-2014 Jin Yang + * Copyright (c) 2014-2018 Pavel Pisa + * + * Initial development supported by Google GSoC 2013 from RTEMS project sl= ot + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#ifndef NET_CAN_EMU_H +#define NET_CAN_EMU_H + +#include "qemu/queue.h" + +/* NOTE: the following two structures is copied from . */ + +/* + * Controller Area Network Identifier structure + * + * bit 0-28 : CAN identifier (11/29 bit) + * bit 29 : error frame flag (0 =3D data frame, 1 =3D error frame) + * bit 30 : remote transmission request flag (1 =3D rtr frame) + * bit 31 : frame format flag (0 =3D standard 11 bit, 1 =3D extended = 29 bit) + */ +typedef uint32_t qemu_canid_t; + +typedef struct qemu_can_frame { + qemu_canid_t can_id; /* 32 bit CAN_ID + EFF/RTR/ERR flags */ + uint8_t can_dlc; /* data length code: 0 .. 8 */ + uint8_t data[8] QEMU_ALIGNED(8); +} qemu_can_frame; + +/* Keep defines for QEMU separate from Linux ones for now */ + +#define QEMU_CAN_EFF_FLAG 0x80000000U /* EFF/SFF is set in the MSB */ +#define QEMU_CAN_RTR_FLAG 0x40000000U /* remote transmission request */ +#define QEMU_CAN_ERR_FLAG 0x20000000U /* error message frame */ + +#define QEMU_CAN_SFF_MASK 0x000007FFU /* standard frame format (SFF) */ +#define QEMU_CAN_EFF_MASK 0x1FFFFFFFU /* extended frame format (EFF) */ + +/** + * struct qemu_can_filter - CAN ID based filter in can_register(). + * @can_id: relevant bits of CAN ID which are not masked out. + * @can_mask: CAN mask (see description) + * + * Description: + * A filter matches, when + * + * & mask =3D=3D can_id & mask + * + * The filter can be inverted (QEMU_CAN_INV_FILTER bit set in can_id) or i= t can + * filter for error message frames (QEMU_CAN_ERR_FLAG bit set in mask). + */ +typedef struct qemu_can_filter { + qemu_canid_t can_id; + qemu_canid_t can_mask; +} qemu_can_filter; + +/* QEMU_CAN_INV_FILTER can be set in qemu_can_filter.can_id */ +#define QEMU_CAN_INV_FILTER 0x20000000U + +typedef struct CanBusClientState CanBusClientState; +typedef struct CanBusState CanBusState; + +typedef struct CanBusClientInfo { + size_t size; + int (*can_receive)(CanBusClientState *); + ssize_t (*receive)(CanBusClientState *, + const struct qemu_can_frame *frames, size_t frames_cnt); + void (*cleanup) (CanBusClientState *); + void (*poll)(CanBusClientState *, bool enable); +} CanBusClientInfo; + +struct CanBusClientState { + CanBusClientInfo *info; + CanBusState *bus; + int link_down; + QTAILQ_ENTRY(CanBusClientState) next; + CanBusClientState *peer; + char *model; + char *name; + void (*destructor)(CanBusClientState *); +}; + +struct CanBusState { + char *name; + QTAILQ_HEAD(, CanBusClientState) clients; + QTAILQ_ENTRY(CanBusState) next; +}; + +extern int (*can_bus_connect_to_host_variant)(CanBusState *bus, + const char *name); + +int can_bus_filter_match(struct qemu_can_filter *filter, qemu_canid_t can_= id); + +CanBusState *can_bus_find_by_name(const char *name, bool create_missing); + +int can_bus_insert_client(CanBusState *bus, CanBusClientState *client); + +int can_bus_remove_client(CanBusClientState *client); + +ssize_t can_bus_client_send(CanBusClientState *, + const struct qemu_can_frame *frames, + size_t frames_cnt); + +int can_bus_client_set_filters(CanBusClientState *, + const struct qemu_can_filter *filters, + size_t filters_cnt); + +int can_bus_connect_to_host_device(CanBusState *bus, const char *host_dev_= name); + +#endif --=20 2.11.0 From nobody Sat May 4 20:54:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1515961137558203.1966825103384; Sun, 14 Jan 2018 12:18:57 -0800 (PST) Received: from localhost ([::1]:33652 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eaok4-0000zX-M1 for importer@patchew.org; Sun, 14 Jan 2018 15:18:56 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42094) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eaogX-0007GM-FE for qemu-devel@nongnu.org; Sun, 14 Jan 2018 15:15:18 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eaogU-0005Z0-85 for qemu-devel@nongnu.org; Sun, 14 Jan 2018 15:15:17 -0500 Received: from smtp8.web4u.cz ([81.91.87.88]:45501 helo=mx-8.mail.web4u.cz) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eaogT-0005XM-TX for qemu-devel@nongnu.org; Sun, 14 Jan 2018 15:15:14 -0500 Received: from mx-8.mail.web4u.cz (localhost [127.0.0.1]) by mx-8.mail.web4u.cz (Postfix) with ESMTP id 0D6A6200AED; Sun, 14 Jan 2018 21:15:11 +0100 (CET) Received: from baree.pikron.com (unknown [89.102.4.32]) (Authenticated sender: ppisa@pikron.com) by mx-8.mail.web4u.cz (Postfix) with ESMTPA id C16B5200ABB; Sun, 14 Jan 2018 21:15:10 +0100 (CET) From: pisa@cmp.felk.cvut.cz To: qemu-devel@nongnu.org Date: Sun, 14 Jan 2018 21:14:08 +0100 Message-Id: <425e38f28bba536cfb1ae389ffa963984990f306.1515960078.git.pisa@cmp.felk.cvut.cz> X-Mailer: git-send-email 2.11.0 In-Reply-To: References: In-Reply-To: References: X-W4U-Auth: 5126d988da5540ebee2a97f4e5934f502142138e X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 81.91.87.88 Subject: [Qemu-devel] [PATCH V4 2/7] CAN bus support to connect bust to Linux host SocketCAN interface. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marek Vasut , Oliver Hartkopp , Stefan Hajnoczi , Deniz Eren , Oleksij Rempel , Konrad Frederic , Jan Kiszka , Pavel Pisa Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Pavel Pisa Connection to the real host CAN bus network through SocketCAN network interface is available only for Linux host system. Mechanism is generic, support for another CAN API and operating systems can be implemented in future. Signed-off-by: Pavel Pisa --- hw/can/Makefile.objs | 4 + hw/can/can_socketcan.c | 314 +++++++++++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 318 insertions(+) create mode 100644 hw/can/can_socketcan.c diff --git a/hw/can/Makefile.objs b/hw/can/Makefile.objs index 1028d7c455..f999085f7a 100644 --- a/hw/can/Makefile.objs +++ b/hw/can/Makefile.objs @@ -2,5 +2,9 @@ =20 ifeq ($(CONFIG_CAN_CORE),y) common-obj-y +=3D can_core.o +ifeq ($(CONFIG_LINUX),y) +common-obj-y +=3D can_socketcan.o +else common-obj-y +=3D can_host_stub.o endif +endif diff --git a/hw/can/can_socketcan.c b/hw/can/can_socketcan.c new file mode 100644 index 0000000000..f6df747c5a --- /dev/null +++ b/hw/can/can_socketcan.c @@ -0,0 +1,314 @@ +/* + * CAN socketcan support to connect to the Linux host SocketCAN interfaces + * + * Copyright (c) 2013-2014 Jin Yang + * Copyright (c) 2014-2018 Pavel Pisa + * + * Initial development supported by Google GSoC 2013 from RTEMS project sl= ot + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/error-report.h" +#include "chardev/char.h" +#include "qemu/sockets.h" +#include "qemu/error-report.h" +#include "hw/hw.h" +#include "can/can_emu.h" + +#include +#include +#include +#include + +#ifndef DEBUG_CAN +#define DEBUG_CAN 0 +#endif /*DEBUG_CAN*/ + +#define CAN_READ_BUF_LEN 5 +typedef struct { + CanBusClientState bus_client; + qemu_can_filter *rfilter; + int rfilter_num; + can_err_mask_t err_mask; + + qemu_can_frame buf[CAN_READ_BUF_LEN]; + int bufcnt; + int bufptr; + + int fd; +} CanBusSocketcanConnectState; + +static void can_bus_socketcan_display_msg(struct qemu_can_frame *msg) +{ + int i; + + /* Check that QEMU and Linux kernel flags encoding matches */ + assert(QEMU_CAN_EFF_FLAG =3D=3D CAN_EFF_FLAG); + assert(QEMU_CAN_RTR_FLAG =3D=3D CAN_RTR_FLAG); + assert(QEMU_CAN_ERR_FLAG =3D=3D CAN_ERR_FLAG); + + assert(QEMU_CAN_INV_FILTER =3D=3D CAN_INV_FILTER); + + assert(offsetof(qemu_can_frame, data) =3D=3D offsetof(struct can_frame= , data)); + + qemu_log_lock(); + qemu_log("[cansocketcan]: %03X [%01d] %s %s", + msg->can_id & QEMU_CAN_EFF_MASK, + msg->can_dlc, + msg->can_id & QEMU_CAN_EFF_FLAG ? "EFF" : "SFF", + msg->can_id & QEMU_CAN_RTR_FLAG ? "RTR" : "DAT"); + + for (i =3D 0; i < msg->can_dlc; i++) { + qemu_log(" %02X", msg->data[i]); + } + qemu_log("\n"); + qemu_log_flush(); + qemu_log_unlock(); +} + +static void can_bus_socketcan_read(void *opaque) +{ + CanBusSocketcanConnectState *c; + c =3D (CanBusSocketcanConnectState *)opaque; + + + + /* CAN_READ_BUF_LEN for multiple messages syscall is possible for futu= re */ + c->bufcnt =3D read(c->fd, c->buf, sizeof(qemu_can_frame)); + if (c->bufcnt < 0) { + warn_report("CAN bus host read failed (%s)", strerror(errno)); + return; + } + + can_bus_client_send(&c->bus_client, c->buf, 1); + + if (DEBUG_CAN) { + can_bus_socketcan_display_msg(c->buf); + } +} + +static int can_bus_socketcan_can_receive(CanBusClientState *client) +{ + CanBusSocketcanConnectState *c; + c =3D container_of(client, CanBusSocketcanConnectState, bus_client); + + if (c->fd < 0) { + return -1; + } + + return 1; +} + +static ssize_t can_bus_socketcan_receive(CanBusClientState *client, + const qemu_can_frame *frames, size_t frames_cn= t) +{ + CanBusSocketcanConnectState *c; + c =3D container_of(client, CanBusSocketcanConnectState, bus_client); + size_t len =3D sizeof(qemu_can_frame); + int res; + + if (c->fd < 0) { + return -1; + } + + res =3D write(c->fd, frames, len); + + if (!res) { + warn_report("[cansocketcan]: write message to host returns zero"); + return -1; + } + + if (res !=3D len) { + if (res < 0) { + warn_report("[cansocketcan]: write to host failed (%s)", + strerror(errno)); + } else { + warn_report("[cansocketcan]: write to host truncated"); + } + return -1; + } + + return 1; +} + +static void can_bus_socketcan_cleanup(CanBusClientState *client) +{ + CanBusSocketcanConnectState *c; + c =3D container_of(client, CanBusSocketcanConnectState, bus_client); + + if (c->fd >=3D 0) { + qemu_set_fd_handler(c->fd, NULL, NULL, c); + close(c->fd); + c->fd =3D -1; + } + + c->rfilter_num =3D 0; + if (c->rfilter !=3D NULL) { + g_free(c->rfilter); + } +} + +static int can_bus_socketcan_set_filters(CanBusClientState *client, + const struct qemu_can_filter *filters, size_t filters_c= nt) +{ + CanBusSocketcanConnectState *c; + c =3D container_of(client, CanBusSocketcanConnectState, bus_client); + + int i; + + if (DEBUG_CAN) { + qemu_log_lock(); + qemu_log("[cansocketcan]: filters set for channel\n"); + for (i =3D 0; i < filters_cnt; i++) { + fprintf(stderr, "[%i] id=3D0x%08x maks=3D0x%08x\n", + i, filters[i].can_id, filters[i].can_mask); + } + qemu_log("\n"); + qemu_log_flush(); + qemu_log_unlock(); + } + + setsockopt(c->fd, SOL_CAN_RAW, CAN_RAW_FILTER, + filters, filters_cnt * sizeof(qemu_can_filter)); + + return 0; +} + +static +void can_bus_socketcan_update_read_handler(CanBusSocketcanConnectState *c) +{ + if (c->fd >=3D 0) { + qemu_set_fd_handler(c->fd, can_bus_socketcan_read, NULL, c); + } +} + +static CanBusClientInfo can_bus_socketcan_bus_client_info =3D { + .can_receive =3D can_bus_socketcan_can_receive, + .receive =3D can_bus_socketcan_receive, + .cleanup =3D can_bus_socketcan_cleanup, + .poll =3D NULL +}; + +static CanBusSocketcanConnectState * + can_bus_socketcan_connect_new(const char *host_dev_name) +{ + int s; /* can raw socket */ + CanBusSocketcanConnectState *c; + struct sockaddr_can addr; + struct ifreq ifr; + + c =3D g_malloc0(sizeof(CanBusSocketcanConnectState)); + if (c =3D=3D NULL) { + goto fail1; + } + + c->fd =3D -1; + + /* open socket */ + s =3D socket(PF_CAN, SOCK_RAW, CAN_RAW); + if (s < 0) { + error_report("[cansocketcan]: CAN_RAW socket create failed (%s)", + strerror(errno)); + goto fail; + } + + addr.can_family =3D AF_CAN; + memset(&ifr.ifr_name, 0, sizeof(ifr.ifr_name)); + strcpy(ifr.ifr_name, host_dev_name); + if (ioctl(s, SIOCGIFINDEX, &ifr) < 0) { + error_report("[cansocketcan]: host interface %s not available (%s)= ", + host_dev_name, strerror(errno)); + goto fail; + } + addr.can_ifindex =3D ifr.ifr_ifindex; + + c->err_mask =3D 0xffffffff; /* Receive error frame. */ + setsockopt(s, SOL_CAN_RAW, CAN_RAW_ERR_FILTER, + &c->err_mask, sizeof(c->err_mask)); + + c->rfilter_num =3D 1; + c->rfilter =3D g_malloc0(c->rfilter_num * sizeof(struct qemu_can_filte= r)); + if (c->rfilter =3D=3D NULL) { + goto fail; + } + + /* Receive all data frame. If |=3D CAN_INV_FILTER no data. */ + c->rfilter[0].can_id =3D 0; + c->rfilter[0].can_mask =3D 0; + c->rfilter[0].can_mask &=3D ~CAN_ERR_FLAG; + + setsockopt(s, SOL_CAN_RAW, CAN_RAW_FILTER, c->rfilter, + c->rfilter_num * sizeof(struct qemu_can_filter)); + + if (bind(s, (struct sockaddr *)&addr, sizeof(addr)) < 0) { + error_report("[cansocketcan]: bind to host interface %s failed (%s= )", + host_dev_name, strerror(errno)); + goto fail; + } + + c->fd =3D s; + + c->bus_client.info =3D &can_bus_socketcan_bus_client_info; + + can_bus_socketcan_update_read_handler(c); + + return c; + +fail: + can_bus_socketcan_cleanup(&c->bus_client); + g_free(c); +fail1: + + return NULL; +} + +static int can_bus_connect_to_host_socketcan(CanBusState *bus, + const char *host_dev_name) +{ + CanBusSocketcanConnectState *c; + + c =3D can_bus_socketcan_connect_new(host_dev_name); + if (c =3D=3D NULL) { + error_report("CAN bus setup of host connect to \"%s\" failed", + host_dev_name); + exit(1); + } + + if (can_bus_insert_client(bus, &c->bus_client) < 0) { + error_report("CAN host device \"%s\" connect to bus \"%s\" failed", + host_dev_name, bus->name); + exit(1); + } + + if (0) { + /* + * Not used there or as a CanBusSocketcanConnectState method + * for now but included there for documentation purposes + * and to suppress warning. + */ + can_bus_socketcan_set_filters(&c->bus_client, NULL, 0); + } + + return 0; +} + +int (*can_bus_connect_to_host_variant)(CanBusState *bus, const char *name)= =3D + can_bus_connect_to_host_socketcan; --=20 2.11.0 From nobody Sat May 4 20:54:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1515961060449992.6560496076136; Sun, 14 Jan 2018 12:17:40 -0800 (PST) Received: from localhost ([::1]:33611 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eaoik-0008TQ-BB for importer@patchew.org; Sun, 14 Jan 2018 15:17:34 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42154) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eaogk-0007PA-PL for qemu-devel@nongnu.org; Sun, 14 Jan 2018 15:15:34 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eaogg-0005lU-Ot for qemu-devel@nongnu.org; Sun, 14 Jan 2018 15:15:30 -0500 Received: from smtp8.web4u.cz ([81.91.87.88]:45528 helo=mx-8.mail.web4u.cz) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eaogg-0005kT-7t for qemu-devel@nongnu.org; Sun, 14 Jan 2018 15:15:26 -0500 Received: from mx-8.mail.web4u.cz (localhost [127.0.0.1]) by mx-8.mail.web4u.cz (Postfix) with ESMTP id 29E301FF69C; Sun, 14 Jan 2018 21:15:23 +0100 (CET) Received: from baree.pikron.com (unknown [89.102.4.32]) (Authenticated sender: ppisa@pikron.com) by mx-8.mail.web4u.cz (Postfix) with ESMTPA id C63541FF62C; Sun, 14 Jan 2018 21:15:22 +0100 (CET) From: pisa@cmp.felk.cvut.cz To: qemu-devel@nongnu.org Date: Sun, 14 Jan 2018 21:14:09 +0100 Message-Id: <7b291e4c0fd03581e00c6c22b5be7fe764ab0b76.1515960078.git.pisa@cmp.felk.cvut.cz> X-Mailer: git-send-email 2.11.0 In-Reply-To: References: In-Reply-To: References: X-W4U-Auth: 2e60acb730a9e1a22a037481c87915f7bfd23ed5 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 81.91.87.88 Subject: [Qemu-devel] [PATCH V4 3/7] CAN bus SJA1000 chip register level emulation for QEMU X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marek Vasut , Oliver Hartkopp , Stefan Hajnoczi , Deniz Eren , Oleksij Rempel , Konrad Frederic , Jan Kiszka , Pavel Pisa Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Pavel Pisa The core SJA1000 support is independent of following patches which map SJA1000 chip to PCI boards. The work is based on Jin Yang GSoC 2013 work funded by Google and mentored in frame of RTEMS project GSoC slot donated to QEMU. Rewritten for QEMU-2.0+ versions and architecture cleanup by Pavel Pisa (Czech Technical University in Prague). Signed-off-by: Pavel Pisa --- default-configs/pci.mak | 1 + hw/can/Makefile.objs | 1 + hw/can/can_sja1000.c | 1013 +++++++++++++++++++++++++++++++++++++++++++= ++++ hw/can/can_sja1000.h | 167 ++++++++ 4 files changed, 1182 insertions(+) create mode 100644 hw/can/can_sja1000.c create mode 100644 hw/can/can_sja1000.h diff --git a/default-configs/pci.mak b/default-configs/pci.mak index bbe11887a1..979b649fe5 100644 --- a/default-configs/pci.mak +++ b/default-configs/pci.mak @@ -32,6 +32,7 @@ CONFIG_SERIAL=3Dy CONFIG_SERIAL_ISA=3Dy CONFIG_SERIAL_PCI=3Dy CONFIG_CAN_CORE=3Dy +CONFIG_CAN_SJA1000=3Dy CONFIG_IPACK=3Dy CONFIG_WDT_IB6300ESB=3Dy CONFIG_PCI_TESTDEV=3Dy diff --git a/hw/can/Makefile.objs b/hw/can/Makefile.objs index f999085f7a..3c4bf3bfc1 100644 --- a/hw/can/Makefile.objs +++ b/hw/can/Makefile.objs @@ -7,4 +7,5 @@ common-obj-y +=3D can_socketcan.o else common-obj-y +=3D can_host_stub.o endif +common-obj-$(CONFIG_CAN_SJA1000) +=3D can_sja1000.o endif diff --git a/hw/can/can_sja1000.c b/hw/can/can_sja1000.c new file mode 100644 index 0000000000..7f7a6ea244 --- /dev/null +++ b/hw/can/can_sja1000.c @@ -0,0 +1,1013 @@ +/* + * CAN device - SJA1000 chip emulation for QEMU + * + * Copyright (c) 2013-2014 Jin Yang + * Copyright (c) 2014-2018 Pavel Pisa + * + * Initial development supported by Google GSoC 2013 from RTEMS project sl= ot + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "chardev/char.h" +#include "hw/hw.h" +#include "can/can_emu.h" + +#include "can_sja1000.h" + +#ifndef DEBUG_FILTER +#define DEBUG_FILTER 0 +#endif /*DEBUG_FILTER*/ + +#ifndef DEBUG_CAN +#define DEBUG_CAN 0 +#endif /*DEBUG_CAN*/ + +#define DPRINTF(fmt, ...) \ + do { \ + if (DEBUG_CAN) { \ + qemu_log("[cansja]: " fmt , ## __VA_ARGS__); \ + } \ + } while (0) + +static void can_sja_software_reset(CanSJA1000State *s) +{ + s->mode &=3D ~0x31; + s->mode |=3D 0x01; + s->status_pel &=3D ~0x37; + s->status_pel |=3D 0x34; + + s->rxbuf_start =3D 0x00; + s->rxmsg_cnt =3D 0x00; + s->rx_cnt =3D 0x00; +} + +void can_sja_hardware_reset(CanSJA1000State *s) +{ + /* Reset by hardware, p10 */ + s->mode =3D 0x01; + s->status_pel =3D 0x3c; + s->interrupt_pel =3D 0x00; + s->clock =3D 0x00; + s->rxbuf_start =3D 0x00; + s->rxmsg_cnt =3D 0x00; + s->rx_cnt =3D 0x00; + + s->control =3D 0x01; + s->status_bas =3D 0x0c; + s->interrupt_bas =3D 0x00; + + s->irq_lower(s->irq_opaque); +} + +static +void can_sja_single_filter(struct qemu_can_filter *filter, + const uint8_t *acr, const uint8_t *amr, int extended) +{ + if (extended) { + filter->can_id =3D (uint32_t)acr[0] << 21; + filter->can_id |=3D (uint32_t)acr[1] << 13; + filter->can_id |=3D (uint32_t)acr[2] << 5; + filter->can_id |=3D (uint32_t)acr[3] >> 3; + if (acr[3] & 4) { + filter->can_id |=3D QEMU_CAN_RTR_FLAG; + } + + filter->can_mask =3D (uint32_t)amr[0] << 21; + filter->can_mask |=3D (uint32_t)amr[1] << 13; + filter->can_mask |=3D (uint32_t)amr[2] << 5; + filter->can_mask |=3D (uint32_t)amr[3] >> 3; + filter->can_mask =3D ~filter->can_mask & QEMU_CAN_EFF_MASK; + if (!(amr[3] & 4)) { + filter->can_mask |=3D QEMU_CAN_RTR_FLAG; + } + } else { + filter->can_id =3D (uint32_t)acr[0] << 3; + filter->can_id |=3D (uint32_t)acr[1] >> 5; + if (acr[1] & 0x10) { + filter->can_id |=3D QEMU_CAN_RTR_FLAG; + } + + filter->can_mask =3D (uint32_t)amr[0] << 3; + filter->can_mask |=3D (uint32_t)amr[1] << 5; + filter->can_mask =3D ~filter->can_mask & QEMU_CAN_SFF_MASK; + if (!(amr[1] & 4)) { + filter->can_mask |=3D QEMU_CAN_RTR_FLAG; + } + } +} + +static +void can_sja_dual_filter(struct qemu_can_filter *filter, + const uint8_t *acr, const uint8_t *amr, int extended) +{ + if (extended) { + filter->can_id =3D (uint32_t)acr[0] << 21; + filter->can_id |=3D (uint32_t)acr[1] << 13; + + filter->can_mask =3D (uint32_t)amr[0] << 21; + filter->can_mask |=3D (uint32_t)amr[1] << 13; + filter->can_mask =3D ~filter->can_mask & QEMU_CAN_EFF_MASK & ~0x1f= ff; + } else { + filter->can_id =3D (uint32_t)acr[0] << 3; + filter->can_id |=3D (uint32_t)acr[1] >> 5; + if (acr[1] & 0x10) { + filter->can_id |=3D QEMU_CAN_RTR_FLAG; + } + + filter->can_mask =3D (uint32_t)amr[0] << 3; + filter->can_mask |=3D (uint32_t)amr[1] >> 5; + filter->can_mask =3D ~filter->can_mask & QEMU_CAN_SFF_MASK; + if (!(amr[1] & 0x10)) { + filter->can_mask |=3D QEMU_CAN_RTR_FLAG; + } + } +} + +/* Details in DS-p22, what we need to do here is to test the data. */ +static +int can_sja_accept_filter(CanSJA1000State *s, + const qemu_can_frame *frame) +{ + + struct qemu_can_filter filter; + + if (s->clock & 0x80) { /* PeliCAN Mode */ + if (s->mode & (1 << 3)) { /* Single mode. */ + if (frame->can_id & QEMU_CAN_EFF_FLAG) { /* EFF */ + can_sja_single_filter(&filter, + s->code_mask + 0, s->code_mask + 4, 1); + + if (!can_bus_filter_match(&filter, frame->can_id)) { + return 0; + } + } else { /* SFF */ + can_sja_single_filter(&filter, + s->code_mask + 0, s->code_mask + 4, 0); + + if (!can_bus_filter_match(&filter, frame->can_id)) { + return 0; + } + + if (frame->can_id & QEMU_CAN_RTR_FLAG) { /* RTR */ + return 1; + } + + if (frame->can_dlc =3D=3D 0) { + return 1; + } + + if ((frame->data[0] & ~(s->code_mask[6])) !=3D + (s->code_mask[2] & ~(s->code_mask[6]))) { + return 0; + } + + if (frame->can_dlc < 2) { + return 1; + } + + if ((frame->data[1] & ~(s->code_mask[7])) =3D=3D + (s->code_mask[3] & ~(s->code_mask[7]))) { + return 1; + } + + return 0; + } + } else { /* Dual mode */ + if (frame->can_id & QEMU_CAN_EFF_FLAG) { /* EFF */ + can_sja_dual_filter(&filter, + s->code_mask + 0, s->code_mask + 4, 1); + + if (can_bus_filter_match(&filter, frame->can_id)) { + return 1; + } + + can_sja_dual_filter(&filter, + s->code_mask + 2, s->code_mask + 6, 1); + + if (can_bus_filter_match(&filter, frame->can_id)) { + return 1; + } + + return 0; + } else { + can_sja_dual_filter(&filter, + s->code_mask + 0, s->code_mask + 4, 0); + + if (can_bus_filter_match(&filter, frame->can_id)) { + uint8_t expect; + uint8_t mask; + expect =3D s->code_mask[1] << 4; + expect |=3D s->code_mask[3] & 0x0f; + + mask =3D s->code_mask[5] << 4; + mask |=3D s->code_mask[7] & 0x0f; + mask =3D ~mask & 0xff; + + if ((frame->data[0] & mask) =3D=3D + (expect & mask)) { + return 1; + } + } + + can_sja_dual_filter(&filter, + s->code_mask + 2, s->code_mask + 6, 0); + + if (can_bus_filter_match(&filter, frame->can_id)) { + return 1; + } + + return 0; + } + } + } + + return 1; +} + +static void can_display_msg(const char *prefix, const qemu_can_frame *msg) +{ + int i; + + qemu_log_lock(); + qemu_log("%s%03X [%01d] %s %s", + prefix, + msg->can_id & QEMU_CAN_EFF_MASK, + msg->can_dlc, + msg->can_id & QEMU_CAN_EFF_FLAG ? "EFF" : "SFF", + msg->can_id & QEMU_CAN_RTR_FLAG ? "RTR" : "DAT"); + + for (i =3D 0; i < msg->can_dlc; i++) { + qemu_log(" %02X", msg->data[i]); + } + qemu_log("\n"); + qemu_log_flush(); + qemu_log_unlock(); +} + +static void buff2frame_pel(const uint8_t *buff, qemu_can_frame *frame) +{ + uint8_t i; + + frame->can_id =3D 0; + if (buff[0] & 0x40) { /* RTR */ + frame->can_id =3D QEMU_CAN_RTR_FLAG; + } + frame->can_dlc =3D buff[0] & 0x0f; + + if (buff[0] & 0x80) { /* Extended */ + frame->can_id |=3D QEMU_CAN_EFF_FLAG; + frame->can_id |=3D buff[1] << 21; /* ID.28~ID.21 */ + frame->can_id |=3D buff[2] << 13; /* ID.20~ID.13 */ + frame->can_id |=3D buff[3] << 5; + frame->can_id |=3D buff[4] >> 3; + for (i =3D 0; i < frame->can_dlc; i++) { + frame->data[i] =3D buff[5 + i]; + } + for (; i < 8; i++) { + frame->data[i] =3D 0; + } + } else { + frame->can_id |=3D buff[1] << 3; + frame->can_id |=3D buff[2] >> 5; + for (i =3D 0; i < frame->can_dlc; i++) { + frame->data[i] =3D buff[3 + i]; + } + for (; i < 8; i++) { + frame->data[i] =3D 0; + } + } +} + + +static void buff2frame_bas(const uint8_t *buff, qemu_can_frame *frame) +{ + uint8_t i; + + frame->can_id =3D ((buff[0] << 3) & (0xff << 3)) + ((buff[1] >> 5) & 0= x07); + if (buff[1] & 0x10) { /* RTR */ + frame->can_id =3D QEMU_CAN_RTR_FLAG; + } + frame->can_dlc =3D buff[1] & 0x0f; + + for (i =3D 0; i < frame->can_dlc; i++) { + frame->data[i] =3D buff[2 + i]; + } + for (; i < 8; i++) { + frame->data[i] =3D 0; + } +} + + +static int frame2buff_pel(const qemu_can_frame *frame, uint8_t *buff) +{ + int i; + + if (frame->can_id & QEMU_CAN_ERR_FLAG) { /* error frame, NOT support n= ow. */ + return -1; + } + + buff[0] =3D 0x0f & frame->can_dlc; /* DLC */ + if (frame->can_id & QEMU_CAN_RTR_FLAG) { /* RTR */ + buff[0] |=3D (1 << 6); + } + if (frame->can_id & QEMU_CAN_EFF_FLAG) { /* EFF */ + buff[0] |=3D (1 << 7); + buff[1] =3D extract32(frame->can_id, 21, 8); /* ID.28~ID.21 */ + buff[2] =3D extract32(frame->can_id, 13, 8); /* ID.20~ID.13 */ + buff[3] =3D extract32(frame->can_id, 5, 8); /* ID.12~ID.05 */ + buff[4] =3D extract32(frame->can_id, 0, 5) << 3; /* ID.04~ID.00,xx= x */ + for (i =3D 0; i < frame->can_dlc; i++) { + buff[5 + i] =3D frame->data[i]; + } + return frame->can_dlc + 5; + } else { /* SFF */ + buff[1] =3D extract32(frame->can_id, 3, 8); /* ID.10~ID.03 */ + buff[2] =3D extract32(frame->can_id, 0, 3) << 5; /* ID.02~ID.00,xx= xxx */ + for (i =3D 0; i < frame->can_dlc; i++) { + buff[3 + i] =3D frame->data[i]; + } + + return frame->can_dlc + 3; + } + + return -1; +} + +static int frame2buff_bas(const qemu_can_frame *frame, uint8_t *buff) +{ + int i; + + /* + * EFF, no support for BasicMode + * No use for Error frames now, + * they could be used in future to update SJA1000 error state + */ + if ((frame->can_id & QEMU_CAN_EFF_FLAG) || + (frame->can_id & QEMU_CAN_ERR_FLAG)) { + return -1; + } + + buff[0] =3D extract32(frame->can_id, 3, 8); /* ID.10~ID.03 */ + buff[1] =3D extract32(frame->can_id, 0, 3) << 5; /* ID.02~ID.00,xxxxx = */ + if (frame->can_id & QEMU_CAN_RTR_FLAG) { /* RTR */ + buff[1] |=3D (1 << 4); + } + buff[1] |=3D frame->can_dlc & 0x0f; + for (i =3D 0; i < frame->can_dlc; i++) { + buff[2 + i] =3D frame->data[i]; + } + + return frame->can_dlc + 2; +} + +void can_sja_mem_write(CanSJA1000State *s, hwaddr addr, uint64_t val, + unsigned size) +{ + qemu_can_frame frame; + uint32_t tmp; + uint8_t tmp8, count; + + + DPRINTF("write 0x%02llx addr 0x%02x\n", + (unsigned long long)val, (unsigned int)addr); + + if (addr > CAN_SJA_MEM_SIZE) { + return ; + } + + if (s->clock & 0x80) { /* PeliCAN Mode */ + switch (addr) { + case SJA_MOD: /* Mode register */ + s->mode =3D 0x1f & val; + if ((s->mode & 0x01) && ((val & 0x01) =3D=3D 0)) { + /* Go to operation mode from reset mode. */ + if (s->mode & (1 << 3)) { /* Single mode. */ + /* For EFF */ + can_sja_single_filter(&s->filter[0], + s->code_mask + 0, s->code_mask + 4, 1); + + /* For SFF */ + can_sja_single_filter(&s->filter[1], + s->code_mask + 0, s->code_mask + 4, 0); + + can_bus_client_set_filters(&s->bus_client, s->filter, = 2); + } else { /* Dual mode */ + /* For EFF */ + can_sja_dual_filter(&s->filter[0], + s->code_mask + 0, s->code_mask + 4, 1); + + can_sja_dual_filter(&s->filter[1], + s->code_mask + 2, s->code_mask + 6, 1); + + /* For SFF */ + can_sja_dual_filter(&s->filter[2], + s->code_mask + 0, s->code_mask + 4, 0); + + can_sja_dual_filter(&s->filter[3], + s->code_mask + 2, s->code_mask + 6, 0); + + can_bus_client_set_filters(&s->bus_client, s->filter, = 4); + } + + s->rxmsg_cnt =3D 0; + s->rx_cnt =3D 0; + } + break; + + case SJA_CMR: /* Command register. */ + if (0x01 & val) { /* Send transmission request. */ + buff2frame_pel(s->tx_buff, &frame); + if (DEBUG_FILTER) { + can_display_msg("[cansja]: Tx request " , &frame); + } + + /* + * Clear transmission complete status, + * and Transmit Buffer Status. + * write to the backends. + */ + s->status_pel &=3D ~(3 << 2); + + can_bus_client_send(&s->bus_client, &frame, 1); + + /* + * Set transmission complete status + * and Transmit Buffer Status. + */ + s->status_pel |=3D (3 << 2); + + /* Clear transmit status. */ + s->status_pel &=3D ~(1 << 5); + s->interrupt_pel |=3D 0x02; + if (s->interrupt_en & 0x02) { + s->irq_raise(s->irq_opaque); + } + } + if (0x04 & val) { /* Release Receive Buffer */ + if (s->rxmsg_cnt <=3D 0) { + break; + } + + tmp8 =3D s->rx_buff[s->rxbuf_start]; count =3D 0; + if (tmp8 & (1 << 7)) { /* EFF */ + count +=3D 2; + } + count +=3D 3; + if (!(tmp8 & (1 << 6))) { /* DATA */ + count +=3D (tmp8 & 0x0f); + } + + if (DEBUG_FILTER) { + qemu_log("[cansja]: message released from " + "Rx FIFO cnt=3D%d, count=3D%d\n", s->rx_cnt, = count); + } + + s->rxbuf_start +=3D count; + s->rxbuf_start %=3D SJA_RCV_BUF_LEN; + + s->rx_cnt -=3D count; + s->rxmsg_cnt--; + if (s->rxmsg_cnt =3D=3D 0) { + s->status_pel &=3D ~(1 << 0); + s->interrupt_pel &=3D ~(1 << 0); + } + if ((s->interrupt_en & 0x01) && (s->interrupt_pel =3D=3D 0= )) { + /* no other interrupts. */ + s->irq_lower(s->irq_opaque); + } + } + if (0x08 & val) { /* Clear data overrun */ + s->status_pel &=3D ~(1 << 1); + s->interrupt_pel &=3D ~(1 << 3); + if ((s->interrupt_en & 0x80) && (s->interrupt_pel =3D=3D 0= )) { + /* no other interrupts. */ + s->irq_lower(s->irq_opaque); + } + } + break; + case SJA_SR: /* Status register */ + case SJA_IR: /* Interrupt register */ + break; /* Do nothing */ + case SJA_IER: /* Interrupt enable register */ + s->interrupt_en =3D val; + break; + case 16: /* RX frame information addr16-28. */ + s->status_pel |=3D (1 << 5); /* Set transmit status. */ + case 17: + case 18: + case 19: + case 20: + case 21: + case 22: + case 23: + case 24: + case 25: + case 26: + case 27: + case 28: + if (s->mode & 0x01) { /* Reset mode */ + if (addr < 24) { + s->code_mask[addr - 16] =3D val; + } + } else { /* Operation mode */ + s->tx_buff[addr - 16] =3D val; /* Store to TX buffer direc= tly. */ + } + break; + case SJA_CDR: + s->clock =3D val; + break; + } + } else { /* Basic Mode */ + switch (addr) { + case SJA_BCAN_CTR: /* Control register, addr 0 */ + if ((s->control & 0x01) && ((val & 0x01) =3D=3D 0)) { + /* Go to operation mode from reset mode. */ + s->filter[0].can_id =3D (s->code << 3) & (0xff << 3); + tmp =3D (~(s->mask << 3)) & (0xff << 3); + tmp |=3D QEMU_CAN_EFF_FLAG; /* Only Basic CAN Frame. */ + s->filter[0].can_mask =3D tmp; + can_bus_client_set_filters(&s->bus_client, s->filter, 1); + + s->rxmsg_cnt =3D 0; + s->rx_cnt =3D 0; + } else if (!(s->control & 0x01) && !(val & 0x01)) { + can_sja_software_reset(s); + } + + s->control =3D 0x1f & val; + break; + case SJA_BCAN_CMR: /* Command register, addr 1 */ + if (0x01 & val) { /* Send transmission request. */ + buff2frame_bas(s->tx_buff, &frame); + if (DEBUG_FILTER) { + can_display_msg("[cansja]: Tx request " , &frame); + } + + /* + * Clear transmission complete status, + * and Transmit Buffer Status. + */ + s->status_bas &=3D ~(3 << 2); + + /* write to the backends. */ + can_bus_client_send(&s->bus_client, &frame, 1); + + /* + * Set transmission complete status, + * and Transmit Buffer Status. + */ + s->status_bas |=3D (3 << 2); + + /* Clear transmit status. */ + s->status_bas &=3D ~(1 << 5); + s->interrupt_bas |=3D 0x02; + if (s->control & 0x04) { + s->irq_raise(s->irq_opaque); + } + } + if (0x04 & val) { /* Release Receive Buffer */ + if (s->rxmsg_cnt <=3D 0) { + break; + } + + qemu_mutex_lock(&s->rx_lock); + tmp8 =3D s->rx_buff[(s->rxbuf_start + 1) % SJA_RCV_BUF_LEN= ]; + count =3D 2 + (tmp8 & 0x0f); + + if (DEBUG_FILTER) { + qemu_log("[cansja]: message released from " + "Rx FIFO cnt=3D%d, count=3D%d\n", s->rx_cnt, = count); + } + + s->rxbuf_start +=3D count; + s->rxbuf_start %=3D SJA_RCV_BUF_LEN; + s->rx_cnt -=3D count; + s->rxmsg_cnt--; + qemu_mutex_unlock(&s->rx_lock); + + if (s->rxmsg_cnt =3D=3D 0) { + s->status_bas &=3D ~(1 << 0); + s->interrupt_bas &=3D ~(1 << 0); + } + if ((s->control & 0x02) && (s->interrupt_bas =3D=3D 0)) { + /* no other interrupts. */ + s->irq_lower(s->irq_opaque); + } + } + if (0x08 & val) { /* Clear data overrun */ + s->status_bas &=3D ~(1 << 1); + s->interrupt_bas &=3D ~(1 << 3); + if ((s->control & 0x10) && (s->interrupt_bas =3D=3D 0)) { + /* no other interrupts. */ + s->irq_lower(s->irq_opaque); + } + } + break; + case 4: + s->code =3D val; + break; + case 5: + s->mask =3D val; + break; + case 10: + s->status_bas |=3D (1 << 5); /* Set transmit status. */ + case 11: + case 12: + case 13: + case 14: + case 15: + case 16: + case 17: + case 18: + case 19: + if ((s->control & 0x01) =3D=3D 0) { /* Operation mode */ + s->tx_buff[addr - 10] =3D val; /* Store to TX buffer direc= tly. */ + } + break; + case SJA_CDR: + s->clock =3D val; + break; + } + } +} + +uint64_t can_sja_mem_read(CanSJA1000State *s, hwaddr addr, unsigned size) +{ + uint64_t temp =3D 0; + + DPRINTF("read addr 0x%02x ...\n", (unsigned int)addr); + + if (addr > CAN_SJA_MEM_SIZE) { + return 0; + } + + if (s->clock & 0x80) { /* PeliCAN Mode */ + switch (addr) { + case SJA_MOD: /* Mode register, addr 0 */ + temp =3D s->mode; + break; + case SJA_CMR: /* Command register, addr 1 */ + temp =3D 0x00; /* Command register, cannot be read. */ + break; + case SJA_SR: /* Status register, addr 2 */ + temp =3D s->status_pel; + break; + case SJA_IR: /* Interrupt register, addr 3 */ + temp =3D s->interrupt_pel; + s->interrupt_pel =3D 0; + if (s->rxmsg_cnt) { + s->interrupt_pel |=3D (1 << 0); /* Receive interrupt. */ + break; + } + s->irq_lower(s->irq_opaque); + break; + case SJA_IER: /* Interrupt enable register, addr 4 */ + temp =3D s->interrupt_en; + break; + case 5: /* Reserved */ + case 6: /* Bus timing 0, hardware related, not support now. */ + case 7: /* Bus timing 1, hardware related, not support now. */ + case 8: /* + * Output control register, hardware related, + * not supported for now. + */ + case 9: /* Test. */ + case 10: /* Reserved */ + case 11: + case 12: + case 13: + case 14: + case 15: + temp =3D 0x00; + break; + + case 16: + case 17: + case 18: + case 19: + case 20: + case 21: + case 22: + case 23: + case 24: + case 25: + case 26: + case 27: + case 28: + if (s->mode & 0x01) { /* Reset mode */ + if (addr < 24) { + temp =3D s->code_mask[addr - 16]; + } else { + temp =3D 0x00; + } + } else { /* Operation mode */ + temp =3D s->rx_buff[(s->rxbuf_start + addr - 16) % + SJA_RCV_BUF_LEN]; + } + break; + case SJA_CDR: + temp =3D s->clock; + break; + default: + temp =3D 0xff; + } + } else { /* Basic Mode */ + switch (addr) { + case SJA_BCAN_CTR: /* Control register, addr 0 */ + temp =3D s->control; + break; + case SJA_BCAN_SR: /* Status register, addr 2 */ + temp =3D s->status_bas; + break; + case SJA_BCAN_IR: /* Interrupt register, addr 3 */ + temp =3D s->interrupt_bas; + s->interrupt_bas =3D 0; + if (s->rxmsg_cnt) { + s->interrupt_bas |=3D (1 << 0); /* Receive interrupt. */ + break; + } + s->irq_lower(s->irq_opaque); + break; + case 4: + temp =3D s->code; + break; + case 5: + temp =3D s->mask; + break; + case 20: + case 21: + case 22: + case 23: + case 24: + case 25: + case 26: + case 27: + case 28: + case 29: + temp =3D s->rx_buff[(s->rxbuf_start + addr - 20) % SJA_RCV_BUF= _LEN]; + break; + case 31: + temp =3D s->clock; + break; + default: + temp =3D 0xff; + break; + } + } + DPRINTF("read addr 0x%02x, %d bytes, content 0x%02lx\n", + (int)addr, size, (long unsigned int)temp); + + return temp; +} + +int can_sja_can_receive(CanBusClientState *client) +{ + CanSJA1000State *s =3D container_of(client, CanSJA1000State, bus_clien= t); + + if (s->clock & 0x80) { /* PeliCAN Mode */ + if (s->mode & 0x01) { /* reset mode. */ + return 0; + } + } else { /* BasicCAN mode */ + if (s->control & 0x01) { + return 0; + } + } + + return 1; /* always return 1, when operation mode */ +} + +ssize_t can_sja_receive(CanBusClientState *client, const qemu_can_frame *f= rames, + size_t frames_cnt) +{ + CanSJA1000State *s =3D container_of(client, CanSJA1000State, bus_clien= t); + static uint8_t rcv[SJA_MSG_MAX_LEN]; + int i; + int ret =3D -1; + const qemu_can_frame *frame =3D frames; + + if (frames_cnt <=3D 0) { + return 0; + } + if (DEBUG_FILTER) { + can_display_msg("[cansja]: receive ", frame); + } + + qemu_mutex_lock(&s->rx_lock); /* Just do it quickly :) */ + if (s->clock & 0x80) { /* PeliCAN Mode */ + + /* the CAN controller is receiving a message */ + s->status_pel |=3D (1 << 4); + + if (can_sja_accept_filter(s, frame) =3D=3D 0) { + s->status_pel &=3D ~(1 << 4); + if (DEBUG_FILTER) { + qemu_log("[cansja]: filter rejects message\n"); + } + goto fail; + } + + ret =3D frame2buff_pel(frame, rcv); + if (ret < 0) { + s->status_pel &=3D ~(1 << 4); + if (DEBUG_FILTER) { + qemu_log("[cansja]: message store failed\n"); + } + goto fail; /* maybe not support now. */ + } + + if (s->rx_cnt + ret > SJA_RCV_BUF_LEN) { /* Data overrun. */ + s->status_pel |=3D (1 << 1); /* Overrun status */ + s->interrupt_pel |=3D (1 << 3); + if (s->interrupt_en & (1 << 3)) { /* Overrun interrupt enable = */ + s->irq_raise(s->irq_opaque); + } + s->status_pel &=3D ~(1 << 4); + if (DEBUG_FILTER) { + qemu_log("[cansja]: receive FIFO overrun\n"); + } + goto fail; + } + s->rx_cnt +=3D ret; + s->rxmsg_cnt++; + if (DEBUG_FILTER) { + qemu_log("[cansja]: message stored in receive FIFO\n"); + } + + for (i =3D 0; i < ret; i++) { + s->rx_buff[(s->rx_ptr++) % SJA_RCV_BUF_LEN] =3D rcv[i]; + } + s->rx_ptr %=3D SJA_RCV_BUF_LEN; /* update the pointer. */ + + s->status_pel |=3D 0x01; /* Set the Receive Buffer Status. DS-p23 = */ + s->interrupt_pel |=3D 0x01; + s->status_pel &=3D ~(1 << 4); + s->status_pel |=3D (1 << 0); + if (s->interrupt_en & 0x01) { /* Receive Interrupt enable. */ + s->irq_raise(s->irq_opaque); + } + } else { /* BasicCAN mode */ + + /* the CAN controller is receiving a message */ + s->status_bas |=3D (1 << 4); + + ret =3D frame2buff_bas(frame, rcv); + if (ret < 0) { + s->status_bas &=3D ~(1 << 4); + if (DEBUG_FILTER) { + qemu_log("[cansja]: message store failed\n"); + } + goto fail; /* maybe not support now. */ + } + + if (s->rx_cnt + ret > SJA_RCV_BUF_LEN) { /* Data overrun. */ + s->status_bas |=3D (1 << 1); /* Overrun status */ + s->status_bas &=3D ~(1 << 4); + s->interrupt_bas |=3D (1 << 3); + if (s->control & (1 << 4)) { /* Overrun interrupt enable */ + s->irq_raise(s->irq_opaque); + } + if (DEBUG_FILTER) { + qemu_log("[cansja]: receive FIFO overrun\n"); + } + goto fail; + } + s->rx_cnt +=3D ret; + s->rxmsg_cnt++; + + if (DEBUG_FILTER) { + qemu_log("[cansja]: message stored\n"); + } + + for (i =3D 0; i < ret; i++) { + s->rx_buff[(s->rx_ptr++) % SJA_RCV_BUF_LEN] =3D rcv[i]; + } + s->rx_ptr %=3D SJA_RCV_BUF_LEN; /* update the pointer. */ + + s->status_bas |=3D 0x01; /* Set the Receive Buffer Status. DS-p15 = */ + s->status_bas &=3D ~(1 << 4); + s->interrupt_bas |=3D 0x01; + if (s->control & 0x02) { /* Receive Interrupt enable. */ + s->irq_raise(s->irq_opaque); + } + } + ret =3D 1; +fail: + qemu_mutex_unlock(&s->rx_lock); + + return ret; +} + +static CanBusClientInfo can_sja_bus_client_info =3D { + .can_receive =3D can_sja_can_receive, + .receive =3D can_sja_receive, + .cleanup =3D NULL, + .poll =3D NULL +}; + + +int can_sja_connect_to_bus(CanSJA1000State *s, CanBusState *bus) +{ + s->bus_client.info =3D &can_sja_bus_client_info; + + if (can_bus_insert_client(bus, &s->bus_client) < 0) { + return -1; + } + + return 0; +} + +void can_sja_disconnect(CanSJA1000State *s) +{ + can_bus_remove_client(&s->bus_client); +} + +int can_sja_init(CanSJA1000State *s, CanSJAIrqRaiseLower *irq_raise, + CanSJAIrqRaiseLower *irq_lower, void *irq_opaque) +{ + qemu_mutex_init(&s->rx_lock); + + s->irq_raise =3D irq_raise; + s->irq_lower =3D irq_lower; + s->irq_opaque =3D irq_opaque; + + s->irq_lower(s->irq_opaque); + + can_sja_hardware_reset(s); + + return 0; +} + +void can_sja_exit(CanSJA1000State *s) +{ + qemu_mutex_destroy(&s->rx_lock); +} + +const VMStateDescription vmstate_qemu_can_filter =3D { + .name =3D "qemu_can_filter", + .version_id =3D 1, + .minimum_version_id =3D 1, + .minimum_version_id_old =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32(can_id, qemu_can_filter), + VMSTATE_UINT32(can_mask, qemu_can_filter), + VMSTATE_END_OF_LIST() + } +}; + +/* VMState is needed for live migration of QEMU images */ +const VMStateDescription vmstate_can_sja =3D { + .name =3D "can_sja", + .version_id =3D 1, + .minimum_version_id =3D 1, + .minimum_version_id_old =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT8(mode, CanSJA1000State), + + VMSTATE_UINT8(status_pel, CanSJA1000State), + VMSTATE_UINT8(interrupt_pel, CanSJA1000State), + VMSTATE_UINT8(interrupt_en, CanSJA1000State), + VMSTATE_UINT8(rxmsg_cnt, CanSJA1000State), + VMSTATE_UINT8(rxbuf_start, CanSJA1000State), + VMSTATE_UINT8(clock, CanSJA1000State), + + VMSTATE_BUFFER(code_mask, CanSJA1000State), + VMSTATE_BUFFER(tx_buff, CanSJA1000State), + + VMSTATE_BUFFER(rx_buff, CanSJA1000State), + + VMSTATE_UINT32(rx_ptr, CanSJA1000State), + VMSTATE_UINT32(rx_cnt, CanSJA1000State), + + VMSTATE_UINT8(control, CanSJA1000State), + + VMSTATE_UINT8(status_bas, CanSJA1000State), + VMSTATE_UINT8(interrupt_bas, CanSJA1000State), + VMSTATE_UINT8(code, CanSJA1000State), + VMSTATE_UINT8(mask, CanSJA1000State), + + VMSTATE_STRUCT_ARRAY(filter, CanSJA1000State, 4, 0, + vmstate_qemu_can_filter, qemu_can_filter), + + + VMSTATE_END_OF_LIST() + } +}; diff --git a/hw/can/can_sja1000.h b/hw/can/can_sja1000.h new file mode 100644 index 0000000000..6f2cfbcb72 --- /dev/null +++ b/hw/can/can_sja1000.h @@ -0,0 +1,167 @@ +/* + * CAN device - SJA1000 chip emulation for QEMU + * + * Copyright (c) 2013-2014 Jin Yang + * Copyright (c) 2014-2018 Pavel Pisa + * + * Initial development supported by Google GSoC 2013 from RTEMS project sl= ot + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ +#ifndef HW_CAN_SJA1000_H +#define HW_CAN_SJA1000_H + +#include "can/can_emu.h" + +#define CAN_SJA_MEM_SIZE 128 + +/* The max size for a message buffer, EFF and DLC=3D8, DS-p39 */ +#define SJA_MSG_MAX_LEN 13 +/* The receive buffer size. */ +#define SJA_RCV_BUF_LEN 64 + +typedef void (CanSJAIrqRaiseLower)(void *opaque); + +typedef struct CanSJA1000State { + /* PeliCAN state and registers sorted by address */ + uint8_t mode; /* 0 .. Mode register, DS-p26 */ + /* 1 .. Command register */ + uint8_t status_pel; /* 2 .. Status register, p15 */ + uint8_t interrupt_pel; /* 3 .. Interrupt register */ + uint8_t interrupt_en; /* 4 .. Interrupt Enable register */ + uint8_t rxmsg_cnt; /* 29 .. RX message counter. DS-p49 */ + uint8_t rxbuf_start; /* 30 .. RX buffer start address, DS-p4= 9 */ + uint8_t clock; /* 31 .. Clock Divider register, DS-p55= */ + + uint8_t code_mask[8]; /* 16~23 */ + uint8_t tx_buff[13]; /* 96~108 .. transmit buffer */ + /* 10~19 .. transmit buffer for BasicC= AN */ + + uint8_t rx_buff[SJA_RCV_BUF_LEN]; /* 32~95 .. 64bytes Rx FIFO= */ + uint32_t rx_ptr; /* Count by bytes. */ + uint32_t rx_cnt; /* Count by bytes. */ + + /* PeliCAN state and registers sorted by address */ + uint8_t control; /* 0 .. Control register */ + /* 1 .. Command register */ + uint8_t status_bas; /* 2 .. Status register */ + uint8_t interrupt_bas; /* 3 .. Interrupt register */ + uint8_t code; /* 4 .. Acceptance code register */ + uint8_t mask; /* 5 .. Acceptance mask register */ + + qemu_can_filter filter[4]; + + QemuMutex rx_lock; + CanSJAIrqRaiseLower *irq_raise; + CanSJAIrqRaiseLower *irq_lower; + void *irq_opaque; + CanBusClientState bus_client; +} CanSJA1000State; + +/* PeliCAN mode */ +enum SJA1000_PeliCAN_regs { + SJA_MOD =3D 0x00, +/* Command register */ + SJA_CMR =3D 0x01, +/* Status register */ + SJA_SR =3D 0x02, +/* Interrupt register */ + SJA_IR =3D 0x03, +/* Interrupt Enable */ + SJA_IER =3D 0x04, +/* Bus Timing register 0 */ + SJA_BTR0 =3D 0x06, +/* Bus Timing register 1 */ + SJA_BTR1 =3D 0x07, +/* Output Control register */ + SJA_OCR =3D 0x08, +/* Arbitration Lost Capture */ + SJA_ALC =3D 0x0b, +/* Error Code Capture */ + SJA_ECC =3D 0x0c, +/* Error Warning Limit */ + SJA_EWLR =3D 0x0d, +/* RX Error Counter */ + SJA_RXERR =3D 0x0e, +/* TX Error Counter */ + SJA_TXERR0 =3D 0x0e, + SJA_TXERR1 =3D 0x0f, +/* Rx Message Counter (number of msgs. in RX FIFO */ + SJA_RMC =3D 0x1d, +/* Rx Buffer Start Addr. (address of current MSG) */ + SJA_RBSA =3D 0x1e, +/* Transmit Buffer (write) Receive Buffer (read) Frame Information */ + SJA_FRM =3D 0x10, +/* + * ID bytes (11 bits in 0 and 1 for standard message or + * 16 bits in 0,1 and 13 bits in 2,3 for extended message) + */ + SJA_ID0 =3D 0x11, SJA_ID1 =3D 0x12, +/* ID cont. for extended frames */ + SJA_ID2 =3D 0x13, SJA_ID3 =3D 0x14, +/* Data start standard frame */ + SJA_DATS =3D 0x13, +/* Data start extended frame */ + SJA_DATE =3D 0x15, +/* Acceptance Code (4 bytes) in RESET mode */ + SJA_ACR0 =3D 0x10, +/* Acceptance Mask (4 bytes) in RESET mode */ + SJA_AMR0 =3D 0x14, +/* 4 bytes */ + SJA_PeliCAN_AC_LEN =3D 4, +/* Clock Divider */ + SJA_CDR =3D 0x1f +}; + + +/* PeliCAN mode */ +enum SJA1000_BasicCAN_regs { + SJA_BCAN_CTR =3D 0x00, +/* Command register */ + SJA_BCAN_CMR =3D 0x01, +/* Status register */ + SJA_BCAN_SR =3D 0x02, +/* Interrupt register */ + SJA_BCAN_IR =3D 0x03 +}; + +void can_sja_hardware_reset(CanSJA1000State *s); + +void can_sja_mem_write(CanSJA1000State *s, hwaddr addr, uint64_t val, + unsigned size); + +uint64_t can_sja_mem_read(CanSJA1000State *s, hwaddr addr, unsigned size); + +int can_sja_connect_to_bus(CanSJA1000State *s, CanBusState *bus); + +void can_sja_disconnect(CanSJA1000State *s); + +int can_sja_init(CanSJA1000State *s, CanSJAIrqRaiseLower *irq_raise, + CanSJAIrqRaiseLower *irq_lower, void *irq_opaque); + +void can_sja_exit(CanSJA1000State *s); + +int can_sja_can_receive(CanBusClientState *client); + +ssize_t can_sja_receive(CanBusClientState *client, + const qemu_can_frame *frames, size_t frames_cnt); + +extern const VMStateDescription vmstate_can_sja; + +#endif --=20 2.11.0 From nobody Sat May 4 20:54:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1515961276342269.4991253652647; Sun, 14 Jan 2018 12:21:16 -0800 (PST) Received: from localhost ([::1]:33814 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eaomG-0002b0-Ac for importer@patchew.org; Sun, 14 Jan 2018 15:21:12 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42166) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eaogn-0007Qm-0j for qemu-devel@nongnu.org; Sun, 14 Jan 2018 15:15:35 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eaogk-0005nj-8j for qemu-devel@nongnu.org; Sun, 14 Jan 2018 15:15:32 -0500 Received: from smtp8.web4u.cz ([81.91.87.88]:45544 helo=mx-8.mail.web4u.cz) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eaogj-0005n1-TK for qemu-devel@nongnu.org; Sun, 14 Jan 2018 15:15:30 -0500 Received: from mx-8.mail.web4u.cz (localhost [127.0.0.1]) by mx-8.mail.web4u.cz (Postfix) with ESMTP id 640FD1FFCDB; Sun, 14 Jan 2018 21:15:27 +0100 (CET) Received: from baree.pikron.com (unknown [89.102.4.32]) (Authenticated sender: ppisa@pikron.com) by mx-8.mail.web4u.cz (Postfix) with ESMTPA id 27B7D1FF62C; Sun, 14 Jan 2018 21:15:27 +0100 (CET) From: pisa@cmp.felk.cvut.cz To: qemu-devel@nongnu.org Date: Sun, 14 Jan 2018 21:14:10 +0100 Message-Id: <48c4af3c240286a89fc5fdbcaa254ea386c979b9.1515960078.git.pisa@cmp.felk.cvut.cz> X-Mailer: git-send-email 2.11.0 In-Reply-To: References: In-Reply-To: References: X-W4U-Auth: fe595fdd8fa72a6e7a602c3ad434171f4095a9d5 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 81.91.87.88 Subject: [Qemu-devel] [PATCH V4 4/7] CAN bus Kvaser PCI CAN-S (single SJA1000 channel) emulation added. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marek Vasut , Oliver Hartkopp , Stefan Hajnoczi , Deniz Eren , Oleksij Rempel , Konrad Frederic , Jan Kiszka , Pavel Pisa Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Pavel Pisa Signed-off-by: Pavel Pisa --- default-configs/pci.mak | 1 + hw/can/Makefile.objs | 1 + hw/can/can_kvaser_pci.c | 375 ++++++++++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 377 insertions(+) create mode 100644 hw/can/can_kvaser_pci.c diff --git a/default-configs/pci.mak b/default-configs/pci.mak index 979b649fe5..72c0802ced 100644 --- a/default-configs/pci.mak +++ b/default-configs/pci.mak @@ -33,6 +33,7 @@ CONFIG_SERIAL_ISA=3Dy CONFIG_SERIAL_PCI=3Dy CONFIG_CAN_CORE=3Dy CONFIG_CAN_SJA1000=3Dy +CONFIG_CAN_PCI=3Dy CONFIG_IPACK=3Dy CONFIG_WDT_IB6300ESB=3Dy CONFIG_PCI_TESTDEV=3Dy diff --git a/hw/can/Makefile.objs b/hw/can/Makefile.objs index 3c4bf3bfc1..c9d07b9b16 100644 --- a/hw/can/Makefile.objs +++ b/hw/can/Makefile.objs @@ -8,4 +8,5 @@ else common-obj-y +=3D can_host_stub.o endif common-obj-$(CONFIG_CAN_SJA1000) +=3D can_sja1000.o +common-obj-$(CONFIG_CAN_PCI) +=3D can_kvaser_pci.o endif diff --git a/hw/can/can_kvaser_pci.c b/hw/can/can_kvaser_pci.c new file mode 100644 index 0000000000..7e3f28d83c --- /dev/null +++ b/hw/can/can_kvaser_pci.c @@ -0,0 +1,375 @@ +/* + * Kvaser PCI CAN device (SJA1000 based) emulation + * + * Copyright (c) 2013-2014 Jin Yang + * Copyright (c) 2014-2018 Pavel Pisa + * + * Partially based on educational PCIexpress APOHW hardware + * emulator used fro class A0B36APO at CTU FEE course by + * Rostislav Lisovy and Pavel Pisa + * + * Initial development supported by Google GSoC 2013 from RTEMS project sl= ot + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "qemu/event_notifier.h" +#include "qemu/thread.h" +#include "qemu/sockets.h" +#include "qemu/error-report.h" +#include "chardev/char.h" +#include "hw/hw.h" +#include "hw/pci/pci.h" +#include "can/can_emu.h" + +#include "can_sja1000.h" + +#define TYPE_CAN_PCI_DEV "kvaser_pci" + +#define KVASER_PCI_DEV(obj) \ + OBJECT_CHECK(KvaserPCIState, (obj), TYPE_CAN_PCI_DEV) + +#ifndef KVASER_PCI_VENDOR_ID1 +#define KVASER_PCI_VENDOR_ID1 0x10e8 /* the PCI device and vendor I= Ds */ +#endif + +#ifndef KVASER_PCI_DEVICE_ID1 +#define KVASER_PCI_DEVICE_ID1 0x8406 +#endif + +#define KVASER_PCI_S5920_RANGE 0x80 +#define KVASER_PCI_SJA_RANGE 0x80 +#define KVASER_PCI_XILINX_RANGE 0x8 + +#define KVASER_PCI_BYTES_PER_SJA 0x20 + +#define S5920_OMB 0x0C +#define S5920_IMB 0x1C +#define S5920_MBEF 0x34 +#define S5920_INTCSR 0x38 +#define S5920_RCR 0x3C +#define S5920_PTCR 0x60 + +#define S5920_INTCSR_ADDON_INTENABLE_M 0x2000 +#define S5920_INTCSR_INTERRUPT_ASSERTED_M 0x800000 + +#define KVASER_PCI_XILINX_VERINT 7 /* Lower nibble simulate interrupts, + high nibble version number. */ + +#define KVASER_PCI_XILINX_VERSION_NUMBER 13 + +typedef struct KvaserPCIState { + /*< private >*/ + PCIDevice dev; + /*< public >*/ + MemoryRegion s5920_io; + MemoryRegion sja_io; + MemoryRegion xilinx_io; + + CanSJA1000State sja_state; + qemu_irq irq; + + uint32_t s5920_intcsr; + uint32_t s5920_irqstate; + + char *model; /* The model that support, only SJA1000 now. */ + char *canbus; + char *host; +} KvaserPCIState; + +static void kvaser_pci_irq_raise(void *opaque) +{ + KvaserPCIState *d =3D (KvaserPCIState *)opaque; + d->s5920_irqstate =3D 1; + + if (d->s5920_intcsr & S5920_INTCSR_ADDON_INTENABLE_M) { + qemu_irq_raise(d->irq); + } +} + +static void kvaser_pci_irq_lower(void *opaque) +{ + KvaserPCIState *d =3D (KvaserPCIState *)opaque; + d->s5920_irqstate =3D 0; + qemu_irq_lower(d->irq); +} + +static void +kvaser_pci_reset(void *opaque) +{ + KvaserPCIState *d =3D (KvaserPCIState *)opaque; + CanSJA1000State *s =3D &d->sja_state; + + can_sja_hardware_reset(s); +} + +static uint64_t kvaser_pci_s5920_io_read(void *opaque, hwaddr addr, + unsigned size) +{ + KvaserPCIState *d =3D opaque; + uint64_t val; + + switch (addr) { + case S5920_INTCSR: + val =3D d->s5920_intcsr; + val &=3D ~S5920_INTCSR_INTERRUPT_ASSERTED_M; + if (d->s5920_irqstate) { + val |=3D S5920_INTCSR_INTERRUPT_ASSERTED_M; + } + return val; + } + return 0; +} + +static void kvaser_pci_s5920_io_write(void *opaque, hwaddr addr, uint64_t = data, + unsigned size) +{ + KvaserPCIState *d =3D opaque; + + switch (addr) { + case S5920_INTCSR: + if (~d->s5920_intcsr & data & S5920_INTCSR_ADDON_INTENABLE_M) { + if (d->s5920_irqstate) { + qemu_irq_raise(d->irq); + } + } + d->s5920_intcsr =3D data; + break; + } +} + +static uint64_t kvaser_pci_sja_io_read(void *opaque, hwaddr addr, unsigned= size) +{ + KvaserPCIState *d =3D opaque; + CanSJA1000State *s =3D &d->sja_state; + + if (addr >=3D KVASER_PCI_BYTES_PER_SJA) { + return 0; + } + + return can_sja_mem_read(s, addr, size); +} + +static void kvaser_pci_sja_io_write(void *opaque, hwaddr addr, uint64_t da= ta, + unsigned size) +{ + KvaserPCIState *d =3D opaque; + CanSJA1000State *s =3D &d->sja_state; + + if (addr >=3D KVASER_PCI_BYTES_PER_SJA) { + return; + } + + can_sja_mem_write(s, addr, data, size); +} + +static uint64_t kvaser_pci_xilinx_io_read(void *opaque, hwaddr addr, + unsigned size) +{ + /*KvaserPCIState *d =3D opaque;*/ + + switch (addr) { + case KVASER_PCI_XILINX_VERINT: + return (KVASER_PCI_XILINX_VERSION_NUMBER << 4) | 0; + } + + return 0; +} + +static void kvaser_pci_xilinx_io_write(void *opaque, hwaddr addr, uint64_t= data, + unsigned size) +{ + /*KvaserPCIState *d =3D opaque;*/ +} + +static const MemoryRegionOps kvaser_pci_s5920_io_ops =3D { + .read =3D kvaser_pci_s5920_io_read, + .write =3D kvaser_pci_s5920_io_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .impl =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, +}; + +static const MemoryRegionOps kvaser_pci_sja_io_ops =3D { + .read =3D kvaser_pci_sja_io_read, + .write =3D kvaser_pci_sja_io_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .impl =3D { + .min_access_size =3D 1, + .max_access_size =3D 1, + }, +}; + +static const MemoryRegionOps kvaser_pci_xilinx_io_ops =3D { + .read =3D kvaser_pci_xilinx_io_read, + .write =3D kvaser_pci_xilinx_io_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .impl =3D { + .min_access_size =3D 1, + .max_access_size =3D 1, + }, +}; + +static int kvaser_pci_init(PCIDevice *pci_dev) +{ + KvaserPCIState *d =3D KVASER_PCI_DEV(pci_dev); + CanSJA1000State *s =3D &d->sja_state; + uint8_t *pci_conf; + CanBusState *can_bus; + + if (d->model) { + if (strncmp(d->model, "pcican-s", 256)) { /* for security reason */ + error_report("Can't create CAN device, " + "the model %s is not supported now.", d->model); + exit(1); + } + } + + can_bus =3D can_bus_find_by_name(d->canbus, true); + if (can_bus =3D=3D NULL) { + error_report("Cannot create can find/allocate CAN bus"); + exit(1); + + } + + if (d->host !=3D NULL) { + if (can_bus_connect_to_host_device(can_bus, d->host) < 0) { + error_report("Cannot connect CAN bus to host device \"%s\"", + d->host); + exit(1); + } + } + + pci_conf =3D pci_dev->config; + pci_conf[PCI_INTERRUPT_PIN] =3D 0x01; /* interrupt pin A */ + + d->irq =3D pci_allocate_irq(&d->dev); + + can_sja_init(s, kvaser_pci_irq_raise, kvaser_pci_irq_lower, d); + + qemu_register_reset(kvaser_pci_reset, d); + + if (can_sja_connect_to_bus(s, can_bus) < 0) { + error_report("can_sja_connect_to_bus failed"); + exit(1); + } + + memory_region_init_io(&d->s5920_io, OBJECT(d), &kvaser_pci_s5920_io_op= s, + d, "kvaser_pci-s5920", KVASER_PCI_S5920_RANGE); + memory_region_init_io(&d->sja_io, OBJECT(d), &kvaser_pci_sja_io_ops, + d, "kvaser_pci-sja", KVASER_PCI_SJA_RANGE); + memory_region_init_io(&d->xilinx_io, OBJECT(d), &kvaser_pci_xilinx_io_= ops, + d, "kvaser_pci-xilinx", KVASER_PCI_XILINX_RANGE); + + pci_register_bar(&d->dev, /*BAR*/ 0, PCI_BASE_ADDRESS_SPACE_IO, + &d->s5920_io); + pci_register_bar(&d->dev, /*BAR*/ 1, PCI_BASE_ADDRESS_SPACE_IO, + &d->sja_io); + pci_register_bar(&d->dev, /*BAR*/ 2, PCI_BASE_ADDRESS_SPACE_IO, + &d->xilinx_io); + + return 0; +} + +static void kvaser_pci_exit(PCIDevice *pci_dev) +{ + KvaserPCIState *d =3D KVASER_PCI_DEV(pci_dev); + CanSJA1000State *s =3D &d->sja_state; + + can_sja_disconnect(s); + + qemu_unregister_reset(kvaser_pci_reset, d); + + /* + * regions d->s5920_io, d->sja_io and d->xilinx_io + * are destroyed by QOM now + */ + + can_sja_exit(s); + + qemu_free_irq(d->irq); +} + +static const VMStateDescription vmstate_kvaser_pci =3D { + .name =3D "kvaser_pci", + .version_id =3D 1, + .minimum_version_id =3D 1, + .minimum_version_id_old =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_PCI_DEVICE(dev, KvaserPCIState), + VMSTATE_STRUCT(sja_state, KvaserPCIState, 0, vmstate_can_sja, + CanSJA1000State), + /*char *model,*/ + VMSTATE_UINT32(s5920_intcsr, KvaserPCIState), + VMSTATE_UINT32(s5920_irqstate, KvaserPCIState), + VMSTATE_END_OF_LIST() + } +}; + +static void qdev_kvaser_pci_reset(DeviceState *dev) +{ + KvaserPCIState *d =3D KVASER_PCI_DEV(dev); + kvaser_pci_reset(d); +} + +static Property kvaser_pci_properties[] =3D { + DEFINE_PROP_STRING("canbus", KvaserPCIState, canbus), + DEFINE_PROP_STRING("host", KvaserPCIState, host), + DEFINE_PROP_STRING("model", KvaserPCIState, model), + DEFINE_PROP_END_OF_LIST(), +}; + +static void kvaser_pci_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); + + k->init =3D kvaser_pci_init; + k->exit =3D kvaser_pci_exit; + k->vendor_id =3D KVASER_PCI_VENDOR_ID1; + k->device_id =3D KVASER_PCI_DEVICE_ID1; + k->revision =3D 0x00; + k->class_id =3D 0x00ff00; + dc->desc =3D "Kvaser PCICANx"; + dc->props =3D kvaser_pci_properties; + dc->vmsd =3D &vmstate_kvaser_pci; + set_bit(DEVICE_CATEGORY_MISC, dc->categories); + dc->reset =3D qdev_kvaser_pci_reset; +} + +static const TypeInfo kvaser_pci_info =3D { + .name =3D TYPE_CAN_PCI_DEV, + .parent =3D TYPE_PCI_DEVICE, + .instance_size =3D sizeof(KvaserPCIState), + .class_init =3D kvaser_pci_class_init, + .interfaces =3D (InterfaceInfo[]) { + { INTERFACE_CONVENTIONAL_PCI_DEVICE }, + { }, + }, +}; + +static void kvaser_pci_register_types(void) +{ + type_register_static(&kvaser_pci_info); +} + +type_init(kvaser_pci_register_types) --=20 2.11.0 From nobody Sat May 4 20:54:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1515961415977818.0890901342847; Sun, 14 Jan 2018 12:23:35 -0800 (PST) Received: from localhost ([::1]:33969 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eaooY-00046H-VQ for importer@patchew.org; Sun, 14 Jan 2018 15:23:35 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42198) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eaogs-0007V1-66 for qemu-devel@nongnu.org; Sun, 14 Jan 2018 15:15:39 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eaogp-0005rK-11 for qemu-devel@nongnu.org; Sun, 14 Jan 2018 15:15:38 -0500 Received: from smtp8.web4u.cz ([81.91.87.88]:45560 helo=mx-8.mail.web4u.cz) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eaogo-0005qQ-EF for qemu-devel@nongnu.org; Sun, 14 Jan 2018 15:15:34 -0500 Received: from mx-8.mail.web4u.cz (localhost [127.0.0.1]) by mx-8.mail.web4u.cz (Postfix) with ESMTP id 8430F1FF69C; Sun, 14 Jan 2018 21:15:31 +0100 (CET) Received: from baree.pikron.com (unknown [89.102.4.32]) (Authenticated sender: ppisa@pikron.com) by mx-8.mail.web4u.cz (Postfix) with ESMTPA id 44FB71FF62C; Sun, 14 Jan 2018 21:15:31 +0100 (CET) From: pisa@cmp.felk.cvut.cz To: qemu-devel@nongnu.org Date: Sun, 14 Jan 2018 21:14:11 +0100 Message-Id: <3aa888748c9d7e636e08e7d1c1dbe13e3e8e0e6c.1515960078.git.pisa@cmp.felk.cvut.cz> X-Mailer: git-send-email 2.11.0 In-Reply-To: References: In-Reply-To: References: X-W4U-Auth: a8ac4e6e3a71c8195f61751ed511d9acd76c741a X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 81.91.87.88 Subject: [Qemu-devel] [PATCH V4 5/7] QEMU CAN bus emulation documentation X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marek Vasut , Oliver Hartkopp , Stefan Hajnoczi , Deniz Eren , Oleksij Rempel , Konrad Frederic , Jan Kiszka , Pavel Pisa Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Pavel Pisa Signed-off-by: Pavel Pisa --- docs/can.txt | 78 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 78 insertions(+) create mode 100644 docs/can.txt diff --git a/docs/can.txt b/docs/can.txt new file mode 100644 index 0000000000..ac3170e947 --- /dev/null +++ b/docs/can.txt @@ -0,0 +1,78 @@ +QEMU CAN bus emulation support +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D + +The CAN bus emulation provides mechanism to connect multiple +emulated CAN controller chips together by one or multiple CAN busses +(the controller device "canbus" parameter). The individual busses +can be connected to host system CAN API (at this time only Linux +SocketCAN is supported). + +The concept of busses is generic and different CAN controllers +can be implemented for it but at this time only SJA1000 chip +controller is implemented. + +The PCI addon card hardware has been selected as the first CAN +interface to implement because such device can be easily connected +to systems with different CPU architectures (x86, PowerPC, ARM, etc.). + +The project has been initially started in frame of RTEMS GSoC 2013 +slot by Jin Yang under our mentoring The initial idea was to provide gene= ric +CAN subsystem for RTEMS. But lack of common environment for code and RTEMS +testing lead to goal change to provide environment which provides complete +emulated environment for testing and RTEMS GSoC slot has been donated +to work on CAN hardware emulation on QEMU. + +Examples how to use CAN emulation +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D + +When QEMU with CAN PCI support is compiled then one of the next +CAN boards can be selected + + (1) CAN bus Kvaser PCI CAN-S (single SJA1000 channel) boad. QEMU startup = options + -device kvaser_pci,canbus=3Dcanbus0 + Add "host" parameter to connect device to host system CAN bus + -device kvaser_pci,canbus=3Dcanbus0,host=3Dcan0 + + (2) CAN bus PCM-3680I PCI (dual SJA1000 channel) emulation + -device pcm3680_pci,canbus=3Dcanbus0,host=3Dcan0 + + (3) CAN bus MIOe-3680 PCI (dual SJA1000 channel) emulation + -device mioe3680_pci,canbus=3Dcanbus0,host=3Dcan0 + + +The ''kvaser_pci'' board/device model is compatible with and has been test= ed with +''kvaser_pci'' driver included in mainline Linux kernel. +The tested setup was Linux 4.9 kernel on the host and guest side. + +Next parameters has been used for qemu-system-x86_64 + + qemu-system-x86_64 -enable-kvm -kernel /boot/vmlinuz-4.9.0-4-amd64 \ + -initrd ramdisk.cpio \ + -virtfs local,path=3Dshareddir,security_model=3Dnone,mount_tag=3Dsha= reddir \ + -vga cirrus \ + -device kvaser_pci,canbus=3Dcanbus0,host=3Dcan0 \ + -nographic -append "console=3DttyS0" + +The list of parameters for qemu-system-arm + + qemu-system-arm -cpu arm1176 -m 256 -M versatilepb \ + -kernel kernel-qemu-arm1176-versatilepb \ + -hda rpi-wheezy-overlay \ + -append "console=3DttyAMA0 root=3D/dev/sda2 ro init=3D/sbin/init-ove= rlay" \ + -nographic \ + -virtfs local,path=3Dshareddir,security_model=3Dnone,mount_tag=3Dsha= reddir \ + -device kvaser_pci,canbus=3Dcanbus0,host=3Dcan0 \ + +Links to other resources +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + + (1) Repository with development branch can-pci at Czech Technical Univers= ity + https://gitlab.fel.cvut.cz/canbus/qemu-canbus + (2) GitHub repository with can-pci and our other changes included + https://gitlab.fel.cvut.cz/canbus/qemu-canbus + (3) RTEMS page describing project + https://devel.rtems.org/wiki/Developer/Simulators/QEMU/CANEmulation + (4) RTLWS 2015 article about the projevt and its use with CANopen emulati= on + http://rtime.felk.cvut.cz/publications/public/rtlws2015-qemu-can.pdf + Slides + http://rtime.felk.cvut.cz/publications/public/rtlws2015-qemu-can-slid= es.pdf --=20 2.11.0 From nobody Sat May 4 20:54:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1515961159040505.44154399724744; Sun, 14 Jan 2018 12:19:19 -0800 (PST) Received: from localhost ([::1]:33707 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eaokM-0001HP-O2 for importer@patchew.org; Sun, 14 Jan 2018 15:19:18 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42209) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eaogt-0007Vy-2b for qemu-devel@nongnu.org; Sun, 14 Jan 2018 15:15:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eaogr-0005sj-7N for qemu-devel@nongnu.org; Sun, 14 Jan 2018 15:15:39 -0500 Received: from smtp8.web4u.cz ([81.91.87.88]:45574 helo=mx-8.mail.web4u.cz) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eaogq-0005s8-TD for qemu-devel@nongnu.org; Sun, 14 Jan 2018 15:15:37 -0500 Received: from mx-8.mail.web4u.cz (localhost [127.0.0.1]) by mx-8.mail.web4u.cz (Postfix) with ESMTP id 5313E1FFCDB; Sun, 14 Jan 2018 21:15:34 +0100 (CET) Received: from baree.pikron.com (unknown [89.102.4.32]) (Authenticated sender: ppisa@pikron.com) by mx-8.mail.web4u.cz (Postfix) with ESMTPA id 1870F1FF62C; Sun, 14 Jan 2018 21:15:34 +0100 (CET) From: pisa@cmp.felk.cvut.cz To: qemu-devel@nongnu.org Date: Sun, 14 Jan 2018 21:14:12 +0100 Message-Id: <07099f0ebd7a206ee94eb555be35995e69ab31f5.1515960078.git.pisa@cmp.felk.cvut.cz> X-Mailer: git-send-email 2.11.0 In-Reply-To: References: In-Reply-To: References: X-W4U-Auth: a14e450c380b5771314f382bb7637547deef0733 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 81.91.87.88 Subject: [Qemu-devel] [PATCH V4 6/7] CAN bus PCM-3680I PCI (dual SJA1000 channel) emulation added. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marek Vasut , Oliver Hartkopp , Stefan Hajnoczi , Deniz Eren , Oleksij Rempel , Konrad Frederic , Jan Kiszka , Pavel Pisa Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Deniz Eren Signed-off-by: Deniz Eren Signed-off-by: Pavel Pisa --- hw/can/Makefile.objs | 1 + hw/can/can_pcm3680_pci.c | 336 +++++++++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 337 insertions(+) create mode 100644 hw/can/can_pcm3680_pci.c diff --git a/hw/can/Makefile.objs b/hw/can/Makefile.objs index c9d07b9b16..6a328f0c3a 100644 --- a/hw/can/Makefile.objs +++ b/hw/can/Makefile.objs @@ -9,4 +9,5 @@ common-obj-y +=3D can_host_stub.o endif common-obj-$(CONFIG_CAN_SJA1000) +=3D can_sja1000.o common-obj-$(CONFIG_CAN_PCI) +=3D can_kvaser_pci.o +common-obj-$(CONFIG_CAN_PCI) +=3D can_pcm3680_pci.o endif diff --git a/hw/can/can_pcm3680_pci.c b/hw/can/can_pcm3680_pci.c new file mode 100644 index 0000000000..e85b61849a --- /dev/null +++ b/hw/can/can_pcm3680_pci.c @@ -0,0 +1,336 @@ +/* + * PCM-3680i PCI CAN device (SJA1000 based) emulation + * + * Copyright (c) 2016 Deniz Eren (deniz.eren@icloud.com) + * + * Based on Kvaser PCI CAN device (SJA1000 based) emulation implemented by + * Jin Yang and Pavel Pisa + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "qemu/event_notifier.h" +#include "qemu/thread.h" +#include "qemu/sockets.h" +#include "qemu/error-report.h" +#include "chardev/char.h" +#include "hw/hw.h" +#include "hw/pci/pci.h" +#include "can/can_emu.h" + +#include "can_sja1000.h" + +#define TYPE_CAN_PCI_DEV "pcm3680_pci" + +#define PCM3680i_PCI_DEV(obj) \ + OBJECT_CHECK(Pcm3680iPCIState, (obj), TYPE_CAN_PCI_DEV) + +/* the PCI device and vendor IDs */ +#ifndef PCM3680i_PCI_VENDOR_ID1 +#define PCM3680i_PCI_VENDOR_ID1 0x13fe +#endif + +#ifndef PCM3680i_PCI_DEVICE_ID1 +#define PCM3680i_PCI_DEVICE_ID1 0xc002 +#endif + +#define PCM3680i_PCI_SJA_RANGE 0x200 + +#define PCM3680i_PCI_BYTES_PER_SJA 0x20 + +typedef struct Pcm3680iPCIState { + /*< private >*/ + PCIDevice dev; + /*< public >*/ + MemoryRegion sja_io[2]; + + CanSJA1000State sja_state[2]; + qemu_irq irq; + + char *model; /* The model that support, only SJA1000 now. */ + char *canbus[2]; + char *host[2]; +} Pcm3680iPCIState; + +static void pcm3680i_pci_irq_raise(void *opaque) +{ + Pcm3680iPCIState *d =3D (Pcm3680iPCIState *)opaque; + + qemu_irq_raise(d->irq); +} + +static void pcm3680i_pci_irq_lower(void *opaque) +{ + Pcm3680iPCIState *d =3D (Pcm3680iPCIState *)opaque; + + qemu_irq_lower(d->irq); +} + +static void +pcm3680i_pci_reset(void *opaque) +{ + Pcm3680iPCIState *d =3D (Pcm3680iPCIState *)opaque; + CanSJA1000State *s1 =3D &d->sja_state[0]; + CanSJA1000State *s2 =3D &d->sja_state[1]; + + can_sja_hardware_reset(s1); + can_sja_hardware_reset(s2); +} + +static uint64_t pcm3680i_pci_sja1_io_read(void *opaque, hwaddr addr, + unsigned size) +{ + Pcm3680iPCIState *d =3D opaque; + CanSJA1000State *s =3D &d->sja_state[0]; + + if (addr >=3D PCM3680i_PCI_BYTES_PER_SJA) { + return 0; + } + + return can_sja_mem_read(s, addr, size); +} + +static void pcm3680i_pci_sja1_io_write(void *opaque, hwaddr addr, + uint64_t data, unsigned size) +{ + Pcm3680iPCIState *d =3D opaque; + CanSJA1000State *s =3D &d->sja_state[0]; + + if (addr >=3D PCM3680i_PCI_BYTES_PER_SJA) { + return; + } + + can_sja_mem_write(s, addr, data, size); +} + +static uint64_t pcm3680i_pci_sja2_io_read(void *opaque, hwaddr addr, + unsigned size) +{ + Pcm3680iPCIState *d =3D opaque; + CanSJA1000State *s =3D &d->sja_state[1]; + + if (addr >=3D PCM3680i_PCI_BYTES_PER_SJA) { + return 0; + } + + return can_sja_mem_read(s, addr, size); +} + +static void pcm3680i_pci_sja2_io_write(void *opaque, hwaddr addr, uint64_t= data, + unsigned size) +{ + Pcm3680iPCIState *d =3D opaque; + CanSJA1000State *s =3D &d->sja_state[1]; + + if (addr >=3D PCM3680i_PCI_BYTES_PER_SJA) { + return; + } + + can_sja_mem_write(s, addr, data, size); +} + +static const MemoryRegionOps pcm3680i_pci_sja1_io_ops =3D { + .read =3D pcm3680i_pci_sja1_io_read, + .write =3D pcm3680i_pci_sja1_io_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .impl =3D { + .min_access_size =3D 1, + .max_access_size =3D 1, + }, +}; + +static const MemoryRegionOps pcm3680i_pci_sja2_io_ops =3D { + .read =3D pcm3680i_pci_sja2_io_read, + .write =3D pcm3680i_pci_sja2_io_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .impl =3D { + .min_access_size =3D 1, + .max_access_size =3D 1, + }, +}; + +static int pcm3680i_pci_init(PCIDevice *pci_dev) +{ + Pcm3680iPCIState *d =3D PCM3680i_PCI_DEV(pci_dev); + CanSJA1000State *s1 =3D &d->sja_state[0]; + CanSJA1000State *s2 =3D &d->sja_state[1]; + uint8_t *pci_conf; + CanBusState *can_bus1; + CanBusState *can_bus2; + + if (d->model) { + if (strncmp(d->model, "pcican-s", 256)) { /* for security reason */ + error_report("Can't create CAN device, " + "the model %s is not supported now.", d->model); + exit(1); + } + } + + can_bus1 =3D can_bus_find_by_name(d->canbus[0], true); + if (can_bus1 =3D=3D NULL) { + error_report("Cannot create can find/allocate CAN bus #1"); + exit(1); + } + + can_bus2 =3D can_bus_find_by_name(d->canbus[1], true); + if (can_bus2 =3D=3D NULL) { + error_report("Cannot create can find/allocate CAN bus #2"); + exit(1); + } + + if (d->host[0] !=3D NULL) { + if (can_bus_connect_to_host_device(can_bus1, d->host[0]) < 0) { + error_report("Cannot connect CAN bus to host #1 device \"%s\"", + d->host[0]); + exit(1); + } + } + + if (d->host[1] !=3D NULL) { + if (can_bus_connect_to_host_device(can_bus2, d->host[1]) < 0) { + error_report("Cannot connect CAN bus to host #2 device \"%s\"", + d->host[1]); + exit(1); + } + } + + pci_conf =3D pci_dev->config; + pci_conf[PCI_INTERRUPT_PIN] =3D 0x01; /* interrupt pin A */ + + d->irq =3D pci_allocate_irq(&d->dev); + + can_sja_init(s1, pcm3680i_pci_irq_raise, pcm3680i_pci_irq_lower, d); + can_sja_init(s2, pcm3680i_pci_irq_raise, pcm3680i_pci_irq_lower, d); + + qemu_register_reset(pcm3680i_pci_reset, d); + + if (can_sja_connect_to_bus(s1, can_bus1) < 0) { + error_report("can_sja_connect_to_bus failed"); + exit(1); + } + + if (can_sja_connect_to_bus(s2, can_bus2) < 0) { + error_report("can_sja_connect_to_bus failed"); + exit(1); + } + + memory_region_init_io(&d->sja_io[0], OBJECT(d), &pcm3680i_pci_sja1_io_= ops, + d, "pcm3680i_pci-sja1", PCM3680i_PCI_SJA_RANGE /= 2); + memory_region_init_io(&d->sja_io[1], OBJECT(d), &pcm3680i_pci_sja2_io_= ops, + d, "pcm3680i_pci-sja2", PCM3680i_PCI_SJA_RANGE /= 2); + + pci_register_bar(&d->dev, /*BAR*/ 0, PCI_BASE_ADDRESS_SPACE_IO, + &d->sja_io[0]); + pci_register_bar(&d->dev, /*BAR*/ 1, PCI_BASE_ADDRESS_SPACE_IO, + &d->sja_io[1]); + + return 0; +} + +static void pcm3680i_pci_exit(PCIDevice *pci_dev) +{ + Pcm3680iPCIState *d =3D PCM3680i_PCI_DEV(pci_dev); + CanSJA1000State *s1 =3D &d->sja_state[0]; + CanSJA1000State *s2 =3D &d->sja_state[1]; + + can_sja_disconnect(s1); + can_sja_disconnect(s2); + + qemu_unregister_reset(pcm3680i_pci_reset, d); + + /* + * region d->sja_io is destroyed by QOM now + */ + /* memory_region_destroy(&d->sja_io[0]); */ + /* memory_region_destroy(&d->sja_io[1]); */ + + can_sja_exit(s1); + can_sja_exit(s2); + + qemu_free_irq(d->irq); +} + +static const VMStateDescription vmstate_pcm3680i_pci =3D { + .name =3D "pcm3680i_pci", + .version_id =3D 1, + .minimum_version_id =3D 1, + .minimum_version_id_old =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_PCI_DEVICE(dev, Pcm3680iPCIState), + VMSTATE_STRUCT(sja_state[0], Pcm3680iPCIState, 0, + vmstate_can_sja, CanSJA1000State), + VMSTATE_STRUCT(sja_state[1], Pcm3680iPCIState, 0, + vmstate_can_sja, CanSJA1000State), + VMSTATE_END_OF_LIST() + } +}; + +static void qdev_pcm3680i_pci_reset(DeviceState *dev) +{ + Pcm3680iPCIState *d =3D PCM3680i_PCI_DEV(dev); + pcm3680i_pci_reset(d); +} + +static Property pcm3680i_pci_properties[] =3D { + DEFINE_PROP_STRING("canbus1", Pcm3680iPCIState, canbus[0]), + DEFINE_PROP_STRING("canbus2", Pcm3680iPCIState, canbus[1]), + DEFINE_PROP_STRING("host1", Pcm3680iPCIState, host[0]), + DEFINE_PROP_STRING("host2", Pcm3680iPCIState, host[1]), + DEFINE_PROP_STRING("model", Pcm3680iPCIState, model), + DEFINE_PROP_END_OF_LIST(), +}; + +static void pcm3680i_pci_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); + + k->init =3D pcm3680i_pci_init; + k->exit =3D pcm3680i_pci_exit; + k->vendor_id =3D PCM3680i_PCI_VENDOR_ID1; + k->device_id =3D PCM3680i_PCI_DEVICE_ID1; + k->revision =3D 0x00; + k->class_id =3D 0x000c09; + k->subsystem_vendor_id =3D PCM3680i_PCI_VENDOR_ID1; + k->subsystem_id =3D PCM3680i_PCI_DEVICE_ID1; + dc->desc =3D "Pcm3680i PCICANx"; + dc->props =3D pcm3680i_pci_properties; + dc->vmsd =3D &vmstate_pcm3680i_pci; + set_bit(DEVICE_CATEGORY_MISC, dc->categories); + dc->reset =3D qdev_pcm3680i_pci_reset; +} + +static const TypeInfo pcm3680i_pci_info =3D { + .name =3D TYPE_CAN_PCI_DEV, + .parent =3D TYPE_PCI_DEVICE, + .instance_size =3D sizeof(Pcm3680iPCIState), + .class_init =3D pcm3680i_pci_class_init, + .interfaces =3D (InterfaceInfo[]) { + { INTERFACE_CONVENTIONAL_PCI_DEVICE }, + { }, + }, +}; + +static void pcm3680i_pci_register_types(void) +{ + type_register_static(&pcm3680i_pci_info); +} + +type_init(pcm3680i_pci_register_types) --=20 2.11.0 From nobody Sat May 4 20:54:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1515961508190626.7331231329164; Sun, 14 Jan 2018 12:25:08 -0800 (PST) Received: from localhost ([::1]:34073 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eaoq3-0005N3-BB for importer@patchew.org; Sun, 14 Jan 2018 15:25:07 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42227) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eaogv-0007Xt-DT for qemu-devel@nongnu.org; Sun, 14 Jan 2018 15:15:43 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eaogt-0005ub-Nb for qemu-devel@nongnu.org; Sun, 14 Jan 2018 15:15:41 -0500 Received: from smtp8.web4u.cz ([81.91.87.88]:45588 helo=mx-8.mail.web4u.cz) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eaogt-0005tZ-DK for qemu-devel@nongnu.org; Sun, 14 Jan 2018 15:15:39 -0500 Received: from mx-8.mail.web4u.cz (localhost [127.0.0.1]) by mx-8.mail.web4u.cz (Postfix) with ESMTP id C9F051FF69C; Sun, 14 Jan 2018 21:15:36 +0100 (CET) Received: from baree.pikron.com (unknown [89.102.4.32]) (Authenticated sender: ppisa@pikron.com) by mx-8.mail.web4u.cz (Postfix) with ESMTPA id 7D9631FF62C; Sun, 14 Jan 2018 21:15:36 +0100 (CET) From: pisa@cmp.felk.cvut.cz To: qemu-devel@nongnu.org Date: Sun, 14 Jan 2018 21:14:13 +0100 Message-Id: <7f4a5fc62ab96fd20c82f9edd74f82efe1195219.1515960078.git.pisa@cmp.felk.cvut.cz> X-Mailer: git-send-email 2.11.0 In-Reply-To: References: In-Reply-To: References: X-W4U-Auth: 7c5b6e7879f8a6d9d30b81a747fb637c41513946 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 81.91.87.88 Subject: [Qemu-devel] [PATCH V4 7/7] CAN bus MIOe-3680 PCI (dual SJA1000 channel) emulation added. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marek Vasut , Oliver Hartkopp , Stefan Hajnoczi , Deniz Eren , Oleksij Rempel , Konrad Frederic , Jan Kiszka , Pavel Pisa Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Deniz Eren Signed-off-by: Deniz Eren Signed-off-by: Pavel Pisa --- hw/can/Makefile.objs | 1 + hw/can/can_mioe3680_pci.c | 336 ++++++++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 337 insertions(+) create mode 100644 hw/can/can_mioe3680_pci.c diff --git a/hw/can/Makefile.objs b/hw/can/Makefile.objs index 6a328f0c3a..8fcc455800 100644 --- a/hw/can/Makefile.objs +++ b/hw/can/Makefile.objs @@ -10,4 +10,5 @@ endif common-obj-$(CONFIG_CAN_SJA1000) +=3D can_sja1000.o common-obj-$(CONFIG_CAN_PCI) +=3D can_kvaser_pci.o common-obj-$(CONFIG_CAN_PCI) +=3D can_pcm3680_pci.o +common-obj-$(CONFIG_CAN_PCI) +=3D can_mioe3680_pci.o endif diff --git a/hw/can/can_mioe3680_pci.c b/hw/can/can_mioe3680_pci.c new file mode 100644 index 0000000000..7e761a838a --- /dev/null +++ b/hw/can/can_mioe3680_pci.c @@ -0,0 +1,336 @@ +/* + * MIOe-3680 PCI CAN device (SJA1000 based) emulation + * + * Copyright (c) 2016 Deniz Eren (deniz.eren@icloud.com) + * + * Based on Kvaser PCI CAN device (SJA1000 based) emulation implemented by + * Jin Yang and Pavel Pisa + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "qemu/event_notifier.h" +#include "qemu/thread.h" +#include "qemu/sockets.h" +#include "qemu/error-report.h" +#include "chardev/char.h" +#include "hw/hw.h" +#include "hw/pci/pci.h" +#include "can/can_emu.h" + +#include "can_sja1000.h" + +#define TYPE_CAN_PCI_DEV "mioe3680_pci" + +#define MIOe3680_PCI_DEV(obj) \ + OBJECT_CHECK(Mioe3680PCIState, (obj), TYPE_CAN_PCI_DEV) + +/* the PCI device and vendor IDs */ +#ifndef MIOe3680_PCI_VENDOR_ID1 +#define MIOe3680_PCI_VENDOR_ID1 0x13fe +#endif + +#ifndef MIOe3680_PCI_DEVICE_ID1 +#define MIOe3680_PCI_DEVICE_ID1 0xc302 +#endif + +#define MIOe3680_PCI_SJA_RANGE 0x800 + +#define MIOe3680_PCI_BYTES_PER_SJA 0x80 + +typedef struct Mioe3680PCIState { + /*< private >*/ + PCIDevice dev; + /*< public >*/ + MemoryRegion sja_io[2]; + + CanSJA1000State sja_state[2]; + qemu_irq irq; + + char *model; /* The model that support, only SJA1000 now. */ + char *canbus[2]; + char *host[2]; +} Mioe3680PCIState; + +static void mioe3680_pci_irq_raise(void *opaque) +{ + Mioe3680PCIState *d =3D (Mioe3680PCIState *)opaque; + + qemu_irq_raise(d->irq); +} + +static void mioe3680_pci_irq_lower(void *opaque) +{ + Mioe3680PCIState *d =3D (Mioe3680PCIState *)opaque; + + qemu_irq_lower(d->irq); +} + +static void +mioe3680_pci_reset(void *opaque) +{ + Mioe3680PCIState *d =3D (Mioe3680PCIState *)opaque; + CanSJA1000State *s1 =3D &d->sja_state[0]; + CanSJA1000State *s2 =3D &d->sja_state[1]; + + can_sja_hardware_reset(s1); + can_sja_hardware_reset(s2); +} + +static uint64_t mioe3680_pci_sja1_io_read(void *opaque, hwaddr addr, + unsigned size) +{ + Mioe3680PCIState *d =3D opaque; + CanSJA1000State *s =3D &d->sja_state[0]; + + if (addr >=3D MIOe3680_PCI_BYTES_PER_SJA) { + return 0; + } + + return can_sja_mem_read(s, addr >> 2, size); +} + +static void mioe3680_pci_sja1_io_write(void *opaque, hwaddr addr, uint64_t= data, + unsigned size) +{ + Mioe3680PCIState *d =3D opaque; + CanSJA1000State *s =3D &d->sja_state[0]; + + if (addr >=3D MIOe3680_PCI_BYTES_PER_SJA) { + return; + } + + can_sja_mem_write(s, addr >> 2, data, size); +} + +static uint64_t mioe3680_pci_sja2_io_read(void *opaque, hwaddr addr, + unsigned size) +{ + Mioe3680PCIState *d =3D opaque; + CanSJA1000State *s =3D &d->sja_state[1]; + + if (addr >=3D MIOe3680_PCI_BYTES_PER_SJA) { + return 0; + } + + return can_sja_mem_read(s, addr >> 2, size); +} + +static void mioe3680_pci_sja2_io_write(void *opaque, hwaddr addr, uint64_t= data, + unsigned size) +{ + Mioe3680PCIState *d =3D opaque; + CanSJA1000State *s =3D &d->sja_state[1]; + + if (addr >=3D MIOe3680_PCI_BYTES_PER_SJA) { + return; + } + + can_sja_mem_write(s, addr >> 2, data, size); +} + +static const MemoryRegionOps mioe3680_pci_sja1_io_ops =3D { + .read =3D mioe3680_pci_sja1_io_read, + .write =3D mioe3680_pci_sja1_io_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .impl =3D { + .min_access_size =3D 1, + .max_access_size =3D 1, + }, +}; + +static const MemoryRegionOps mioe3680_pci_sja2_io_ops =3D { + .read =3D mioe3680_pci_sja2_io_read, + .write =3D mioe3680_pci_sja2_io_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .impl =3D { + .min_access_size =3D 1, + .max_access_size =3D 1, + }, +}; + +static int mioe3680_pci_init(PCIDevice *pci_dev) +{ + Mioe3680PCIState *d =3D MIOe3680_PCI_DEV(pci_dev); + CanSJA1000State *s1 =3D &d->sja_state[0]; + CanSJA1000State *s2 =3D &d->sja_state[1]; + uint8_t *pci_conf; + CanBusState *can_bus1; + CanBusState *can_bus2; + + if (d->model) { + if (strncmp(d->model, "pcican-s", 256)) { /* for security reason */ + error_report("Can't create CAN device, " + "the model %s is not supported now.", d->model); + exit(1); + } + } + + can_bus1 =3D can_bus_find_by_name(d->canbus[0], true); + if (can_bus1 =3D=3D NULL) { + error_report("Cannot create can find/allocate CAN bus #1"); + exit(1); + } + + can_bus2 =3D can_bus_find_by_name(d->canbus[1], true); + if (can_bus2 =3D=3D NULL) { + error_report("Cannot create can find/allocate CAN bus #2"); + exit(1); + } + + if (d->host[0] !=3D NULL) { + if (can_bus_connect_to_host_device(can_bus1, d->host[0]) < 0) { + error_report("Cannot connect CAN bus to host #1 device \"%s\"", + d->host[0]); + exit(1); + } + } + + if (d->host[1] !=3D NULL) { + if (can_bus_connect_to_host_device(can_bus2, d->host[1]) < 0) { + error_report("Cannot connect CAN bus to host #2 device \"%s\"", + d->host[1]); + exit(1); + } + } + + pci_conf =3D pci_dev->config; + pci_conf[PCI_INTERRUPT_PIN] =3D 0x01; /* interrupt pin A */ + + d->irq =3D pci_allocate_irq(&d->dev); + + can_sja_init(s1, mioe3680_pci_irq_raise, mioe3680_pci_irq_lower, d); + can_sja_init(s2, mioe3680_pci_irq_raise, mioe3680_pci_irq_lower, d); + + qemu_register_reset(mioe3680_pci_reset, d); + + if (can_sja_connect_to_bus(s1, can_bus1) < 0) { + error_report("can_sja_connect_to_bus failed"); + exit(1); + } + + if (can_sja_connect_to_bus(s2, can_bus2) < 0) { + error_report("can_sja_connect_to_bus failed"); + exit(1); + } + + memory_region_init_io(&d->sja_io[0], OBJECT(d), &mioe3680_pci_sja1_io_= ops, + d, "mioe3680_pci-sja1", MIOe3680_PCI_SJA_RANGE /= 2); + memory_region_init_io(&d->sja_io[1], OBJECT(d), &mioe3680_pci_sja2_io_= ops, + d, "mioe3680_pci-sja2", MIOe3680_PCI_SJA_RANGE /= 2); + + pci_register_bar(&d->dev, /*BAR*/ 0, PCI_BASE_ADDRESS_SPACE_IO, + &d->sja_io[0]); + pci_register_bar(&d->dev, /*BAR*/ 1, PCI_BASE_ADDRESS_SPACE_IO, + &d->sja_io[1]); + + return 0; +} + +static void mioe3680_pci_exit(PCIDevice *pci_dev) +{ + Mioe3680PCIState *d =3D MIOe3680_PCI_DEV(pci_dev); + CanSJA1000State *s1 =3D &d->sja_state[0]; + CanSJA1000State *s2 =3D &d->sja_state[1]; + + can_sja_disconnect(s1); + can_sja_disconnect(s2); + + qemu_unregister_reset(mioe3680_pci_reset, d); + + /* + * region d->sja_io is destroyed by QOM now + */ + /* memory_region_destroy(&d->sja_io[0]); */ + /* memory_region_destroy(&d->sja_io[1]); */ + + can_sja_exit(s1); + can_sja_exit(s2); + + qemu_free_irq(d->irq); +} + +static const VMStateDescription vmstate_mioe3680_pci =3D { + .name =3D "mioe3680_pci", + .version_id =3D 1, + .minimum_version_id =3D 1, + .minimum_version_id_old =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_PCI_DEVICE(dev, Mioe3680PCIState), + VMSTATE_STRUCT(sja_state[0], Mioe3680PCIState, 0, vmstate_can_sja, + CanSJA1000State), + VMSTATE_STRUCT(sja_state[1], Mioe3680PCIState, 0, vmstate_can_sja, + CanSJA1000State), + VMSTATE_END_OF_LIST() + } +}; + +static void qdev_mioe3680_pci_reset(DeviceState *dev) +{ + Mioe3680PCIState *d =3D MIOe3680_PCI_DEV(dev); + mioe3680_pci_reset(d); +} + +static Property mioe3680_pci_properties[] =3D { + DEFINE_PROP_STRING("canbus1", Mioe3680PCIState, canbus[0]), + DEFINE_PROP_STRING("canbus2", Mioe3680PCIState, canbus[1]), + DEFINE_PROP_STRING("host1", Mioe3680PCIState, host[0]), + DEFINE_PROP_STRING("host2", Mioe3680PCIState, host[1]), + DEFINE_PROP_STRING("model", Mioe3680PCIState, model), + DEFINE_PROP_END_OF_LIST(), +}; + +static void mioe3680_pci_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); + + k->init =3D mioe3680_pci_init; + k->exit =3D mioe3680_pci_exit; + k->vendor_id =3D MIOe3680_PCI_VENDOR_ID1; + k->device_id =3D MIOe3680_PCI_DEVICE_ID1; + k->revision =3D 0x00; + k->class_id =3D 0x000c09; + k->subsystem_vendor_id =3D MIOe3680_PCI_VENDOR_ID1; + k->subsystem_id =3D MIOe3680_PCI_DEVICE_ID1; + dc->desc =3D "Mioe3680 PCICANx"; + dc->props =3D mioe3680_pci_properties; + dc->vmsd =3D &vmstate_mioe3680_pci; + set_bit(DEVICE_CATEGORY_MISC, dc->categories); + dc->reset =3D qdev_mioe3680_pci_reset; +} + +static const TypeInfo mioe3680_pci_info =3D { + .name =3D TYPE_CAN_PCI_DEV, + .parent =3D TYPE_PCI_DEVICE, + .instance_size =3D sizeof(Mioe3680PCIState), + .class_init =3D mioe3680_pci_class_init, + .interfaces =3D (InterfaceInfo[]) { + { INTERFACE_CONVENTIONAL_PCI_DEVICE }, + { }, + }, +}; + +static void mioe3680_pci_register_types(void) +{ + type_register_static(&mioe3680_pci_info); +} + +type_init(mioe3680_pci_register_types) --=20 2.11.0