Update the reset values of the Xilinx ZynqMP QSPI device to match the
resister spec here:
https://www.xilinx.com/html_docs/registers/ug1087/ug1087-zynq-ultrascale-registers.html

V3:
 - Match documented name
V2:
 - Don't double set registers

Based-on: 20171126231634.9531-14-frasse.iglesias@gmail.com

Alistair Francis (3):
  xilinx_spips: Update the QSPI Mod ID reset value
  xilinx_spips: Set all of the reset values
  xilinx_spips: Use memset instead of a for loop to zero registers

 hw/ssi/xilinx_spips.c         | 45 +++++++++++++++++++++++++++++++------------
 include/hw/ssi/xilinx_spips.h |  2 +-
 2 files changed, 34 insertions(+), 13 deletions(-)

-- 
2.14.1

On 12 December 2017 at 18:54, Alistair Francis
<alistair.francis@xilinx.com> wrote:
> Update the reset values of the Xilinx ZynqMP QSPI device to match the
> resister spec here:
> https://www.xilinx.com/html_docs/registers/ug1087/ug1087-zynq-ultrascale-registers.html
>
> V3:
>  - Match documented name
> V2:
>  - Don't double set registers
>
> Based-on: 20171126231634.9531-14-frasse.iglesias@gmail.com



Applied to target-arm.next, thanks.

-- PMM