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X-Received-From: 2607:f8b0:4001:c0b::243 Subject: [Qemu-devel] [PATCH 01/17] openpic: debug w/ info_report() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Davidsaver , qemu-ppc@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Replace *printf() with *_report(). Remove trailing new lines. Signed-off-by: Michael Davidsaver --- hw/intc/openpic.c | 102 +++++++++++++++++++++++++++-----------------------= ---- 1 file changed, 51 insertions(+), 51 deletions(-) diff --git a/hw/intc/openpic.c b/hw/intc/openpic.c index 10d6e871fb..9159a06f07 100644 --- a/hw/intc/openpic.c +++ b/hw/intc/openpic.c @@ -46,6 +46,7 @@ #include "qapi/qmp/qerror.h" #include "qemu/log.h" #include "qemu/timer.h" +#include "qemu/error-report.h" =20 //#define DEBUG_OPENPIC =20 @@ -58,8 +59,7 @@ static const int debug_openpic =3D 0; static int get_current_cpu(void); #define DPRINTF(fmt, ...) do { \ if (debug_openpic) { \ - printf("Core%d: ", get_current_cpu()); \ - printf(fmt , ## __VA_ARGS__); \ + info_report("Core%d: " fmt, get_current_cpu(), ## __VA_ARGS__)= ; \ } \ } while (0) =20 @@ -173,7 +173,7 @@ static int inttgt_to_output(int inttgt) } } =20 - fprintf(stderr, "%s: unsupported inttgt %d\n", __func__, inttgt); + error_report("%s: unsupported inttgt %d", __func__, inttgt); return OPENPIC_OUTPUT_INT; } =20 @@ -372,7 +372,7 @@ static void IRQ_check(OpenPICState *opp, IRQQueue *q) break; } =20 - DPRINTF("IRQ_check: irq %d set ivpr_pr=3D%d pr=3D%d\n", + DPRINTF("IRQ_check: irq %d set ivpr_pr=3D%d pr=3D%d", irq, IVPR_PRIORITY(opp->src[irq].ivpr), priority); =20 if (IVPR_PRIORITY(opp->src[irq].ivpr) > priority) { @@ -403,11 +403,11 @@ static void IRQ_local_pipe(OpenPICState *opp, int n_C= PU, int n_IRQ, dst =3D &opp->dst[n_CPU]; src =3D &opp->src[n_IRQ]; =20 - DPRINTF("%s: IRQ %d active %d was %d\n", + DPRINTF("%s: IRQ %d active %d was %d", __func__, n_IRQ, active, was_active); =20 if (src->output !=3D OPENPIC_OUTPUT_INT) { - DPRINTF("%s: output %d irq %d active %d was %d count %d\n", + DPRINTF("%s: output %d irq %d active %d was %d count %d", __func__, src->output, n_IRQ, active, was_active, dst->outputs_active[src->output]); =20 @@ -417,13 +417,13 @@ static void IRQ_local_pipe(OpenPICState *opp, int n_C= PU, int n_IRQ, */ if (active) { if (!was_active && dst->outputs_active[src->output]++ =3D=3D 0= ) { - DPRINTF("%s: Raise OpenPIC output %d cpu %d irq %d\n", + DPRINTF("%s: Raise OpenPIC output %d cpu %d irq %d", __func__, src->output, n_CPU, n_IRQ); qemu_irq_raise(dst->irqs[src->output]); } } else { if (was_active && --dst->outputs_active[src->output] =3D=3D 0)= { - DPRINTF("%s: Lower OpenPIC output %d cpu %d irq %d\n", + DPRINTF("%s: Lower OpenPIC output %d cpu %d irq %d", __func__, src->output, n_CPU, n_IRQ); qemu_irq_lower(dst->irqs[src->output]); } @@ -446,7 +446,7 @@ static void IRQ_local_pipe(OpenPICState *opp, int n_CPU= , int n_IRQ, IRQ_check(opp, &dst->raised); =20 if (active && priority <=3D dst->ctpr) { - DPRINTF("%s: IRQ %d priority %d too low for ctpr %d on CPU %d\n", + DPRINTF("%s: IRQ %d priority %d too low for ctpr %d on CPU %d", __func__, n_IRQ, priority, dst->ctpr, n_CPU); active =3D 0; } @@ -454,10 +454,10 @@ static void IRQ_local_pipe(OpenPICState *opp, int n_C= PU, int n_IRQ, if (active) { if (IRQ_get_next(opp, &dst->servicing) >=3D 0 && priority <=3D dst->servicing.priority) { - DPRINTF("%s: IRQ %d is hidden by servicing IRQ %d on CPU %d\n", + DPRINTF("%s: IRQ %d is hidden by servicing IRQ %d on CPU %d", __func__, n_IRQ, dst->servicing.next, n_CPU); } else { - DPRINTF("%s: Raise OpenPIC INT output cpu %d irq %d/%d\n", + DPRINTF("%s: Raise OpenPIC INT output cpu %d irq %d/%d", __func__, n_CPU, n_IRQ, dst->raised.next); qemu_irq_raise(opp->dst[n_CPU].irqs[OPENPIC_OUTPUT_INT]); } @@ -465,12 +465,12 @@ static void IRQ_local_pipe(OpenPICState *opp, int n_C= PU, int n_IRQ, IRQ_get_next(opp, &dst->servicing); if (dst->raised.priority > dst->ctpr && dst->raised.priority > dst->servicing.priority) { - DPRINTF("%s: IRQ %d inactive, IRQ %d prio %d above %d/%d, CPU = %d\n", + DPRINTF("%s: IRQ %d inactive, IRQ %d prio %d above %d/%d, CPU = %d", __func__, n_IRQ, dst->raised.next, dst->raised.priorit= y, dst->ctpr, dst->servicing.priority, n_CPU); /* IRQ line stays asserted */ } else { - DPRINTF("%s: IRQ %d inactive, current prio %d/%d, CPU %d\n", + DPRINTF("%s: IRQ %d inactive, current prio %d/%d, CPU %d", __func__, n_IRQ, dst->ctpr, dst->servicing.priority, n= _CPU); qemu_irq_lower(opp->dst[n_CPU].irqs[OPENPIC_OUTPUT_INT]); } @@ -489,7 +489,7 @@ static void openpic_update_irq(OpenPICState *opp, int n= _IRQ) =20 if ((src->ivpr & IVPR_MASK_MASK) && !src->nomask) { /* Interrupt source is disabled */ - DPRINTF("%s: IRQ %d is disabled\n", __func__, n_IRQ); + DPRINTF("%s: IRQ %d is disabled", __func__, n_IRQ); active =3D false; } =20 @@ -500,7 +500,7 @@ static void openpic_update_irq(OpenPICState *opp, int n= _IRQ) * ctpr may have changed and we need to withdraw the interrupt. */ if (!active && !was_active) { - DPRINTF("%s: IRQ %d is already inactive\n", __func__, n_IRQ); + DPRINTF("%s: IRQ %d is already inactive", __func__, n_IRQ); return; } =20 @@ -512,7 +512,7 @@ static void openpic_update_irq(OpenPICState *opp, int n= _IRQ) =20 if (src->destmask =3D=3D 0) { /* No target */ - DPRINTF("%s: IRQ %d has no target\n", __func__, n_IRQ); + DPRINTF("%s: IRQ %d has no target", __func__, n_IRQ); return; } =20 @@ -547,12 +547,12 @@ static void openpic_set_irq(void *opaque, int n_IRQ, = int level) IRQSource *src; =20 if (n_IRQ >=3D OPENPIC_MAX_IRQ) { - fprintf(stderr, "%s: IRQ %d out of range\n", __func__, n_IRQ); + error_report("%s: IRQ %d out of range", __func__, n_IRQ); abort(); } =20 src =3D &opp->src[n_IRQ]; - DPRINTF("openpic: set irq %d =3D %d ivpr=3D0x%08x\n", + DPRINTF("openpic: set irq %d =3D %d ivpr=3D0x%08x", n_IRQ, level, src->ivpr); if (src->level) { /* level-sensitive irq */ @@ -612,13 +612,13 @@ static inline void write_IRQreg_idr(OpenPICState *opp= , int n_IRQ, uint32_t val) } =20 src->idr =3D val & mask; - DPRINTF("Set IDR %d to 0x%08x\n", n_IRQ, src->idr); + DPRINTF("Set IDR %d to 0x%08x", n_IRQ, src->idr); =20 if (opp->flags & OPENPIC_FLAG_IDR_CRIT) { if (src->idr & crit_mask) { if (src->idr & normal_mask) { DPRINTF("%s: IRQ configured for multiple output types, usi= ng " - "critical\n", __func__); + "critical", __func__); } =20 src->output =3D OPENPIC_OUTPUT_CINT; @@ -648,7 +648,7 @@ static inline void write_IRQreg_ilr(OpenPICState *opp, = int n_IRQ, uint32_t val) IRQSource *src =3D &opp->src[n_IRQ]; =20 src->output =3D inttgt_to_output(val & ILR_INTTGT_MASK); - DPRINTF("Set ILR %d to 0x%08x, output %d\n", n_IRQ, src->idr, + DPRINTF("Set ILR %d to 0x%08x, output %d", n_IRQ, src->idr, src->output); =20 /* TODO: on MPIC v4.0 only, set nomask for non-INT */ @@ -688,7 +688,7 @@ static inline void write_IRQreg_ivpr(OpenPICState *opp,= int n_IRQ, uint32_t val) } =20 openpic_update_irq(opp, n_IRQ); - DPRINTF("Set IVPR %d to 0x%08x -> 0x%08x\n", n_IRQ, val, + DPRINTF("Set IVPR %d to 0x%08x -> 0x%08x", n_IRQ, val, opp->src[n_IRQ].ivpr); } =20 @@ -719,7 +719,7 @@ static void openpic_gbl_write(void *opaque, hwaddr addr= , uint64_t val, IRQDest *dst; int idx; =20 - DPRINTF("%s: addr %#" HWADDR_PRIx " <=3D %08" PRIx64 "\n", + DPRINTF("%s: addr %#" HWADDR_PRIx " <=3D %08" PRIx64, __func__, addr, val); if (addr & 0xF) { return; @@ -747,11 +747,11 @@ static void openpic_gbl_write(void *opaque, hwaddr ad= dr, uint64_t val, case 0x1090: /* PIR */ for (idx =3D 0; idx < opp->nb_cpus; idx++) { if ((val & (1 << idx)) && !(opp->pir & (1 << idx))) { - DPRINTF("Raise OpenPIC RESET output for CPU %d\n", idx); + DPRINTF("Raise OpenPIC RESET output for CPU %d", idx); dst =3D &opp->dst[idx]; qemu_irq_raise(dst->irqs[OPENPIC_OUTPUT_RESET]); } else if (!(val & (1 << idx)) && (opp->pir & (1 << idx))) { - DPRINTF("Lower OpenPIC RESET output for CPU %d\n", idx); + DPRINTF("Lower OpenPIC RESET output for CPU %d", idx); dst =3D &opp->dst[idx]; qemu_irq_lower(dst->irqs[OPENPIC_OUTPUT_RESET]); } @@ -781,7 +781,7 @@ static uint64_t openpic_gbl_read(void *opaque, hwaddr a= ddr, unsigned len) OpenPICState *opp =3D opaque; uint32_t retval; =20 - DPRINTF("%s: addr %#" HWADDR_PRIx "\n", __func__, addr); + DPRINTF("%s: addr %#" HWADDR_PRIx, __func__, addr); retval =3D 0xFFFFFFFF; if (addr & 0xF) { return retval; @@ -828,7 +828,7 @@ static uint64_t openpic_gbl_read(void *opaque, hwaddr a= ddr, unsigned len) default: break; } - DPRINTF("%s: =3D> 0x%08x\n", __func__, retval); + DPRINTF("%s: =3D> 0x%08x", __func__, retval); =20 return retval; } @@ -843,7 +843,7 @@ static void qemu_timer_cb(void *opaque) uint32_t val =3D tmr->tbcr & ~TBCR_CI; uint32_t tog =3D ((tmr->tccr & TCCR_TOG) ^ TCCR_TOG); /* invert toggl= e. */ =20 - DPRINTF("%s n_IRQ=3D%d\n", __func__, n_IRQ); + DPRINTF("%s n_IRQ=3D%d", __func__, n_IRQ); /* Reload current count from base count and setup timer. */ tmr->tccr =3D val | tog; openpic_tmr_set_tmr(tmr, val, /*enabled=3D*/true); @@ -898,7 +898,7 @@ static void openpic_tmr_write(void *opaque, hwaddr addr= , uint64_t val, OpenPICState *opp =3D opaque; int idx; =20 - DPRINTF("%s: addr %#" HWADDR_PRIx " <=3D %08" PRIx64 "\n", + DPRINTF("%s: addr %#" HWADDR_PRIx " <=3D %08" PRIx64, __func__, (addr + 0x10f0), val); if (addr & 0xF) { return; @@ -943,7 +943,7 @@ static uint64_t openpic_tmr_read(void *opaque, hwaddr a= ddr, unsigned len) uint32_t retval =3D -1; int idx; =20 - DPRINTF("%s: addr %#" HWADDR_PRIx "\n", __func__, addr + 0x10f0); + DPRINTF("%s: addr %#" HWADDR_PRIx, __func__, addr + 0x10f0); if (addr & 0xF) { goto out; } @@ -970,7 +970,7 @@ static uint64_t openpic_tmr_read(void *opaque, hwaddr a= ddr, unsigned len) } =20 out: - DPRINTF("%s: =3D> 0x%08x\n", __func__, retval); + DPRINTF("%s: =3D> 0x%08x", __func__, retval); =20 return retval; } @@ -981,7 +981,7 @@ static void openpic_src_write(void *opaque, hwaddr addr= , uint64_t val, OpenPICState *opp =3D opaque; int idx; =20 - DPRINTF("%s: addr %#" HWADDR_PRIx " <=3D %08" PRIx64 "\n", + DPRINTF("%s: addr %#" HWADDR_PRIx " <=3D %08" PRIx64, __func__, addr, val); =20 addr =3D addr & 0xffff; @@ -1006,7 +1006,7 @@ static uint64_t openpic_src_read(void *opaque, uint64= _t addr, unsigned len) uint32_t retval; int idx; =20 - DPRINTF("%s: addr %#" HWADDR_PRIx "\n", __func__, addr); + DPRINTF("%s: addr %#" HWADDR_PRIx, __func__, addr); retval =3D 0xFFFFFFFF; =20 addr =3D addr & 0xffff; @@ -1024,7 +1024,7 @@ static uint64_t openpic_src_read(void *opaque, uint64= _t addr, unsigned len) break; } =20 - DPRINTF("%s: =3D> 0x%08x\n", __func__, retval); + DPRINTF("%s: =3D> 0x%08x", __func__, retval); return retval; } =20 @@ -1035,7 +1035,7 @@ static void openpic_msi_write(void *opaque, hwaddr ad= dr, uint64_t val, int idx =3D opp->irq_msi; int srs, ibs; =20 - DPRINTF("%s: addr %#" HWADDR_PRIx " <=3D 0x%08" PRIx64 "\n", + DPRINTF("%s: addr %#" HWADDR_PRIx " <=3D 0x%08" PRIx64, __func__, addr, val); if (addr & 0xF) { return; @@ -1061,7 +1061,7 @@ static uint64_t openpic_msi_read(void *opaque, hwaddr= addr, unsigned size) uint64_t r =3D 0; int i, srs; =20 - DPRINTF("%s: addr %#" HWADDR_PRIx "\n", __func__, addr); + DPRINTF("%s: addr %#" HWADDR_PRIx, __func__, addr); if (addr & 0xF) { return -1; } @@ -1096,7 +1096,7 @@ static uint64_t openpic_summary_read(void *opaque, hw= addr addr, unsigned size) { uint64_t r =3D 0; =20 - DPRINTF("%s: addr %#" HWADDR_PRIx "\n", __func__, addr); + DPRINTF("%s: addr %#" HWADDR_PRIx, __func__, addr); =20 /* TODO: EISR/EIMR */ =20 @@ -1106,7 +1106,7 @@ static uint64_t openpic_summary_read(void *opaque, hw= addr addr, unsigned size) static void openpic_summary_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) { - DPRINTF("%s: addr %#" HWADDR_PRIx " <=3D 0x%08" PRIx64 "\n", + DPRINTF("%s: addr %#" HWADDR_PRIx " <=3D 0x%08" PRIx64, __func__, addr, val); =20 /* TODO: EISR/EIMR */ @@ -1120,7 +1120,7 @@ static void openpic_cpu_write_internal(void *opaque, = hwaddr addr, IRQDest *dst; int s_IRQ, n_IRQ; =20 - DPRINTF("%s: cpu %d addr %#" HWADDR_PRIx " <=3D 0x%08x\n", __func__, i= dx, + DPRINTF("%s: cpu %d addr %#" HWADDR_PRIx " <=3D 0x%08x", __func__, idx, addr, val); =20 if (idx < 0 || idx >=3D opp->nb_cpus) { @@ -1146,16 +1146,16 @@ static void openpic_cpu_write_internal(void *opaque= , hwaddr addr, case 0x80: /* CTPR */ dst->ctpr =3D val & 0x0000000F; =20 - DPRINTF("%s: set CPU %d ctpr to %d, raised %d servicing %d\n", + DPRINTF("%s: set CPU %d ctpr to %d, raised %d servicing %d", __func__, idx, dst->ctpr, dst->raised.priority, dst->servicing.priority); =20 if (dst->raised.priority <=3D dst->ctpr) { - DPRINTF("%s: Lower OpenPIC INT output cpu %d due to ctpr\n", + DPRINTF("%s: Lower OpenPIC INT output cpu %d due to ctpr", __func__, idx); qemu_irq_lower(dst->irqs[OPENPIC_OUTPUT_INT]); } else if (dst->raised.priority > dst->servicing.priority) { - DPRINTF("%s: Raise OpenPIC INT output cpu %d irq %d\n", + DPRINTF("%s: Raise OpenPIC INT output cpu %d irq %d", __func__, idx, dst->raised.next); qemu_irq_raise(dst->irqs[OPENPIC_OUTPUT_INT]); } @@ -1168,11 +1168,11 @@ static void openpic_cpu_write_internal(void *opaque= , hwaddr addr, /* Read-only register */ break; case 0xB0: /* EOI */ - DPRINTF("EOI\n"); + DPRINTF("EOI"); s_IRQ =3D IRQ_get_next(opp, &dst->servicing); =20 if (s_IRQ < 0) { - DPRINTF("%s: EOI with no interrupt in service\n", __func__); + DPRINTF("%s: EOI with no interrupt in service", __func__); break; } =20 @@ -1185,7 +1185,7 @@ static void openpic_cpu_write_internal(void *opaque, = hwaddr addr, if (n_IRQ !=3D -1 && (s_IRQ =3D=3D -1 || IVPR_PRIORITY(src->ivpr) > dst->servicing.priority)) { - DPRINTF("Raise OpenPIC INT output cpu %d irq %d\n", + DPRINTF("Raise OpenPIC INT output cpu %d irq %d", idx, n_IRQ); qemu_irq_raise(opp->dst[idx].irqs[OPENPIC_OUTPUT_INT]); } @@ -1207,11 +1207,11 @@ static uint32_t openpic_iack(OpenPICState *opp, IRQ= Dest *dst, int cpu) IRQSource *src; int retval, irq; =20 - DPRINTF("Lower OpenPIC INT output\n"); + DPRINTF("Lower OpenPIC INT output"); qemu_irq_lower(dst->irqs[OPENPIC_OUTPUT_INT]); =20 irq =3D IRQ_get_next(opp, &dst->raised); - DPRINTF("IACK: irq=3D%d\n", irq); + DPRINTF("IACK: irq=3D%d", irq); =20 if (irq =3D=3D -1) { /* No more interrupt pending */ @@ -1221,7 +1221,7 @@ static uint32_t openpic_iack(OpenPICState *opp, IRQDe= st *dst, int cpu) src =3D &opp->src[irq]; if (!(src->ivpr & IVPR_ACTIVITY_MASK) || !(IVPR_PRIORITY(src->ivpr) > dst->ctpr)) { - fprintf(stderr, "%s: bad raised IRQ %d ctpr %d ivpr 0x%08x\n", + error_report("%s: bad raised IRQ %d ctpr %d ivpr 0x%08x", __func__, irq, dst->ctpr, src->ivpr); openpic_update_irq(opp, irq); retval =3D opp->spve; @@ -1241,7 +1241,7 @@ static uint32_t openpic_iack(OpenPICState *opp, IRQDe= st *dst, int cpu) /* Timers and IPIs support multicast. */ if (((irq >=3D opp->irq_ipi0) && (irq < (opp->irq_ipi0 + OPENPIC_MAX_I= PI))) || ((irq >=3D opp->irq_tim0) && (irq < (opp->irq_tim0 + OPENPIC_MAX_T= MR)))) { - DPRINTF("irq is IPI or TMR\n"); + DPRINTF("irq is IPI or TMR"); src->destmask &=3D ~(1 << cpu); if (src->destmask && !src->level) { /* trigger on CPUs that didn't know about it yet */ @@ -1262,7 +1262,7 @@ static uint32_t openpic_cpu_read_internal(void *opaqu= e, hwaddr addr, IRQDest *dst; uint32_t retval; =20 - DPRINTF("%s: cpu %d addr %#" HWADDR_PRIx "\n", __func__, idx, addr); + DPRINTF("%s: cpu %d addr %#" HWADDR_PRIx, __func__, idx, addr); retval =3D 0xFFFFFFFF; =20 if (idx < 0 || idx >=3D opp->nb_cpus) { @@ -1290,7 +1290,7 @@ static uint32_t openpic_cpu_read_internal(void *opaqu= e, hwaddr addr, default: break; } - DPRINTF("%s: =3D> 0x%08x\n", __func__, retval); + DPRINTF("%s: =3D> 0x%08x", __func__, retval); =20 return retval; } --=20 2.11.0 From nobody Sun May 5 13:59:26 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1511733730453944.7983562892517; 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X-Received-From: 2607:f8b0:4001:c0b::244 Subject: [Qemu-devel] [PATCH 02/17] i2c: start trace-events X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Davidsaver , qemu-ppc@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_6 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Michael Davidsaver --- Makefile.objs | 1 + hw/i2c/trace-events | 1 + 2 files changed, 2 insertions(+) create mode 100644 hw/i2c/trace-events diff --git a/Makefile.objs b/Makefile.objs index 285c6f3c15..984ae8ecba 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -155,6 +155,7 @@ trace-events-subdirs +=3D hw/arm trace-events-subdirs +=3D hw/alpha trace-events-subdirs +=3D hw/xen trace-events-subdirs +=3D hw/ide +trace-events-subdirs +=3D hw/i2c trace-events-subdirs +=3D ui trace-events-subdirs +=3D audio trace-events-subdirs +=3D net diff --git a/hw/i2c/trace-events b/hw/i2c/trace-events new file mode 100644 index 0000000000..9284b1fbad --- /dev/null +++ b/hw/i2c/trace-events @@ -0,0 +1 @@ +# See docs/devel/tracing.txt for syntax documentation. --=20 2.11.0 From nobody Sun May 5 13:59:26 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1511733910808115.68573783918589; Sun, 26 Nov 2017 14:05:10 -0800 (PST) Received: from localhost ([::1]:58157 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eJ52v-0002pF-20 for importer@patchew.org; Sun, 26 Nov 2017 17:05:05 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56779) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eJ4xm-000727-87 for qemu-devel@nongnu.org; Sun, 26 Nov 2017 16:59:50 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eJ4xk-0002rR-Jh for qemu-devel@nongnu.org; Sun, 26 Nov 2017 16:59:46 -0500 Received: from mail-io0-x231.google.com ([2607:f8b0:4001:c06::231]:41646) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eJ4xk-0002rB-DL; Sun, 26 Nov 2017 16:59:44 -0500 Received: by mail-io0-x231.google.com with SMTP id g73so34259601ioj.8; Sun, 26 Nov 2017 13:59:44 -0800 (PST) Received: from localhost.localdomain (173-29-146-33.client.mchsi.com. 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X-Received-From: 2607:f8b0:4001:c06::231 Subject: [Qemu-devel] [PATCH 03/17] i2c: add mpc8540 i2c controller X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Davidsaver , qemu-ppc@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Michael Davidsaver --- hw/i2c/Makefile.objs | 1 + hw/i2c/mpc8540_i2c.c | 307 +++++++++++++++++++++++++++++++++++++++++++++++= ++++ hw/i2c/trace-events | 6 + 3 files changed, 314 insertions(+) create mode 100644 hw/i2c/mpc8540_i2c.c diff --git a/hw/i2c/Makefile.objs b/hw/i2c/Makefile.objs index 0594dea3ae..79af1dd901 100644 --- a/hw/i2c/Makefile.objs +++ b/hw/i2c/Makefile.objs @@ -9,3 +9,4 @@ common-obj-$(CONFIG_IMX_I2C) +=3D imx_i2c.o common-obj-$(CONFIG_ASPEED_SOC) +=3D aspeed_i2c.o obj-$(CONFIG_OMAP) +=3D omap_i2c.o obj-$(CONFIG_PPC4XX) +=3D ppc4xx_i2c.o +obj-$(CONFIG_E500) +=3D mpc8540_i2c.o diff --git a/hw/i2c/mpc8540_i2c.c b/hw/i2c/mpc8540_i2c.c new file mode 100644 index 0000000000..b9f5773b35 --- /dev/null +++ b/hw/i2c/mpc8540_i2c.c @@ -0,0 +1,307 @@ +/* + * MPC8540 I2C bus interface + * As described in + * MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev.= 1 + * Part 2 chapter 11 + * + * Compatible I2C controllers are found on other Freescale chips + * including mpc8544 and P2010. + * + * Copyright (c) 2015 Michael Davidsaver + * + * This work is licensed under the terms of the GNU GPL, version 2. See + * the LICENSE file in the top-level directory. + */ +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "hw/hw.h" +#include "hw/registerfields.h" +#include "hw/i2c/i2c.h" +#include "hw/sysbus.h" +#include "qemu/error-report.h" + +#include "trace.h" + +/* #define DEBUG_LVL 0 */ + +#ifdef DEBUG_LVL +#define DPRINTK(LVL, FMT, ...) do { \ + if ((LVL) <=3D DEBUG_LVL) {\ + info_report(TYPE_MPC8540_I2C " : " FMT, ## __VA_ARGS__); \ + } } while (0) +#else +#define DPRINTK(LVL, FMT, ...) do {} while (0) +#endif + +#define LOG(MSK, FMT, ...) qemu_log_mask(MSK, TYPE_MPC8540_I2C \ + " : " FMT "\n", ## __VA_ARGS__) + +#define TYPE_MPC8540_I2C "mpc8540-i2c" +#define MPC8540_I2C(obj) OBJECT_CHECK(MPC8540I2CState, (obj), TYPE_MPC8540= _I2C) + +/* offsets relative to CCSR offset 0x3000 */ +#define R_I2CADR (0) +#define R_I2CFDR (4) +#define R_I2CCR (8) +#define R_I2CSR (0xc) +#define R_I2CDR (0x10) +#define R_I2CDFSRR (0x14) + +FIELD(I2CCR, MEN, 7, 1) +FIELD(I2CCR, MIEN, 6, 1) +FIELD(I2CCR, MSTA, 5, 1) +FIELD(I2CCR, MTX, 4, 1) +FIELD(I2CCR, TXAK, 3, 1) +FIELD(I2CCR, RSTA, 2, 1) +FIELD(I2CCR, BCST, 0, 1) + +FIELD(I2CSR, MCF, 7, 1) +FIELD(I2CSR, MAAS, 6, 1) +FIELD(I2CSR, MBB, 5, 1) +FIELD(I2CSR, MAL, 4, 1) +FIELD(I2CSR, BCSTM, 3, 1) +FIELD(I2CSR, SRW, 2, 1) +FIELD(I2CSR, MIF, 1, 1) +FIELD(I2CSR, RXAK, 0, 1) + +typedef struct MPC8540I2CState { + SysBusDevice parent_obj; + + I2CBus *bus; + + uint8_t ctrl, sts; + uint8_t freq, filt; + /* Reads are pipelined, this is the next data value */ + uint8_t dbuf, dbuf_valid; + + qemu_irq irq; + + MemoryRegion mmio; +} MPC8540I2CState; + +#define I2CCR(BIT) FIELD_EX32(i2c->ctrl, I2CCR, BIT) +#define I2CSR(BIT) FIELD_EX32(i2c->sts, I2CSR, BIT) + +#define I2CSR_SET(BIT, VAL) do {\ + i2c->sts =3D FIELD_DP32(i2c->sts, I2CSR, BIT, VAL);\ + } while (0) + +static +void mpc8540_update_irq(MPC8540I2CState *i2c) +{ + int ena =3D i2c->ctrl & 0x40, + sts =3D i2c->sts & 0x02, + act =3D !!(ena && sts); + + DPRINTK(1, "IRQ %c ena %c sts %c", + act ? 'X' : '_', + ena ? 'X' : '_', + sts ? 'X' : '_'); + + qemu_set_irq(i2c->irq, act); +} + +static +uint64_t mpc8540_i2c_read(void *opaque, hwaddr addr, unsigned size) +{ + MPC8540I2CState *i2c =3D opaque; + uint32_t val; + + switch (addr) { + case R_I2CADR: /* ADDR */ + val =3D 0; + break; + case R_I2CFDR: /* Freq Div. */ + val =3D i2c->freq; + break; + case R_I2CCR: /* CONTROL */ + val =3D i2c->ctrl & ~0x06; + break; + case R_I2CSR: /* STATUS */ + val =3D i2c->sts; + break; + case R_I2CDR: /* DATA */ + /* Reads are "pipelined" and so return the previous value of the + * register + */ + val =3D i2c->dbuf; + if (I2CCR(MEN) && I2CSR(MBB)) { /* enabled and busy */ + if (!i2c_bus_busy(i2c->bus) || I2CCR(MTX)) { + if (!i2c->dbuf_valid) { + LOG(LOG_GUEST_ERROR, "Read during addr or tx"); + } + i2c->dbuf =3D 0xff; + i2c->dbuf_valid =3D false; + } else { + int ret =3D i2c_recv(i2c->bus); + i2c->dbuf =3D (uint8_t)ret; + i2c->dbuf_valid =3D true; + trace_mpc8540_i2c_read(i2c->dbuf); + I2CSR_SET(MIF, 1); + I2CSR_SET(RXAK, 0); + mpc8540_update_irq(i2c); + } + } else { + i2c->dbuf =3D 0xff; + i2c->dbuf_valid =3D false; + LOG(LOG_GUEST_ERROR, "Read when not enabled or busy"); + } + break; + case R_I2CDFSRR: /* FILTER */ + val =3D i2c->filt; + break; + default: + val =3D 0xff; + } + + DPRINTK(addr =3D=3D 0xc ? 2 : 1, " read %08x -> %08x", + (unsigned)addr, (unsigned)val); + return val; +} + +static +void mpc8540_i2c_write(void *opaque, hwaddr addr, uint64_t val, unsigned s= ize) +{ + MPC8540I2CState *i2c =3D opaque; + + DPRINTK(1, " write %08x <- %08x", (unsigned)addr, (unsigned)val); + + switch (addr) { + case R_I2CADR: /* ADDR */ + break; + case R_I2CFDR: /* Freq Div. */ + i2c->freq =3D val & 0x3f; + break; + case R_I2CCR: /* CONTROL CCR */ + if (!FIELD_EX32(val, I2CCR, MEN)) { + DPRINTK(0, "Not Enabled"); + + } else if (!I2CCR(MSTA) && FIELD_EX32(val, I2CCR, MSTA)) { + /* MSTA 0 -> 1 is START */ + + I2CSR_SET(MBB, 1); + if (I2CCR(MTX)) { + trace_mpc8540_i2c_event("START Tx"); + } else { + trace_mpc8540_i2c_event("START Rx"); + } + i2c_end_transfer(i2c->bus); /* paranoia */ + + } else if (I2CCR(MSTA) && !FIELD_EX32(val, I2CCR, MSTA)) { + /* MSTA 1 -> 0 is STOP */ + + I2CSR_SET(MBB, 0); + trace_mpc8540_i2c_event("STOP"); + i2c_end_transfer(i2c->bus); + + } else if (I2CCR(MSTA) && FIELD_EX32(val, I2CCR, RSTA)) { + i2c_end_transfer(i2c->bus); + I2CSR_SET(MBB, 1); + if (I2CCR(MTX)) { + trace_mpc8540_i2c_event("REPEAT START Tx"); + } else { + trace_mpc8540_i2c_event("REPEAT START Rx"); + } + + } + /* RSTA always reads zero, bit 1 unusd */ + val &=3D 0xf9; + i2c->ctrl =3D val; + mpc8540_update_irq(i2c); + break; + case R_I2CSR: /* STATUS CSR */ + /* only MAL and MIF are writable */ + val &=3D 0x12; + i2c->sts &=3D ~0x12; + i2c->sts |=3D val; + mpc8540_update_irq(i2c); + break; + case R_I2CDR: /* DATA CDR */ + if (I2CCR(MEN) && I2CSR(MBB)) { /* enabled and busy */ + if (!i2c_bus_busy(i2c->bus)) { + if (i2c_start_transfer(i2c->bus, val >> 1, val & 1)) { + LOG(LOG_GUEST_ERROR, "I2C no device %02x", + (unsigned)(val & 0xfe)); + } else { + trace_mpc8540_i2c_address((unsigned)(val & 0xfe), + (val & 0x1) ? 'R' : 'T'); + } + I2CSR_SET(MIF, 1); + I2CSR_SET(RXAK, 0); + + } else if (I2CCR(MTX)) { + trace_mpc8540_i2c_write((unsigned)val); + i2c_send(i2c->bus, val); + I2CSR_SET(MIF, 1); + I2CSR_SET(RXAK, 0); + } else { + LOG(LOG_GUEST_ERROR, "I2CDR Write during read"); + } + mpc8540_update_irq(i2c); + } else { + LOG(LOG_GUEST_ERROR, "I2CDR Write when not enabled or busy"); + } + break; + case R_I2CDFSRR: /* FILTER */ + val &=3D 0x3f; + i2c->filt =3D val; + break; + } + + DPRINTK(1, "I2CCR =3D %02x I2SCR =3D %02x", i2c->ctrl, i2c->sts); +} + +static const MemoryRegionOps i2c_ops =3D { + .read =3D mpc8540_i2c_read, + .write =3D mpc8540_i2c_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .impl =3D { + .min_access_size =3D 1, + .max_access_size =3D 1, + }, +}; + +static +void mpc8540_i2c_reset(DeviceState *dev) +{ + MPC8540I2CState *i2c =3D MPC8540_I2C(dev); + + i2c->sts =3D 0x81; /* transfer complete and ack received */ + i2c->dbuf_valid =3D false; +} + +static void mpc8540_i2c_inst_init(DeviceState *dev, Error **errp) +{ + MPC8540I2CState *i2c =3D MPC8540_I2C(dev); + + i2c->bus =3D i2c_init_bus(dev, "bus"); + + memory_region_init_io(&i2c->mmio, OBJECT(dev), + &i2c_ops, i2c, TYPE_MPC8540_I2C, 0x18); + + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &i2c->mmio); + sysbus_init_irq(SYS_BUS_DEVICE(dev), &i2c->irq); +} + +static void mpc8540_i2c_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->realize =3D &mpc8540_i2c_inst_init; + dc->reset =3D &mpc8540_i2c_reset; +} + +static const TypeInfo mpc8540_i2c_type =3D { + .name =3D TYPE_MPC8540_I2C, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(MPC8540I2CState), + .class_size =3D sizeof(SysBusDeviceClass), + .class_init =3D mpc8540_i2c_class_init, +}; + +static void mpc8540_i2c_register(void) +{ + type_register_static(&mpc8540_i2c_type); +} + +type_init(mpc8540_i2c_register) diff --git a/hw/i2c/trace-events b/hw/i2c/trace-events index 9284b1fbad..ac38d76984 100644 --- a/hw/i2c/trace-events +++ b/hw/i2c/trace-events @@ -1 +1,7 @@ # See docs/devel/tracing.txt for syntax documentation. + +# hw/i2c/mpc8540_i2c.c +mpc8540_i2c_event(const char *evt) "Bus Event %s" +mpc8540_i2c_address(uint8_t addr, const char direction) "Address device 0x= %02x for %cX" +mpc8540_i2c_write(uint8_t byte) "Write 0x%02x" +mpc8540_i2c_read(uint8_t byte) "Read 0x%02x" --=20 2.11.0 From nobody Sun May 5 13:59:26 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1511733731160931.2214555558371; Sun, 26 Nov 2017 14:02:11 -0800 (PST) Received: from localhost ([::1]:58147 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eJ4zu-0008Qb-0O for importer@patchew.org; Sun, 26 Nov 2017 17:01:58 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56788) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eJ4xm-00072G-Rm for qemu-devel@nongnu.org; Sun, 26 Nov 2017 16:59:50 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eJ4xl-0002rs-Fc for qemu-devel@nongnu.org; Sun, 26 Nov 2017 16:59:46 -0500 Received: from mail-io0-x244.google.com ([2607:f8b0:4001:c06::244]:44913) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eJ4xl-0002rk-Af; Sun, 26 Nov 2017 16:59:45 -0500 Received: by mail-io0-x244.google.com with SMTP id w127so34263754iow.11; Sun, 26 Nov 2017 13:59:45 -0800 (PST) Received: from localhost.localdomain (173-29-146-33.client.mchsi.com. [173.29.146.33]) by smtp.gmail.com with ESMTPSA id n184sm6517218itg.9.2017.11.26.13.59.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 26 Nov 2017 13:59:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=pyTrrSquw4d1Nle1yjS1JoLIC5veExrkfU3XwIcr/Sk=; b=LgS5xVbHtD69VrnJFUziRr+ybSCN2Ry1Lf85Bji5vVZh9DpBkGKMYIxJE6gm1IVDfq T3eXMrLEcsbUqAR3vLBWrfnD2qNsZQnSHLwRcA2NJVLaCEPRRBccTYaDKVA7b/Mglkjs +pfYIJUWKLCY5vlFTLT7Jwfk1qQfV4eP1f6zophlLQPu9cmnbHNNJtQTPQf3KAhaNpn0 OZjoqWFtI7Hgh+yj6qyfEJt2UB6BURIE6thuuhB35bIOKR1SxgdFe+eEZhhh2EFW5Zya ytCXC/GFdkFFXe+myw5yy1LZ8hZHbJL37jlnpH24YsKnHpzJWvAQ/YENyizuZDxJNryz PnXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=pyTrrSquw4d1Nle1yjS1JoLIC5veExrkfU3XwIcr/Sk=; b=HFliImmnbfMBh6WGgc2ibrbqLfxLxfxgAZk9deNoQl6eBhXWs4AJHwPh6JABaES0IN SdI0Vnu/CIaNqIpd4MajSXiby2+kefUwJ9QpOxFpC+tOIb2XizL/I8YHY1mCxtgIMlRq uXTHEE5+uh5k6fs/vZftAcCBrXX64e3YYoPtns4WbN+br+6bguMhWM4dUHkIzSngX85j jwpAxJWW/wyfTHpyXgksowNaHYyhr6GoyQ5JKQyX6/Q3NquM/+KbGcQUO8urJzFD3s2F euA90uPMspckbwmVNq8Z1DlH/9x9kFQ5l7IUJtp1ZrA9lyGuCnWdRaT54yg/6+VDGz0I JFaQ== X-Gm-Message-State: AJaThX5/AYQM7pb1QZnOrW4oRJvWwRVHpehnPCh048iQQ/gY6zpOdzWs tjPxgrwskCK4JtXicmmOXG4= X-Google-Smtp-Source: AGs4zMacuKvjp/r5WrWStn77jObVJ7KLvMNoClmSmOYwFx6vB8xtXEeO3/cOofq0xLUUGpjywJxUvA== X-Received: by 10.107.10.69 with SMTP id u66mr39442277ioi.230.1511733584588; Sun, 26 Nov 2017 13:59:44 -0800 (PST) From: Michael Davidsaver To: Alexander Graf , David Gibson Date: Sun, 26 Nov 2017 15:59:02 -0600 Message-Id: <5525ca41a3ce3d5af7755d337b382fede3ef530e.1511731946.git.mdavidsaver@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4001:c06::244 Subject: [Qemu-devel] [PATCH 04/17] qtest: add e500_i2c_create() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Davidsaver , qemu-ppc@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add interface for testing i2c devices with PPC e500. Signed-off-by: Michael Davidsaver --- tests/Makefile.include | 1 + tests/libqos/i2c-e500.c | 66 +++++++++++++++++++++++++++++++++++++++++++++= ++++ tests/libqos/i2c.h | 3 +++ 3 files changed, 70 insertions(+) create mode 100644 tests/libqos/i2c-e500.c diff --git a/tests/Makefile.include b/tests/Makefile.include index c002352134..ad1c219423 100644 --- a/tests/Makefile.include +++ b/tests/Makefile.include @@ -721,6 +721,7 @@ libqos-pc-obj-y +=3D tests/libqos/malloc-pc.o tests/lib= qos/libqos-pc.o libqos-pc-obj-y +=3D tests/libqos/ahci.o libqos-omap-obj-y =3D $(libqos-obj-y) tests/libqos/i2c-omap.o libqos-imx-obj-y =3D $(libqos-obj-y) tests/libqos/i2c-imx.o +libqos-e500-obj-y =3D $(libqos-obj-y) tests/libqos/i2c-e500.o libqos-usb-obj-y =3D $(libqos-spapr-obj-y) $(libqos-pc-obj-y) tests/libqos= /usb.o libqos-virtio-obj-y =3D $(libqos-spapr-obj-y) $(libqos-pc-obj-y) tests/lib= qos/virtio.o tests/libqos/virtio-pci.o tests/libqos/virtio-mmio.o tests/lib= qos/malloc-generic.o =20 diff --git a/tests/libqos/i2c-e500.c b/tests/libqos/i2c-e500.c new file mode 100644 index 0000000000..4272ada0a5 --- /dev/null +++ b/tests/libqos/i2c-e500.c @@ -0,0 +1,66 @@ +/* + * QTest I2C driver + * + * Copyright (c) 2016 Michael Davidsaver + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ +#include "qemu/osdep.h" +#include "libqos/i2c.h" + + +#include "qemu/bswap.h" +#include "libqtest.h" + +typedef struct E500I2C { + I2CAdapter parent; + + uint64_t addr; +} E500I2C; + +static void e500_i2c_send(I2CAdapter *i2c, uint8_t addr, + const uint8_t *buf, uint16_t len) +{ + E500I2C *s =3D (E500I2C *)i2c; + + writeb(s->addr + 0x8, 0xb0); /* Enable and START a write */ + writeb(s->addr + 0x10, addr & 0xfe); /* Send address for write */ + + while (len--) { + writeb(s->addr + 0x10, *buf++); + } + + writeb(s->addr + 0x8, 0x80); /* STOP but leave enabled */ +} + +static void e500_i2c_recv(I2CAdapter *i2c, uint8_t addr, + uint8_t *buf, uint16_t len) +{ + E500I2C *s =3D (E500I2C *)i2c; + + writeb(s->addr + 0x8, 0xa0); /* Enable and START a read */ + writeb(s->addr + 0x10, addr | 1); /* Send address for read */ + + /* reads are "pipelined" so the initial value is junk */ + readb(s->addr + 0x10); + + while (len--) { + *buf++ =3D readb(s->addr + 0x10); + } + + writeb(s->addr + 0x8, 0x80); /* STOP but leave enabled */ +} + +I2CAdapter *e500_i2c_create(uint64_t ccsr_base) +{ + E500I2C *s =3D g_malloc0(sizeof(*s)); + I2CAdapter *i2c =3D (I2CAdapter *)s; + + s->addr =3D ccsr_base + 0x3000; + + i2c->send =3D e500_i2c_send; + i2c->recv =3D e500_i2c_recv; + + return i2c; +} diff --git a/tests/libqos/i2c.h b/tests/libqos/i2c.h index 6e648f922a..40c59a7997 100644 --- a/tests/libqos/i2c.h +++ b/tests/libqos/i2c.h @@ -29,4 +29,7 @@ I2CAdapter *omap_i2c_create(uint64_t addr); /* libi2c-imx.c */ I2CAdapter *imx_i2c_create(uint64_t addr); =20 +/* i2c-e500.c */ +I2CAdapter *e500_i2c_create(uint64_t ccsr_base); + #endif --=20 2.11.0 From nobody Sun May 5 13:59:26 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1511734281445574.0429800919162; Sun, 26 Nov 2017 14:11:21 -0800 (PST) Received: from localhost ([::1]:58203 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eJ58w-0008MM-JC for importer@patchew.org; Sun, 26 Nov 2017 17:11:18 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56836) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eJ4xp-00072c-JJ for qemu-devel@nongnu.org; Sun, 26 Nov 2017 16:59:52 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eJ4xn-0002t8-5p for qemu-devel@nongnu.org; Sun, 26 Nov 2017 16:59:49 -0500 Received: from mail-io0-x232.google.com ([2607:f8b0:4001:c06::232]:34464) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eJ4xm-0002sh-VU; Sun, 26 Nov 2017 16:59:47 -0500 Received: by mail-io0-x232.google.com with SMTP id q101so34254744ioi.1; Sun, 26 Nov 2017 13:59:46 -0800 (PST) Received: from localhost.localdomain (173-29-146-33.client.mchsi.com. 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X-Received-From: 2607:f8b0:4001:c06::232 Subject: [Qemu-devel] [PATCH 05/17] timer: generalize Dallas/Maxim RTC i2c devices X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Davidsaver , qemu-ppc@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Support for: ds1307, ds1337, ds1338, ds1339, ds1340, ds1375, ds1388, and ds3231. Tested with ds1338 and ds1375. Signed-off-by: Michael Davidsaver --- default-configs/arm-softmmu.mak | 2 +- hw/timer/Makefile.objs | 2 +- hw/timer/ds-rtc-i2c.c | 461 ++++++++++++++++++++++++++++++++++++= ++++ hw/timer/ds1338.c | 239 --------------------- 4 files changed, 463 insertions(+), 241 deletions(-) create mode 100644 hw/timer/ds-rtc-i2c.c delete mode 100644 hw/timer/ds1338.c diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.= mak index d37edc4312..b857823681 100644 --- a/default-configs/arm-softmmu.mak +++ b/default-configs/arm-softmmu.mak @@ -31,7 +31,7 @@ CONFIG_SMC91C111=3Dy CONFIG_ALLWINNER_EMAC=3Dy CONFIG_IMX_FEC=3Dy CONFIG_FTGMAC100=3Dy -CONFIG_DS1338=3Dy +CONFIG_DSRTCI2C=3Dy CONFIG_PFLASH_CFI01=3Dy CONFIG_PFLASH_CFI02=3Dy CONFIG_MICRODRIVE=3Dy diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs index 8c19eac3b6..290015ebec 100644 --- a/hw/timer/Makefile.objs +++ b/hw/timer/Makefile.objs @@ -3,7 +3,7 @@ common-obj-$(CONFIG_ARM_MPTIMER) +=3D arm_mptimer.o common-obj-$(CONFIG_ARM_V7M) +=3D armv7m_systick.o common-obj-$(CONFIG_A9_GTIMER) +=3D a9gtimer.o common-obj-$(CONFIG_CADENCE) +=3D cadence_ttc.o -common-obj-$(CONFIG_DS1338) +=3D ds1338.o +common-obj-$(CONFIG_DSRTCI2C) +=3D ds-rtc-i2c.o common-obj-$(CONFIG_HPET) +=3D hpet.o common-obj-$(CONFIG_I8254) +=3D i8254_common.o i8254.o common-obj-$(CONFIG_M48T59) +=3D m48t59.o diff --git a/hw/timer/ds-rtc-i2c.c b/hw/timer/ds-rtc-i2c.c new file mode 100644 index 0000000000..ad2f8f2a68 --- /dev/null +++ b/hw/timer/ds-rtc-i2c.c @@ -0,0 +1,461 @@ +/* Emulation of various Dallas/Maxim RTCs accessed via I2C bus + * + * Copyright (c) 2017 Michael Davidsaver + * Copyright (c) 2009 CodeSourcery + * + * Authors: Michael Davidsaver + * Paul Brook + * + * This work is licensed under the terms of the GNU GPL, version 2. See + * the LICENSE file in the top-level directory. + * + * Models real time read/set and NVRAM. + * Does not model alarms, or control/status registers. + * + * Generalized register map is: + * [Current time] + * [Alarm settings] (optional) + * [Control/Status] (optional) + * [Non-volatile memory] (optional) + * + * The current time registers are almost always the same, + * with the exception being that some have a CENTURY bit + * in the month register. + */ +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/timer.h" +#include "qemu/bcd.h" +#include "hw/hw.h" +#include "hw/registerfields.h" +#include "hw/i2c/i2c.h" +#include "sysemu/qtest.h" +#include "qemu/error-report.h" + +/* #define DEBUG_DSRTC */ + +#ifdef DEBUG_DSRTC +#define DPRINTK(FMT, ...) info_report(TYPE_DSRTC " : " FMT, ## __VA_ARGS__) +#else +#define DPRINTK(FMT, ...) do {} while (0) +#endif + +#define LOG(MSK, FMT, ...) qemu_log_mask(MSK, TYPE_DSRTC " : " FMT "\n", \ + ## __VA_ARGS__) + +#define DSRTC_REGSIZE (0x40) + +/* values stored in BCD */ +/* 00-59 */ +#define R_SEC (0x0) +/* 00-59 */ +#define R_MIN (0x1) +#define R_HOUR (0x2) +/* 1-7 */ +#define R_WDAY (0x3) +/* 0-31 */ +#define R_DATE (0x4) +#define R_MONTH (0x5) +/* 0-99 */ +#define R_YEAR (0x6) + +/* use 12 hour mode when set */ +FIELD(HOUR, SET12, 6, 1) +/* 00-23 */ +FIELD(HOUR, HOUR24, 0, 6) +FIELD(HOUR, AMPM, 5, 1) +/* 1-12 (not 0-11!) */ +FIELD(HOUR, HOUR12, 0, 5) + +/* 1-12 */ +FIELD(MONTH, MONTH, 0, 5) +FIELD(MONTH, CENTURY, 7, 1) + +typedef struct DSRTCInfo { + /* if bit 7 of the Month register is set after Y2K */ + bool has_century; + /* address of first non-volatile memory cell. + * nv_start >=3D reg_end means no NV memory. + */ + uint8_t nv_start; + /* total size of register range. When address counter rolls over. */ + uint8_t reg_size; +} DSRTCInfo; + +typedef struct DSRTCState { + I2CSlave parent_obj; + + const DSRTCInfo *info; + + qemu_irq alarm_irq; + + /* register address counter */ + uint8_t addr; + /* when writing, whether the address has been sent */ + bool addrd; + + int64_t time_offset; + int8_t wday_offset; + + uint8_t regs[DSRTC_REGSIZE]; +} DSRTCState; + +typedef struct DSRTCClass { + I2CSlaveClass parent_class; + + const DSRTCInfo *info; +} DSRTCClass; + +#define TYPE_DSRTC "ds-rtc-i2c" +#define DSRTC(obj) OBJECT_CHECK(DSRTCState, (obj), TYPE_DSRTC) +#define DSRTC_GET_CLASS(obj) \ + OBJECT_GET_CLASS(DSRTCClass, obj, TYPE_DSRTC) +#define DSRTC_CLASS(klass) \ + OBJECT_CLASS_CHECK(DSRTCClass, klass, TYPE_DSRTC) + +static const VMStateDescription vmstate_dsrtc =3D { + .name =3D TYPE_DSRTC, + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_I2C_SLAVE(parent_obj, DSRTCState), + VMSTATE_INT64(time_offset, DSRTCState), + VMSTATE_INT8_V(wday_offset, DSRTCState, 2), + VMSTATE_UINT8_ARRAY(regs, DSRTCState, DSRTC_REGSIZE), + VMSTATE_UINT8(addr, DSRTCState), + VMSTATE_BOOL(addrd, DSRTCState), + VMSTATE_END_OF_LIST() + } +}; + +static void dsrtc_reset(DeviceState *device); + +/* update current time registers */ +static +void dsrtc_latch(DSRTCState *ds) +{ + struct tm now; + bool use12; + + qemu_get_timedate(&now, ds->time_offset); + + DPRINTK("Current Time %3u/%2u/%u %2u:%2u:%2u (wday %u)", + now.tm_year, now.tm_mon, now.tm_mday, + now.tm_hour, now.tm_min, now.tm_sec, + now.tm_wday); + + use12 =3D ARRAY_FIELD_EX32(ds->regs, HOUR, SET12); + + /* ensure unused bits are zero */ + memset(ds->regs, 0, R_YEAR + 1); + + ds->regs[R_SEC] =3D to_bcd(now.tm_sec); + ds->regs[R_MIN] =3D to_bcd(now.tm_min); + + if (!use12) { + /* 24 hour (0-23) */ + ARRAY_FIELD_DP32(ds->regs, HOUR, HOUR24, to_bcd(now.tm_hour)); + } else { + /* 12 hour am/pm (1-12) */ + ARRAY_FIELD_DP32(ds->regs, HOUR, SET12, 1); + ARRAY_FIELD_DP32(ds->regs, HOUR, AMPM, now.tm_hour >=3D 12u); + ARRAY_FIELD_DP32(ds->regs, HOUR, HOUR12, + to_bcd(1u + (now.tm_hour % 12u))); + } + + ds->regs[R_WDAY] =3D (now.tm_wday + ds->wday_offset) % 7u + 1u; + ds->regs[R_DATE] =3D to_bcd(now.tm_mday); + + ARRAY_FIELD_DP32(ds->regs, MONTH, MONTH, to_bcd(now.tm_mon + 1)); + if (ds->info->has_century) { + ARRAY_FIELD_DP32(ds->regs, MONTH, CENTURY, now.tm_year >=3D 100u); + } + + ds->regs[R_YEAR] =3D to_bcd(now.tm_year % 100u); + + DPRINTK("Latched time"); +} + +/* call after guest writes to current time registers + * to re-compute our offset from host time. + */ +static +void dsrtc_update(DSRTCState *ds) +{ + int user_wday; + struct tm now; + + now.tm_sec =3D from_bcd(ds->regs[R_SEC]); + now.tm_min =3D from_bcd(ds->regs[R_MIN]); + + if (ARRAY_FIELD_EX32(ds->regs, HOUR, SET12)) { + /* 12 hour (1-12) */ + now.tm_hour =3D from_bcd(ARRAY_FIELD_EX32(ds->regs, HOUR, HOUR12))= - 1u; + if (ARRAY_FIELD_EX32(ds->regs, HOUR, AMPM)) { + now.tm_hour +=3D 12; + } + + } else { + /* 23 hour (0-23) */ + now.tm_hour =3D from_bcd(ARRAY_FIELD_EX32(ds->regs, HOUR, HOUR24)); + } + + now.tm_wday =3D from_bcd(ds->regs[R_WDAY]) - 1u; + now.tm_mday =3D from_bcd(ds->regs[R_DATE]); + now.tm_mon =3D from_bcd(ARRAY_FIELD_EX32(ds->regs, MONTH, MONTH)) - 1; + + now.tm_year =3D from_bcd(ds->regs[R_YEAR]); + if (ARRAY_FIELD_EX32(ds->regs, MONTH, CENTURY) || !ds->info->has_centu= ry) { + now.tm_year +=3D 100; + } + + DPRINTK("New Time %3u/%2u/%u %2u:%2u:%2u (wday %u)", + now.tm_year, now.tm_mon, now.tm_mday, + now.tm_hour, now.tm_min, now.tm_sec, + now.tm_wday); + + /* round trip to get real wday_offset based on time delta */ + user_wday =3D now.tm_wday; + ds->time_offset =3D qemu_timedate_diff(&now); + /* race possible if we run at midnight + * TODO: make qemu_timedate_diff() calculate wday offset as well? + */ + qemu_get_timedate(&now, ds->time_offset); + /* calculate wday_offset to achieve guest requested wday */ + ds->wday_offset =3D user_wday - now.tm_wday; + + DPRINTK("Update offset =3D %" PRId64 ", wday_offset =3D %d", + ds->time_offset, ds->wday_offset); +} + +static +void dsrtc_advance(DSRTCState *ds) +{ + ds->addr =3D (ds->addr + 1) % ds->info->reg_size; + if (ds->addr =3D=3D 0) { + /* latch time on roll over */ + dsrtc_latch(ds); + } +} + +static +int dsrtc_event(I2CSlave *s, enum i2c_event event) +{ + DSRTCState *ds =3D DSRTC(s); + + switch (event) { + case I2C_START_SEND: + ds->addrd =3D false; + /* fall through */ + case I2C_START_RECV: + dsrtc_latch(ds); + /* fall through */ + case I2C_FINISH: + DPRINTK("Event %d", (int)event); + /* fall through */ + case I2C_NACK: + break; + } + return 0; +} + +static +int dsrtc_recv(I2CSlave *s) +{ + DSRTCState *ds =3D DSRTC(s); + int ret =3D 0; + + ret =3D ds->regs[ds->addr]; + + if (ds->addr > R_YEAR && ds->addr < ds->info->nv_start) { + LOG(LOG_UNIMP, "Read from unimplemented (%02x) %02x", ds->addr, re= t); + } + + DPRINTK("Recv (%02x) %02x", ds->addr, ret); + + dsrtc_advance(ds); + + return ret; +} + +static +int dsrtc_send(I2CSlave *s, uint8_t data) +{ + DSRTCState *ds =3D DSRTC(s); + + if (!ds->addrd) { + if (data =3D=3D 0xff && qtest_enabled()) { + /* allow test runner to zero offsets */ + DPRINTK("Testing reset"); + dsrtc_reset(DEVICE(s)); + return 0; + } + ds->addr =3D data % DSRTC_REGSIZE; + ds->addrd =3D true; + DPRINTK("Set address pointer %02x", data); + return 0; + } + + DPRINTK("Send (%02x) %02x", ds->addr, data); + + if (ds->addr <=3D R_YEAR) { + ds->regs[ds->addr] =3D data; + dsrtc_update(ds); + + } else if (ds->addr >=3D ds->info->nv_start) { + ds->regs[ds->addr] =3D data; + + } else { + LOG(LOG_UNIMP, "Register not modeled"); + } + + dsrtc_advance(ds); + + return 0; +} + +static +void dsrtc_reset(DeviceState *device) +{ + DSRTCState *ds =3D DSRTC(device); + + memset(ds->regs, 0, sizeof(ds->regs)); + + ds->addr =3D 0; + ds->addrd =3D false; + ds->time_offset =3D 0; + ds->wday_offset =3D 0; + + DPRINTK("Reset"); +} + +static +void dsrtc_realize(DeviceState *device, Error **errp) +{ + DSRTCState *ds =3D DSRTC(device); + DSRTCClass *r =3D DSRTC_GET_CLASS(device); + + ds->info =3D r->info; + + /* Alarms not yet implemented, but allow + * board code to wire up the alarm interrupt + * output anyway. + */ + qdev_init_gpio_out(device, &ds->alarm_irq, 1); +} + +static +void dsrtc_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + I2CSlaveClass *k =3D I2C_SLAVE_CLASS(klass); + DSRTCClass *r =3D DSRTC_CLASS(klass); + + r->info =3D data; + + k->event =3D &dsrtc_event; + k->recv =3D &dsrtc_recv; + k->send =3D &dsrtc_send; + + dc->vmsd =3D &vmstate_dsrtc; + dc->realize =3D dsrtc_realize; + dc->reset =3D dsrtc_reset; + dc->user_creatable =3D true; +} + +static +const TypeInfo ds_rtc_base_type =3D { + .abstract =3D true, + .name =3D TYPE_DSRTC, + .parent =3D TYPE_I2C_SLAVE, + .instance_size =3D sizeof(DSRTCState), +}; + +#define DSRTC_CONFIG(NAME) \ +static const TypeInfo NAME##_type =3D { \ + .name =3D #NAME, \ + .parent =3D TYPE_DSRTC, \ + .class_size =3D sizeof(I2CSlaveClass), \ + .class_init =3D dsrtc_class_init, \ + .class_data =3D (void *)&NAME##_info, \ +}; + +/* ds3231 - alarms, no eeprom */ +static const DSRTCInfo ds3231_info =3D { + .has_century =3D true, + .nv_start =3D 0x13, /* no nv memory */ + .reg_size =3D 0x13, +}; +DSRTC_CONFIG(ds3231) + +/* only model block 0 (RTC), blocks 1,2 (eeprom) not modeled. + * blocks have different i2c addresses + */ +static const DSRTCInfo ds1388_info =3D { + .has_century =3D false, + .nv_start =3D 0x0d, + .reg_size =3D 0x0d, +}; +DSRTC_CONFIG(ds1388) + +/* alarms, eeprom */ +static const DSRTCInfo ds1375_info =3D { + .has_century =3D true, + .nv_start =3D 0x10, + .reg_size =3D 0x20, +}; +DSRTC_CONFIG(ds1375) + +/* no alarms, no eeprom */ +static const DSRTCInfo ds1340_info =3D { + .has_century =3D false, + .nv_start =3D 0x10, + .reg_size =3D 0x10, +}; +DSRTC_CONFIG(ds1340) + +/* alarms, no eeprom */ +static const DSRTCInfo ds1339_info =3D { + .has_century =3D false, + .nv_start =3D 0x11, + .reg_size =3D 0x11, +}; +DSRTC_CONFIG(ds1339) + +/* no alarms, eeprom */ +static const DSRTCInfo ds1338_info =3D { + .has_century =3D false, + .nv_start =3D 0x08, + .reg_size =3D 0x40, +}; +DSRTC_CONFIG(ds1338) + +/* alarms, no eeprom */ +static const DSRTCInfo ds1337_info =3D { + .has_century =3D true, + .nv_start =3D 0x10, + .reg_size =3D 0x10, +}; +DSRTC_CONFIG(ds1337) + +/* ds1307 registers are identical to ds1338 */ +static +const TypeInfo ds1307_type =3D { + .name =3D "ds1307", + .parent =3D "ds1338", +}; + +static void ds_rtc_i2c_register(void) +{ + type_register_static(&ds_rtc_base_type); + type_register_static(&ds3231_type); + type_register_static(&ds1388_type); + type_register_static(&ds1375_type); + type_register_static(&ds1340_type); + type_register_static(&ds1339_type); + type_register_static(&ds1338_type); + type_register_static(&ds1337_type); + type_register_static(&ds1307_type); +} + +type_init(ds_rtc_i2c_register) diff --git a/hw/timer/ds1338.c b/hw/timer/ds1338.c deleted file mode 100644 index 3849b74a68..0000000000 --- a/hw/timer/ds1338.c +++ /dev/null @@ -1,239 +0,0 @@ -/* - * MAXIM DS1338 I2C RTC+NVRAM - * - * Copyright (c) 2009 CodeSourcery. - * Written by Paul Brook - * - * This code is licensed under the GNU GPL v2. - * - * Contributions after 2012-01-13 are licensed under the terms of the - * GNU GPL, version 2 or (at your option) any later version. - */ - -#include "qemu/osdep.h" -#include "qemu-common.h" -#include "hw/i2c/i2c.h" -#include "qemu/bcd.h" - -/* Size of NVRAM including both the user-accessible area and the - * secondary register area. - */ -#define NVRAM_SIZE 64 - -/* Flags definitions */ -#define SECONDS_CH 0x80 -#define HOURS_12 0x40 -#define HOURS_PM 0x20 -#define CTRL_OSF 0x20 - -#define TYPE_DS1338 "ds1338" -#define DS1338(obj) OBJECT_CHECK(DS1338State, (obj), TYPE_DS1338) - -typedef struct DS1338State { - I2CSlave parent_obj; - - int64_t offset; - uint8_t wday_offset; - uint8_t nvram[NVRAM_SIZE]; - int32_t ptr; - bool addr_byte; -} DS1338State; - -static const VMStateDescription vmstate_ds1338 =3D { - .name =3D "ds1338", - .version_id =3D 2, - .minimum_version_id =3D 1, - .fields =3D (VMStateField[]) { - VMSTATE_I2C_SLAVE(parent_obj, DS1338State), - VMSTATE_INT64(offset, DS1338State), - VMSTATE_UINT8_V(wday_offset, DS1338State, 2), - VMSTATE_UINT8_ARRAY(nvram, DS1338State, NVRAM_SIZE), - VMSTATE_INT32(ptr, DS1338State), - VMSTATE_BOOL(addr_byte, DS1338State), - VMSTATE_END_OF_LIST() - } -}; - -static void capture_current_time(DS1338State *s) -{ - /* Capture the current time into the secondary registers - * which will be actually read by the data transfer operation. - */ - struct tm now; - qemu_get_timedate(&now, s->offset); - s->nvram[0] =3D to_bcd(now.tm_sec); - s->nvram[1] =3D to_bcd(now.tm_min); - if (s->nvram[2] & HOURS_12) { - int tmp =3D now.tm_hour; - if (tmp % 12 =3D=3D 0) { - tmp +=3D 12; - } - if (tmp <=3D 12) { - s->nvram[2] =3D HOURS_12 | to_bcd(tmp); - } else { - s->nvram[2] =3D HOURS_12 | HOURS_PM | to_bcd(tmp - 12); - } - } else { - s->nvram[2] =3D to_bcd(now.tm_hour); - } - s->nvram[3] =3D (now.tm_wday + s->wday_offset) % 7 + 1; - s->nvram[4] =3D to_bcd(now.tm_mday); - s->nvram[5] =3D to_bcd(now.tm_mon + 1); - s->nvram[6] =3D to_bcd(now.tm_year - 100); -} - -static void inc_regptr(DS1338State *s) -{ - /* The register pointer wraps around after 0x3F; wraparound - * causes the current time/date to be retransferred into - * the secondary registers. - */ - s->ptr =3D (s->ptr + 1) & (NVRAM_SIZE - 1); - if (!s->ptr) { - capture_current_time(s); - } -} - -static int ds1338_event(I2CSlave *i2c, enum i2c_event event) -{ - DS1338State *s =3D DS1338(i2c); - - switch (event) { - case I2C_START_RECV: - /* In h/w, capture happens on any START condition, not just a - * START_RECV, but there is no need to actually capture on - * START_SEND, because the guest can't get at that data - * without going through a START_RECV which would overwrite it. - */ - capture_current_time(s); - break; - case I2C_START_SEND: - s->addr_byte =3D true; - break; - default: - break; - } - - return 0; -} - -static int ds1338_recv(I2CSlave *i2c) -{ - DS1338State *s =3D DS1338(i2c); - uint8_t res; - - res =3D s->nvram[s->ptr]; - inc_regptr(s); - return res; -} - -static int ds1338_send(I2CSlave *i2c, uint8_t data) -{ - DS1338State *s =3D DS1338(i2c); - - if (s->addr_byte) { - s->ptr =3D data & (NVRAM_SIZE - 1); - s->addr_byte =3D false; - return 0; - } - if (s->ptr < 7) { - /* Time register. */ - struct tm now; - qemu_get_timedate(&now, s->offset); - switch(s->ptr) { - case 0: - /* TODO: Implement CH (stop) bit. */ - now.tm_sec =3D from_bcd(data & 0x7f); - break; - case 1: - now.tm_min =3D from_bcd(data & 0x7f); - break; - case 2: - if (data & HOURS_12) { - int tmp =3D from_bcd(data & (HOURS_PM - 1)); - if (data & HOURS_PM) { - tmp +=3D 12; - } - if (tmp % 12 =3D=3D 0) { - tmp -=3D 12; - } - now.tm_hour =3D tmp; - } else { - now.tm_hour =3D from_bcd(data & (HOURS_12 - 1)); - } - break; - case 3: - { - /* The day field is supposed to contain a value in - the range 1-7. Otherwise behavior is undefined. - */ - int user_wday =3D (data & 7) - 1; - s->wday_offset =3D (user_wday - now.tm_wday + 7) % 7; - } - break; - case 4: - now.tm_mday =3D from_bcd(data & 0x3f); - break; - case 5: - now.tm_mon =3D from_bcd(data & 0x1f) - 1; - break; - case 6: - now.tm_year =3D from_bcd(data) + 100; - break; - } - s->offset =3D qemu_timedate_diff(&now); - } else if (s->ptr =3D=3D 7) { - /* Control register. */ - - /* Ensure bits 2, 3 and 6 will read back as zero. */ - data &=3D 0xB3; - - /* Attempting to write the OSF flag to logic 1 leaves the - value unchanged. */ - data =3D (data & ~CTRL_OSF) | (data & s->nvram[s->ptr] & CTRL_OSF); - - s->nvram[s->ptr] =3D data; - } else { - s->nvram[s->ptr] =3D data; - } - inc_regptr(s); - return 0; -} - -static void ds1338_reset(DeviceState *dev) -{ - DS1338State *s =3D DS1338(dev); - - /* The clock is running and synchronized with the host */ - s->offset =3D 0; - s->wday_offset =3D 0; - memset(s->nvram, 0, NVRAM_SIZE); - s->ptr =3D 0; - s->addr_byte =3D false; -} - -static void ds1338_class_init(ObjectClass *klass, void *data) -{ - DeviceClass *dc =3D DEVICE_CLASS(klass); - I2CSlaveClass *k =3D I2C_SLAVE_CLASS(klass); - - k->event =3D ds1338_event; - k->recv =3D ds1338_recv; - k->send =3D ds1338_send; - dc->reset =3D ds1338_reset; - dc->vmsd =3D &vmstate_ds1338; -} - -static const TypeInfo ds1338_info =3D { - .name =3D TYPE_DS1338, - .parent =3D TYPE_I2C_SLAVE, - .instance_size =3D sizeof(DS1338State), - .class_init =3D ds1338_class_init, -}; - -static void ds1338_register_types(void) -{ - type_register_static(&ds1338_info); -} - -type_init(ds1338_register_types) --=20 2.11.0 From nobody Sun May 5 13:59:26 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1511733913665630.4934752877933; Sun, 26 Nov 2017 14:05:13 -0800 (PST) Received: from localhost ([::1]:58160 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eJ532-0002x4-Ua for importer@patchew.org; Sun, 26 Nov 2017 17:05:12 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56884) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eJ4xs-00075N-RL for qemu-devel@nongnu.org; Sun, 26 Nov 2017 16:59:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eJ4xo-0002tt-Cv for qemu-devel@nongnu.org; Sun, 26 Nov 2017 16:59:52 -0500 Received: from mail-io0-x243.google.com ([2607:f8b0:4001:c06::243]:32959) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eJ4xo-0002tg-8A; Sun, 26 Nov 2017 16:59:48 -0500 Received: by mail-io0-x243.google.com with SMTP id i184so26886058ioa.0; Sun, 26 Nov 2017 13:59:48 -0800 (PST) Received: from localhost.localdomain (173-29-146-33.client.mchsi.com. [173.29.146.33]) by smtp.gmail.com with ESMTPSA id n184sm6517218itg.9.2017.11.26.13.59.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 26 Nov 2017 13:59:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=En+JWL/qkAVFTvSzskEOJVA+r+axFS5Jwyg0ggs3F0M=; b=H4Qj+qfQsbILdHpbcAq6egQBrAsiNdoInxB9IwJ0YFFN8q30L5BEoE1VnaIV0cvvYv TPs4d1SU5mpNMWy7BqIqYtKNooud45HYxI+7v0YZhusQSTlSy4YbBdBlCcRBT2nd0wOf 0eIg/hd5Tbo86HxGskNzuRwvvUqdVy+f1s8ifn8wsR/AvOsrshAZ+T32/8m5oIfs0zzm HJxtmkNkxTnAFKPW0zW9vyDmxizT0eToNJ+6dETByfhEczFNjCDGijPeGDLt2g4mBbC9 pMt+xJcgjYj/HUGxdkxaKIIAEbhI13/blJkRooGnaBnneNfVDgpTl1M/m0duZKeqJj3S xlGg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=En+JWL/qkAVFTvSzskEOJVA+r+axFS5Jwyg0ggs3F0M=; b=j/6UXdfg7dKhglvGH0ICbmY9WtHCEA5jqJSygdpUq3iZ1ixIg61L73sC8T367aqCxT 3YyoFw8tzwS03XQ+P7USjDo6gm6Mc1Sp3YISELmkf3fHr71vxs5cAOVDiyIbEYog87HW TiN6mjE1MG2WjU1gI9XJAYa6VroL7vZknrJxrKy4MeBSfn6PTA5No6AASUVBXtV9X/vF WnKIVg9g+Xnvul1CXFw3K15waiIVp9FUuWhkj94pKNfJUnx9Lrq3YfyTNV2sgVIbgAFL lQ1MEZYJENAPx/doJK0YLgqfIsoemYsI3Ah4NzKRhxz9op+P9Ny9QTI90byd1ggS/kK/ gpSQ== X-Gm-Message-State: AJaThX50GTQghyKLVO0QGSeaaO0eMaq/6RT3y//tvSqxfg4Q4LxqKE+o CcKBWlypc7ykHRfVLgXyILTkPg== X-Google-Smtp-Source: AGs4zMaKF/291IxdeGxBjNlU5o0/AgkB4ieJO7oeLG0fn7uMa3LSqGoy3w9B1KOeLC8GgXImNq6Afw== X-Received: by 10.107.70.6 with SMTP id t6mr39537406ioa.72.1511733587415; Sun, 26 Nov 2017 13:59:47 -0800 (PST) From: Michael Davidsaver To: Alexander Graf , David Gibson Date: Sun, 26 Nov 2017 15:59:04 -0600 Message-Id: <027efd940a2268e69d9d6d0363858688b22baf11.1511731946.git.mdavidsaver@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4001:c06::243 Subject: [Qemu-devel] [PATCH 06/17] tests: rewrite testing for DS RTC devices X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Davidsaver , qemu-ppc@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Replace existing ds1338-test with more thorough test of time read and set. Signed-off-by: Michael Davidsaver --- tests/Makefile.include | 4 +- tests/ds-rtc-i2c-test.c | 162 ++++++++++++++++++++++++++++++++++++++++++++= ++++ tests/ds1338-test.c | 77 ----------------------- 3 files changed, 164 insertions(+), 79 deletions(-) create mode 100644 tests/ds-rtc-i2c-test.c delete mode 100644 tests/ds1338-test.c diff --git a/tests/Makefile.include b/tests/Makefile.include index ad1c219423..56045cdf09 100644 --- a/tests/Makefile.include +++ b/tests/Makefile.include @@ -348,7 +348,7 @@ check-qtest-sparc64-y =3D tests/endianness-test$(EXESUF) check-qtest-sparc64-y +=3D tests/prom-env-test$(EXESUF) =20 check-qtest-arm-y =3D tests/tmp105-test$(EXESUF) -check-qtest-arm-y +=3D tests/ds1338-test$(EXESUF) +check-qtest-arm-y +=3D tests/ds-rtc-i2c-test$(EXESUF) check-qtest-arm-y +=3D tests/m25p80-test$(EXESUF) gcov-files-arm-y +=3D hw/misc/tmp105.c check-qtest-arm-y +=3D tests/virtio-blk-test$(EXESUF) @@ -745,7 +745,7 @@ tests/bios-tables-test$(EXESUF): tests/bios-tables-test= .o \ tests/boot-sector.o tests/acpi-utils.o $(libqos-obj-y) tests/pxe-test$(EXESUF): tests/pxe-test.o tests/boot-sector.o $(libqos-obj= -y) tests/tmp105-test$(EXESUF): tests/tmp105-test.o $(libqos-omap-obj-y) -tests/ds1338-test$(EXESUF): tests/ds1338-test.o $(libqos-imx-obj-y) +tests/ds-rtc-i2c-test$(EXESUF): tests/ds-rtc-i2c-test.o $(libqos-imx-obj-y) tests/m25p80-test$(EXESUF): tests/m25p80-test.o tests/i440fx-test$(EXESUF): tests/i440fx-test.o $(libqos-pc-obj-y) tests/q35-test$(EXESUF): tests/q35-test.o $(libqos-pc-obj-y) diff --git a/tests/ds-rtc-i2c-test.c b/tests/ds-rtc-i2c-test.c new file mode 100644 index 0000000000..0586dbd467 --- /dev/null +++ b/tests/ds-rtc-i2c-test.c @@ -0,0 +1,162 @@ +/* Testing of Dallas/Maxim I2C bus RTC devices + * + * Copyright (c) 2017 Michael Davidsaver + * + * This work is licensed under the terms of the GNU GPL, version 2. See + * the LICENSE file in the top-level directory. + */ +#include + +#include "qemu/osdep.h" +#include "qemu/bcd.h" +#include "qemu/cutils.h" +#include "qemu/timer.h" +#include "libqtest.h" +#include "libqos/libqos.h" +#include "libqos/i2c.h" + +#define IMX25_I2C_0_BASE 0x43F80000 +#define DS1338_ADDR 0x68 + +static I2CAdapter *i2c; +static uint8_t addr; +static bool use_century; + +static +time_t rtc_gettime(void) +{ + struct tm parts; + uint8_t buf[7]; + + buf[0] =3D 0; + i2c_send(i2c, addr, buf, 1); + i2c_recv(i2c, addr, buf, 7); + + parts.tm_sec =3D from_bcd(buf[0]); + parts.tm_min =3D from_bcd(buf[1]); + if (buf[2] & 0x40) { + /* 12 hour */ + parts.tm_hour =3D from_bcd(buf[2] & 0x1f) % 12u; + if (buf[2] & 0x20) { + parts.tm_hour +=3D 12u; + } + } else { + /* 24 hour */ + parts.tm_hour =3D from_bcd(buf[2] & 0x3f); + } + parts.tm_wday =3D from_bcd(buf[3]); + parts.tm_mday =3D from_bcd(buf[4]); + parts.tm_mon =3D from_bcd((buf[5] & 0x1f) - 1u); + parts.tm_year =3D from_bcd(buf[6]); + if (!use_century || (buf[5] & 0x80)) { + parts.tm_year +=3D 100u; + } + + return mktimegm(&parts); +} + +/* read back and compare with current system time */ +static +void test_rtc_current(void) +{ + uint8_t buf; + time_t expected, actual; + + /* magic address to zero RTC time offset + * as tests may be run in any order + */ + buf =3D 0xff; + i2c_send(i2c, addr, &buf, 1); + + actual =3D time(NULL); + /* new second may start here */ + expected =3D rtc_gettime(); + g_assert_cmpuint(expected, <=3D, actual + 1); + g_assert_cmpuint(expected, >=3D, actual); +} + + +static uint8_t test_time_24[8] =3D { + 0, /* address */ + /* Wed, 22 Nov 2017 18:30:53 +0000 */ + 0x53, + 0x30, + 0x18, /* 6 PM in 24 hour mode */ + 0x03, /* monday is our day 1 */ + 0x22, + 0x11 | 0x80, + 0x17, +}; + +static uint8_t test_time_12[8] =3D { + 0, /* address */ + /* Wed, 22 Nov 2017 18:30:53 +0000 */ + 0x53, + 0x30, + 0x67, /* 6 PM in 12 hour mode */ + 0x03, /* monday is our day 1 */ + 0x22, + 0x11 | 0x80, + 0x17, +}; + +/* write in and read back known time */ +static +void test_rtc_set(const void *raw) +{ + const uint8_t *testtime =3D raw; + uint8_t buf[7]; + unsigned retry =3D 2; + + for (; retry; retry--) { + i2c_send(i2c, addr, testtime, 8); + /* new second may start here */ + i2c_send(i2c, addr, testtime, 1); + i2c_recv(i2c, addr, buf, 7); + + if (testtime[1] =3D=3D buf[0]) { + break; + } + /* we raced start of second, retry */ + }; + + g_assert_cmpuint(testtime[1], =3D=3D, buf[0]); + g_assert_cmpuint(testtime[2], =3D=3D, buf[1]); + g_assert_cmpuint(testtime[3], =3D=3D, buf[2]); + g_assert_cmpuint(testtime[4], =3D=3D, buf[3]); + g_assert_cmpuint(testtime[5], =3D=3D, buf[4]); + if (use_century) { + g_assert_cmpuint(testtime[6], =3D=3D, buf[5]); + } else { + g_assert_cmpuint(testtime[6] & 0x7f, =3D=3D, buf[5]); + } + g_assert_cmpuint(testtime[7], =3D=3D, buf[6]); + + g_assert_cmpuint(retry, >, 0); +} + +int main(int argc, char *argv[]) +{ + int ret; + const char *arch =3D qtest_get_arch(); + + g_test_init(&argc, &argv, NULL); + + if (strcmp(arch, "arm") =3D=3D 0) { + qtest_start("-display none -machine imx25-pdk"); + i2c =3D imx_i2c_create(IMX25_I2C_0_BASE); + addr =3D DS1338_ADDR; + use_century =3D false; + + } + + qtest_add_data_func("/ds-rtc-i2c/set24", test_time_24, test_rtc_set); + qtest_add_data_func("/ds-rtc-i2c/set12", test_time_12, test_rtc_set); + qtest_add_func("/ds-rtc-i2c/current", test_rtc_current); + + ret =3D g_test_run(); + + qtest_end(); + + return ret; +} diff --git a/tests/ds1338-test.c b/tests/ds1338-test.c deleted file mode 100644 index 26968bc82a..0000000000 --- a/tests/ds1338-test.c +++ /dev/null @@ -1,77 +0,0 @@ -/* - * QTest testcase for the DS1338 RTC - * - * Copyright (c) 2013 Jean-Christophe Dubois - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but WI= THOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, see . - */ - -#include "qemu/osdep.h" -#include "libqtest.h" -#include "libqos/i2c.h" - -#define IMX25_I2C_0_BASE 0x43F80000 - -#define DS1338_ADDR 0x68 - -static I2CAdapter *i2c; -static uint8_t addr; - -static inline uint8_t bcd2bin(uint8_t x) -{ - return ((x) & 0x0f) + ((x) >> 4) * 10; -} - -static void send_and_receive(void) -{ - uint8_t cmd[1]; - uint8_t resp[7]; - time_t now =3D time(NULL); - struct tm *tm_ptr =3D gmtime(&now); - - /* reset the index in the RTC memory */ - cmd[0] =3D 0; - i2c_send(i2c, addr, cmd, 1); - - /* retrieve the date */ - i2c_recv(i2c, addr, resp, 7); - - /* check retrieved time againt local time */ - g_assert_cmpuint(bcd2bin(resp[4]), =3D=3D , tm_ptr->tm_mday); - g_assert_cmpuint(bcd2bin(resp[5]), =3D=3D , 1 + tm_ptr->tm_mon); - g_assert_cmpuint(2000 + bcd2bin(resp[6]), =3D=3D , 1900 + tm_ptr->tm_y= ear); -} - -int main(int argc, char **argv) -{ - QTestState *s =3D NULL; - int ret; - - g_test_init(&argc, &argv, NULL); - - s =3D qtest_start("-display none -machine imx25-pdk"); - i2c =3D imx_i2c_create(IMX25_I2C_0_BASE); - addr =3D DS1338_ADDR; - - qtest_add_func("/ds1338/tx-rx", send_and_receive); - - ret =3D g_test_run(); - - if (s) { - qtest_quit(s); - } - g_free(i2c); - - return ret; -} --=20 2.11.0 From nobody Sun May 5 13:59:26 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1511734126208332.5479852968389; Sun, 26 Nov 2017 14:08:46 -0800 (PST) Received: from localhost ([::1]:58182 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eJ56B-00061V-9E for importer@patchew.org; Sun, 26 Nov 2017 17:08:27 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56846) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eJ4xq-00072q-Mf for qemu-devel@nongnu.org; Sun, 26 Nov 2017 16:59:51 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eJ4xp-0002ub-RJ for qemu-devel@nongnu.org; Sun, 26 Nov 2017 16:59:50 -0500 Received: from mail-io0-x242.google.com ([2607:f8b0:4001:c06::242]:40551) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eJ4xp-0002uG-Lv; Sun, 26 Nov 2017 16:59:49 -0500 Received: by mail-io0-x242.google.com with SMTP id d21so12098492ioe.7; Sun, 26 Nov 2017 13:59:49 -0800 (PST) Received: from localhost.localdomain (173-29-146-33.client.mchsi.com. [173.29.146.33]) by smtp.gmail.com with ESMTPSA id n184sm6517218itg.9.2017.11.26.13.59.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 26 Nov 2017 13:59:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=1D6D4D+EEW+DmRhqVSXquFmHWOWoJJE5BzTUo/5DgyY=; b=Fynvea6FkL7UpHL4BnjDyYiimf3v8guZsrq/vajRLxHX5I/6v/n0R19BqkgKyM9tqk kL3GBBgb9n46wH9cD/V5hVUb8fe6+iW9fLv0WLUV+5pTU2iFwLrWZmXp3zyS/mHhRmHX Jeww32D9aws4X1GPkBTSFTXKflNw8EKHTQguXNszxZRhLsU+3of4+cr40K7WczTuTaww 3Ev+75eS0naVLviQoFf+obUxaa6kkFwNqINSBsKjqEBn4bykntd578qKPcKyJAhbMGdN wpI7gktERVPBo9tDP8r6ifY9d6bZ52XZOTP7212QHAXM/drudCqOD5KDLi7Gr68qzE02 svyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=1D6D4D+EEW+DmRhqVSXquFmHWOWoJJE5BzTUo/5DgyY=; b=SZVscsijZ6sKOnlf143NFrKFBNq1LXYIn4lY+35f0SvCjDme3/UUDUvLN6WLj7Rjlx VwLruTxye6+VcolQLxnyvAENHn5fbU9cr6mAAsdCeRR7DYO0kmkXLI0jN+lYATDmCgmb 6KDCDfSd4QXZwqKBeMce6n6uw41vcR/sy3WCYHRb6b4ZFMqZT7riXUTNDSWc6i+BRbqB te+au7FsmWSxAhlibYtjY80skyertYevDyW1/BqEIBpLoymtOuGQ8jt/1oLSUyEavpCI oBlmhjef4iscM0xxmb3jXIG9Md5RWvocm5QvSfVGbtFgWkSH+bPPqsBf8Et5aC8uC1IH E7aQ== X-Gm-Message-State: AJaThX65VDPpIs5lsOORktL8jaR1Tb7Ek2oFBrZS5XLrKYOXqwouui3m yLSGdh+EzI9xr3/KFsFyXsU= X-Google-Smtp-Source: AGs4zMYA6sayBW6eqz/kRhIFlWc5cgt4Xyz0eIhS46cVbaig0YwZVC/M927jHq3ZkVXEf5E1zvGYyQ== X-Received: by 10.107.171.68 with SMTP id u65mr38707632ioe.210.1511733588953; Sun, 26 Nov 2017 13:59:48 -0800 (PST) From: Michael Davidsaver To: Alexander Graf , David Gibson Date: Sun, 26 Nov 2017 15:59:05 -0600 Message-Id: <2e4d338f84913729f8ab51837fbcb94b0958a745.1511731946.git.mdavidsaver@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4001:c06::242 Subject: [Qemu-devel] [PATCH 07/17] e500: fix pci host bridge class/type X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Davidsaver , qemu-ppc@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Correct some confusion wrt. the PCI facing side of the PCI host bridge (not PCIe root complex). The ref. manual for the mpc8533 (as well as mpc8540 and mpc8540) give the class code as PCI_CLASS_PROCESSOR_POWERPC. While the PCI_HEADER_TYPE field is oddly omitted, the tables in the "PCI Configuration Header" section shows a type 0 layout using all 6 BAR registers (as 2x 32, and 2x 64 bit regions) So 997505065dc92e533debf5cb23012ba4e673d387 seems to be in error. Although there was perhaps some confusion as the mpc8533 has a separate PCIe root complex. With PCIe, a root complex has PCI_HEADER_TYPE=3D1. Neither the PCI host bridge, nor the PCIe root complex advertise class PCI_CLASS_BRIDGE_PCI. This was confusing Linux guests, which try to interpret the host bridge as a pci-pci bridge, but get confused and re-enumerate the bus when the primary/secondary/subordinate bus registers don't have valid values. Signed-off-by: Michael Davidsaver --- hw/pci-host/ppce500.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/hw/pci-host/ppce500.c b/hw/pci-host/ppce500.c index f2d108bc8a..8073d396ff 100644 --- a/hw/pci-host/ppce500.c +++ b/hw/pci-host/ppce500.c @@ -423,11 +423,6 @@ static void e500_pcihost_bridge_realize(PCIDevice *d, = Error **errp) "/e500-ccsr")); MemoryRegion *ccsr_mr =3D sysbus_mmio_get_region(ccsr, 0); =20 - pci_config_set_class(d->config, PCI_CLASS_BRIDGE_PCI); - d->config[PCI_HEADER_TYPE] =3D - (d->config[PCI_HEADER_TYPE] & PCI_HEADER_TYPE_MULTI_FUNCTION) | - PCI_HEADER_TYPE_BRIDGE; - memory_region_init_alias(&b->bar0, OBJECT(ccsr), "e500-pci-bar0", ccsr= _mr, 0, memory_region_size(ccsr_mr)); pci_register_bar(d, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &b->bar0); --=20 2.11.0 From nobody Sun May 5 13:59:26 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1511734126192750.8706472143059; Sun, 26 Nov 2017 14:08:46 -0800 (PST) Received: from localhost ([::1]:58183 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eJ56E-000636-Nb for importer@patchew.org; Sun, 26 Nov 2017 17:08:30 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56914) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eJ4xv-00078c-Rv for qemu-devel@nongnu.org; Sun, 26 Nov 2017 16:59:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eJ4xr-0002vT-7f for qemu-devel@nongnu.org; Sun, 26 Nov 2017 16:59:55 -0500 Received: from mail-io0-x244.google.com ([2607:f8b0:4001:c06::244]:44018) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eJ4xr-0002uy-2d; Sun, 26 Nov 2017 16:59:51 -0500 Received: by mail-io0-x244.google.com with SMTP id s37so23390884ioe.10; Sun, 26 Nov 2017 13:59:50 -0800 (PST) Received: from localhost.localdomain (173-29-146-33.client.mchsi.com. [173.29.146.33]) by smtp.gmail.com with ESMTPSA id n184sm6517218itg.9.2017.11.26.13.59.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 26 Nov 2017 13:59:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=F2nGHHpOBxZXvkCeKld5QOa9LzVghfBK41dhV0Ihz4I=; b=Z1R0tUlJcw74EICZ8TRveJ1Gj4O1JM6DyZ0JNV3UTDuDjjaNbgBhaO33N1TON8YPmu O9yBjvW0KtMQWAY/6H82tsstUmB11BDlLE63bpJ1qC3Zdx5IsKQs11xYOuMX9bDkr6hB S7zCH8p9r5OMv69r9kQ3wb++OnL0uZwJYAUuJl/Wd1rJKgHiz3oNIq/BZDzSQ7tfLn3L DtJ6/ySSWACQjyWI4AdeRKMAbYxn/iPlbtRbjFZyacQF779L9m2octNlFx++6IveyQD4 37h7GNrBvALQJtNURp5vzado+MOk9clwH2E4pGnx03ivBINgJrLsRmd8fyWWYI/u0KO9 Qtmg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=F2nGHHpOBxZXvkCeKld5QOa9LzVghfBK41dhV0Ihz4I=; b=L87BS0oL3aYsT4WuRdTzRKUvmYn5ycq6wm8fZRs+Io89d1oR1s1WKvo8lXPdfcXK4M SPryJOPpqgWr3H7GMGHxuzXrRnqxtYNWCBSoi5oLqhQuXLEQJ9eOg/NQkKqVu2vzyp0z YMGHg2pvhCDnfTsscOsJCkWDZV42oJdjOcnqkbyZQqErdO5Pe3iT84UU5NsaM4ExYWd4 yofh0zSuLGjq6bPpW/+kpKf40INNVioZgeFicMbCXMRFLPPo0vUGpZc30kCyRPGxr49w QDPNpnlYXen+3AtZKB6bzUYrgQWLrxaZKV0L8PShncoIzM1oXuvMLr/FEsshAY9FIJlo qEow== X-Gm-Message-State: AJaThX5UzJMRyrYIMJGyHO3R8xqfxC1YUCiiwA5UdGF7KKyeQvpljWWq CWUlitthFhxuuxWmfLENF/kkqQ== X-Google-Smtp-Source: AGs4zMaUJMHob3TSK6uoYRRsYfbtkJECwVs7qfe42fdfy0Lj+6z72wQwOO/PfB/3kayVFggzUcTQ/w== X-Received: by 10.107.34.206 with SMTP id i197mr37915182ioi.134.1511733590389; Sun, 26 Nov 2017 13:59:50 -0800 (PST) From: Michael Davidsaver To: Alexander Graf , David Gibson Date: Sun, 26 Nov 2017 15:59:06 -0600 Message-Id: <11edba0f74534a8013e6264f8a4f0cdf064a9ecd.1511731946.git.mdavidsaver@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4001:c06::244 Subject: [Qemu-devel] [PATCH 08/17] e500: additional CCSR registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Davidsaver , qemu-ppc@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_6 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add CCSRBAR to allow CCSR region to be relocated. Guest memory size introspection via RAM config registers. Dummy RAM error controls. Clock introspection via Power on Reset PLL Status Register. Signed-off-by: Michael Davidsaver ccsrbase also update iack --- hw/ppc/e500.c | 5 ++- hw/ppc/e500_ccsr.c | 93 ++++++++++++++++++++++++++++++++++++++++++++++++++= ++-- 2 files changed, 95 insertions(+), 3 deletions(-) diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index b90f4231a6..e22919f4f1 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -51,7 +51,9 @@ =20 #define RAM_SIZES_ALIGN (64UL << 20) =20 -/* TODO: parameterize */ +/* TODO: parameterize + * Some CCSR offsets duplicated in e500_ccsr.c + */ #define MPC8544_CCSRBAR_SIZE 0x00100000ULL #define MPC8544_MPIC_REGS_OFFSET 0x40000ULL #define MPC8544_MSI_REGS_OFFSET 0x41600ULL @@ -856,6 +858,7 @@ void ppce500_init(MachineState *machine, PPCE500Params = *params) object_property_add_child(qdev_get_machine(), "e500-ccsr", OBJECT(dev), NULL); qdev_prop_set_uint32(dev, "base", params->ccsrbar_base); + qdev_prop_set_uint32(dev, "ram-size", ram_size); qdev_init_nofail(dev); ccsr_addr_space =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); =20 diff --git a/hw/ppc/e500_ccsr.c b/hw/ppc/e500_ccsr.c index 1b586c3f42..9400d7cf13 100644 --- a/hw/ppc/e500_ccsr.c +++ b/hw/ppc/e500_ccsr.c @@ -30,13 +30,26 @@ #include "hw/sysbus.h" =20 /* E500_ denotes registers common to all */ +/* Some CCSR offsets duplicated in e500.c */ =20 +#define E500_CCSRBAR (0) + +#define E500_CS0_BNDS (0x2000) + +#define E500_CS0_CONFIG (0x2080) + +#define E500_ERR_DETECT (0x2e40) +#define E500_ERR_DISABLE (0x2e44) + +#define E500_PORPLLSR (0xE0000) #define E500_PVR (0xE00A0) #define E500_SVR (0xE00A4) =20 #define MPC8544_RSTCR (0xE00B0) #define MPC8544_RSTCR_RESET (0x02) =20 +#define E500_MPIC_OFFSET (0x40000ULL) + typedef struct { /*< private >*/ SysBusDevice parent_obj; @@ -44,19 +57,59 @@ typedef struct { =20 MemoryRegion iomem; =20 - uint32_t defbase; + uint32_t defbase, base; + uint32_t ram_size; + uint32_t merrd; + + uint32_t porpllsr; + + DeviceState *pic; } CCSRState; =20 #define TYPE_E500_CCSR "e500-ccsr" #define E500_CCSR(obj) OBJECT_CHECK(CCSRState, (obj), TYPE_E500_CCSR) =20 +/* call after changing CCSRState::base */ +static void e500_ccsr_post_move(CCSRState *ccsr) +{ + CPUState *cs; + + CPU_FOREACH(cs) { + PowerPCCPU *cpu =3D POWERPC_CPU(cs); + CPUPPCState *env =3D &cpu->env; + + env->mpic_iack =3D ccsr->base + + E500_MPIC_OFFSET + 0xa0; + } + + sysbus_mmio_map(SYS_BUS_DEVICE(ccsr), 0, ccsr->base); +} + static uint64_t e500_ccsr_read(void *opaque, hwaddr addr, unsigned size) { + CCSRState *ccsr =3D opaque; PowerPCCPU *cpu =3D POWERPC_CPU(current_cpu); CPUPPCState *env =3D &cpu->env; =20 switch (addr) { + case E500_CCSRBAR: + return ccsr->base >> 12; + case E500_CS0_BNDS: + /* we model all RAM in a single chip with addresses [0, ram_size) = */ + return (ccsr->ram_size - 1) >> 24; + case E500_CS0_CONFIG: + return 1 << 31; + case E500_ERR_DETECT: + return 0; /* (errors not modeled) */ + case E500_ERR_DISABLE: + return ccsr->merrd; + case E500_PORPLLSR: + if (!ccsr->porpllsr) { + qemu_log_mask(LOG_UNIMP, + "Machine does not provide valid PORPLLSR\n"); + } + return ccsr->porpllsr; case E500_PVR: return env->spr[SPR_PVR]; case E500_SVR: @@ -72,10 +125,22 @@ static uint64_t e500_ccsr_read(void *opaque, hwaddr ad= dr, static void e500_ccsr_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { + CCSRState *ccsr =3D opaque; PowerPCCPU *cpu =3D POWERPC_CPU(current_cpu); CPUPPCState *env =3D &cpu->env; uint32_t svr =3D env->spr[SPR_E500_SVR] >> 16; =20 + switch (addr) { + case E500_CCSRBAR: + value &=3D 0x000fff00; + ccsr->base =3D value << 12; + e500_ccsr_post_move(ccsr); + return; + case E500_ERR_DISABLE: + ccsr->merrd =3D value & 0xd; + return; + } + switch (svr) { case 0: /* generic. assumed to be mpc8544ds or e500plat board */ case 0x8034: /* mpc8544 */ @@ -104,11 +169,20 @@ static const MemoryRegionOps e500_ccsr_ops =3D { } }; =20 +static int e500_ccsr_post_load(void *opaque, int version_id) +{ + CCSRState *ccsr =3D opaque; + + e500_ccsr_post_move(ccsr); + return 0; +} + static void e500_ccsr_reset(DeviceState *dev) { CCSRState *ccsr =3D E500_CCSR(dev); =20 - sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, ccsr->defbase); + ccsr->base =3D ccsr->defbase; + e500_ccsr_post_move(ccsr); } =20 static void e500_ccsr_initfn(Object *obj) @@ -123,15 +197,30 @@ static void e500_ccsr_initfn(Object *obj) =20 static Property e500_ccsr_props[] =3D { DEFINE_PROP_UINT32("base", CCSRState, defbase, 0xff700000), + DEFINE_PROP_UINT32("ram-size", CCSRState, ram_size, 0), + DEFINE_PROP_UINT32("porpllsr", CCSRState, porpllsr, 0), DEFINE_PROP_END_OF_LIST() }; =20 +static const VMStateDescription vmstate_e500_ccsr =3D { + .name =3D TYPE_E500_CCSR, + .version_id =3D 1, + .minimum_version_id =3D 1, + .post_load =3D e500_ccsr_post_load, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32(base, CCSRState), + VMSTATE_UINT32(merrd, CCSRState), + VMSTATE_END_OF_LIST() + } +}; + static void e500_ccsr_class_initfn(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); =20 dc->props =3D e500_ccsr_props; + dc->vmsd =3D &vmstate_e500_ccsr; dc->reset =3D e500_ccsr_reset; } =20 --=20 2.11.0 From nobody Sun May 5 13:59:26 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1511734201417411.6133145199897; Sun, 26 Nov 2017 14:10:01 -0800 (PST) Received: from localhost ([::1]:58185 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eJ57X-00078j-HP for importer@patchew.org; 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[173.29.146.33]) by smtp.gmail.com with ESMTPSA id n184sm6517218itg.9.2017.11.26.13.59.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 26 Nov 2017 13:59:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=sa46CU80/eGaEiYeH4n1ldQOXd6pv3zhYHdDqBP2v5g=; b=N9+9++VhAFUK2apv9p7bSsRY5gCaWCEdrUt6gBsFG1wV5pigs/Hr7mPONBJYEoAcOT QThqUlVJek7g/pN3ZNVtGo0wt1OxRDxfZ3xcjsdNNFQ9Yl3S7QarvnUHYt4PtW5su+P6 igT3sm5d2TGS5w2t3RMB8+iHRXjKU5C75i5Dih44jx23FwBNAHZaKrTLFwrInIhyqGmN vTQNHyh7AgCAmJNng11Xsy7xwmOXSPbB4Mu8rOzjz4JCP5OXacc+G9GGPX6Dw7TJGrrH DZA1snElgKQ9GFTaO6jRY1RmrwVVv435pyc3ZUz7vE3f+VhcCQg6g4J1+c/TSc7ls4cd BrWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=sa46CU80/eGaEiYeH4n1ldQOXd6pv3zhYHdDqBP2v5g=; b=aqp81D9tkMsioK7lgbqGSTkM42I8qfe60H2F/dlYKmu+zjeZYQIP8MR9KTPGxJJWcm q4QD3emDO1sWewROto+2a3NUYPFFbIGjdATxIs8FlG7yglSO26KS0tPi6RyClHg0/nob 2+MpXpi+XLDkZud1CL0dkOffeDj79FNEdZrLQAuqPp72kdkK+veYBOASgAyjZ2xfIMFg klAtDI97bStCtHL/PWtSZGzyIUWQb+FDb8TLnBq5hIIeREfNZsQZBCrH6M4Wa6ufRCI3 4IC67T55A68Eo+LSJxnAEubymz7mxiZcL1AbvlsyHAO4qxQAo5Mcr2wZ69Fi3GnIcRn2 vOCA== X-Gm-Message-State: AJaThX6yax055bNnT22zPlk39eBD/n9qKqnvL+df3CPA9spmhCpUGV4r Q/J+XxYpZlDdpQ+HVHJ1QjA= X-Google-Smtp-Source: AGs4zMbd3W6tFcpyzyakmZWEu/cVBWJ/tdYRQydyLqrlhHDRD2nhdI2Kayz1feTbN6mPMXGYdh4cgg== X-Received: by 10.107.128.152 with SMTP id k24mr8024239ioi.184.1511733591731; Sun, 26 Nov 2017 13:59:51 -0800 (PST) From: Michael Davidsaver To: Alexander Graf , David Gibson Date: Sun, 26 Nov 2017 15:59:07 -0600 Message-Id: X-Mailer: git-send-email 2.11.0 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4001:c06::241 Subject: [Qemu-devel] [PATCH 09/17] e500: move mpic under CCSR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Davidsaver , qemu-ppc@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Start moving code out of ppce500_init() Existing ppce500_init_mpic() suggests that MPIC may not be created w/ KVM. However, ppce500_init() used mpicdev unconditionally, and would fail if the MPIC isn't created. So require creation. Not tested with KVM for lack of hardware. Signed-off-by: Michael Davidsaver --- hw/ppc/e500.c | 102 +++----------------------------------------------= ---- hw/ppc/e500_ccsr.c | 85 +++++++++++++++++++++++++++++++++++++++++--- 2 files changed, 84 insertions(+), 103 deletions(-) diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index e22919f4f1..1872bb8eaa 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -29,7 +29,6 @@ #include "sysemu/kvm.h" #include "kvm_ppc.h" #include "sysemu/device_tree.h" -#include "hw/ppc/openpic.h" #include "hw/ppc/ppc.h" #include "hw/loader.h" #include "elf.h" @@ -679,92 +678,6 @@ static void ppce500_cpu_reset(void *opaque) mmubooke_create_initial_mapping(env); } =20 -static DeviceState *ppce500_init_mpic_qemu(PPCE500Params *params, - qemu_irq **irqs) -{ - DeviceState *dev; - SysBusDevice *s; - int i, j, k; - - dev =3D qdev_create(NULL, TYPE_OPENPIC); - object_property_add_child(qdev_get_machine(), "pic", OBJECT(dev), - &error_fatal); - qdev_prop_set_uint32(dev, "model", params->mpic_version); - qdev_prop_set_uint32(dev, "nb_cpus", smp_cpus); - - qdev_init_nofail(dev); - s =3D SYS_BUS_DEVICE(dev); - - k =3D 0; - for (i =3D 0; i < smp_cpus; i++) { - for (j =3D 0; j < OPENPIC_OUTPUT_NB; j++) { - sysbus_connect_irq(s, k++, irqs[i][j]); - } - } - - return dev; -} - -static DeviceState *ppce500_init_mpic_kvm(PPCE500Params *params, - qemu_irq **irqs, Error **errp) -{ - Error *err =3D NULL; - DeviceState *dev; - CPUState *cs; - - dev =3D qdev_create(NULL, TYPE_KVM_OPENPIC); - qdev_prop_set_uint32(dev, "model", params->mpic_version); - - object_property_set_bool(OBJECT(dev), true, "realized", &err); - if (err) { - error_propagate(errp, err); - object_unparent(OBJECT(dev)); - return NULL; - } - - CPU_FOREACH(cs) { - if (kvm_openpic_connect_vcpu(dev, cs)) { - fprintf(stderr, "%s: failed to connect vcpu to irqchip\n", - __func__); - abort(); - } - } - - return dev; -} - -static DeviceState *ppce500_init_mpic(MachineState *machine, - PPCE500Params *params, - MemoryRegion *ccsr, - qemu_irq **irqs) -{ - DeviceState *dev =3D NULL; - SysBusDevice *s; - - if (kvm_enabled()) { - Error *err =3D NULL; - - if (machine_kernel_irqchip_allowed(machine)) { - dev =3D ppce500_init_mpic_kvm(params, irqs, &err); - } - if (machine_kernel_irqchip_required(machine) && !dev) { - error_reportf_err(err, - "kernel_irqchip requested but unavailable: "= ); - exit(1); - } - } - - if (!dev) { - dev =3D ppce500_init_mpic_qemu(params, irqs); - } - - s =3D SYS_BUS_DEVICE(dev); - memory_region_add_subregion(ccsr, MPC8544_MPIC_REGS_OFFSET, - s->mmio[0].memory); - - return dev; -} - static void ppce500_power_off(void *opaque, int line, int on) { if (on) { @@ -794,18 +707,14 @@ void ppce500_init(MachineState *machine, PPCE500Param= s *params) /* irq num for pin INTA, INTB, INTC and INTD is 1, 2, 3 and * 4 respectively */ unsigned int pci_irq_nrs[PCI_NUM_PINS] =3D {1, 2, 3, 4}; - qemu_irq **irqs; DeviceState *dev, *mpicdev; CPUPPCState *firstenv =3D NULL; MemoryRegion *ccsr_addr_space; SysBusDevice *s; =20 - irqs =3D g_malloc0(smp_cpus * sizeof(qemu_irq *)); - irqs[0] =3D g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB); for (i =3D 0; i < smp_cpus; i++) { PowerPCCPU *cpu; CPUState *cs; - qemu_irq *input; =20 cpu =3D POWERPC_CPU(cpu_create(machine->cpu_type)); env =3D &cpu->env; @@ -821,13 +730,7 @@ void ppce500_init(MachineState *machine, PPCE500Params= *params) firstenv =3D env; } =20 - irqs[i] =3D irqs[0] + (i * OPENPIC_OUTPUT_NB); - input =3D (qemu_irq *)env->irq_inputs; - irqs[i][OPENPIC_OUTPUT_INT] =3D input[PPCE500_INPUT_INT]; - irqs[i][OPENPIC_OUTPUT_CINT] =3D input[PPCE500_INPUT_CINT]; env->spr_cb[SPR_BOOKE_PIR].default_value =3D cs->cpu_index =3D i; - env->mpic_iack =3D params->ccsrbar_base + - MPC8544_MPIC_REGS_OFFSET + 0xa0; =20 ppc_booke_timers_init(cpu, 400000000, PPC_TIMER_E500); =20 @@ -857,12 +760,15 @@ void ppce500_init(MachineState *machine, PPCE500Param= s *params) dev =3D qdev_create(NULL, "e500-ccsr"); object_property_add_child(qdev_get_machine(), "e500-ccsr", OBJECT(dev), NULL); + qdev_prop_set_uint32(dev, "mpic-model", params->mpic_version); qdev_prop_set_uint32(dev, "base", params->ccsrbar_base); qdev_prop_set_uint32(dev, "ram-size", ram_size); qdev_init_nofail(dev); ccsr_addr_space =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); =20 - mpicdev =3D ppce500_init_mpic(machine, params, ccsr_addr_space, irqs); + /* created under "e500-ccsr" */ + mpicdev =3D DEVICE(object_resolve_path("/machine/pic", 0)); + assert(mpicdev); =20 /* Serial */ if (serial_hds[0]) { diff --git a/hw/ppc/e500_ccsr.c b/hw/ppc/e500_ccsr.c index 9400d7cf13..68d952794e 100644 --- a/hw/ppc/e500_ccsr.c +++ b/hw/ppc/e500_ccsr.c @@ -24,10 +24,14 @@ #include "qemu-common.h" #include "qemu/log.h" #include "qemu/error-report.h" +#include "qapi/error.h" #include "cpu.h" #include "hw/hw.h" +#include "hw/boards.h" #include "sysemu/sysemu.h" +#include "sysemu/kvm.h" #include "hw/sysbus.h" +#include "hw/ppc/openpic.h" =20 /* E500_ denotes registers common to all */ /* Some CCSR offsets duplicated in e500.c */ @@ -185,20 +189,90 @@ static void e500_ccsr_reset(DeviceState *dev) e500_ccsr_post_move(ccsr); } =20 -static void e500_ccsr_initfn(Object *obj) +static void e500_ccsr_init(Object *obj) { - CCSRState *ccsr =3D E500_CCSR(obj); + DeviceState *dev =3D DEVICE(obj); + CCSRState *ccsr =3D E500_CCSR(dev); + + assert(current_machine); + if (kvm_enabled()) { + + if (!machine_kernel_irqchip_allowed(current_machine)) { + error_report("Machine does not allow PIC," + " but this is not supported"); + exit(1); + } =20 - memory_region_init_io(&ccsr->iomem, obj, &e500_ccsr_ops, + ccsr->pic =3D qdev_create(NULL, TYPE_KVM_OPENPIC); + } else { + ccsr->pic =3D qdev_create(NULL, TYPE_OPENPIC); + } + + if (!ccsr->pic) { + error_report("Failed to create PIC"); + exit(1); + } + + object_property_add_child(qdev_get_machine(), "pic", OBJECT(ccsr->pic), + &error_fatal); + + qdev_prop_set_uint32(ccsr->pic, "nb_cpus", smp_cpus); + + object_property_add_alias(obj, "mpic-model", + OBJECT(ccsr->pic), "model", + &error_fatal); +} + +static void e500_ccsr_realize(DeviceState *dev, Error **errp) +{ + CCSRState *ccsr =3D E500_CCSR(dev); + SysBusDevice *pic; + + /* Base 1MB CCSR Region */ + memory_region_init_io(&ccsr->iomem, OBJECT(dev), &e500_ccsr_ops, ccsr, "e500-ccsr", 1024 * 1024); - sysbus_init_mmio(SYS_BUS_DEVICE(obj), &ccsr->iomem); + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &ccsr->iomem); + + qdev_init_nofail(ccsr->pic); + pic =3D SYS_BUS_DEVICE(ccsr->pic); + + /* connect MPIC to CPU(s) */ + if (kvm_enabled()) { + CPUState *cs; + + CPU_FOREACH(cs) { + if (kvm_openpic_connect_vcpu(ccsr->pic, cs)) { + error_setg(errp, "%s: failed to connect vcpu to irqchip", + __func__); + return; + } + } + + } else { + CPUState *cs; + + CPU_FOREACH(cs) { + PowerPCCPU *cpu =3D POWERPC_CPU(cs); + CPUPPCState *env =3D &cpu->env; + qemu_irq *inputs =3D (qemu_irq *)env->irq_inputs; + int base =3D cs->cpu_index * PPCE500_INPUT_NB; + + sysbus_connect_irq(pic, base + OPENPIC_OUTPUT_INT, + inputs[PPCE500_INPUT_INT]); + sysbus_connect_irq(pic, base + OPENPIC_OUTPUT_CINT, + inputs[PPCE500_INPUT_CINT]); + } + } =20 + memory_region_add_subregion(&ccsr->iomem, E500_MPIC_OFFSET, + sysbus_mmio_get_region(pic, 0)); } =20 static Property e500_ccsr_props[] =3D { DEFINE_PROP_UINT32("base", CCSRState, defbase, 0xff700000), DEFINE_PROP_UINT32("ram-size", CCSRState, ram_size, 0), DEFINE_PROP_UINT32("porpllsr", CCSRState, porpllsr, 0), + /* "mpic-model" aliased from MPIC */ DEFINE_PROP_END_OF_LIST() }; =20 @@ -221,6 +295,7 @@ void e500_ccsr_class_initfn(ObjectClass *klass, void *d= ata) =20 dc->props =3D e500_ccsr_props; dc->vmsd =3D &vmstate_e500_ccsr; + dc->realize =3D e500_ccsr_realize; dc->reset =3D e500_ccsr_reset; } =20 @@ -228,7 +303,7 @@ static const TypeInfo e500_ccsr_info =3D { .name =3D TYPE_E500_CCSR, .parent =3D TYPE_SYS_BUS_DEVICE, .instance_size =3D sizeof(CCSRState), - .instance_init =3D e500_ccsr_initfn, + .instance_init =3D e500_ccsr_init, .class_size =3D sizeof(SysBusDeviceClass), .class_init =3D e500_ccsr_class_initfn }; --=20 2.11.0 From nobody Sun May 5 13:59:26 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1511733733935183.46539311982679; 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X-Received-From: 2607:f8b0:4001:c06::242 Subject: [Qemu-devel] [PATCH 10/17] e500: move uarts CCSR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Davidsaver , qemu-ppc@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Michael Davidsaver --- hw/ppc/e500.c | 13 ------------- hw/ppc/e500_ccsr.c | 18 ++++++++++++++++++ 2 files changed, 18 insertions(+), 13 deletions(-) diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index 1872bb8eaa..2d87d91582 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -22,7 +22,6 @@ #include "net/net.h" #include "qemu/config-file.h" #include "hw/hw.h" -#include "hw/char/serial.h" #include "hw/pci/pci.h" #include "hw/boards.h" #include "sysemu/sysemu.h" @@ -770,18 +769,6 @@ void ppce500_init(MachineState *machine, PPCE500Params= *params) mpicdev =3D DEVICE(object_resolve_path("/machine/pic", 0)); assert(mpicdev); =20 - /* Serial */ - if (serial_hds[0]) { - serial_mm_init(ccsr_addr_space, MPC8544_SERIAL0_REGS_OFFSET, - 0, qdev_get_gpio_in(mpicdev, 42), 399193, - serial_hds[0], DEVICE_BIG_ENDIAN); - } - - if (serial_hds[1]) { - serial_mm_init(ccsr_addr_space, MPC8544_SERIAL1_REGS_OFFSET, - 0, qdev_get_gpio_in(mpicdev, 42), 399193, - serial_hds[1], DEVICE_BIG_ENDIAN); - } =20 /* PCI */ dev =3D qdev_create(NULL, "e500-pcihost"); diff --git a/hw/ppc/e500_ccsr.c b/hw/ppc/e500_ccsr.c index 68d952794e..f1adba4e54 100644 --- a/hw/ppc/e500_ccsr.c +++ b/hw/ppc/e500_ccsr.c @@ -31,6 +31,7 @@ #include "sysemu/sysemu.h" #include "sysemu/kvm.h" #include "hw/sysbus.h" +#include "hw/char/serial.h" #include "hw/ppc/openpic.h" =20 /* E500_ denotes registers common to all */ @@ -45,6 +46,8 @@ #define E500_ERR_DETECT (0x2e40) #define E500_ERR_DISABLE (0x2e44) =20 +#define E500_DUART_OFFSET(N) (0x4500 + (N) * 0x100) + #define E500_PORPLLSR (0xE0000) #define E500_PVR (0xE00A0) #define E500_SVR (0xE00A4) @@ -266,6 +269,21 @@ static void e500_ccsr_realize(DeviceState *dev, Error = **errp) =20 memory_region_add_subregion(&ccsr->iomem, E500_MPIC_OFFSET, sysbus_mmio_get_region(pic, 0)); + /* Note: MPIC internal interrupts are offset by 16 */ + + /* DUARTS */ + if (serial_hds[0]) { + serial_mm_init(&ccsr->iomem, E500_DUART_OFFSET(0), + 0, qdev_get_gpio_in(ccsr->pic, 16 + 26), 399193, + serial_hds[0], DEVICE_BIG_ENDIAN); + } + + if (serial_hds[1]) { + serial_mm_init(&ccsr->iomem, E500_DUART_OFFSET(1), + 0, qdev_get_gpio_in(ccsr->pic, 16 + 26), 399193, + serial_hds[1], DEVICE_BIG_ENDIAN); + } + } =20 static Property e500_ccsr_props[] =3D { --=20 2.11.0 From nobody Sun May 5 13:59:26 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1511733911041496.3737740262418; Sun, 26 Nov 2017 14:05:11 -0800 (PST) Received: from localhost ([::1]:58159 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eJ52y-0002tO-PD for importer@patchew.org; Sun, 26 Nov 2017 17:05:08 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56926) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eJ4xw-00078s-3K for qemu-devel@nongnu.org; Sun, 26 Nov 2017 16:59:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eJ4xv-0002x5-2I for qemu-devel@nongnu.org; Sun, 26 Nov 2017 16:59:56 -0500 Received: from mail-it0-x243.google.com ([2607:f8b0:4001:c0b::243]:35581) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eJ4xu-0002wv-Sb; Sun, 26 Nov 2017 16:59:54 -0500 Received: by mail-it0-x243.google.com with SMTP id x28so3495176ita.0; Sun, 26 Nov 2017 13:59:54 -0800 (PST) Received: from localhost.localdomain (173-29-146-33.client.mchsi.com. [173.29.146.33]) by smtp.gmail.com with ESMTPSA id n184sm6517218itg.9.2017.11.26.13.59.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 26 Nov 2017 13:59:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=PbqB/VGf4r4Gc9nD+4nF5YJ6K6RaL7p0+A+s4fwSp3U=; b=kiVVGP9iHaqnWRdD95CTzNgQ8iLMsUK14AYJAmBADfHZc6pJmNMm/XmoDlvOL0v9C+ qlCJWy/fgnk1DLKjUZXuxaw4pZs0KDc5+llAw3icx/lSm6iTp1aeG23JFwFGDWnCGh90 QnbjMRISXWXLEXD+kGVbZhaL7HwfN9uIt8FFCJBJIh9SvUfze21LjhqwgFqiGH3KJuqZ zRycJB7C8vtWWJdq8FvJ69RQo257rkdFZOtkbxg8YhmUi6oOuETwqpBtSo/aquSPpOIe +xJ6ULaH/9QbT+UCp7/pPRfNYrMYCdhFJqSNqU+5nQa6FAl4ieMmgOiIIDD1J3wACEcO nxVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=PbqB/VGf4r4Gc9nD+4nF5YJ6K6RaL7p0+A+s4fwSp3U=; b=CKuvhdSFln4R4eOA6niN1dHiAqM+qRtqqNo4jctFy4sEEs5h81gDjIhHkzP/jv7h1T I0OJtT90MPCe7+ZvoCFUnvw0KYutQe8eYrE4QIKKG6lKyrfDcVDzF+JKKJX6hollzS6b VYpmaWLlKGf42OepT7gHfbcNfUCfmvN6v7jJ1iIRjhoeQxKRo5BZN2rhEKHX2BsJcvjC wz/ahhih+AzQocez9nMZhRCLlzXyxF9b+aPOd3g7BU0ow+BTop5aIaehgoa1txfnxMH1 Iy1YJ/yp3N9yr3qVIPQViClgfrit83U9CFHe+TeAa56SjCD2ruXfFMbZ2Kath1Ugaa9e 1Qvg== X-Gm-Message-State: AJaThX4dKQEf9IjjV/goS2a5ha8wmI9xbfhB+LiD1aqNYWb4zZLed22P GP8XEPtQvfQJT1BF95c/CChWzA== X-Google-Smtp-Source: AGs4zMZz/WXSU8ju8O4lyxTCFJtZoXi+3/NFkY8u8fSpYR6PscZS6jHkFZ20blMR6V1aNJasAQ3KlA== X-Received: by 10.36.101.140 with SMTP id u134mr11534606itb.108.1511733594189; Sun, 26 Nov 2017 13:59:54 -0800 (PST) From: Michael Davidsaver To: Alexander Graf , David Gibson Date: Sun, 26 Nov 2017 15:59:09 -0600 Message-Id: X-Mailer: git-send-email 2.11.0 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4001:c0b::243 Subject: [Qemu-devel] [PATCH 11/17] e500: derive baud from CCB clock X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Davidsaver , qemu-ppc@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The CCB (Complex Core Bus) clock is the reference for the DUARTs with an extra divide by 16. From the mpc8540, mpc8544, and P2010 ref manuals. CCB=3D333MHz, with divider=3D0x87a gives ~9600 baud. 333e6 Hz/(16*0x87a) =3D 9591 Hz. This is verified with a real mpc8540. The existing value for the mpc8544ds boards is replaced. Previously the uart "clock-frequency" device tree node was left as zero, and at some point either u-boot or Linux picks a value inconsistent with the frequency given to serial_mm_init(). The FIFO timeout calculated from this was incorrect. Now use an arbitrary (valid) CCB frequency of 333MHz in the device tree and for the UART. Signed-off-by: Michael Davidsaver --- hw/ppc/e500.c | 9 ++++++++- hw/ppc/e500_ccsr.c | 16 ++++++++++++---- 2 files changed, 20 insertions(+), 5 deletions(-) diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index 2d87d91582..cfd5ed0152 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -49,6 +49,12 @@ =20 #define RAM_SIZES_ALIGN (64UL << 20) =20 +/* Somewhat arbitrarily choosen Complex Core Bus frequency + * for our simulation (real freq of mpc8544ds board unknown) + * Used in baud rate calculations. + */ +#define CCB_FREQ (333333333) + /* TODO: parameterize * Some CCSR offsets duplicated in e500_ccsr.c */ @@ -113,7 +119,7 @@ static void dt_serial_create(void *fdt, unsigned long l= ong offset, qemu_fdt_setprop_string(fdt, ser, "compatible", "ns16550"); qemu_fdt_setprop_cells(fdt, ser, "reg", offset, 0x100); qemu_fdt_setprop_cell(fdt, ser, "cell-index", idx); - qemu_fdt_setprop_cell(fdt, ser, "clock-frequency", 0); + qemu_fdt_setprop_cell(fdt, ser, "clock-frequency", CCB_FREQ); qemu_fdt_setprop_cells(fdt, ser, "interrupts", 42, 2); qemu_fdt_setprop_phandle(fdt, ser, "interrupt-parent", mpic); qemu_fdt_setprop_string(fdt, "/aliases", alias, ser); @@ -759,6 +765,7 @@ void ppce500_init(MachineState *machine, PPCE500Params = *params) dev =3D qdev_create(NULL, "e500-ccsr"); object_property_add_child(qdev_get_machine(), "e500-ccsr", OBJECT(dev), NULL); + qdev_prop_set_uint32(dev, "ccb-freq", CCB_FREQ); qdev_prop_set_uint32(dev, "mpic-model", params->mpic_version); qdev_prop_set_uint32(dev, "base", params->ccsrbar_base); qdev_prop_set_uint32(dev, "ram-size", ram_size); diff --git a/hw/ppc/e500_ccsr.c b/hw/ppc/e500_ccsr.c index f1adba4e54..c479ed91ee 100644 --- a/hw/ppc/e500_ccsr.c +++ b/hw/ppc/e500_ccsr.c @@ -69,6 +69,7 @@ typedef struct { uint32_t merrd; =20 uint32_t porpllsr; + uint32_t ccb_freq; =20 DeviceState *pic; } CCSRState; @@ -272,15 +273,21 @@ static void e500_ccsr_realize(DeviceState *dev, Error= **errp) /* Note: MPIC internal interrupts are offset by 16 */ =20 /* DUARTS */ + /* for mpc8540, mpc8544, and P2010 (unmodeled), the DUART reference cl= ock + * is the CCB clock divided by 16. + * So baud rate is CCB/(16*divider) + */ if (serial_hds[0]) { - serial_mm_init(&ccsr->iomem, E500_DUART_OFFSET(0), - 0, qdev_get_gpio_in(ccsr->pic, 16 + 26), 399193, + serial_mm_init(&ccsr->iomem, E500_DUART_OFFSET(0), 0, + qdev_get_gpio_in(ccsr->pic, 16 + 26), + ccsr->ccb_freq / 16u, serial_hds[0], DEVICE_BIG_ENDIAN); } =20 if (serial_hds[1]) { - serial_mm_init(&ccsr->iomem, E500_DUART_OFFSET(1), - 0, qdev_get_gpio_in(ccsr->pic, 16 + 26), 399193, + serial_mm_init(&ccsr->iomem, E500_DUART_OFFSET(1), 0, + qdev_get_gpio_in(ccsr->pic, 16 + 26), + ccsr->ccb_freq / 16u, serial_hds[1], DEVICE_BIG_ENDIAN); } =20 @@ -290,6 +297,7 @@ static Property e500_ccsr_props[] =3D { DEFINE_PROP_UINT32("base", CCSRState, defbase, 0xff700000), DEFINE_PROP_UINT32("ram-size", CCSRState, ram_size, 0), DEFINE_PROP_UINT32("porpllsr", CCSRState, porpllsr, 0), + DEFINE_PROP_UINT32("ccb-freq", CCSRState, ccb_freq, 333333333u), /* "mpic-model" aliased from MPIC */ DEFINE_PROP_END_OF_LIST() }; --=20 2.11.0 From nobody Sun May 5 13:59:26 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1511734440308113.3149925384813; Sun, 26 Nov 2017 14:14:00 -0800 (PST) Received: from localhost ([::1]:58225 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eJ5BT-0002kO-7C for importer@patchew.org; Sun, 26 Nov 2017 17:13:55 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56963) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eJ4xx-0007AO-Gp for qemu-devel@nongnu.org; Sun, 26 Nov 2017 16:59:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eJ4xw-0002ye-LW for qemu-devel@nongnu.org; Sun, 26 Nov 2017 16:59:57 -0500 Received: from mail-io0-x241.google.com ([2607:f8b0:4001:c06::241]:40552) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eJ4xw-0002y4-F1; Sun, 26 Nov 2017 16:59:56 -0500 Received: by mail-io0-x241.google.com with SMTP id d21so12098612ioe.7; Sun, 26 Nov 2017 13:59:56 -0800 (PST) Received: from localhost.localdomain (173-29-146-33.client.mchsi.com. [173.29.146.33]) by smtp.gmail.com with ESMTPSA id n184sm6517218itg.9.2017.11.26.13.59.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 26 Nov 2017 13:59:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=JN9e7QU5+Myvn+318HquTAq4+YYP+TFzyDd/cmWdAUM=; b=RMUkdT0QwSkqYgTZyHOiymdvEUOpp8h4peJ5k9LV5WrOVUSLi6Iww8wZYoEr2C7dcK /DizbkxSu3TgberTtiuQ1fnXhQtTK9OBXORFOVM2zjdxzaOEzFpD0hEnP6anaKh6DYtb V7dOad424A5lGGWMFyuubmdtiMUZr7/hTFLoxJT3sg6qu6wCQpGjL9uirree5CSc10eb mfikfIpCOGwF08KPHVG+B6EtuS8W5msK4zv4yPll+DYTCaC/ebl/i8h04ait7idNy1UV DQDnFbow/b9E4H4dlQBJoaeQQR7HjsHdpriaTssbhH7auLExhiBMGdNONtZCaKw56Cmp /yAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=JN9e7QU5+Myvn+318HquTAq4+YYP+TFzyDd/cmWdAUM=; b=mRELrHwuGWpYpMBcz0WLxSSlxRrGo0BZoDiAYqFKFsexw73ykD33gxLy2ZfkxLA+PY 0vUglGVkDuuh4nZKKf+ea1iPA6h1d1StnoKZd04kS3Sh/H4oi618B7M+oxmK5iv/lh8e YPt6WnjZNlyBTpWsIBp1Hjgwxt7mmZG8ZOhzBGpHYV7LGzTbTXNxKZ0REQiuTI8KVG22 ipNPOC6688kFSrsvPw7jqS8XH+XRLQrOTReOnJoxMkyL68bD4ESB8LmJSqC+kt8ndm2m FfKL/gNG0DLKRUKobI3uF/oHb/6TDP4dQ32yVZZkWcgFW3CjICSnCZopLYOQoyHuLkNQ GpwA== X-Gm-Message-State: AJaThX7K/smUemeiUWAe3Q/p+8x+jF4vmjB7RNbcAyTR0SkYia7yxQFE BHh6sJw/2fSB5E6gsC+TTOs= X-Google-Smtp-Source: AGs4zMbCG/w9Oqhm+wKZEXHEwq8Uy494fC//kb0M6T2x+YMCtQUyVaA9M/hOkzIYf0CNe3FroZBhyw== X-Received: by 10.107.144.198 with SMTP id s189mr38209972iod.223.1511733595826; Sun, 26 Nov 2017 13:59:55 -0800 (PST) From: Michael Davidsaver To: Alexander Graf , David Gibson Date: Sun, 26 Nov 2017 15:59:10 -0600 Message-Id: <6cafcb638eb9c002b16e2459475d8ef7a2440849.1511731946.git.mdavidsaver@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4001:c06::241 Subject: [Qemu-devel] [PATCH 12/17] e500: add i2c controller to CCSR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Davidsaver , qemu-ppc@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_6 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add i2c controller found on mpc8540, mpc8544, and P2010 (newer ppc, unmodeled). Signed-off-by: Michael Davidsaver --- hw/ppc/e500_ccsr.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/hw/ppc/e500_ccsr.c b/hw/ppc/e500_ccsr.c index c479ed91ee..cd8216daaf 100644 --- a/hw/ppc/e500_ccsr.c +++ b/hw/ppc/e500_ccsr.c @@ -46,6 +46,8 @@ #define E500_ERR_DETECT (0x2e40) #define E500_ERR_DISABLE (0x2e44) =20 +#define E500_I2C_OFFSET (0x3000) + #define E500_DUART_OFFSET(N) (0x4500 + (N) * 0x100) =20 #define E500_PORPLLSR (0xE0000) @@ -72,6 +74,7 @@ typedef struct { uint32_t ccb_freq; =20 DeviceState *pic; + DeviceState *i2c; } CCSRState; =20 #define TYPE_E500_CCSR "e500-ccsr" @@ -272,6 +275,18 @@ static void e500_ccsr_realize(DeviceState *dev, Error = **errp) sysbus_mmio_get_region(pic, 0)); /* Note: MPIC internal interrupts are offset by 16 */ =20 + /* attach I2C controller */ + ccsr->i2c =3D qdev_create(NULL, "mpc8540-i2c"); + object_property_add_child(qdev_get_machine(), "i2c[*]", + OBJECT(ccsr->i2c), NULL); + qdev_init_nofail(ccsr->i2c); + memory_region_add_subregion(&ccsr->iomem, E500_I2C_OFFSET, + sysbus_mmio_get_region( + SYS_BUS_DEVICE(ccsr->i2c), 0)); + sysbus_connect_irq(SYS_BUS_DEVICE(ccsr->i2c), 0, + qdev_get_gpio_in(ccsr->pic, 16 + 27)); + + /* DUARTS */ /* for mpc8540, mpc8544, and P2010 (unmodeled), the DUART reference cl= ock * is the CCB clock divided by 16. --=20 2.11.0 From nobody Sun May 5 13:59:26 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1511734143426497.1246319089287; Sun, 26 Nov 2017 14:09:03 -0800 (PST) Received: from localhost ([::1]:58184 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eJ56f-0006Q1-Kf for importer@patchew.org; Sun, 26 Nov 2017 17:08:57 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57012) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eJ4xz-0007CO-0j for qemu-devel@nongnu.org; Sun, 26 Nov 2017 17:00:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eJ4xy-00030H-28 for qemu-devel@nongnu.org; Sun, 26 Nov 2017 16:59:59 -0500 Received: from mail-it0-x241.google.com ([2607:f8b0:4001:c0b::241]:35580) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eJ4xx-000302-TI; Sun, 26 Nov 2017 16:59:58 -0500 Received: by mail-it0-x241.google.com with SMTP id x28so3495249ita.0; Sun, 26 Nov 2017 13:59:57 -0800 (PST) Received: from localhost.localdomain (173-29-146-33.client.mchsi.com. [173.29.146.33]) by smtp.gmail.com with ESMTPSA id n184sm6517218itg.9.2017.11.26.13.59.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 26 Nov 2017 13:59:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=beuW+4oEiE3auuui59g2l58/rm+03bI6kGFcMei6OBU=; b=DeXl/ADK16h9ejgmJblef+AsLg+dld348EkU3doqUjkX4OsUq1mP6hR2hd1RjDKteI pzlImmqNgV1IzRFsuoWKqxNANZTNW2j9cbeeRgMfgKs3cBgo9UMMf/hSxdnUumMEJl8d ofxqnwnpnUnCVywkfrlKqWctR/BEzvMx+X34sKeSsIdzGTCOPd1gI+EYhOG4AKxEfP2w FwnSV0I4wsGg+ghUCMg0oke/uDVD7ij6bFGqRQ+8HqtOz0SIQu+X3mSYX6gQPQRGiGmY ZOP4hy9OGYDJAj4BzSnVAta7+8n+wOr0V/ePOGeSTVdGOkk0d4Ffljh59ih3Nqay0k5H 42eA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=beuW+4oEiE3auuui59g2l58/rm+03bI6kGFcMei6OBU=; b=S5TxvzpXRuiYZt/zKVEj/7LxtF2XaEDLS+SeBoUjAghnZ7IHJgeIaVV8eMrNz+NR3Z Sr826EBSjLEfvlL8lG85MmIBB4N5iXwxGgxqHECE3qYxRC1tWHNPS1BvntswfNwBdI05 EbmXoEFPAE2dp/GIHgT2cey4ympMJdRyLWlR5anZmR4aDf6T2bm7vo5ysbMpturZs0oK d0n+9Xv8ecjI9mGeI9PP8qbAl+bREo4w3hZz8j13IVSodGZoDkGEHcRMX1WUguoq+8Ol 3bp6oji7JXIO41afTpQkaxn1Kspih17jKFcble15krRX/sUu04fc6SnnfiCRHBUlNB1e Nz8g== X-Gm-Message-State: AJaThX7t6UiSLw2jf0k+6up5/83ukvdeH7Xs9pEP1slm6ZXuubZC+Mn9 B8+3d9pmecCjYJngu/2nWyeJ5Q== X-Google-Smtp-Source: AGs4zMY1h3tJpmTsW6r8sTt9tATcC4/AYnBrFDjEeRpgO5mvrWZz+YdYc4gaU6MxB6Oj2D1DZQx+kA== X-Received: by 10.36.253.73 with SMTP id m70mr25596805ith.49.1511733597186; Sun, 26 Nov 2017 13:59:57 -0800 (PST) From: Michael Davidsaver To: Alexander Graf , David Gibson Date: Sun, 26 Nov 2017 15:59:11 -0600 Message-Id: <15378780eee5dc9ebc68361463a0fd6acea55556.1511731946.git.mdavidsaver@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4001:c0b::241 Subject: [Qemu-devel] [PATCH 13/17] e500: move PCI host bridge into CCSR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Davidsaver , qemu-ppc@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Michael Davidsaver --- hw/ppc/e500.c | 13 ++++--------- hw/ppc/e500_ccsr.c | 27 +++++++++++++++++++++++++++ 2 files changed, 31 insertions(+), 9 deletions(-) diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index cfd5ed0152..b0c8495aef 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -769,6 +769,8 @@ void ppce500_init(MachineState *machine, PPCE500Params = *params) qdev_prop_set_uint32(dev, "mpic-model", params->mpic_version); qdev_prop_set_uint32(dev, "base", params->ccsrbar_base); qdev_prop_set_uint32(dev, "ram-size", ram_size); + qdev_prop_set_uint32(dev, "pci_first_slot", params->pci_first_slot); + qdev_prop_set_uint32(dev, "pci_first_pin_irq", pci_irq_nrs[0]); qdev_init_nofail(dev); ccsr_addr_space =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); =20 @@ -778,20 +780,13 @@ void ppce500_init(MachineState *machine, PPCE500Param= s *params) =20 =20 /* PCI */ - dev =3D qdev_create(NULL, "e500-pcihost"); - object_property_add_child(qdev_get_machine(), "pci-host", OBJECT(dev), - &error_abort); - qdev_prop_set_uint32(dev, "first_slot", params->pci_first_slot); - qdev_prop_set_uint32(dev, "first_pin_irq", pci_irq_nrs[0]); - qdev_init_nofail(dev); + dev =3D DEVICE(object_resolve_path("/machine/pci-host", 0)); + assert(dev); s =3D SYS_BUS_DEVICE(dev); for (i =3D 0; i < PCI_NUM_PINS; i++) { sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, pci_irq_nrs[i])= ); } =20 - memory_region_add_subregion(ccsr_addr_space, MPC8544_PCI_REGS_OFFSET, - sysbus_mmio_get_region(s, 0)); - pci_bus =3D (PCIBus *)qdev_get_child_bus(dev, "pci.0"); if (!pci_bus) printf("couldn't create PCI controller!\n"); diff --git a/hw/ppc/e500_ccsr.c b/hw/ppc/e500_ccsr.c index cd8216daaf..4ec8f7524d 100644 --- a/hw/ppc/e500_ccsr.c +++ b/hw/ppc/e500_ccsr.c @@ -50,6 +50,8 @@ =20 #define E500_DUART_OFFSET(N) (0x4500 + (N) * 0x100) =20 +#define E500_PCI_OFFSET (0x8000ULL) + #define E500_PORPLLSR (0xE0000) #define E500_PVR (0xE00A0) #define E500_SVR (0xE00A4) @@ -75,6 +77,7 @@ typedef struct { =20 DeviceState *pic; DeviceState *i2c; + DeviceState *pcihost; } CCSRState; =20 #define TYPE_E500_CCSR "e500-ccsr" @@ -201,6 +204,7 @@ static void e500_ccsr_init(Object *obj) DeviceState *dev =3D DEVICE(obj); CCSRState *ccsr =3D E500_CCSR(dev); =20 + /* prepare MPIC */ assert(current_machine); if (kvm_enabled()) { =20 @@ -228,6 +232,18 @@ static void e500_ccsr_init(Object *obj) object_property_add_alias(obj, "mpic-model", OBJECT(ccsr->pic), "model", &error_fatal); + + /* prepare PCI host bridge */ + ccsr->pcihost =3D qdev_create(NULL, "e500-pcihost"); + object_property_add_child(qdev_get_machine(), "pci-host", OBJECT(ccsr-= >pcihost), + &error_abort); + + object_property_add_alias(obj, "pci_first_slot", + OBJECT(ccsr->pcihost), "first_slot", + &error_fatal); + object_property_add_alias(obj, "pci_first_pin_irq", + OBJECT(ccsr->pcihost), "first_pin_irq", + &error_fatal); } =20 static void e500_ccsr_realize(DeviceState *dev, Error **errp) @@ -240,6 +256,7 @@ static void e500_ccsr_realize(DeviceState *dev, Error *= *errp) ccsr, "e500-ccsr", 1024 * 1024); sysbus_init_mmio(SYS_BUS_DEVICE(dev), &ccsr->iomem); =20 + /* realize MPIC */ qdev_init_nofail(ccsr->pic); pic =3D SYS_BUS_DEVICE(ccsr->pic); =20 @@ -275,6 +292,13 @@ static void e500_ccsr_realize(DeviceState *dev, Error = **errp) sysbus_mmio_get_region(pic, 0)); /* Note: MPIC internal interrupts are offset by 16 */ =20 + /* realize PCI host bridge*/ + qdev_init_nofail(ccsr->pcihost); + + memory_region_add_subregion(&ccsr->iomem, E500_PCI_OFFSET, + sysbus_mmio_get_region( + SYS_BUS_DEVICE(ccsr->pcihost), 0)); + /* attach I2C controller */ ccsr->i2c =3D qdev_create(NULL, "mpc8540-i2c"); object_property_add_child(qdev_get_machine(), "i2c[*]", @@ -314,6 +338,9 @@ static Property e500_ccsr_props[] =3D { DEFINE_PROP_UINT32("porpllsr", CCSRState, porpllsr, 0), DEFINE_PROP_UINT32("ccb-freq", CCSRState, ccb_freq, 333333333u), /* "mpic-model" aliased from MPIC */ + /* "pci_first_slot" + * "pci_first_pin_irq" aliased from PCI host bridge + */ DEFINE_PROP_END_OF_LIST() }; =20 --=20 2.11.0 From nobody Sun May 5 13:59:26 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1511734330004733.2920729260759; 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[173.29.146.33]) by smtp.gmail.com with ESMTPSA id n184sm6517218itg.9.2017.11.26.13.59.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 26 Nov 2017 13:59:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=TJAJXOR/ehzfP1ww7RkAbe452LOJolfOsTRo8k3iy/c=; b=C+78g0SG4iA9n6vBgOedySPMEztC39aPnJ0606w/kZ3GeFsEKTn7psoraUi5LJT9C4 ShBSnAewbJxrf/7yU2BV0hFlRteFXLNpmFY7gWC0kAOlEcAZi9GKvTiWHtcxgrLW4uNi v/HuNi4EYlIq3p7euaJuTcqrHVgT9Hmp09Bzj9SKd18ycD+arULkDYimXkTGkzdgr2em l9If2EZmJXTY9aWsqt+4oi62YrEc7vfvWlQae8893C5TYUzU5zjCH00SyGIASUeqpyF0 GefzHzLCBOxj46mUT1M/7+mD3X+N0SRQmKu+e6lRD9S5QP2JoTHl2MiT5yX5Il0vOSBH l7BA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=TJAJXOR/ehzfP1ww7RkAbe452LOJolfOsTRo8k3iy/c=; b=DwBPHGYT0hyGUkgKDy9U2LFOe5Z824MEZy9gABHGJS+oUbMxg5rdM1O2GJCV/fBvSF RH9819IOxYulXG7BM5sPPFVvay/qRMyAjFZ9OWhl7nzi8755v3zm0lGh24gRrwp9ZnO7 QoVh57uH8BNOd6maxacq9c2oi9fuOmRjcnm6ssCSxE78kiR7GLV8jn6NZRqzmhMGW7so 9vhvsWFmfw4m31bH9Hz+dr7YjKSUUKDpbdyIxShYWTg7Me8Snu3GZJ2Qg+zcXFALlgXc m3aFhXaAkEzZ5a5nZmFQtTcrgPwCO/bMlb4a6fs8r2eAYpYsVEnFQAEVd/6SHrUKOs2C /cyA== X-Gm-Message-State: AJaThX7V7LgajgswZVZQ1vsdbqdZyspZrOhSV7/tr3ZJWwSU/QR2jN/3 UE6MhlpLpYDtJnx5aN95NyU= X-Google-Smtp-Source: AGs4zMYmND0Ip068A/YT5J+6AelEDQLaZ2SRWfBUC/hEuzNsryDTNi6lQWAeUS3iFXM2IsmL5IZulA== X-Received: by 10.107.47.93 with SMTP id j90mr32579224ioo.262.1511733598530; Sun, 26 Nov 2017 13:59:58 -0800 (PST) From: Michael Davidsaver To: Alexander Graf , David Gibson Date: Sun, 26 Nov 2017 15:59:12 -0600 Message-Id: <9eb62eb9ad147fef563d259f24c1891b4b2e8511.1511731946.git.mdavidsaver@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4001:c06::243 Subject: [Qemu-devel] [PATCH 14/17] e500: split mpc8544ds specific initialization X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Davidsaver , qemu-ppc@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" split off the remaining board specific parts of e500_init() as mpc85xx_init() which will be used by the existing mpc8544ds and generic e500 boards. Signed-off-by: Michael Davidsaver --- hw/ppc/e500.c | 49 ++++++++++++++++++++++++++++++++----------------- hw/ppc/e500.h | 3 ++- hw/ppc/e500plat.c | 2 +- hw/ppc/mpc8544ds.c | 2 +- 4 files changed, 36 insertions(+), 20 deletions(-) diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index b0c8495aef..0ac7cdf6a1 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -690,7 +690,32 @@ static void ppce500_power_off(void *opaque, int line, = int on) } } =20 -void ppce500_init(MachineState *machine, PPCE500Params *params) + +void ppce500_init(MachineState *machine, uint32_t decrementer_freq) +{ + int i; + for (i =3D 0; i < smp_cpus; i++) { + PowerPCCPU *cpu; + CPUState *cs; + CPUPPCState *env; + + cpu =3D POWERPC_CPU(cpu_create(machine->cpu_type)); + env =3D &cpu->env; + cs =3D CPU(cpu); + + if (env->mmu_model !=3D POWERPC_MMU_BOOKE206) { + error_report("MMU model %i not supported by this machine.", + env->mmu_model); + exit(1); + } + + env->spr_cb[SPR_BOOKE_PIR].default_value =3D cs->cpu_index =3D i; + + ppc_booke_timers_init(cpu, decrementer_freq, PPC_TIMER_E500); + } +} + +void mpc85xx_init(MachineState *machine, PPCE500Params *params) { MemoryRegion *address_space_mem =3D get_system_memory(); MemoryRegion *ram =3D g_new(MemoryRegion, 1); @@ -716,31 +741,21 @@ void ppce500_init(MachineState *machine, PPCE500Param= s *params) CPUPPCState *firstenv =3D NULL; MemoryRegion *ccsr_addr_space; SysBusDevice *s; + CPUState *cs; =20 - for (i =3D 0; i < smp_cpus; i++) { + ppce500_init(machine, 400000000); + + CPU_FOREACH(cs) { PowerPCCPU *cpu; - CPUState *cs; =20 - cpu =3D POWERPC_CPU(cpu_create(machine->cpu_type)); + cpu =3D POWERPC_CPU(cs); env =3D &cpu->env; - cs =3D CPU(cpu); =20 - if (env->mmu_model !=3D POWERPC_MMU_BOOKE206) { - fprintf(stderr, "MMU model %i not supported by this machine.\n= ", - env->mmu_model); - exit(1); - } =20 + /* Register reset handler */ if (!firstenv) { firstenv =3D env; - } =20 - env->spr_cb[SPR_BOOKE_PIR].default_value =3D cs->cpu_index =3D i; - - ppc_booke_timers_init(cpu, 400000000, PPC_TIMER_E500); - - /* Register reset handler */ - if (!i) { /* Primary CPU */ struct boot_info *boot_info; boot_info =3D g_malloc0(sizeof(struct boot_info)); diff --git a/hw/ppc/e500.h b/hw/ppc/e500.h index 70ba1d8f4f..350be17462 100644 --- a/hw/ppc/e500.h +++ b/hw/ppc/e500.h @@ -24,7 +24,8 @@ typedef struct PPCE500Params { hwaddr spin_base; } PPCE500Params; =20 -void ppce500_init(MachineState *machine, PPCE500Params *params); +void ppce500_init(MachineState *machine, uint32_t decrementer_freq); +void mpc85xx_init(MachineState *machine, PPCE500Params *params); =20 hwaddr booke206_page_size_to_tlb(uint64_t size); =20 diff --git a/hw/ppc/e500plat.c b/hw/ppc/e500plat.c index e59e80fb9e..103efc68c2 100644 --- a/hw/ppc/e500plat.c +++ b/hw/ppc/e500plat.c @@ -55,7 +55,7 @@ static void e500plat_init(MachineState *machine) params.mpic_version =3D OPENPIC_MODEL_FSL_MPIC_20; } =20 - ppce500_init(machine, ¶ms); + mpc85xx_init(machine, ¶ms); } =20 static void e500plat_machine_init(MachineClass *mc) diff --git a/hw/ppc/mpc8544ds.c b/hw/ppc/mpc8544ds.c index 1717953ec7..7de4ed8ae2 100644 --- a/hw/ppc/mpc8544ds.c +++ b/hw/ppc/mpc8544ds.c @@ -47,7 +47,7 @@ static void mpc8544ds_init(MachineState *machine) exit(1); } =20 - ppce500_init(machine, ¶ms); + mpc85xx_init(machine, ¶ms); } =20 =20 --=20 2.11.0 From nobody Sun May 5 13:59:26 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1511734466081684.4688253045136; Sun, 26 Nov 2017 14:14:26 -0800 (PST) Received: from localhost ([::1]:58227 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eJ5Bk-0002uc-Ka for importer@patchew.org; Sun, 26 Nov 2017 17:14:12 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57130) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eJ4y9-0007Rm-JP for qemu-devel@nongnu.org; Sun, 26 Nov 2017 17:00:12 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eJ4y1-00032A-Cw for qemu-devel@nongnu.org; Sun, 26 Nov 2017 17:00:09 -0500 Received: from mail-io0-x232.google.com ([2607:f8b0:4001:c06::232]:34465) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eJ4y1-00031x-5D; Sun, 26 Nov 2017 17:00:01 -0500 Received: by mail-io0-x232.google.com with SMTP id q101so34255070ioi.1; Sun, 26 Nov 2017 14:00:00 -0800 (PST) Received: from localhost.localdomain (173-29-146-33.client.mchsi.com. [173.29.146.33]) by smtp.gmail.com with ESMTPSA id n184sm6517218itg.9.2017.11.26.13.59.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 26 Nov 2017 13:59:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=fY/yt3t/rh2m2AggDAUwtZn/4hS1otroQYwAVourqOE=; b=S2KBr+0DMa4cSA0PImxcPDWQYK2GchWZ0fkdMbYODtfbEjDc9344SpemmjlEopsuVf lHIWBJwNg8Bm0tb65UXv2NVC2pq91ia769MFLdPDNjbk0EyflxiVtxzTSw33PplKhPK9 MSKRhEyI9bJiWc+v3cIv+jltLFXlGAn8NL+rR/5H+YAOSN6HNx8E3u5oRUNAmNn+r3PS sccO4rpk1HRdWwYIsQhifKM55l2w4VPKmUs4/QR1EQFM4hEAbTMCyAsYzv7L4N92rwfQ 6rpl6uX8SHGW/g23JXtHV07eq54QZzy9/txtg0/qEZWh8quF9lHOSCykF4Zaoq1F4/8W RVKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=fY/yt3t/rh2m2AggDAUwtZn/4hS1otroQYwAVourqOE=; b=qLzMEG5sOaHBUPsAxrtgouoppdkCLoAsxOU/im9RUf5N6mTToGhHvbl+WS170uwn7S 0iuHYLfOsJ58D3X5GqQy9Yu8/kz3cMu6Nf6CMyCZXSqikQpwKDzCQuvbDZ5TaZnNKju9 MnO3zUIqXD3OBAvGoSSjQDbC9ulGqxNns1S1zQl4Zyb6GRB3xXoW3wHPEHyppnUSoLsO ne1IOoDvmFLnd+2BRmnuO8MbQBMlejZmGyHs4NjDeDyNBClcShu6DGdTSrW/P+UqbrOr I240a8uiDieX6/P9WJSU5M6d1eIqGtWN9AkKha74UE25ZQj5mlden1Dp5nIT+NgfobeN /T+g== X-Gm-Message-State: AJaThX6qat3TAJiIDBxm64RVjmmeE2PkIJDe99reYE06TBPuOX/TJhzw GwJuzhKx6tMv3UQnKWVGNG2yJQ== X-Google-Smtp-Source: AGs4zMZw9mYgY4aredphKkIxuWGrfhsGPhW2Ctbx8I6B3XsFm0urlF32VGt1QDy0LGPF4GR4g1hgVQ== X-Received: by 10.107.20.1 with SMTP id 1mr38072074iou.170.1511733599940; Sun, 26 Nov 2017 13:59:59 -0800 (PST) From: Michael Davidsaver To: Alexander Graf , David Gibson Date: Sun, 26 Nov 2017 15:59:13 -0600 Message-Id: <2e44be300496e431ca22073c3431eb97a81ff86b.1511731946.git.mdavidsaver@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4001:c06::232 Subject: [Qemu-devel] [PATCH 15/17] ppc: add mvme3100 machine X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Davidsaver , qemu-ppc@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Michael Davidsaver --- default-configs/ppc-softmmu.mak | 1 + hw/ppc/Makefile.objs | 1 + hw/ppc/mvme3100.c | 740 ++++++++++++++++++++++++++++++++++++= ++++ hw/ppc/mvme3100_cpld.c | 192 +++++++++++ 4 files changed, 934 insertions(+) create mode 100644 hw/ppc/mvme3100.c create mode 100644 hw/ppc/mvme3100_cpld.c diff --git a/default-configs/ppc-softmmu.mak b/default-configs/ppc-softmmu.= mak index bb225c6e46..3777194a4a 100644 --- a/default-configs/ppc-softmmu.mak +++ b/default-configs/ppc-softmmu.mak @@ -52,3 +52,4 @@ CONFIG_SERIAL_ISA=3Dy CONFIG_MC146818RTC=3Dy CONFIG_ISA_TESTDEV=3Dy CONFIG_RS6000_MC=3Dy +CONFIG_DSRTCI2C=3Dy diff --git a/hw/ppc/Makefile.objs b/hw/ppc/Makefile.objs index c1a63d0c39..c1118aaa42 100644 --- a/hw/ppc/Makefile.objs +++ b/hw/ppc/Makefile.objs @@ -26,5 +26,6 @@ obj-$(CONFIG_MAC) +=3D mac_newworld.o obj-$(CONFIG_E500) +=3D e500.o mpc8544ds.o e500plat.o obj-$(CONFIG_E500) +=3D ppce500_spin.o obj-$(CONFIG_E500) +=3D e500_ccsr.o +obj-$(CONFIG_E500) +=3D mvme3100.o mvme3100_cpld.o # PowerPC 440 Xilinx ML507 reference board. obj-$(CONFIG_XILINX) +=3D virtex_ml507.o diff --git a/hw/ppc/mvme3100.c b/hw/ppc/mvme3100.c new file mode 100644 index 0000000000..8eb6a3a9a4 --- /dev/null +++ b/hw/ppc/mvme3100.c @@ -0,0 +1,740 @@ +/* + * MVME3100 board emulation + * + * Copyright (c) 2015 Michael Davidsaver + * + * This work is licensed under the terms of the GNU GPL, version 2. See + * the LICENSE file in the top-level directory. + * + * This model was developed according to the + * MVME3100 Single Board Computer Programmer's Reference + * P/N: 6806800G37B + * July 2014 + * + * mvme3100-1152 + * 677MHz core, 256MB ram, 64MB flash + * mvme3100-1263 + * 833MHz core, 512MB ram, 128MB flash + * + * MOTLoad on mvme3100-1152 says: + * MPU-Type =3DMPC8540 + * MPU-Int Clock Speed =3D666MHz + * MPU-CCB Clock Speed =3D333MHz + * MPU-DDR Clock Speed =3D166MHz + * MPU-PCI Clock Speed =3D66MHz, PCI, 64-bit + * MPU-Int Cache(L2) Enabled, 256KB, L2CTL =3DA8000300 + * Reset/Boot Vector =3DFlash0 + * Local Memory Found =3D10000000 (&268435456) + * + * MOTLoad on mvme3100-1263 says: + * MPU-Type =3DMPC8540 + * MPU-Int Clock Speed =3D833MHz + * MPU-CCB Clock Speed =3D333MHz + * MPU-DDR Clock Speed =3D166MHz + * MPU-PCI Clock Speed =3D66MHz, PCI, 64-bit + * MPU-Int Cache(L2) Enabled, 256KB, L2CTL =3DA8000300 + * Reset/Boot Vector =3DFlash0 + * Local Memory Found =3D20000000 (&536870912) + * + * Clock ratios + * CCB/PCI -> 5/1 + * core/CCB -> 2/1 (-1152) + * -> 5/2 (-1263) + * + * The overall memory map is determined by the Local Address Windows. + * We do not model the LAWs explicitly. + * + * MOTLoad configures as follows (a super set of table 1-4) + * (MOTLoad RTOS Version 2.0, PAL Version 1.2 RM04) + * LAW 0, 7 - disabled + * LAW 1 - 0x00000000 -> 0x7fffffff - RAM 2G + * LAW 2 - 0x80000000 -> 0xbfffffff - PCI 1G + * LAW 3 - 0xc0000000 -> 0xdfffffff - PCI 512MB + * LAW 4 - 0xe0000000 -> 0xe0ffffff - PCI 16MB + * gap - 0xe1000000 -> 0xbfffffff - CCSR @ 0xe1000000 + * LAW 5 - 0xe2000000 -> 0xe2ffffff - LBC 16MB + * gap - 0xe3000000 -> 0xefffffff + * LAW 6 - 0xf0000000 -> 0xffffffff - LBC 256MB + * + * And validated against the RTEMS 4.9.6 mvme3100 BSP + */ +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qapi/error.h" +#include "qapi/visitor.h" +#include "e500.h" +#include "cpu.h" +#include "qemu-common.h" +#include "cpu-qom.h" +#include "sysemu/sysemu.h" +#include "sysemu/dma.h" +#include "sysemu/block-backend.h" +#include "hw/loader.h" +#include "hw/pci/pci.h" +#include "hw/boards.h" +#include "hw/ppc/ppc.h" +#include "hw/net/fsl_etsec/etsec.h" +#include "sysemu/device_tree.h" +#include "sysemu/qtest.h" +#include "hw/ppc/openpic.h" +#include "qemu/error-report.h" + +/* Same as prep.c and other PPC boards */ +#define CFG_ADDR 0xf0000510 + +#define TYPE_MVME3100 MACHINE_TYPE_NAME("mvme3100") +#define MVME3100(obj) OBJECT_CHECK(MVME3100State, (obj), TYPE_MVME3100) +#define MVME3100_GET_CLASS(obj) \ + OBJECT_GET_CLASS(MVME3100Class, (obj), TYPE_MVME3100) +#define MVME3100_CLASS(klass) \ + OBJECT_CLASS_CHECK(MVME3100Class, (klass), TYPE_MVME3100) + +#define E500_TSEC_OFFSET(N) (0x24000 + (N) * 0x1000) + +/* Complex Core Bus frequency */ +#define CCB_FREQ (333333333u) + +typedef struct mvme3100_info { + const char *desc; + uint32_t cpu_freq; + uint32_t porpllsr; + uint32_t ram_size; +} mvme3100_info; + +typedef struct MVME3100Class { + /*< private >*/ + MachineClass parent_class; + /*< public >*/ + + const mvme3100_info *info; +} MVME3100Class; + +typedef struct MVME3100State { + /*< private >*/ + MachineState parent_obj; + /*< public >*/ + + uint32_t load_address, + entry_address; + + MemoryRegion ram; +} MVME3100State; + + +/* motload "global environment" variables */ +static +const char *gev[] =3D { + /* TODO: somehow snoop in slirp_instances to pick up IP config? */ + "mot-/dev/enet0-cipa=3D10.0.2.15", + "mot-/dev/enet0-gipa=3D10.0.2.2", + "mot-/dev/enet0-snma=3D255.255.255.0", + "mot-/dev/enet0-sipa=3D10.0.2.2", + /* RTEMS specific names for things motload doesn't have */ + "rtems-dns-server=3D10.0.2.3", + "rtems-client-name=3Dqemu", + NULL, +}; + +/* Prepare Motorola Vital Product Data eeprom image. + * Provided to bootloader for use as a default. + * + * Begins with constant "MOTLOAD" followed by variable length records + * with a two byte header (ID code then body length in bytes). + * + * | ID | Length | body .... | repeated until ID=3D0xFF + * + * ID Codes: + * 1 - Product ID (string) + * 2 - Assembly # (string) + * 3 - Serial # (string) + * 5 - CPU Speed (Hz, 4 byte integer + 1 nil) + * 6 - Bus Speed (Hz, 4 byte integer + 1 nil) + * 8 - Ethernet MAC (6 bytes + 1 nil) + * 9 - CPU type + * A - VPD CRC (4 bytes) + * B - Flash Config (??) + * E - L2 Cache Config (??) + * F - VPD Version (4 bytes) + * 19 - L3 Cache Config (??) + * FF - End of VPD (size zero) + * + * Repeat entries for repeated units. eg. two ID=3D0x8 for two NICs + * + * MOTLoad uses the same eeprom to hold it's user configuration + * Global Environment Variable (GEV) list. + */ +typedef struct vpdeeprom { + char * const base; + char *cur; + size_t total; +} vpdeeprom; + +static +void append_gev_vpd(vpdeeprom *vpd, const char *str) +{ + const size_t remaining =3D vpd->total - (vpd->cur - vpd->base), + len =3D strlen(str); + + if ((len =3D=3D 0 && remaining < 1) + || (remaining < len + 2)) + { + fprintf(stderr, "VPD GEV overflow\n"); + return; + } + + memcpy(vpd->cur, str, len + 1); + + vpd->cur +=3D len + 1; +} + +static +void append_vpd(vpdeeprom *vpd, uint8_t id, size_t cnt, const void *val) +{ + const size_t remaining =3D vpd->total - (vpd->cur - vpd->base); + + /* must have enough space for this entry and final ID=3D0xff */ + if ((id =3D=3D 0xff && remaining < 2) + || (remaining + 4 < cnt || cnt > 255)) + { + fprintf(stderr, "VPD overflow\n"); + return; + } + + vpd->cur[0] =3D id; + vpd->cur[1] =3D cnt; + memcpy(vpd->cur + 2, val, cnt); + + vpd->cur +=3D 2 + cnt; +} + +static +void append_string_vpd(vpdeeprom *vpd, uint8_t id, const char *str) +{ + /* include trailing nil */ + append_vpd(vpd, id, strlen(str) + 1, str); +} + +static +void append_mac_vpd(vpdeeprom *vpd, uint8_t id, const MACAddr *addr) +{ + char buf[7]; + memcpy(buf, addr->a, 6); + buf[6] =3D 0; + + append_vpd(vpd, id, 7, buf); +} + +static +void append_u32_vpd(vpdeeprom *vpd, uint8_t id, uint32_t val) +{ + union { + uint32_t ival; + char bytes[5]; /* include trailing nil */ + } buf; + buf.ival =3D cpu_to_be32(val); + buf.bytes[4] =3D 0; + + append_vpd(vpd, id, 5, buf.bytes); +} + +static +void build_vpd(const mvme3100_info *info, char *buf, size_t cnt, + const char *extra) +{ + vpdeeprom vpd =3D {buf, buf, cnt}; + size_t i; + + memset(buf, 0, cnt); + + strcpy(buf, "MOTOROLA"); + vpd.cur +=3D 8; + + /* Product ID (eg. "MVME3100-1152") */ + append_string_vpd(&vpd, 1, info->desc); + + /* serial number */ + append_string_vpd(&vpd, 3, "E0120000"); + + /* CPU Freq. */ + append_u32_vpd(&vpd, 5, info->cpu_freq); + + /* PCI Bus Freq. */ + append_u32_vpd(&vpd, 6, 66666666); + + for (i =3D 0; i < MAX_NICS; i++) { + if (nd_table[i].used) { + append_mac_vpd(&vpd, 8, &nd_table[i].macaddr); + } + } + + append_vpd(&vpd, 0xff, 0, NULL); + + if (vpd.cur - vpd.base > 0x10f8) { + fprintf(stderr, "VPD overflows GEV area.\n"); + return; + } + + /* MOTLOAD's Global Environment Variables + * start at offset 0x10f8. + * This is a set of nil terminated strings of the form "name=3Dvalue" + * with a zero length string signaling the end. + */ + vpd.cur =3D vpd.base + 0x10f8; + + for (i =3D 0; gev[i]; i++) { + append_gev_vpd(&vpd, gev[i]); + } + + if (extra) { + char *E =3D g_strdup(extra); + char **opts =3D g_strsplit(E, " ", 0); + size_t i; + + g_free(E); + + for (i =3D 0; opts[i]; i++) { + char *opt =3D g_strstrip(opts[i]); + size_t olen =3D strlen(opt); + + if (olen =3D=3D 0) { + continue; + } else if (!strchr(opt, '=3D')) { + fprintf(stderr, "Missing '=3D' in -append %s\n", extra); + continue; + } + + append_gev_vpd(&vpd, opt); + } + + g_strfreev(opts); + } + + /* zero length string signals end */ + append_gev_vpd(&vpd, ""); +} + +static +void set_map(CPUPPCState *env, unsigned way, + target_ulong va, hwaddr pa, + unsigned size) +{ + ppcmas_tlb_t *tlb =3D booke206_get_tlbm(env, 1, 0, way); + + tlb->mas1 =3D MAS1_VALID | (size << MAS1_TSIZE_SHIFT); + tlb->mas2 =3D (va & TARGET_PAGE_MASK) | MAS2_I | MAS2_G; + tlb->mas7_3 =3D (pa & TARGET_PAGE_MASK) | MAS3_SR | MAS3_SW | MAS3_SX; +} + +static +void remap_tlb_bare(CPUPPCState *env) +{ + /* The MPC8540 ref. manual says only the upper 4KB (ROM) + * is mapped, but doesn't say exactly how this mapping + * is setup. So we arbitrarily decide to use TLB1 entry 0. + */ + set_map(env, 0, 0xfffff000, 0xfffff000, 0x02); + + env->tlb_dirty =3D true; +} + +static void mvme3100_cpu_reset(void *opaque) +{ + PowerPCCPU *cpu =3D opaque; + CPUState *cs =3D CPU(cpu); + CPUPPCState *env =3D &cpu->env; + + cpu_reset(cs); + + /* HID0 clock control functions not modeled. + * Decrementer always enabled with CCB/8 as reference. + * HID0[EMCP] and HID0[TBEN] set + */ + env->spr[SPR_HID0] |=3D 0x80004000; + + remap_tlb_bare(&cpu->env); + env->nip =3D 0xfffffffc; +} + +static +void mvme3100_pci1_set_irq(void *opaque, int irq_num, int level) +{ + qemu_irq *pic =3D opaque; + + qemu_set_irq(pic[irq_num], level); +} + +/* PCI config from a real mvme3100 as configured by motload + * + * BUS:SLOT:FUN VENDOR-DEV_ID: COMMAND STATUS BASE_ADDR0 BASE_ADDR1 IRQ_= PIN -> IRQ_LINE + * 0:0x00:0 0x1057-0x0008: 0x0006 0x20B0 0x80000000 0x00000000 = 0 -> 0 (=3D0x00) + * 0:0x11:0 0x10E3-0x0148: 0x0146 0x02B0 0x80100004 0x00000000 = 1 -> 0 (=3D0x00) + * 0:0x12:0 0x10B5-0x6520: 0x0147 0x02B0 0x00000000 0x00000000 = 0 -> 0 (=3D0x00) + * 0:0x13:0 0x10B5-0x6520: 0x0147 0x02B0 0x00000000 0x00000000 = 0 -> 0 (=3D0x00) + * 0:0x14:0 0x8086-0x3200: 0x0145 0x02B0 0x00012001 0x00013001 = 1 -> 2 (=3D0x02) + * 2:0x00:0 0x1033-0x0035: 0x0146 0x0210 0x80300000 0x00000000 = 1 -> 4 (=3D0x04) + * 2:0x00:1 0x1033-0x0035: 0x0146 0x0210 0x80301000 0x00000000 = 2 -> 5 (=3D0x05) + * + * The modeled PCI host bridge differs. + * + * We model one PCI-PCI bridge (0:0x12:0) but with a different vendor/devi= ce + * + * We don't model: + * # The SATA controller GD31244 (0x8086-0x3200) + * # The USB (OHCI) controller uPD740101 (0x1033-0x0035) + * # The second PCI-PCI bridge (0:0x13:0) in front of the USB controllers + * + * (Note that the SATA controller found on newer boards is different) + */ + +static void mvme3100_init(MachineState *machine) +{ + MVME3100State *mvme3100 =3D MVME3100(machine); + const mvme3100_info *info; + DeviceState *dev; + BusState *i2c; + PCIBus *pci0, *pci1; + SysBusDevice *cpld, *pic; + qemu_irq *pci1_pins =3D g_malloc_n(4, sizeof(*pci1_pins)); + FWCfgState *fwinfo; + DriveInfo *drvinfo; + MemoryRegion *ccsr; + + { + MVME3100Class *klass =3D MVME3100_GET_CLASS(machine); + info =3D klass->info; + } + + /* Setup CPU */ + + ppce500_init(machine, CCB_FREQ / 8u); + + memory_region_allocate_system_memory(&mvme3100->ram, NULL, + "mvme3100.ram", ram_size); + memory_region_add_subregion(get_system_memory(), 0, &mvme3100->ram); + + qemu_register_reset(mvme3100_cpu_reset, POWERPC_CPU(first_cpu)); + + /* Create CCSR and builtin periphrials */ + dev =3D qdev_create(NULL, "e500-ccsr"); + object_property_add_child(qdev_get_machine(), "e500-ccsr", + OBJECT(dev), NULL); + qdev_prop_set_uint32(dev, "ccb-freq", CCB_FREQ); + qdev_prop_set_uint32(dev, "mpic-model", OPENPIC_MODEL_FSL_MPIC_20); + qdev_prop_set_uint32(dev, "porpllsr", info->porpllsr); + qdev_prop_set_uint32(dev, "base", 0xff700000ULL); + qdev_prop_set_uint32(dev, "ram-size", ram_size); + qdev_prop_set_uint32(dev, "pci_first_slot", 0); + qdev_prop_set_uint32(dev, "pci_first_pin_irq", 1); + qdev_init_nofail(dev); + + ccsr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); + + pic =3D SYS_BUS_DEVICE(object_resolve_path("/machine/pic", NULL)); + + /* Setup mvme3100 specific CPLD device */ + cpld =3D SYS_BUS_DEVICE(qdev_create(NULL, "mvme3100-cpld")); + object_property_add_child(qdev_get_machine(), "cpld", + OBJECT(cpld), &error_fatal); + qdev_init_nofail(DEVICE(cpld)); + + memory_region_add_subregion(get_system_memory(), + 0xe2000000, + sysbus_mmio_get_region(cpld, 0)); + + fwinfo =3D fw_cfg_init_mem(CFG_ADDR, CFG_ADDR + 2); + fw_cfg_add_i16(fwinfo, FW_CFG_NB_CPUS, 1); + fw_cfg_add_i16(fwinfo, FW_CFG_MAX_CPUS, 1); + fw_cfg_add_i64(fwinfo, FW_CFG_RAM_SIZE, machine->ram_size); + + dev =3D DEVICE(object_resolve_path("/machine/pci-host", NULL)); + assert(dev); + pci0 =3D PCI_BUS(qdev_get_child_bus(dev, "pci.0")); + assert(pci0); + + /* Add expansion PCI bus (2x PMC sites) + * "pci-bridge" is not a PLX bridge, but shouldn't matter? + */ + dev =3D qdev_create(BUS(pci0), "pci-bridge"); + + qdev_prop_set_uint8(dev, "chassis_nr", 1); + qdev_prop_set_int32(dev, "addr", PCI_DEVFN(0x12, 0)); + + qdev_init_nofail(dev); + + pci1 =3D PCI_BUS(qdev_get_child_bus(dev, "pci.1")); + assert(pci1); + + pci1_pins[0] =3D qdev_get_gpio_in(DEVICE(pic), 4); + pci1_pins[1] =3D qdev_get_gpio_in(DEVICE(pic), 5); + pci1_pins[2] =3D qdev_get_gpio_in(DEVICE(pic), 6); + pci1_pins[3] =3D qdev_get_gpio_in(DEVICE(pic), 7); + + pci_bus_irqs(pci1, mvme3100_pci1_set_irq, + pci_swizzle_map_irq_fn, pci1_pins, 4); + + /* the actual PLX bridge doesn't emit interrupts */ + pci_set_byte(PCI_DEVICE(dev)->config + PCI_INTERRUPT_PIN, 0); + + /* root bus is only home to soldered devices, and has a + * an arbitrary IRQ pin mapping. + * Don't allow qdev_device_add() to consider it. + */ + { + BusState *bpci0 =3D BUS(pci0); + BusClass *bcls =3D BUS_GET_CLASS(pci0); + assert(bpci0); + + /* bus 0 is thus declared to be full. + * as a side-effect, expansion PCI bus limited to 15 devices + */ + bpci0->max_index =3D bcls->max_dev =3D 15; + } + + /* I2C Controller */ + dev =3D DEVICE(object_resolve_path("/machine/i2c[0]", NULL)); + assert(dev); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, + qdev_get_gpio_in(DEVICE(pic), 16 + 27)); + i2c =3D qdev_get_child_bus(dev, "bus"); + assert(i2c); + + /* NIC (2x TSEC and 1x FEC) */ + if (nd_table[0].used) { + qemu_check_nic_model(&nd_table[0], "eTSEC"); + + dev =3D etsec_create(E500_TSEC_OFFSET(0), ccsr, &nd_table[0], + qdev_get_gpio_in(DEVICE(pic), 16 + 13), + qdev_get_gpio_in(DEVICE(pic), 16 + 14), + qdev_get_gpio_in(DEVICE(pic), 16 + 18)); + + } else if (nd_table[1].used) { + qemu_check_nic_model(&nd_table[1], "eTSEC"); + + dev =3D etsec_create(E500_TSEC_OFFSET(1), ccsr, &nd_table[1], + qdev_get_gpio_in(DEVICE(pic), 16 + 19), + qdev_get_gpio_in(DEVICE(pic), 16 + 20), + qdev_get_gpio_in(DEVICE(pic), 16 + 23)); + + } else if (nd_table[2].used) { + qemu_log_mask(LOG_UNIMP, "FEC (ethernet #3) not modeled\n"); + } + + /* VPD EEPROM */ + dev =3D qdev_create(i2c, "at24c-eeprom"); + object_property_add_child(qdev_get_machine(), "vpd", OBJECT(dev), + &error_fatal); + qdev_prop_set_uint8(dev, "address", 0xa8 >> 1); + qdev_prop_set_uint32(dev, "rom-size", 8192 * 8); + + drvinfo =3D drive_get(IF_PFLASH, 0, 0); + if (drvinfo) { + qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(drvinfo), + &error_fatal); + } + + qdev_init_nofail(dev); + + { + char *buf; + + buf =3D g_malloc0(8192 * 8); + + build_vpd(info, buf, 8192 * 8, machine->kernel_cmdline); + + fw_cfg_add_file(fwinfo, "tomload/vpd", buf, 8192 * 8); + } + + /* DS1375 RTC */ + dev =3D qdev_create(i2c, "ds1375"); + object_property_add_child(qdev_get_machine(), "rtc", OBJECT(dev), + &error_fatal); + qdev_prop_set_uint8(dev, "address", 0xd0 >> 1); + qdev_init_nofail(dev); + qdev_connect_gpio_out(dev, 0, qdev_get_gpio_in(DEVICE(pic), 11)); + + /* TODO: unmodeled i2c devices. + * 0x90 - ds1621 temperature sensor + * 0xa0 - 256*8 byte DDR SPD (???) + * 0xa4 - 64k*8 byte eeprom for "user" configuration + * 0xa6 - 64k*8 byte eeprom for "user" configuration + * 0xaa - 8k*8 byte eeprom for VPD of rear expansion card + */ + + if (!bios_name) { + bios_name =3D "tomload.bin"; + } + + if (!qtest_enabled()) { + MemoryRegion *rom =3D g_malloc0(sizeof(*rom)); + char *fullname =3D qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); + + if (!fullname) { + fprintf(stderr, "qemu: could not find bios file '%s'\n", + bios_name); + exit(1); + } + + memory_region_init_ram(rom, OBJECT(cpld), "rom", + 0x800000, &error_fatal); + + memory_region_add_subregion(get_system_memory(), + 0xff800000, rom); + + /* BIOS =3D=3D image in rom (last 8MB of address space). + * Execution starts with the final word 0xfffffffc + */ + int bsize =3D get_image_size(fullname); + if (bsize !=3D 8 * 1024 * 1024 || + -1 =3D=3D load_image_targphys(fullname, + 0xff800000, 8 * 1024 * 1024)) + { + fprintf(stderr, "qemu: could not load bios file '%s'" + " (%u bytes, requires 8MB)\n", + fullname, (unsigned)bsize); + exit(1); + } + + memory_region_set_readonly(rom, true); + + g_free(fullname); + } + + { + hwaddr image_addr =3D mvme3100->load_address; + + int image_size =3D load_image_targphys(machine->kernel_filename, + image_addr, 0x01000000); + if (machine->kernel_filename && + -1 =3D=3D image_size) + { + fprintf(stderr, "qemu: could not load file '%s'\n", + machine->kernel_filename); + exit(1); + + } else if (mvme3100->entry_address =3D=3D 0) { + mvme3100->entry_address =3D image_addr; + + } else if (mvme3100->entry_address < image_addr + || mvme3100->entry_address >=3D image_addr + image_size) + { + fprintf(stderr, "qemu: entry-address out of range\n"); + exit(1); + } + + if (machine->kernel_cmdline) { + fw_cfg_add_i32(fwinfo, FW_CFG_CMDLINE_SIZE, + strlen(machine->kernel_cmdline) + 1); + fw_cfg_add_string(fwinfo, FW_CFG_CMDLINE_DATA, + machine->kernel_cmdline); + } + + fw_cfg_add_i32(fwinfo, FW_CFG_KERNEL_ADDR, image_addr); + fw_cfg_add_i32(fwinfo, FW_CFG_KERNEL_ENTRY, mvme3100->entry_addres= s); + fw_cfg_add_i32(fwinfo, FW_CFG_KERNEL_SIZE, image_size); + } +} + +static void mvme3100_inst_init(Object *obj) +{ + MVME3100State *mvme3100 =3D MVME3100(obj); + mvme3100->load_address =3D 0x10000; + mvme3100->entry_address =3D 0; +} + +static void mvme3100_visit_addr(Object *obj, + Visitor *v, + const char *name, + void *opaque, + Error **errp) +{ + MVME3100State *mvme3100 =3D MVME3100(obj); + uint32_t *ptr; + + if (strcmp(name, "load-address") =3D=3D 0) { + ptr =3D &mvme3100->load_address; + } else if (strcmp(name, "entry-address") =3D=3D 0) { + ptr =3D &mvme3100->entry_address; + } else { + fprintf(stderr, "logic error: mvme3100 has no prop '%s'\n", name); + exit(1); + } + + visit_type_uint32(v, name, ptr, errp); +} + +static void ppce500_machine_class_init(ObjectClass *klass, void *raw) +{ + mvme3100_info *info =3D raw; + MachineClass *mc =3D MACHINE_CLASS(klass); + MVME3100Class *m3c =3D MVME3100_CLASS(klass); + + m3c->info =3D info; + + mc->desc =3D info->desc; + mc->init =3D mvme3100_init; + mc->max_cpus =3D 1; + mc->default_ram_size =3D info->ram_size; + mc->default_cpu_type =3D POWERPC_CPU_TYPE_NAME("mpc8540_v21"); + + object_class_property_add(OBJECT_CLASS(mc), "load-address", "uint32", + &mvme3100_visit_addr, &mvme3100_visit_addr, = NULL, + NULL, &error_fatal); + object_class_property_add(OBJECT_CLASS(mc), "entry-address", "uint32", + &mvme3100_visit_addr, &mvme3100_visit_addr, = NULL, + NULL, &error_fatal); +} + +static const TypeInfo mvme3100_type =3D { + .abstract =3D true, + .name =3D TYPE_MVME3100, + .parent =3D TYPE_MACHINE, + .instance_size =3D sizeof(MVME3100State), + .instance_init =3D mvme3100_inst_init, + .class_size =3D sizeof(MVME3100Class), +}; + +static mvme3100_info mvme3100_1152 =3D { + .desc =3D "MVME3100-1152", + .cpu_freq =3D 666666666u, + /* CCB/PCI -> 5/1 + * core/CCB -> 2/1 + * + * plat ratio =3D 5 -> 5:1 CCB:PCI + * e500 ratio =3D 4 -> 4:1 e500:CCB + */ + .porpllsr =3D 0x0004000a, + .ram_size =3D 256 * (1 << 20), +}; + +static const TypeInfo mvme3100_1152_type =3D { + .name =3D MACHINE_TYPE_NAME("mvme3100-1152"), + .parent =3D TYPE_MVME3100, + .class_init =3D ppce500_machine_class_init, + .class_data =3D &mvme3100_1152, +}; + +static mvme3100_info mvme3100_1263 =3D { + .desc =3D "MVME3100-1263", + .cpu_freq =3D 833333333u, + /* CCB/PCI -> 5/1 + * core/CCB -> 5/2 + */ + .porpllsr =3D 0x0005000a, + .ram_size =3D 512 * (1 << 20), +}; + +static const TypeInfo mvme3100_1263_type =3D { + .name =3D MACHINE_TYPE_NAME("mvme3100-1263"), + .parent =3D TYPE_MVME3100, + .class_init =3D ppce500_machine_class_init, + .class_data =3D &mvme3100_1263, +}; + +static void mvme3100_machine_init(void) +{ + type_register_static(&mvme3100_type); + type_register_static(&mvme3100_1152_type); + type_register_static(&mvme3100_1263_type); +} + +type_init(mvme3100_machine_init) diff --git a/hw/ppc/mvme3100_cpld.c b/hw/ppc/mvme3100_cpld.c new file mode 100644 index 0000000000..41024566ce --- /dev/null +++ b/hw/ppc/mvme3100_cpld.c @@ -0,0 +1,192 @@ +/* + * MVME3100 board CPLD (local logic) + * + * Copyright (c) 2015 Michael Davidsaver + * + * This work is licensed under the terms of the GNU GPL, version 2. See + * the LICENSE file in the top-level directory. + * + * This model was developed according to the + * MVME3100 Single Board Computer Programmer's Reference + * P/N: 6806800G37B + * July 2014 + * + * And validated against the RTEMS 4.9.6 mvme3100 BSP + */ +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "exec/address-spaces.h" +#include "qemu-common.h" +#include "sysemu/sysemu.h" +#include "hw/sysbus.h" + +/* #define DEBUG_3100CPLD */ + +#define TYPE_CPLD "mvme3100-cpld" + +#define CPLD(obj) OBJECT_CHECK(MVMECPLD, (obj), TYPE_CPLD) + +#ifdef DEBUG_3100CPLD +#define DPRINTK(FMT, ...) printf(TYPE_CPLD " : " FMT, ## __VA_ARGS__) +#else +#define DPRINTK(FMT, ...) do {} while (0) +#endif + +#define LOG(MSK, FMT, ...) qemu_log_mask(MSK, TYPE_CPLD " : " FMT, \ + ## __VA_ARGS__) + +#define CPLD_SIZE 0x20 + +typedef struct { + SysBusDevice parent_obj; + + uint8_t mem[0x10]; + uint32_t test; + + MemoryRegion mmio; +} MVMECPLD; + +static +uint64_t cpld_read(void *opaque, hwaddr addr, unsigned size) +{ + MVMECPLD *self =3D opaque; + uint32_t offset =3D addr; + uint32_t val, A; + + switch (offset) { + case 1 ... 0xf: + val =3D 0; + A =3D offset; + while (size--) { + val <<=3D 8; + val |=3D self->mem[A++]; + } + break; + case 0x10: + val =3D self->test; + break; + case 0x14: + val =3D ~self->test; + break; + default: + LOG(LOG_UNIMP, "read from unimplimented register %08x\n", + (unsigned)offset); + val =3D 0; + } + + DPRINTK("read %08x -> %08x\n", (unsigned)offset, (unsigned)val); + + return val; +} + +static +void cpld_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) +{ + MVMECPLD *self =3D opaque; + uint32_t offset =3D addr; + + DPRINTK("write %08x <- %08x\n", (unsigned)offset, (unsigned)val); + + switch (offset) { + case 0: + break; + case 1: + /* TODO: TSTAT_MASK and EEPROM_WPEEPROM */ + if ((val & 0xe0) =3D=3D 0xa0) { + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); + } + self->mem[offset >> 2] =3D val & 0x3; + break; + case 2: + self->mem[offset >> 2] =3D val & 0xf; + break; + case 3: + self->mem[offset >> 2] =3D val & 0x18; + break; + case 4 ... 9: + break; + case 10 ... 13: + /* TODO: allow date to be changed? */ + break; + case 0x10: + self->test =3D val; + break; + case 0x11: + self->test =3D ~val; + break; + default: + LOG(LOG_UNIMP, "write to unimplimented register %08x\n", + (unsigned)offset); + break; + } +} + +static const MemoryRegionOps cpld_ops =3D { + .read =3D cpld_read, + .write =3D cpld_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, +}; +static +void mvme3100_cpld_realize(DeviceState *dev, Error **errp) +{ + MVMECPLD *self =3D CPLD(dev); + + memory_region_init_io(&self->mmio, OBJECT(self), &cpld_ops, self, + TYPE_CPLD, CPLD_SIZE); + + sysbus_init_mmio(&self->parent_obj, &self->mmio); +} + +static Property mvme3100_cpld_props[] =3D { + DEFINE_PROP_END_OF_LIST() +}; + +static +void mvme3100_cpld_reset(DeviceState *dev) +{ + MVMECPLD *self =3D CPLD(dev); + + self->mem[0] =3D 0; /* Type VME SBC, SAFE_START=3D=3D0 */ + self->mem[1] =3D 3; + self->mem[2] =3D 1; + self->mem[3] =3D 9; + self->mem[4] =3D 9; + self->mem[5] =3D 0xa9; + self->mem[6] =3D 1; + self->mem[7] =3D 0xe0; /* TODO, TSEC phy irq status */ + self->mem[8] =3D 1; /* TODO: PMC presence ...? */ + self->mem[9] =3D 1; /* TODO: real rev. # */ + self->mem[10] =3D 15; /* TODO: real date code */ + self->mem[11] =3D 11; + self->mem[12] =3D 14; + self->mem[13] =3D 1; + self->test =3D 0; +} + +static +void mvme3100_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->realize =3D &mvme3100_cpld_realize; + dc->reset =3D &mvme3100_cpld_reset; + dc->desc =3D "mvme3100 CPLD logic"; + dc->props =3D mvme3100_cpld_props; +} + +static const TypeInfo mvme3100_cpld_info =3D { + .name =3D TYPE_CPLD, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(MVMECPLD), + .class_size =3D sizeof(SysBusDeviceClass), + .class_init =3D mvme3100_class_init, +}; + +static +void mvme3100_cpld_register(void) +{ + type_register_static(&mvme3100_cpld_info); +} + +type_init(mvme3100_cpld_register) --=20 2.11.0 From nobody Sun May 5 13:59:26 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1511734499505337.60332239862385; Sun, 26 Nov 2017 14:14:59 -0800 (PST) Received: from localhost ([::1]:58230 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eJ5CI-0003PB-Nb for importer@patchew.org; Sun, 26 Nov 2017 17:14:46 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57131) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eJ4y9-0007Rn-JO for qemu-devel@nongnu.org; Sun, 26 Nov 2017 17:00:11 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eJ4y1-00032u-UA for qemu-devel@nongnu.org; Sun, 26 Nov 2017 17:00:09 -0500 Received: from mail-io0-x242.google.com ([2607:f8b0:4001:c06::242]:40552) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eJ4y1-00032J-Qr; Sun, 26 Nov 2017 17:00:01 -0500 Received: by mail-io0-x242.google.com with SMTP id d21so12098727ioe.7; Sun, 26 Nov 2017 14:00:01 -0800 (PST) Received: from localhost.localdomain (173-29-146-33.client.mchsi.com. [173.29.146.33]) by smtp.gmail.com with ESMTPSA id n184sm6517218itg.9.2017.11.26.14.00.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 26 Nov 2017 14:00:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=1Pzg0ugFmn+AJy+ohyCzHJaGYX46O3pZarttnJ8Hesw=; b=S+/eUiQWY4EXFUqS4VdX6AwzELYsFG2FcZMg9og80Y+hweGWrA8U1z3HETooQgAe4v x9GYj7hQyrBQjrhL+UBfqhUq8qQ6oaa8gTP5SRrrH7i29wxpjJwjuX5Nnemvh2piipUI c/3LmVucp0XMnS+9b72AbPQYYhVS/y8A74yusvLQk7kQGGVJRK6r6sIgrwYu29yOiAcm uT7QFWkh8kOJjBJ/UbFyMx3GIcgXsJwkP6DojksqRI4H+zE4ImtWkFG0O9dnIJhpY6zR p8xgb+lk/FujNNl7BXHSRHERAJjMbDD6Dbn3RgpXVgCEUE9rKyL1j/+5f8EJ7QLLnsrZ 7TSQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=1Pzg0ugFmn+AJy+ohyCzHJaGYX46O3pZarttnJ8Hesw=; b=dbAySykmHE5GiUXzJgZzzUBuho3nKll26oRoOVXsM4DlYPOk6GhsyFkXAFymX+/r2T HVHtWXK5+Wyqlnn0FYoifrdFyv8kevNV/kM2a2fghgeWLB2apWiu0P7v54D0isRJ1vtO MGNzibQDTZLA2pjllN3ib/d8VxesCIbTFN7eYoZ3voHR7nYJszqom3MoAWwQhhKR2MIG aubh/qT9/nJDasjuslP5YYpoUslfrXvCEw9vflTZshY7dhaH/5PuKqHgNz+L1mu2npb5 3lid/nGFkDvYWt81V9d/4iljqey3Jj5GcAzoPFaUpoUq70VjkPBNwgENzRlXX5Ha8CCu mETw== X-Gm-Message-State: AJaThX4QDuqh7vFRp2YSgh/9OSJ4Y6yYHoGL95lleMN7+wGHfTCCmQH9 w0Lc5qmR49m5pkTaVn8EQcw= X-Google-Smtp-Source: AGs4zMZ8E7QEsJM7BXFInL1iz+p7QkpemGmArlMfDUuEaRTyheImZvMETNmaCuyj+7GD8EVIc7a4Ig== X-Received: by 10.107.166.3 with SMTP id p3mr38983718ioe.53.1511733601190; Sun, 26 Nov 2017 14:00:01 -0800 (PST) From: Michael Davidsaver To: Alexander Graf , David Gibson Date: Sun, 26 Nov 2017 15:59:14 -0600 Message-Id: <890b7a4e88ca271acd6f19ce20a7979fbac424ae.1511731946.git.mdavidsaver@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4001:c06::242 Subject: [Qemu-devel] [PATCH 16/17] tests: run ds-rtc-i2c-test w/ ppc/mvme3100 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Davidsaver , qemu-ppc@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_6 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Michael Davidsaver Reviewed-by: David Gibson --- tests/Makefile.include | 3 ++- tests/ds-rtc-i2c-test.c | 8 ++++++++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/tests/Makefile.include b/tests/Makefile.include index 56045cdf09..062d4e5b7b 100644 --- a/tests/Makefile.include +++ b/tests/Makefile.include @@ -308,6 +308,7 @@ check-qtest-ppc-y +=3D tests/boot-order-test$(EXESUF) check-qtest-ppc-y +=3D tests/prom-env-test$(EXESUF) check-qtest-ppc-y +=3D tests/drive_del-test$(EXESUF) check-qtest-ppc-y +=3D tests/boot-serial-test$(EXESUF) +check-qtest-ppc-y +=3D tests/ds-rtc-i2c-test$(EXESUF) =20 check-qtest-ppc64-y =3D tests/spapr-phb-test$(EXESUF) gcov-files-ppc64-y =3D ppc64-softmmu/hw/ppc/spapr_pci.c @@ -745,7 +746,7 @@ tests/bios-tables-test$(EXESUF): tests/bios-tables-test= .o \ tests/boot-sector.o tests/acpi-utils.o $(libqos-obj-y) tests/pxe-test$(EXESUF): tests/pxe-test.o tests/boot-sector.o $(libqos-obj= -y) tests/tmp105-test$(EXESUF): tests/tmp105-test.o $(libqos-omap-obj-y) -tests/ds-rtc-i2c-test$(EXESUF): tests/ds-rtc-i2c-test.o $(libqos-imx-obj-y) +tests/ds-rtc-i2c-test$(EXESUF): tests/ds-rtc-i2c-test.o $(libqos-imx-obj-y= ) $(libqos-e500-obj-y) tests/m25p80-test$(EXESUF): tests/m25p80-test.o tests/i440fx-test$(EXESUF): tests/i440fx-test.o $(libqos-pc-obj-y) tests/q35-test$(EXESUF): tests/q35-test.o $(libqos-pc-obj-y) diff --git a/tests/ds-rtc-i2c-test.c b/tests/ds-rtc-i2c-test.c index 0586dbd467..f7dab1863e 100644 --- a/tests/ds-rtc-i2c-test.c +++ b/tests/ds-rtc-i2c-test.c @@ -18,6 +18,9 @@ #define IMX25_I2C_0_BASE 0x43F80000 #define DS1338_ADDR 0x68 =20 +#define E500_CCSR_BASE 0xff700000 +#define DS1375_ADDR 0xd0 + static I2CAdapter *i2c; static uint8_t addr; static bool use_century; @@ -148,6 +151,11 @@ int main(int argc, char *argv[]) addr =3D DS1338_ADDR; use_century =3D false; =20 + } else if (strcmp(arch, "ppc") =3D=3D 0) { + qtest_start("-machine mvme3100-1152"); + i2c =3D e500_i2c_create(E500_CCSR_BASE); + addr =3D DS1375_ADDR; + use_century =3D true; } =20 qtest_add_data_func("/ds-rtc-i2c/set24", test_time_24, test_rtc_set); --=20 2.11.0 From nobody Sun May 5 13:59:26 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1511734316194417.736306432721; Sun, 26 Nov 2017 14:11:56 -0800 (PST) Received: from localhost ([::1]:58206 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eJ59X-0000S5-D7 for importer@patchew.org; Sun, 26 Nov 2017 17:11:55 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57132) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eJ4y9-0007Ro-JV for qemu-devel@nongnu.org; Sun, 26 Nov 2017 17:00:11 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eJ4y3-00033V-BV for qemu-devel@nongnu.org; Sun, 26 Nov 2017 17:00:09 -0500 Received: from mail-io0-x243.google.com ([2607:f8b0:4001:c06::243]:32960) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eJ4y3-00033I-7R; Sun, 26 Nov 2017 17:00:03 -0500 Received: by mail-io0-x243.google.com with SMTP id i184so26886412ioa.0; Sun, 26 Nov 2017 14:00:03 -0800 (PST) Received: from localhost.localdomain (173-29-146-33.client.mchsi.com. [173.29.146.33]) by smtp.gmail.com with ESMTPSA id n184sm6517218itg.9.2017.11.26.14.00.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 26 Nov 2017 14:00:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=o/XYFQQ7a15RxrxH7YM9wNqcxcrsOXXpT0F3bRrTECc=; b=BmSnsevADCfasHza5BQIzTRLiUtMDVk0vC8i8Pkhjeo3vQJmw00AyiPGui2QA/zlfX CIv4Hbdr5+7yG1Wf+LprPfy8T44WcK5efaV+dpWOgsXdU7HBqZLIfHJRig8BJ48W45jY YbMo0xz9sp8z63+SAbaYjAIxiirxgMcnPM0xAemFyxqZGb2WUcB22Ewsi6pyqyVsIhWm t75wEWRl9z5xr5c7yjrbFGsSklLHF7oXGcs+d7/ZQJnrNFI232o5lVKF74QspYna/Q6a /YoEsSiaT/L2CmudIQN9l1SejZLZlsjNCd+yVh/ynC5gMjubIP2Ht5SgK5eTS24aBp0J Sv8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=o/XYFQQ7a15RxrxH7YM9wNqcxcrsOXXpT0F3bRrTECc=; b=aEsZ8c7SIXNhKGGHoIzUI8MOv8v1gtBkbPZfGCWyqhe6i7RMF5I2MRht57TwajyE7f IYRJgSwqU83xWyM+ZGXD+ei88JVH69AY9CqG+fzoEReZFDfTOeQPLLXc7MWxKLKdC8/t DQi8eGBrJymV1v1vPfV1i+MHu8u3G5YlS1IDguJLbqxijmNxYQLLtZuemsPcbZhICRVW 59rNAMf65CtBGI1JtwSBYWTBboclHjaZy1JFhh1tQrCApTzN+R9K9trLUGF1910QkTCN RDqd9JffJFzNPAY1bTfpRjLvrlZNQo0RfZhPpRj5EPnY0/VzagXwI6eRDtUDIjBGHYk6 3KtA== X-Gm-Message-State: AJaThX5YeBbg4vBIxpp3OqGIhy54JBdwlkGF84lHRa4ZTql8gdxgGyzR VLa/hC/H27i/GgcBTeAjW3HVaw== X-Google-Smtp-Source: AGs4zMZLIVTFYuPmY9TDZW/a/ATaj6e+LyHs8Is3Q5gK0lO2ShOAHYgASMEyldOlu/+Xe7SGoZZtCg== X-Received: by 10.107.158.193 with SMTP id h184mr38245956ioe.256.1511733602535; Sun, 26 Nov 2017 14:00:02 -0800 (PST) From: Michael Davidsaver To: Alexander Graf , David Gibson Date: Sun, 26 Nov 2017 15:59:15 -0600 Message-Id: <6417d3123f961850c57474272c717152100b917a.1511731946.git.mdavidsaver@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4001:c06::243 Subject: [Qemu-devel] [PATCH 17/17] tests: add mvme3100-test X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Davidsaver , qemu-ppc@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Exercise some features of the mvme3100 CPLD logic and read from the eeprom w/ VPD. Signed-off-by: Michael Davidsaver --- tests/Makefile.include | 3 ++ tests/mvme3100-test.c | 79 ++++++++++++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 82 insertions(+) create mode 100644 tests/mvme3100-test.c diff --git a/tests/Makefile.include b/tests/Makefile.include index 062d4e5b7b..97bce77ee4 100644 --- a/tests/Makefile.include +++ b/tests/Makefile.include @@ -373,6 +373,8 @@ check-qtest-s390x-y +=3D tests/virtio-balloon-test$(EXE= SUF) check-qtest-s390x-y +=3D tests/virtio-console-test$(EXESUF) check-qtest-s390x-y +=3D tests/virtio-serial-test$(EXESUF) =20 +check-qtest-ppc-$(CONFIG_E500) +=3D tests/mvme3100-test$(EXESUF) + check-qtest-generic-y +=3D tests/qom-test$(EXESUF) check-qtest-generic-y +=3D tests/test-hmp$(EXESUF) =20 @@ -782,6 +784,7 @@ tests/i82801b11-test$(EXESUF): tests/i82801b11-test.o tests/ac97-test$(EXESUF): tests/ac97-test.o tests/es1370-test$(EXESUF): tests/es1370-test.o tests/intel-hda-test$(EXESUF): tests/intel-hda-test.o +tests/mvme3100-test$(EXESUF): tests/mvme3100-test.o $(libqos-e500-obj-y) tests/ioh3420-test$(EXESUF): tests/ioh3420-test.o tests/usb-hcd-ohci-test$(EXESUF): tests/usb-hcd-ohci-test.o $(libqos-usb-o= bj-y) tests/usb-hcd-uhci-test$(EXESUF): tests/usb-hcd-uhci-test.o $(libqos-usb-o= bj-y) diff --git a/tests/mvme3100-test.c b/tests/mvme3100-test.c new file mode 100644 index 0000000000..6dde8d1d29 --- /dev/null +++ b/tests/mvme3100-test.c @@ -0,0 +1,79 @@ +#include + +#include "qemu/osdep.h" +#include "libqtest.h" +#include "libqos/libqos.h" +#include "libqos/i2c.h" + +#define assert_equal(A, B) g_assert_cmphex((A), =3D=3D, (B)) + +static +I2CAdapter *i2c; + +static +void test_ccsr(void) +{ + /* CCSRBAR is self referential */ + assert_equal(readl(0xff700000), 0x000ff700); + + /* introspect memory size */ + assert_equal(readl(0xff702080), 0x80000000); + /* value is (ram_size-1)>>24 */ + assert_equal(readl(0xff702000), 15); +} + +static +void test_cpld(void) +{ + /* read/write to test register */ + assert_equal(readl(0xe2000010), 0x00000000); + assert_equal(readl(0xe2000014), 0xffffffff); + + writel(0xe2000010, 0x12345678); + + assert_equal(readl(0xe2000010), 0x12345678); + assert_equal(readl(0xe2000014), 0x12345678 ^ 0xffffffff); +} + +static +void test_eeprom(void) +{ + char buf[] =3D "\x00\x00MOTOROLA"; + + /* 1. zero address pointer + * 2. write 8 bytes, + * 3. re-zero address pointer + */ + i2c_send(i2c, 0xa8, (uint8_t *)buf, 10); + i2c_send(i2c, 0xa8, (uint8_t *)buf, 2); + + /* read 8 bytes */ + i2c_recv(i2c, 0xa8, (uint8_t *)buf, 8); + buf[8] =3D '\0'; + + /* Read header for Motorola VPD info */ + g_assert_cmpstr(buf, =3D=3D, "MOTOROLA"); +} + +int main(int argc, char *argv[]) +{ + int ret; + g_test_init(&argc, &argv, NULL); + + qtest_start("-machine mvme3100-1152"); + + i2c =3D e500_i2c_create(0xff700000); + + qtest_add_func("/mvme3100/ccsr", test_ccsr); + qtest_add_func("/mvme3100/cpld", test_cpld); + qtest_add_func("/mvme3100/eeprom", test_eeprom); + + ret =3D g_test_run(); + + printf("Tests done\n"); + + qtest_end(); + printf("Tests end\n"); + + return ret; +} --=20 2.11.0