It turns out that my recent fix to set rip_offset when emulating some
SSE4.1 instructions needs generalizing to cover a wider class of
instructions. Specifically, every instruction in the sse_op_table7
table, coming from various instruction set extensions, has an 8-bit
immediate operand that comes after any memory operand, and so needs
rip_offset set for correctness if there is a memory operand that is
rip-relative, and my patch only set it for a subset of those
instructions. This patch moves the rip_offset setting to cover the
wider class of instructions, so fixing 9 further gcc testsuite
failures in my GCC 6-based testing. (I do not know whether there
might be still further classes of instructions missing this setting.)
Signed-off-by: Joseph Myers <joseph@codesourcery.com>
---
diff --git a/target/i386/translate.c b/target/i386/translate.c
index 5fdadf9..95f7261 100644
--- a/target/i386/translate.c
+++ b/target/i386/translate.c
@@ -4077,10 +4077,11 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if (!(s->cpuid_ext_features & sse_op_table7[b].ext_mask))
goto illegal_op;
+ s->rip_offset = 1;
+
if (sse_fn_eppi == SSE_SPECIAL) {
ot = mo_64_32(s->dflag);
rm = (modrm & 7) | REX_B(s);
- s->rip_offset = 1;
if (mod != 3)
gen_lea_modrm(env, s, modrm);
reg = ((modrm >> 3) & 7) | rex_r;
--
Joseph S. Myers
joseph@codesourcery.com
On 09/08/2017 01:51, Joseph Myers wrote: > It turns out that my recent fix to set rip_offset when emulating some > SSE4.1 instructions needs generalizing to cover a wider class of > instructions. Specifically, every instruction in the sse_op_table7 > table, coming from various instruction set extensions, has an 8-bit > immediate operand that comes after any memory operand, and so needs > rip_offset set for correctness if there is a memory operand that is > rip-relative, and my patch only set it for a subset of those > instructions. This patch moves the rip_offset setting to cover the > wider class of instructions, so fixing 9 further gcc testsuite > failures in my GCC 6-based testing. (I do not know whether there > might be still further classes of instructions missing this setting.) > > Signed-off-by: Joseph Myers <joseph@codesourcery.com> > > --- > > diff --git a/target/i386/translate.c b/target/i386/translate.c > index 5fdadf9..95f7261 100644 > --- a/target/i386/translate.c > +++ b/target/i386/translate.c > @@ -4077,10 +4077,11 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, > if (!(s->cpuid_ext_features & sse_op_table7[b].ext_mask)) > goto illegal_op; > > + s->rip_offset = 1; > + > if (sse_fn_eppi == SSE_SPECIAL) { > ot = mo_64_32(s->dflag); > rm = (modrm & 7) | REX_B(s); > - s->rip_offset = 1; > if (mod != 3) > gen_lea_modrm(env, s, modrm); > reg = ((modrm >> 3) & 7) | rex_r; > Queued, thanks. Paolo
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