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Missing CASA instruction handling for SPARC qemu-user

Luca Bonissi posted 1 patch 9 months, 2 weeks ago
Failed in applying to current master (apply log)
Missing CASA instruction handling for SPARC qemu-user
Posted by Luca Bonissi 9 months, 2 weeks ago 
On qemu-sparc (user-space), the CASA instruction is not handled for 
SPARC32 even if the selected cpu (e.g. LEON3) supports it.

Following the patch that works. I created "fake" ld/st_asi helpers: it 
seems all works fine, but I don't know if we should make real ld/st 
helpers like for SPARC64 user-space. Please check.

The patch also include an incorrect cpu-type for 32bit and missing 
configureable CPU features TA0_SHUTDOWN, ASR17, CACHE_CTRL, POWERDOWN, 
and CASA.


diff -urp qemu-20230327.orig/linux-user/syscall.c 
qemu-20230327/linux-user/syscall.c
--- qemu-20230327.orig/linux-user/syscall.c	2023-03-27 
15:41:42.000000000 +0200
+++ qemu-20230327/linux-user/syscall.c	2023-04-01 13:54:14.709136932 +0200
@@ -8286,7 +8286,11 @@ static int open_net_route(CPUArchState *
  #if defined(TARGET_SPARC)
  static int open_cpuinfo(CPUArchState *cpu_env, int fd)
  {
+#if defined(TARGET_SPARC64)
      dprintf(fd, "type\t\t: sun4u\n");
+#else
+    dprintf(fd, "type\t\t: sun4m\n");
+#endif
      return 0;
  }
  #endif
diff -urp qemu-20230327.orig/target/sparc/cpu.c 
qemu-20230327/target/sparc/cpu.c
--- qemu-20230327.orig/target/sparc/cpu.c	2023-03-27 15:41:42.000000000 
+0200
+++ qemu-20230327/target/sparc/cpu.c	2023-03-31 21:32:54.927008782 +0200
@@ -560,6 +560,11 @@ static const char * const feature_name[]
      "hypv",
      "cmt",
      "gl",
+    "ta0shdn",
+    "asr17",
+    "cachectrl",
+    "powerdown",
+    "casa",
  };

  static void print_features(uint32_t features, const char *prefix)
@@ -852,6 +857,11 @@ static Property sparc_cpu_properties[] =
      DEFINE_PROP_BIT("hypv",     SPARCCPU, env.def.features, 11, false),
      DEFINE_PROP_BIT("cmt",      SPARCCPU, env.def.features, 12, false),
      DEFINE_PROP_BIT("gl",       SPARCCPU, env.def.features, 13, false),
+    DEFINE_PROP_BIT("ta0shdn",  SPARCCPU, env.def.features, 14, false),
+    DEFINE_PROP_BIT("asr17",    SPARCCPU, env.def.features, 15, false),
+    DEFINE_PROP_BIT("cachectrl",SPARCCPU, env.def.features, 16, false),
+    DEFINE_PROP_BIT("powerdown",SPARCCPU, env.def.features, 17, false),
+    DEFINE_PROP_BIT("casa",     SPARCCPU, env.def.features, 18, false),
      DEFINE_PROP_UNSIGNED("iu-version", SPARCCPU, env.def.iu_version, 0,
                           qdev_prop_uint64, target_ulong),
      DEFINE_PROP_UINT32("fpu-version", SPARCCPU, env.def.fpu_version, 0),
diff -urp qemu-20230327.orig/target/sparc/helper.h 
qemu-20230327/target/sparc/helper.h
--- qemu-20230327.orig/target/sparc/helper.h	2023-03-27 
15:41:42.000000000 +0200
+++ qemu-20230327/target/sparc/helper.h	2023-03-31 20:41:36.084224862 +0200
@@ -38,10 +38,10 @@ DEF_HELPER_3(tsubcctv, tl, env, tl, tl)
  DEF_HELPER_FLAGS_3(sdivx, TCG_CALL_NO_WG, s64, env, s64, s64)
  DEF_HELPER_FLAGS_3(udivx, TCG_CALL_NO_WG, i64, env, i64, i64)
  #endif
-#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
+//#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
  DEF_HELPER_FLAGS_4(ld_asi, TCG_CALL_NO_WG, i64, env, tl, int, i32)
  DEF_HELPER_FLAGS_5(st_asi, TCG_CALL_NO_WG, void, env, tl, i64, int, i32)
-#endif
+//#endif
  DEF_HELPER_FLAGS_1(check_ieee_exceptions, TCG_CALL_NO_WG, tl, env)
  DEF_HELPER_FLAGS_3(ldfsr, TCG_CALL_NO_RWG, tl, env, tl, i32)
  DEF_HELPER_FLAGS_1(fabss, TCG_CALL_NO_RWG_SE, f32, f32)
diff -urp qemu-20230327.orig/target/sparc/ldst_helper.c 
qemu-20230327/target/sparc/ldst_helper.c
--- qemu-20230327.orig/target/sparc/ldst_helper.c	2023-03-27 
15:41:42.000000000 +0200
+++ qemu-20230327/target/sparc/ldst_helper.c	2023-03-31 
21:02:21.897968335 +0200
@@ -1167,7 +1168,19 @@ void helper_st_asi(CPUSPARCState *env, t
  #endif
  }

+#else /* CONFIG_USER_ONLY */
+uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr,
+                       int asi, uint32_t memop)
+{
+	return(0);
+}
+void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val,
+                   int asi, uint32_t memop)
+{
+}
+
  #endif /* CONFIG_USER_ONLY */
+
  #else /* TARGET_SPARC64 */

  #ifdef CONFIG_USER_ONLY
diff -urp qemu-20230327.orig/target/sparc/translate.c 
qemu-20230327/target/sparc/translate.c
--- qemu-20230327.orig/target/sparc/translate.c	2023-03-27 
15:41:42.000000000 +0200
+++ qemu-20230327/target/sparc/translate.c	2023-04-01 15:24:18.293176711 
+0200
@@ -1910,7 +1910,8 @@ static void gen_ldstub(DisasContext *dc,
  }

  /* asi moves */
-#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
+//#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
+#if 1
  typedef enum {
      GET_ASI_HELPER,
      GET_ASI_EXCP,
@@ -5521,7 +5522,7 @@ static void disas_sparc_insn(DisasContex
                  case 0x37: /* stdc */
                      goto ncp_insn;
  #endif
-#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
+//#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
                  case 0x3c: /* V9 or LEON3 casa */
  #ifndef TARGET_SPARC64
                      CHECK_IU_FEATURE(dc, CASA);
@@ -5529,8 +5530,8 @@ static void disas_sparc_insn(DisasContex
                      rs2 = GET_FIELD(insn, 27, 31);
                      cpu_src2 = gen_load_gpr(dc, rs2);
                      gen_cas_asi(dc, cpu_addr, cpu_src2, insn, rd);
+//#endif
                      break;
-#endif
                  default:
                      goto illegal_insn;
                  }
Re: [PATCH] Missing CASA instruction handling for SPARC qemu-user
Posted by Luca Bonissi 9 months, 2 weeks ago 
On qemu-sparc (user-space), the CASA instruction is not handled for 
SPARC32 even if the selected cpu (e.g. LEON3) supports it.

Following the patch that works.

The patch also include an incorrect cpu-type for 32bit and missing 
configurable CPU features TA0_SHUTDOWN, ASR17, CACHE_CTRL, POWERDOWN, 
and CASA.

Re-posting to add "signed-off-by" line. Removing also unused functions 
from qemu-sparc (32bit) building, and consequently removed helper patch 
(needed only by unused [removed] functions).


Signed-off-by: Luca Bonissi <qemu@bonslack.org>
---

diff -urp a/linux-user/syscall.c b/linux-user/syscall.c
--- a/linux-user/syscall.c	2023-03-27 15:41:42.000000000 +0200
+++ b/linux-user/syscall.c	2023-04-01 13:54:14.709136932 +0200
@@ -8286,7 +8286,11 @@ static int open_net_route(CPUArchState *
  #if defined(TARGET_SPARC)
  static int open_cpuinfo(CPUArchState *cpu_env, int fd)
  {
+#if defined(TARGET_SPARC64)
      dprintf(fd, "type\t\t: sun4u\n");
+#else
+    dprintf(fd, "type\t\t: sun4m\n");
+#endif
      return 0;
  }
  #endif
diff -urp a/target/sparc/cpu.c b/target/sparc/cpu.c
--- a/target/sparc/cpu.c	2023-03-27 15:41:42.000000000 +0200
+++ b/target/sparc/cpu.c	2023-03-31 21:32:54.927008782 +0200
@@ -560,6 +560,11 @@ static const char * const feature_name[]
      "hypv",
      "cmt",
      "gl",
+    "ta0shdn",
+    "asr17",
+    "cachectrl",
+    "powerdown",
+    "casa",
  };

  static void print_features(uint32_t features, const char *prefix)
@@ -852,6 +857,11 @@ static Property sparc_cpu_properties[] =
      DEFINE_PROP_BIT("hypv",     SPARCCPU, env.def.features, 11, false),
      DEFINE_PROP_BIT("cmt",      SPARCCPU, env.def.features, 12, false),
      DEFINE_PROP_BIT("gl",       SPARCCPU, env.def.features, 13, false),
+    DEFINE_PROP_BIT("ta0shdn",  SPARCCPU, env.def.features, 14, false),
+    DEFINE_PROP_BIT("asr17",    SPARCCPU, env.def.features, 15, false),
+    DEFINE_PROP_BIT("cachectrl",SPARCCPU, env.def.features, 16, false),
+    DEFINE_PROP_BIT("powerdown",SPARCCPU, env.def.features, 17, false),
+    DEFINE_PROP_BIT("casa",     SPARCCPU, env.def.features, 18, false),
      DEFINE_PROP_UNSIGNED("iu-version", SPARCCPU, env.def.iu_version, 0,
                           qdev_prop_uint64, target_ulong),
      DEFINE_PROP_UINT32("fpu-version", SPARCCPU, env.def.fpu_version, 0),
diff -urp a/target/sparc/translate.c b/target/sparc/translate.c
--- a/target/sparc/translate.c	2023-03-27 15:41:42.000000000 +0200
+++ b/target/sparc/translate.c	2023-07-18 17:27:30.681134549 +0200
@@ -1917,7 +1917,6 @@ static void gen_ldstub(DisasContext *dc,
  }

  /* asi moves */
-#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
  typedef enum {
      GET_ASI_HELPER,
      GET_ASI_EXCP,
@@ -2149,6 +2148,7 @@ static DisasASI get_asi(DisasContext *dc
      return (DisasASI){ type, asi, mem_idx, memop };
  }

+#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
  static void gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr,
                         int insn, MemOp memop)
  {
@@ -2277,6 +2277,7 @@ static void gen_swap_asi(DisasContext *d
          break;
      }
  }
+#endif // !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)

  static void gen_cas_asi(DisasContext *dc, TCGv addr, TCGv cmpv,
                          int insn, int rd)
@@ -2300,6 +2301,7 @@ static void gen_cas_asi(DisasContext *dc
      }
  }

+#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
  static void gen_ldstub_asi(DisasContext *dc, TCGv dst, TCGv addr, int 
insn)
  {
      DisasASI da = get_asi(dc, insn, MO_UB);
@@ -5508,7 +5510,6 @@ static void disas_sparc_insn(DisasContex
                  case 0x37: /* stdc */
                      goto ncp_insn;
  #endif
-#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
                  case 0x3c: /* V9 or LEON3 casa */
  #ifndef TARGET_SPARC64
                      CHECK_IU_FEATURE(dc, CASA);
@@ -5517,7 +5518,6 @@ static void disas_sparc_insn(DisasContex
                      cpu_src2 = gen_load_gpr(dc, rs2);
                      gen_cas_asi(dc, cpu_addr, cpu_src2, insn, rd);
                      break;
-#endif
                  default:
                      goto illegal_insn;
                  }
Re: [PATCH] Missing CASA instruction handling for SPARC qemu-user
Posted by Richard Henderson 6 months ago 
On 7/18/23 09:09, Luca Bonissi wrote:
> On qemu-sparc (user-space), the CASA instruction is not handled for SPARC32 even if the 
> selected cpu (e.g. LEON3) supports it.

This should be fixed now, with

commit d0a11d25f0332dbaeb3a4f733a5cfb23ed40413d
Author: Richard Henderson <richard.henderson@linaro.org>
Date:   Thu Oct 5 00:09:36 2023 -0700

     target/sparc: Move CASA, CASXA to decodetree

     Remove gen_cas_asi, gen_casx_asi.
     Rename gen_cas_asi0 to gen_cas_asi.

     Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
     Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
     Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


r~

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