From nobody Thu May 2 01:53:23 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1487530966535136.47354015187443; Sun, 19 Feb 2017 11:02:46 -0800 (PST) Received: from localhost ([::1]:34803 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cfWks-0008W8-TS for importer@patchew.org; Sun, 19 Feb 2017 14:02:42 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50538) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cfWjv-0007wa-DP for qemu-devel@nongnu.org; Sun, 19 Feb 2017 14:01:44 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cfWjs-0007sX-AV for qemu-devel@nongnu.org; Sun, 19 Feb 2017 14:01:43 -0500 Received: from mail.ispras.ru ([83.149.199.45]:47358) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cfWje-0007gi-TK; Sun, 19 Feb 2017 14:01:29 -0500 Received: from [192.168.0.103] (nat-1-33.msu.umos.ru [85.89.127.33]) by mail.ispras.ru (Postfix) with ESMTPSA id 1559E54006E; Sun, 19 Feb 2017 22:01:03 +0300 (MSK) To: Peter Maydell , qemu-arm@nongnu.org, Peter Chubb , QEMU Developers References: <076b0d94-738e-252c-1ed8-4640a864ac34@ispras.ru> <4d2f2d04-e294-bdad-4f77-9a0171357d05@ispras.ru> From: Kurban Mallachiev Message-ID: <332706f6-7b54-89db-6b89-5684362fb2e3@ispras.ru> Date: Sun, 19 Feb 2017 22:00:50 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.7.1 MIME-Version: 1.0 In-Reply-To: <4d2f2d04-e294-bdad-4f77-9a0171357d05@ispras.ru> Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 83.149.199.45 Subject: [Qemu-devel] [PATCH v3] ARM i.MX timers: fix software reset X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8"; format="flowed" Hello! Problem: function imx_gpt_reset is used for soft (requested by guest)=20 and hard resets. But soft and hard resets should have different=20 behaviour (hard reset should clear all registers, while soft reset=20 should preserve some bits). Patch changelog: v1 -> v2: use different approach, patch completely rewritten v2 -> v3: in software reset add preserving of CLKSRC bit as manual says --- Software reset function clears CR bits that should not be cleared and preserve bits that should be cleared. Signed-off-by: Kurban Mallachiev --- hw/timer/imx_gpt.c | 27 +++++++++++++++++++++------ 1 file changed, 21 insertions(+), 6 deletions(-) diff --git a/hw/timer/imx_gpt.c b/hw/timer/imx_gpt.c index 010ccbf207..3ea18ff5de 100644 --- a/hw/timer/imx_gpt.c +++ b/hw/timer/imx_gpt.c @@ -296,18 +296,21 @@ static uint64_t imx_gpt_read(void *opaque, hwaddr=20 offset, unsigned size) return reg_value; } -static void imx_gpt_reset(DeviceState *dev) +static void imx_gpt_reset_common(IMXGPTState *s, int is_soft_reset) { - IMXGPTState *s =3D IMX_GPT(dev); - /* stop timer */ ptimer_stop(s->timer); /* * Soft reset doesn't touch some bits; hard reset clears them */ - s->cr &=3D ~(GPT_CR_EN|GPT_CR_ENMOD|GPT_CR_STOPEN|GPT_CR_DOZEN| - GPT_CR_WAITEN|GPT_CR_DBGEN); + if (is_soft_reset) { + s->cr &=3D GPT_CR_EN|GPT_CR_ENMOD|GPT_CR_STOPEN|GPT_CR_DOZEN| + GPT_CR_WAITEN|GPT_CR_DBGEN| + GPT_CR_CLKSRC_MASK<cr =3D 0; + } s->sr =3D 0; s->pr =3D 0; s->ir =3D 0; @@ -333,6 +336,18 @@ static void imx_gpt_reset(DeviceState *dev) } } +static void imx_gpt_soft_reset(DeviceState *dev) +{ + IMXGPTState *s =3D IMX_GPT(dev); + imx_gpt_reset_common(s, 1); +} + +static void imx_gpt_reset(DeviceState *dev) +{ + IMXGPTState *s =3D IMX_GPT(dev); + imx_gpt_reset_common(s, 0); +} + static void imx_gpt_write(void *opaque, hwaddr offset, uint64_t value, unsigned size) { @@ -348,7 +363,7 @@ static void imx_gpt_write(void *opaque, hwaddr=20 offset, uint64_t value, s->cr =3D value & ~0x7c14; if (s->cr & GPT_CR_SWR) { /* force reset */ /* handle the reset */ - imx_gpt_reset(DEVICE(s)); + imx_gpt_soft_reset(DEVICE(s)); } else { /* set our freq, as the source might have changed */ imx_gpt_set_freq(s); --=20 2.11.1